sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP

Browse Source 
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.

Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82081
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Shuo Liu
2024-04-25 05:41:16 +08:00
committed by Lean Sheng Tan
parent b84d55b582
commit 78439118c8
1 changed files with 4 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/xeon_sp/lockdown.c
View File

@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/cfg.h>
#include <intelblocks/lpc_lib.h> #include <intelblocks/lpc_lib.h>
#include <intelpch/lockdown.h> #include <intelpch/lockdown.h>
#include <soc/lockdown.h> #include <soc/lockdown.h>
@@ -20,6 +21,9 @@ static void lpc_lockdown_config(void)
void soc_lockdown_config(int chipset_lockdown) void soc_lockdown_config(int chipset_lockdown)
{ {
if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
return;
lpc_lockdown_config(); lpc_lockdown_config();
pmc_lockdown_config(); pmc_lockdown_config();
sata_lockdown_config(chipset_lockdown); sata_lockdown_config(chipset_lockdown);