mb/system76/thelio-b1: Fix devicetree formatting
Change-Id: I35b238aaea49b6213c1b4094d0ac153ab9a76c8c Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Jeremy Soller
Jeremy Soller
parent
1ff8f316f4
commit
7ba5665046
@@ -1,240 +1,240 @@
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chip soc/intel/cannonlake
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# ACPI (soc/intel/cannonlake/acpi.c)
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# Enable s0ix
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register "s0ix_enable" = "0"
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# Enable s0ix
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register "s0ix_enable" = "0"
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# PM Timer Enabled
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register "PmTimerDisabled" = "0"
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# PM Timer Enabled
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register "PmTimerDisabled" = "0"
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# Disable DPTF
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register "dptf_enable" = "0"
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# Disable DPTF
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register "dptf_enable" = "0"
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# CPU (soc/intel/cannonlake/cpu.c)
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# Power limit
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#register "tdp_pl1_override" = "15"
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#register "tdp_pl2_override" = "25"
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# Power limit
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#register "tdp_pl1_override" = "15"
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#register "tdp_pl2_override" = "25"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
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register "SaGv" = "SaGv_Enabled"
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#register "enable_c6dram" = "1"
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register "SaGv" = "SaGv_Enabled"
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#register "enable_c6dram" = "1"
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# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
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# SATA
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register "SataMode" = "Sata_AHCI"
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register "SataSalpSupport" = "0"
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# SATA
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register "SataMode" = "Sata_AHCI"
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register "SataSalpSupport" = "0"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsEnable[3]" = "1"
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register "SataPortsEnable[4]" = "1"
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register "SataPortsEnable[5]" = "1"
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register "SataPortsEnable[6]" = "0"
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register "SataPortsEnable[7]" = "0"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsEnable[3]" = "1"
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register "SataPortsEnable[4]" = "1"
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register "SataPortsEnable[5]" = "1"
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register "SataPortsEnable[6]" = "0"
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register "SataPortsEnable[7]" = "0"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "0"
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register "SataPortsDevSlp[2]" = "0"
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register "SataPortsDevSlp[3]" = "0"
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register "SataPortsDevSlp[4]" = "0"
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register "SataPortsDevSlp[5]" = "0"
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register "SataPortsDevSlp[6]" = "0"
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register "SataPortsDevSlp[7]" = "0"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[1]" = "0"
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register "SataPortsDevSlp[2]" = "0"
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register "SataPortsDevSlp[3]" = "0"
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register "SataPortsDevSlp[4]" = "0"
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register "SataPortsDevSlp[5]" = "0"
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register "SataPortsDevSlp[6]" = "0"
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register "SataPortsDevSlp[7]" = "0"
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# Audio
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkDmic0" = "1"
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register "PchHdaAudioLinkDmic1" = "1"
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register "PchHdaAudioLinkSsp0" = "0"
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register "PchHdaAudioLinkSsp1" = "0"
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register "PchHdaAudioLinkSsp2" = "0"
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register "PchHdaAudioLinkSndw1" = "0"
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register "PchHdaAudioLinkSndw2" = "0"
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register "PchHdaAudioLinkSndw3" = "0"
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register "PchHdaAudioLinkSndw4" = "0"
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# Audio
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register "PchHdaDspEnable" = "0"
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register "PchHdaAudioLinkHda" = "1"
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register "PchHdaAudioLinkDmic0" = "1"
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register "PchHdaAudioLinkDmic1" = "1"
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register "PchHdaAudioLinkSsp0" = "0"
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register "PchHdaAudioLinkSsp1" = "0"
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register "PchHdaAudioLinkSsp2" = "0"
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register "PchHdaAudioLinkSndw1" = "0"
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register "PchHdaAudioLinkSndw2" = "0"
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register "PchHdaAudioLinkSndw3" = "0"
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register "PchHdaAudioLinkSndw4" = "0"
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# USB
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register "SsicPortEnable" = "0"
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# USB
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register "SsicPortEnable" = "0"
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
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register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1
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register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC
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register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC
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register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC
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register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC
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register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC
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register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1
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register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
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register "usb2_ports[3]" = "USB2_PORT_EMPTY"
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register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0
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register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0
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register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0
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register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1
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register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1
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register "usb2_ports[10]" = "USB2_PORT_EMPTY"
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register "usb2_ports[11]" = "USB2_PORT_EMPTY"
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register "usb2_ports[12]" = "USB2_PORT_EMPTY"
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register "usb2_ports[13]" = "USB2_PORT_EMPTY"
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register "usb2_ports[14]" = "USB2_PORT_EMPTY"
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register "usb2_ports[15]" = "USB2_PORT_EMPTY"
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P4
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P5
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8
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register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC
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register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P2
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P3
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P4
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register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P5
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register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6
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register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7
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register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8
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register "usb3_ports[8]" = "USB3_PORT_EMPTY"
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register "usb3_ports[9]" = "USB3_PORT_EMPTY"
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# PCI Express Root port #5 x1, Clock 6 (I219-V)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[6]" = "4"
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register "PcieClkSrcClkReq[6]" = "6"
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# PCI Express Root port #5 x1, Clock 6 (I219-V)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[6]" = "4"
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register "PcieClkSrcClkReq[6]" = "6"
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# PCI Express Root port #6 x1, Clock 7 (I211-AT)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[7]" = "5"
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register "PcieClkSrcClkReq[7]" = "7"
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# PCI Express Root port #6 x1, Clock 7 (I211-AT)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[7]" = "5"
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register "PcieClkSrcClkReq[7]" = "7"
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# PCI Express Root port #9 x4, Clock 5 (M.2 P)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[5]" = "8"
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register "PcieClkSrcClkReq[5]" = "5"
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# PCI Express Root port #9 x4, Clock 5 (M.2 P)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[5]" = "8"
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register "PcieClkSrcClkReq[5]" = "5"
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# PCI Express Root port #21 x4, Clock 3 (M.2 Q)
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieClkSrcUsage[3]" = "20"
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register "PcieClkSrcClkReq[3]" = "3"
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# PCI Express Root port #21 x4, Clock 3 (M.2 Q)
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register "PcieRpEnable[20]" = "1"
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register "PcieRpLtrEnable[20]" = "1"
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register "PcieClkSrcUsage[3]" = "20"
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register "PcieClkSrcClkReq[3]" = "3"
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# TODO: Clock 0 is used for PCIE X16
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# TODO: Clock 0 is used for PCIE X16
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# Misc
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register "Device4Enable" = "1"
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register "HeciEnabled" = "1"
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register "AcousticNoiseMitigation" = "1"
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#register "dmipwroptimize" = "1"
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#register "satapwroptimize" = "1"
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# Misc
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register "Device4Enable" = "1"
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register "HeciEnabled" = "1"
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register "AcousticNoiseMitigation" = "1"
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#register "dmipwroptimize" = "1"
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#register "satapwroptimize" = "1"
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Power
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS4MinAssert" = "1" # 1s
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register "PchPmSlpSusMinAssert" = "2" # 500ms
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register "PchPmSlpAMinAssert" = "4" # 2s
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# Thermal
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register "tcc_offset" = "12"
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# Thermal
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register "tcc_offset" = "12"
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# Serial IRQ Continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# Serial IRQ Continuous
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# LPC (soc/intel/cannonlake/lpc.c)
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# LPC configuration from lspci -xxx
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register "gen1_dec" = "0x000c0081"
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register "gen2_dec" = "0x00040069"
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register "gen3_dec" = "0x000c3321"
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register "gen4_dec" = "0x00000000"
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# LPC configuration from lspci -xxx
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register "gen1_dec" = "0x000c0081"
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register "gen2_dec" = "0x00040069"
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register "gen3_dec" = "0x000c3321"
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register "gen4_dec" = "0x00000000"
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# 8254
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register "clock_gate_8254" = "0"
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# 8254
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register "clock_gate_8254" = "0"
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# PMC (soc/intel/cannonlake/pmc.c)
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "0"
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "0"
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# PM Util (soc/intel/cannonlake/pmutil.c)
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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register "gpe0_dw0" = "PMC_GPP_C"
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register "gpe0_dw1" = "PMC_GPP_D"
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register "gpe0_dw2" = "PMC_GPP_E"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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# sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
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register "gpe0_dw0" = "PMC_GPP_C"
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register "gpe0_dw1" = "PMC_GPP_D"
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register "gpe0_dw2" = "PMC_GPP_E"
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# Actual device tree
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 04.0 off end # SA Thermal device
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device pci 12.0 on end # Thermal Subsystem
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device pci 12.5 off end # UFS SCS
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device pci 12.6 off end # GSPI #2
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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#chip drivers/intel/wifi
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# register "wake" = "PME_B0_EN_BIT"
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device pci 14.3 on end # CNVi wifi
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#end
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device pci 14.5 off end # SDCard
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 16.5 off end # Management Engine Interface 4
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device pci 17.0 on end # SATA
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device pci 19.0 off end # I2C #4
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # UART #2
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device pci 1a.0 off end # eMMC
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 on end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 on end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on end # LPC Interface
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 off end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
device domain 0 on
|
||||
device pci 00.0 on end # Host Bridge
|
||||
device pci 02.0 on end # Integrated Graphics Device
|
||||
device pci 04.0 off end # SA Thermal device
|
||||
device pci 12.0 on end # Thermal Subsystem
|
||||
device pci 12.5 off end # UFS SCS
|
||||
device pci 12.6 off end # GSPI #2
|
||||
device pci 13.0 off end # Integrated Sensor Hub
|
||||
device pci 14.0 on end # USB xHCI
|
||||
device pci 14.1 off end # USB xDCI (OTG)
|
||||
#chip drivers/intel/wifi
|
||||
# register "wake" = "PME_B0_EN_BIT"
|
||||
device pci 14.3 on end # CNVi wifi
|
||||
#end
|
||||
device pci 14.5 off end # SDCard
|
||||
device pci 15.0 off end # I2C #0
|
||||
device pci 15.1 off end # I2C #1
|
||||
device pci 15.2 off end # I2C #2
|
||||
device pci 15.3 off end # I2C #3
|
||||
device pci 16.0 on end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT Redirection
|
||||
device pci 16.4 off end # Management Engine Interface 3
|
||||
device pci 16.5 off end # Management Engine Interface 4
|
||||
device pci 17.0 on end # SATA
|
||||
device pci 19.0 off end # I2C #4
|
||||
device pci 19.1 off end # I2C #5
|
||||
device pci 19.2 off end # UART #2
|
||||
device pci 1a.0 off end # eMMC
|
||||
device pci 1c.0 on end # PCI Express Port 1
|
||||
device pci 1c.1 off end # PCI Express Port 2
|
||||
device pci 1c.2 off end # PCI Express Port 3
|
||||
device pci 1c.3 off end # PCI Express Port 4
|
||||
device pci 1c.4 on end # PCI Express Port 5
|
||||
device pci 1c.5 off end # PCI Express Port 6
|
||||
device pci 1c.6 off end # PCI Express Port 7
|
||||
device pci 1c.7 off end # PCI Express Port 8
|
||||
device pci 1d.0 on end # PCI Express Port 9
|
||||
device pci 1d.1 on end # PCI Express Port 10
|
||||
device pci 1d.2 off end # PCI Express Port 11
|
||||
device pci 1d.3 off end # PCI Express Port 12
|
||||
device pci 1d.4 on end # PCI Express Port 13
|
||||
device pci 1d.5 off end # PCI Express Port 14
|
||||
device pci 1d.6 off end # PCI Express Port 15
|
||||
device pci 1d.7 off end # PCI Express Port 16
|
||||
device pci 1e.0 off end # UART #0
|
||||
device pci 1e.1 off end # UART #1
|
||||
device pci 1e.2 off end # GSPI #0
|
||||
device pci 1e.3 off end # GSPI #1
|
||||
device pci 1f.0 on end # LPC Interface
|
||||
device pci 1f.1 off end # P2SB
|
||||
device pci 1f.2 off end # Power Management Controller
|
||||
device pci 1f.3 on end # Intel HDA
|
||||
device pci 1f.4 on end # SMBus
|
||||
device pci 1f.5 on end # PCH SPI
|
||||
device pci 1f.6 off end # GbE
|
||||
end
|
||||
end
|
||||
|
||||
Reference in New Issue
Block a user