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mb/system76/thelio-b1: Fix devicetree formatting

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Change-Id: I35b238aaea49b6213c1b4094d0ac153ab9a76c8c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2020-09-19 18:11:36 -06:00
committed by Jeremy Soller
parent 1ff8f316f4
commit 7ba5665046
1 changed files with 200 additions and 200 deletions
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18
src/mainboard/system76/thelio-b1/devicetree.cb
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@@ -75,19 +75,19 @@ chip soc/intel/cannonlake
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[3]" = "USB2_PORT_EMPTY"
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[10]" = "USB2_PORT_EMPTY"
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[11]" = "USB2_PORT_EMPTY"
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[12]" = "USB2_PORT_EMPTY"
register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[13]" = "USB2_PORT_EMPTY"
register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[14]" = "USB2_PORT_EMPTY"
register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC register "usb2_ports[15]" = "USB2_PORT_EMPTY"
# USB3 # USB3
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1
@@ -98,8 +98,8 @@ chip soc/intel/cannonlake
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7
register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8
register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC register "usb3_ports[8]" = "USB3_PORT_EMPTY"
register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC register "usb3_ports[9]" = "USB3_PORT_EMPTY"
# PCI Express Root port #5 x1, Clock 6 (I219-V) # PCI Express Root port #5 x1, Clock 6 (I219-V)
register "PcieRpEnable[4]" = "1" register "PcieRpEnable[4]" = "1"