intel model_106cx: Include CAR from socket directory

Since the socket layer is implemented with this CPU model, there
could potentially be multiple CPU models included.  There can be
only one cache_as_ram include, so select it directly within
the socket directory.

Change-Id: Ia52bb152276eddfd1fb33ddb7f5d153ab8e8163c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15757
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/cpu/intel/model_106cx/Makefile.inc

@@ -1,6 +1,4 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 
-cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
-romstage-y += ../car/romstage.c
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

src/cpu/intel/socket_441/Makefile.inc

@@ -7,3 +7,6 @@ subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
 subdirs-y += ../speedstep
+
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+romstage-y += ../car/romstage.c

src/cpu/intel/socket_FCBGA559/Makefile.inc

@@ -6,3 +6,6 @@ subdirs-y += ../../x86/cache
 subdirs-y += ../../x86/smm
 subdirs-y += ../microcode
 subdirs-y += ../hyperthreading
+
+cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
+romstage-y += ../car/romstage.c