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Merge remote-tracking branch 'upstream/master' into system76

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Jeremy Soller
2020-02-13 14:03:34 -07:00
parent 3f76a2ec4c 820ad004bb
commit adc0d3b4e9
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2
3rdparty/blobs vendored

Submodule 3rdparty/blobs updated: 034b278184...7ad2d22452

2
3rdparty/vboot vendored

Submodule 3rdparty/vboot updated: f5367d598a...0e97e25e85

28
AUTHORS
View File

@@ -10,6 +10,7 @@
9elements Agency GmbH
Advanced Micro Devices, Inc.
AG Electronics Ltd.
Alex Züpke
Alexander Couzens
Alexandru Gagniuc
@@ -20,20 +21,27 @@ Arthur Heymans
ASPEED Technology Inc.
Atheros Corporation
Atmel Corporation
BAP - Bruhnspace Advanced Projects
Carl-Daniel Hailfinger
Christoph Grenz
coresystems GmbH
Corey Osgood
Damien Zammit
David Brownell
David Hendricks
David Mosberger-Tang
Denis Dowling
DENX Software Engineering
Digital Design Corporation
DMP Electronics Inc.
Drew Eckhardt
Dynon Avionics
Edward O'Callaghan
Egbert Eich
Eltan B.V
Eric Biederman
Eswar Nallusamy
Fabian Kunkel
Facebook, Inc.
Felix Held
Frederic Potter
@@ -41,6 +49,7 @@ Free Software Foundation, Inc.
Freescale Semiconductor, Inc.
Gary Jennejohn
Gerd Hoffmann
Gergely Kiss
Google LLC
Greg Watson
Idwer Vollering
@@ -53,11 +62,13 @@ Jordan Crouse
Joseph Smith
Keith Hui
Keith Packard
Kevin Cody-Little
Kshitij
Kyösti Mälkki
Lei Wen
Li-Ta Lo
Libra Li
Libretrend LDA
Linus Torvalds
Linux Networx, Inc.
Luc Verhaegen
@@ -67,34 +78,44 @@ Marius Gröger
Martin Mares
Marvell International Ltd.
Marvell Semiconductor Inc.
Matt DeVillier
MediaTek Inc.
Mondrian Nuessle
MontaVista Software, Inc.
Myles Watson
Network Appliance Inc.
Nicholas Sielicki
Nick Barker
Nico Huber
Nicola Corna
Ollie Lo
Omar Pakker
Orion Technologies, LLC
Patrick Georgi
Patrick Rudolph
Pavel Sayekat
PC Engines GmbH
Per Odlund
Peter Stuge
Philipp Degler
Protectli
Raptor Engineering, LLC
Red Hat Inc
Reinhard Meyer
Richard Spiegel
Richard Woodruff
Ronald G. Minnich
Rudolf Marek
Russell King
Sage Electronic Engineering, LLC
Samsung Electronics
Samuel Holland
SciTech Software, Inc.
Sebastian Grzywna
secunet Security Networks AG
Siemens AG
Silicon Integrated System Corporation
Silverback ltd.
Stefan Reinauer
Steve Magnani
ST Microelectronics
@@ -102,16 +123,22 @@ SUSE LINUX AG
Sven Schnelle
Syed Mohammed Khasim
Texas Instruments
The ChromiumOS Authors
The Linux Foundation
Thomas Winischhofer
Timothy Pearson
Tobias Diedrich
Tungsten Graphics, Inc.
Tyan Computer Corp.
ucRobotics Inc.
University of Heidelberg
Uwe Hermann
VIA Technologies, Inc
Vipin Kumar
Vladimir Serbinenko
Wang Qing Pei
Ward Vandewege
Win Enterprises
Wolfgang Denk
Yinghai Lu
@@ -125,3 +152,4 @@ src/console
src/cpu
src/device
src/drivers
src/superio

22
Documentation/contributing/project_ideas.md
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@@ -64,28 +64,6 @@ across architectures.
### Mentors
* Timothy Pearson <tpearson@raptorengineering.com>
## Support QEMU AArch64
Having QEMU support for the architectures coreboot can boot helps with
some (limited) compatibility testing: While QEMU generally doesn't need
much hardware init, any CPU state changes in the boot flow will likely
be quite close to reality.
That could be used as a baseline to ensure that changes to architecture
code doesn't entirely break these architectures
### Requirements
* coreboot knowledge: Should know the general boot flow in coreboot.
* other knowledge: This will require knowing how the architecture
typically boots, to adapt the coreboot payload interface to be
appropriate and, for example, provide a device tree in the platform's
typical format.
* hardware requirements: since QEMU runs practically everywhere and
needs no recovery mechanism, these are suitable projects when no special
hardware is available.
### Mentors
* Patrick Georgi <patrick@georgi.software>
## Add Kernel Address Sanitizer functionality to coreboot
The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector.
The idea is to check every memory access (variables) for its validity

75
Documentation/mainboard/facebook/monolith.md
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@@ -3,15 +3,55 @@
This page describes how to run coreboot on the Facebook Monolith.
Please note: the coreboot implementation for this boards is in its
Alpha state and isn't fully tested yet.
Beta state and isn't fully tested yet.
## Required blobs
This board currently requires:
fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd
3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd
Mainboard is based on the Intel Kaby Lake U SoC.
Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md)
(intel FSP 2.0) to initialize this generation silicon. Please see this
[document](../../soc/intel/code_development_model/code_development_model.md).
Microcode 3rdparty/intel-microcode/intel-ucode
FSP Information:
```eval_rst
+-----------------------------+-------------------+-------------------+
| FSP Project Name | Directory | Specification |
+-----------------------------+-------------------+-------------------+
| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 |
| processors and chipsets | | |
| (formerly Kaby Lake) | | |
+-----------------------------+-------------------+-------------------+
```
Microcode: 3rdparty/intel-microcode/intel-ucode
## Flash components
To create a complete flash image, the flash descriptor, GBE and ME blobs are required. The
complete image can be used when e.g. a blank flash should be programmed. In other cases (when
only coreboot needs to be replaced) placeholders can be used for the GBE and ME regions.
These can be extracted from the original flash image as follows:
1) Read the complete image from flash.
2) Create a layout file with the following content:
```
00000000:00000fff fd
00700000:00ffffff bios
00003000:006FFFFF me
00001000:00002fff gbe
```
3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6MB
to 9 MB, this is required to create sufficient space for LinuxBoot.
NOTE: Please make sure only the firmware descriptor (*fd*) region is changed. Older versions
of the ifdtool corrupt the *me* region.
4) Use `ifdtool -x <resized_flash_image>` to extract the components.
The regions extracted can be used to generate a full flash image. The *bios* region is
not needed as this is replaced by the coreboot image.
NOTE: The gbe region contains the MAC address so be careful. When updating the flash using
flashrom it is advisable to leave out the *gbe* area.
## Flashing coreboot
@@ -19,6 +59,17 @@ Microcode 3rdparty/intel-microcode/intel-ucode
The SPI flash can be accessed using [flashrom].
The descriptor area needs to be updated once to resize the *bios* region.
`flashrom -p internal --ifd -i fd -w <coreboot.bin>`
After that only the bios area should to be updated.
`flashrom -p internal --ifd -i bios -w <coreboot.bin>`
The *gbe* and *me* regions should not be updated.
NOTE: As `flashrom --ifd` uses the flash descriptor it is required to update the
descriptor and bios regions in the right sequence. Don't update both in one command.
### External programming
The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
@@ -37,25 +88,29 @@ solution. Wires need to be connected to be able to flash using an external progr
## Untested
- Hardware monitor
- SDIO
- Full Embedded Controller support
- eMMC
- SATA
- xDCI
## Working
- USB
- Gigabit Ethernet
- Gigabit Ethernet (i219 and i210)
- Graphics (Using FSP GOP)
- flashrom
- PCIe
- PCIe including hotplug on FPGA root port
- EC serial port
- EC CPU temperature
- SMBus
- Initialization with FSP
- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
- LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
- eMMC
All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
and LinuxBoot.
All of the above has been briefly tested by booting Linux from the TianoCore payload.
SeaBios has been checked to the extend that it runs to the boot selection and provides display
output.

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@@ -92,6 +92,7 @@ The boards in this section are not real mainboards, but emulators.
- [W530](lenovo/w530.md)
- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
- [T431s](lenovo/t431s.md)
- [Internal flashing](lenovo/ivb_internal_flashing.md)
### Haswell series

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# Ivy Bridge Lenovo ThinkPad Internal Flashing
## Introduction
Old versions of stock BIOS for these models have several security issues.
In order to flash coreboot internally, two of them are of interest.
**First** is the fact the `SMM_BWP` and `BLE` are not enabled in BIOS
versions released before 2014. We have tested many versions on T430 and
X230 and found out that `SMM_BWP=1` only since the update, the changelog
of which contains following line:
> (New) Improved the UEFI BIOS security feature.
**Second** is [S3 Boot Script vulnerability](https://support.lenovo.com/eg/ru/product_security/s3_boot_protect),
that was discovered and fixed later.
## Requirements
- USB drive (in case you need to downgrade BIOS)
- Linux install that (can be) loaded in UEFI mode
- [CHIPSEC](https://github.com/chipsec/chipsec)
## BIOS versions
Below is a table of BIOS versions that are vulnerable enough for our
goals, per model. The version number means that you need to downgrade to
that or earlier version.
```eval_rst
+------------+--------------+
| Model | BIOS version |
+============+==============+
| X230 | 2.60 |
+------------+--------------+
| X230T | 2.58 |
+------------+--------------+
| T430 | 2.64 |
+------------+--------------+
| T430s | 2.59 |
+------------+--------------+
| T530 | 2.60 |
+------------+--------------+
| W530 | 2.58 |
+------------+--------------+
```
If your BIOS version is equal or lower, skip to the
**[Examining protections](#examining-protections-theory)** section. If not,
go through the downgrade process, described next.
## Downgrading BIOS
Go to the Lenovo web site and download BIOS Update Bootable CD for your
machine of needed version (see above).
Lenovo states that BIOS has "security rollback prevention", meaning once
you update it to some version X, you will not be able to downgrade it to
pre-X version. That's not true. It seems that this is completely
client-side restriction in flashing utilities (both Windows utility and
Bootable CD). You just need to call `winflash.exe` or `dosflash.exe`
directly. Therefore you need to modify the bootable CD image you just
downloaded.
Extract an El Torito image:
geteltorito -o ./bios.img g1uj41us.iso
Mount the partition in that image:
sudo mount -t vfat ./bios.img /mnt -o loop,offset=16384
List files, find the `AUTOEXEC.BAT` file and the `FLASH` directory:
ls /mnt
ls /mnt/FLASH
Inside the `FLASH` directory, there should be a directory called
`G1ET93WW` or similar (exact name depends on your ThinkPad model and
BIOS version). See what's inside:
ls /mnt/FLASH/G1ET93WW
There must be a file with `.FL1` extension called `$01D2000.FL1` or
something similar.
Now open the `AUTOEXEC.BAT` file:
sudo vim /mnt/AUTOEXEC.BAT
You will see a list of commands:
@ECHO OFF
PROMPT $p$g
cd c:\flash
command.com
Replace the last line (`command.com`) with this (change path to the
`.FL1` file according to yours):
dosflash.exe /sd /file G1ET93WW\$01D2000.FL1
Save the file, then unmount the partition:
sudo unmount /mnt
Write this image to a USB drive (replace `/dev/sdX` with your USB drive
device name):
sudo dd if=./bios.img of=/dev/sdX bs=1M
Now reboot and press F1 to enter BIOS settings. Open the **Startup** tab
and set the startup mode to **Legacy** (or **Both**/**Legacy First**):
![](ivb_bios_legacy_only.jpg)
Press F10 to save changes and reboot.
Now, before you process, make sure that AC adapter is connected! If your
battery will die during the process, you'll likely need external
programmer to recover.
Boot from the USB drive (press F12 to select boot device), and BIOS
flashing process should begin:
![](ivb_bios_flashing1.jpg)
![](ivb_bios_flashing2.jpg)
It may reboot a couple of times in the process. Do not interrupt it.
When it's completed, go back to the BIOS settings and set startup mode
to **UEFI** (or **Both**/**UEFI First**). This is required for
vulnerability exploitation.
![](ivb_bios_uefi_only.jpg)
Then boot to your system and make sure that `/sys/firmware/efi` or
`/sys/firmware/efivars` exist.
## Examining protections (theory)
There are two main ways that Intel platform provides to protect BIOS
chip:
- **BIOS_CNTL** register of LPC Interface Bridge Registers (accessible
via PCI configuration space, offset 0xDC). It has:
* **SMM_BWP** (*SMM BIOS Write Protect*) bit. If set to 1, the BIOS is
writable only in SMM. Once set to 1, cannot be changed anymore.
* **BLE** (*BIOS Lock Enable*) bit. If set to 1, setting BIOSWE to 1
will raise SMI. Once set to 1, cannot be changed anymore.
* **BIOSWE** (*BIOS Write Enable*) bit. Controls whether BIOS is
writable. This bit is always R/W.
- SPI Protected Range Registers (**PR0**-**PR4**) of SPI Configuration
Registers (SPIBAR+0x74 - SPIBAR+0x84). Each register has bits that
define protected range, plus WP bit, that defines whether write
protection is enabled.
There's also **FLOCKDN** bit of HSFS register (SPIBAR+0x04) of SPI
Configuration Registers. When set to 1, PR0-PR4 registers cannot be
written. Once set to 1, cannot be changed anymore.
To be able to flash, we need `SMM_BWP=0`, `BIOSWE=1`, `BLE=0`, `FLOCKDN=0` or
SPI protected ranges (PRx) to have a WP bit set to 0.
Let's see what we have. Examine `HSFS` register:
sudo chipsec_main -m chipsec.modules.common.spi_lock
You should see that `FLOCKDN=1`:
[x][ =======================================================================
[x][ Module: SPI Flash Controller Configuration Locks
[x][ =======================================================================
[*] HSFS = 0xE009 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4)
[00] FDONE = 1 << Flash Cycle Done
[01] FCERR = 0 << Flash Cycle Error
[02] AEL = 0 << Access Error Log
[03] BERASE = 1 << Block/Sector Erase Size
[05] SCIP = 0 << SPI cycle in progress
[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status
[14] FDV = 1 << Flash Descriptor Valid
[15] FLOCKDN = 1 << Flash Configuration Lock-Down
Then check `BIOS_CNTL` and PR0-PR4:
sudo chipsec_main -m common.bios_wp
Good news: on old BIOS versions, `SMM_BWP=0` and `BLE=0`.
Bad news: there are 4 write protected SPI ranges:
[x][ =======================================================================
[x][ Module: BIOS Region Write Protection
[x][ =======================================================================
[*] BC = 0x 8 << BIOS Control (b:d.f 00:31.0 + 0xDC)
[00] BIOSWE = 0 << BIOS Write Enable
[01] BLE = 0 << BIOS Lock Enable
[02] SRC = 2 << SPI Read Configuration
[04] TSS = 0 << Top Swap Status
[05] SMM_BWP = 0 << SMM BIOS Write Protection
[-] BIOS region write protection is disabled!
[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF
SPI Protected Ranges
------------------------------------------------------------
PRx (offset) | Value | Base | Limit | WP? | RP?
------------------------------------------------------------
PR0 (74) | 00000000 | 00000000 | 00000000 | 0 | 0
PR1 (78) | 8BFF0B40 | 00B40000 | 00BFFFFF | 1 | 0
PR2 (7C) | 8B100B10 | 00B10000 | 00B10FFF | 1 | 0
PR3 (80) | 8ADE0AD0 | 00AD0000 | 00ADEFFF | 1 | 0
PR4 (84) | 8AAF0800 | 00800000 | 00AAFFFF | 1 | 0
Other way to examine SPI configuration registers is to just dump SPIBAR:
sudo chipsec_util mmio dump SPIBAR
You will see `SPIBAR` address (0xFED1F800) and registers (for example,
`00000004` is `HSFS`):
[mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]:
+00000000: 0BFF0500
+00000004: 0004E009
...
As you can see, the only thing we need is to unset WP bit on PR0-PR4.
But that cannot be done once `FLOCKDN` is set to 1.
Now the fun part!
`FLOCKDN` may only be cleared by a hardware reset, which includes S3
state. On S3 resume boot path, the chipset configuration has to be
restored and it's done by executing so-called S3 Boot Scripts. You can
dump these scripts by executing:
sudo chipsec_util uefi s3bootscript
There are many entries. Along them, you can find instructions to write
to `HSFS` (remember, we know that `SPIBAR` is 0xFED1F800):
Entry at offset 0x2B8F (len = 0x17, header len = 0x0):
Data:
02 00 17 02 00 00 00 01 00 00 00 04 f8 d1 fe 00 |
00 00 00 09 e0 04 00 |
Decoded:
Opcode : S3_BOOTSCRIPT_MEM_WRITE (0x0002)
Width : 0x02 (4 bytes)
Address: 0xFED1F804
Count : 0x1
Values : 0x0004E009
These scripts are stored in memory. The vulnerability is that we can
overwrite this memory, change these instructions and they will be
executed on S3 resume. Once we patch that instruction to not set `FLOCKDN`
bit, we will be able to write to PR0-PR4 registers.
## Creating a backup
Before you proceed, please create a backup of the `bios` region. Then,
in case something goes wrong, you'll be able to flash it back externally.
The `me` region is locked, so an attempt to create a full dump will fail.
But you can back up the `bios`:
sudo flashrom -p internal -r bios_backup.rom --ifd -i bios
If you will ever need to flash it back, use `--ifd -i bios` as well:
sudo flashrom -p <YOUR_PROGRAMMER> -w bios_backup.rom --ifd -i bios
**Caution:** if you will omit `--ifd -i bios` for flashing, you will
brick your machine, because your backup has `FF`s in place of `fd` and
`me` regions. Flash only `bios` region!
## Removing protections (practice)
The original boot script writes 0xE009 to `HSFS`. `FLOCKDN` is 15th bit, so
let's write 0x6009 instead:
sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2
You will get a lot of output and in the end you should see something
like this:
[*] Modifying S3 boot script entry at address 0x00000000DAF49B8F..
[mem] 0x00000000DAF49B8F
[*] Original entry:
2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 |
0 0 0 9 e0 4 0 |
[mem] buffer len = 0x17 to PA = 0x00000000DAF49B8F
2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 |
0 0 0 9 60 0 0 | `
[mem] 0x00000000DAF49B8F
[*] Modified entry:
2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 |
0 0 0 9 60 0 0 | `
[*] After sleep/resume, check the value of register 0xFED1F804 is 0x6009
[+] PASSED: The script has been modified. Go to sleep..
Now go to S3, then resume and check `FLOCKDN`. It should be 0:
sudo chipsec_main -m chipsec.modules.common.spi_lock
...
[x][ =======================================================================
[x][ Module: SPI Flash Controller Configuration Locks
[x][ =======================================================================
[*] HSFS = 0x6008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4)
[00] FDONE = 0 << Flash Cycle Done
[01] FCERR = 0 << Flash Cycle Error
[02] AEL = 0 << Access Error Log
[03] BERASE = 1 << Block/Sector Erase Size
[05] SCIP = 0 << SPI cycle in progress
[13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status
[14] FDV = 1 << Flash Descriptor Valid
[15] FLOCKDN = 0 << Flash Configuration Lock-Down
[-] SPI Flash Controller configuration is not locked
[-] FAILED: SPI Flash Controller not locked correctly.
...
Remove WP from protected ranges:
sudo chipsec_util mmio write SPIBAR 0x74 0x4 0xAAF0800
sudo chipsec_util mmio write SPIBAR 0x78 0x4 0xADE0AD0
sudo chipsec_util mmio write SPIBAR 0x7C 0x4 0xB100B10
sudo chipsec_util mmio write SPIBAR 0x80 0x4 0xBFF0B40
Verify that it worked:
sudo chipsec_main -m common.bios_wp
[x][ =======================================================================
[x][ Module: BIOS Region Write Protection
[x][ =======================================================================
[*] BC = 0x 9 << BIOS Control (b:d.f 00:31.0 + 0xDC)
[00] BIOSWE = 1 << BIOS Write Enable
[01] BLE = 0 << BIOS Lock Enable
[02] SRC = 2 << SPI Read Configuration
[04] TSS = 0 << Top Swap Status
[05] SMM_BWP = 0 << SMM BIOS Write Protection
[-] BIOS region write protection is disabled!
[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF
SPI Protected Ranges
------------------------------------------------------------
PRx (offset) | Value | Base | Limit | WP? | RP?
------------------------------------------------------------
PR0 (74) | 0AAF0800 | 00800000 | 00AAF000 | 0 | 0
PR1 (78) | 0ADE0AD0 | 00AD0000 | 00ADE000 | 0 | 0
PR2 (7C) | 0B100B10 | 00B10000 | 00B10000 | 0 | 0
PR3 (80) | 0BFF0B40 | 00B40000 | 00BFF000 | 0 | 0
PR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0
Bingo!
Now you can [flash internally](/flash_tutorial/int_flashrom.md).
Remember to flash only the `bios` region (use `--ifd -i bios -N`
flashrom arguments). `fd` and `me` are still locked.
Note that you should have an external SPI programmer as a backup method.
It will help you recover if you flash non-working ROM by mistake.

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@@ -1,3 +1,4 @@
# System76 Lemur Pro (lemp9)
## Specs

1
Documentation/soc/amd/family15h.md
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@@ -47,3 +47,4 @@ structure.
3. [Models 30h-3Fh BKDG](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
4. [Models 60h-6Fh BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf)
5. [Models 70h-7Fh BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf)
6. [PSP Integration](psp_integration.md)

131
Documentation/soc/amd/family17h.md
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@@ -14,13 +14,12 @@ Family 17h products are x86-based designs. This documentation assumes
familiarity with x86, its reset state and its early initialization
requirements.
To the extent necessary, the role of the Platform Security Processor
(a.k.a. PSP) in system initialization is addressed here. AMD has
historically required an NDA for access to the PSP
specification<sup>1</sup>. coreboot relies on util/amdfwtool to build
the structures and add various other firmware to the final image. The
Family 17h PSP design guide adds a new BIOS Directory Table, similar to
the PSP Directory Table.
To the extent necessary, the role of the AMD Secure Processor (a.k.a.
Platform Security Processor or PSP) in system initialization is addressed
here. The PSP specification<sup>1</sup> is available only with an NDA.
coreboot relies on util/amdfwtool to build the structures and add various
other firmware to the final image<sup>2</sup>. The Family 17h PSP design
guide adds a new BIOS Directory Table, similar to the PSP Directory Table.
Support in coreboot for modern AMD products is based on AMD’s
reference code: AMD Generic Encapsulated Software Architecture
@@ -29,12 +28,12 @@ configuring proprietary core logic, assistance with generating ACPI
tables, and other features.
AGESA for products earlier than Family 17h is known as v5 or
Arch2008<sup>2</sup>. Also note that coreboot currently contains both
Arch2008<sup>3</sup>. Also note that coreboot currently contains both
open source AGESA and closed source implementations (binaryPI) compiled
from AGESA.
The first AMD Family 17h device ported to coreboot is codenamed
“Picasso”<sup>3</sup>, and will be added to soc/amd/picasso.
“Picasso”<sup>4</sup>, and will be added to soc/amd/picasso.
## Additional Definitions
@@ -51,8 +50,13 @@ related firmware images
* Embedded Firmware Structure - Signature and pointers used by the
PSP to locate the PSP Directory Table and BIOS Directory Table; these
items are generated during coreboot build and are located in the SPI ROM
* Verstage - The code to verify the firmware contained in the
writable section of the SPI ROM
* vboot - The generic technology name for verifying/choosing a RW A/B
or fallback RO path.
* verstage - The code (vboot) to verify the firmware contained in the
writable section of the SPI ROM, traditionally run on the x86 processor,
and in some cases a separate stage added to coreboot
* vboot app - A portion of vboot technology designed and compiled
to run on the PSP
* APCB - AMD PSP Customization Block - A binary containing PSP and
system configuration preferences (analogous to v5 BUILDOPT_ options),
and generated by APCBTool to be added to coreboot/utils later
@@ -90,7 +94,8 @@ dependency expressions, much functionality is rewritten as libraries,
etc. It would, in no way, fit into the v5 model used in coreboot.
* For the foreseeable future, AGESA source will distributed only
under NDA.
under NDA. Furthermore, because AGESA's integrated debug services divulge
NDA information, no debug builds will be released to the general public.
## Basic Pre-x86 Boot Flow
@@ -102,15 +107,15 @@ The following steps occur prior to x86 processor operation.
the SPI ROM
* PSP verifies and executes the PSP off-chip bootloader
* ChromeOS systems:
* Off-chip bootloader attempts to locate verstage via the RO BIOS
* Off-chip bootloader attempts to locate vboot app via the RO BIOS
Directory Table
* If verstage is not found, booting continues with ABLs below
* Verstage initializes, setting up GPIOs, UART if needed,
* If vboot app is not found, booting continues with ABLs below
* vboot app initializes, setting up GPIOs, UART if needed,
communication path to the EC, and the SPI controller for direct access
to the flash device.
* Verstage verifies the RW sections (as is typically performed by
* vboot app verifies the RW sections (as is typically performed by
the main processor)
* Verstage locates the Embedded Firmware Directory within the
* vboot app locates the Embedded Firmware Directory within the
verified FMAP section and passes a pointer to the PSP bootloader. If
the verification fails, it passes a pointer to the RO header to the
bootloader.
@@ -166,59 +171,79 @@ jump to protected mode must jump to the physical address in DRAM. Any
code that is position-dependent must be linked to run at the final
destination.
## Initial coreboot Implementation
## Implementation for coreboot
Supporting Picasso doesn’t fit well with many of the coreboot
assumptions. Initial porting shall attempt to fit within existing
coreboot paradigms and make minimal changes to common code.
Supporting Picasso doesn’t fit perfectly with many of the coreboot
assumptions about x86 processors. Changes are introduced primarily
into arch/x86 to accommodate a processor starting in DRAM and at a
nontraditional reset vector.
### CAR and bootblock
### CAR and early stages
The coreboot bootblock contains features Picasso doesn’t require or
can’t use, and is assumed to execute in an unusable location.
Picasso’s requirement for bootblock in coreboot will be eliminated.
The traditional coreboot bootblock and romstage rely on cache-as-RAM
and a linker script that positions temporary storage accordingly. A
substitute for the DCACHE variables, called EARLYRAM, is introduced.
Like DCACHE, this allows for a consistent mapping of early regions
required across multiple stages prior to cbmem coming online.
Examples are the _preram_cbmem_console and _timestamp.
### Hybrid romstage
Due to Picasso's unique nature of starting with DRAM already available,
no early stages run as execute-in-place (XIP). All post-bootblock
stages are copied from the BIOS flash into DRAM for faster
performance, and these regions are marked reserved later in POST.
Picasso’s x86 reset state doesn’t meet the coreboot expectations
for jumping directly to ramstage. The primary feature of romstage is
also not needed, however there are other important features that are
typically in romstage that Picasso does need.
Unlike CAR-based systems, and because Picasso does not run early
stages as XIP, its early stages are not constrained in their use
of .bss or .data sections. All stages' .bss is zeroed, and all
.data sections are fully R/W at load time.
The romstage architecture is designed around the presence of CAR.
Several features implement ROMSTAGE_CBMEM_INIT_HOOK, expecting to move
data from CAR to cbmem. The hybrid romstage consumes DRAM for the
purpose of implementing the expected CAR storage. This region as well
as the DRAM where romstage is decompressed must be reserved and
unavailable to the OS.
### bootblock
The initial Picasso port implements a hybrid romstage that contains the
first instruction fetched at the reset vector. It minimally configures
flat protected mode, initializes cbmem, then loads the next stage.
Future work will consider breaking the dependencies mentioned above
and/or potentially loading ramstage directly from the PSP.
Picasso uses a bootblock that mirrors a traditional bootblock as much
as possible. Because the image is loaded by the PSP, the bootblock is
not restricted to the top of the BIOS flash device. The compressed
image is added into the PSP's `amdfw.rom` build.
### vboot app and verstage
Development is currently underway for the vboot app, and potentially
an x86-based verstage companion. This document shall be updated once
the design is finalized and functioning. Support for the PSP honoring
the presence of the vboot app is available only in certain SKUs.
### romstage and postcar
A traditional romstage is maintained for Picasso. The primary reason for
this choice is to remain compatible with coreboot conventions and
to support the FSP 2.0 driver. Picasso's romstage uses an
fsp_memory_init() call to glean the memory map from AGESA. (See below.)
fsp_memory_init() brings cbmem online before returning to the caller.
No postcar stage is required or supported.
## AGESA v9 on Picasso
Due to the current inability to publish AGESA source, a pre-built
binary solution remains a requirement. The rewrite from v5 to v9 for
direct inclusion into UEFI source makes modifying it for conforming to
the existing v5 interface impractical.
Due to the current restriction on publishing AGESA source, a pre-built
binary solution remains a requirement. Modifying v9 to conform to the
existing v5 binaryPI interface was considered impractical.
Given the UEFI nature of modern AGESA, and the existing open source
work from Intel, Picasso shall support AGESA via an FSP-like prebuilt
image. The Intel Firmware Support Package<sup>4</sup> combines
image. The Intel Firmware Support Package<sup>5</sup> combines
reference code with EDK II source to create a modular image with
discoverable entry points. coreboot source already contains knowledge
of FSP, how to parse it, integrate it, and how to communicate with it.
Picasso's FSP is compatible with rev. 2.0 of the External Architecture
Specification. Deviations, e.g., no FSP-T support, shall be published
in an Integration Guide.
## Footnotes
1. “AMD Platform Security Processor BIOS Architecture Design Guide
for AMD Family 17h Processors” (PID #55758) and “AMD Platform
Security Processor BIOS Architecture Design Guide” (PID #54267) for
1. *AMD Platform Security Processor BIOS Architecture Design Guide
for AMD Family 17h Processors* (PID #55758) and *AMD Platform
Security Processor BIOS Architecture Design Guide* (PID #54267) for
earlier products
2. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf)
3. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso)
4. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html)
2. [PSP Integration](psp_integration.md)
3. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf)
4. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso)
5. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html)

1
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@@ -6,6 +6,7 @@ This section contains documentation about coreboot on specific AMD SOCs.
- [Family 15h](family15h.md)
- [Family 17h](family17h.md)
- [Platform Security Processor Integration](psp_integration.md)
## amd_blobs Repository License

376
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View File

@@ -0,0 +1,376 @@
# AMD Platform Security Processor (PSP) Firmware Integration Guide
The following content defines the structures of PSP tables and describes the
firmware images integrated into a functioning system. Further details of
each Platform Security Processor (PSP) firmware blob or PSP feature are
beyond the scope of this document, and may be found in AMD NDA publications.
The current name for the security technology is "AMD Secure Processor".
To be consistent with the latest documentation, and because of familiarity
with the older name, this document continues with "Platform Security Processor"
and "PSP".
## Platform Security Processor (PSP) Overview
The Platform Security Processor (PSP) is an on-die, isolated security processor
that runs independently from the main x86 cores of the platform.
Security-sensitive components run on the PSP without being affected by the
commodity or untrusted software running on the x86 cores. The PSP executes
its own firmware and shares the SPI flash storage that is used by the
system BIOS.
## Embedded Firmware Structure
The PSP identifies its important tables by first locating the Embedded Firmware
Structure. It reads specific addresses in the SPI flash, from top to bottom,
attempting to identify the signature. The locations (for clarity, the x86
physical addresses) checked are:
* 0xfffa0000
* 0xfff20000
* 0xffe20000
* 0xffc20000
* 0xff820000
* 0xff020000
Most coreboot implementations provide flexibility to position the structure in
any of the eligible locations. Below are typical definitions within the
structure (for all families combined). Individual features supported vary by
family and model.
+--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+
| Signature | 0x00 | 4 | 0x55aa55aa |
|--------------|---------------|------------------|----------------------------|
| IMC FW | 0x04 | 4 | Integrated Micro |
| | | | Controller: unsupported |
| | | | but functional in some |
| | | | systems |
|--------------|---------------|------------------|----------------------------|
| GbE FW | 0x08 | 4 | Gigabit Ethernet |
|--------------|---------------|------------------|----------------------------|
| xHCI FW | 0x0c | 4 | xHCI firmware |
|--------------|---------------|------------------|----------------------------|
| PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory |
| | | | Table (early devices) |
|--------------|---------------|------------------|----------------------------|
| PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory |
| | | | Table (later devices and |
| | | | is combo capable) |
|--------------|---------------|------------------|----------------------------|
| BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory |
| | | | Table for models n* |
|--------------|---------------|------------------|----------------------------|
| BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory |
| | | | Table for models nn |
|--------------|---------------|------------------|----------------------------|
| BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory |
| | | | Table for models nnn |
|--------------|---------------|------------------|----------------------------|
| … | | | ... |
+--------------+---------------+------------------+----------------------------+
* The Embedded Firmware Structure may support pointers to multiple generations
of devices, e.g. Family 17h Models 00h-0Fh, Family 17h Models 10h-1Fh, etc.
Details are specific to the implementation.
## PSP Directory Table
The PSP Directory Table allows the PSP to find and load various images. A
second level table may be generated to allow updates without the risk of
corrupting the primary table. Certain models support a combo type table,
allowing secondary tables to be referenced by device ID. No coreboot
implementations currently use combo tables.
### PSP Directory Table Header
+--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+
| PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to |
| | | | recognize the header. |
| | | | Cookie “$PL2” for level 2 |
|--------------|---------------|------------------|----------------------------|
| Checksum | 0x04 | 4 | 32-bit CRC value of header |
| | | | below this field and |
| | | | including all entries |
|--------------|---------------|------------------|----------------------------|
| Total Entries| 0x08 | 4 | Number of PSP Directory |
| | | | entries in the table |
|--------------|---------------|------------------|----------------------------|
| Reserved | 0x0C | 4 | Reserved - Set to zero |
+--------------+---------------+------------------+----------------------------+
### PSP Directory Table Entries
+--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+
| Type | 0x00 | 8 | Entry type (see below) |
|--------------|---------------|------------------|----------------------------|
| Sub Program | 0x01 | 8 | Specifies sub program |
|--------------|---------------|------------------|----------------------------|
| Reserved | 0x02 | 16 | Reserved - set to 0 |
|--------------|---------------|------------------|----------------------------|
| Size | 0x04 | 32 | Size of PSP entry in bytes |
|--------------|---------------|------------------|----------------------------|
| Location / | 0x08 | 64 | Location: Physical Address |
| Value | | | of SPIROM location where |
| | | | corresponding PSP entry |
| | | | located. |
| | | | |
| | | | Value: 64-bit value for the|
| | | | PSP Entry |
+--------------+---------------+------------------+----------------------------+
### PSP Directory Table Types
**0x00**: AMD public key
* Public key used by on-chip bootcode to verify the signature of PSP boot
loader firmware.
**0x01**: PSP boot loader firmware
* Second stage boot loader firmware to be loaded by on-chip bootcode.
**0x02**: PSP SecureOS firmware
* Off-chip PSP boot loader will be overwritten in SRAM by the Secure/Trusted
OS during initial boot up.
* PSP SecureOS performs:
* Initialization of OS internal structures and instantiates the fTPM as a
trusted application
* Sets up CPU/BIOS-PSP interface registers
* Enters steady state idling and waiting for commands
* In steady state, on notification, prepares for S3 state
* Verify and loading GFX Firmware
**0x03**: PSP recovery boot loader firmware
* Recovery PSP boot loader image, loaded by on-chip bootcode in case of
failure in loading PSP boot loader.
**0x08**: SMU off-chip firmware
**0x12**: SMU off-chip firmware section 2
* Power Management firmware, responsible for system power/clock management.
**0x09**: Secure Debug unlock public key
* Public key token used during Secure Debug unlock process to verify message
payload from AMD server.
**0x0b**: Soft fuse chain
* Refer to documentation for definitions. (See External References below.)
**0x0c**: PSP trustlet binaries
* Optional file to enable fTPM.
**0x13**: PSP Secure Debug unlock debug image
* Secure Debug unlock firmware image, used to unlock the device.
**0x21**: Wrapped iKEK
* Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
This is mandatory in order to support encrypted firmware.
**0x24**: Security policy binary
* A security policy is applied to restrict the untrusted access to security
sensitive regions.
**0x25**: MP2 firmware
* The MP2 of the SMU, also known as the Sensor Fusion Integration is used to
aggregate the data from various sensors such as accelerometer, gyrometer,
ambient light sensor, orientation sensor, etc. This is off-chip firmware
for Sensor Fusion Processor (SFP) subsystem of the SMU.
**0x28**: System driver
* Driver executing on top of SecureOS.
**0x30 - 0x37**: PSP AGESA binaries
* AGESA Boot Loaders (ABLs) are a set of binary images executed by the PSP.
They are responsible for initializing APU silicon components (including but
not limited to APU memory interface) on S5, S4 and S3, prior to releasing
the main cores from reset.
**0x3a**: Whitelist
* Optional image containing a signed whitelist of one or more serial numbers.
**0x40**: Pointer to secondary table
* Pointer to PSP Directory Table level 2.
**0x52**: PSP boot loader usermode OEM application
* Supported only in certain SKUs.
**0x22**: PSP Token Unlock data
* Used to support time-bound Secure Debug unlock during boot. This entry may
be omitted if the Token Unlock debug feature is not required.
### Firmware Version of Binaries
Every firmware binary contains 256 bytes of a PSP Header, which includes
the firmware version. The version is made up of the four bytes located at
offset 0x60 in the binary image.
For example, in the PSP BootLoader:
0000000: 0000 0000 0000 0000 0000 0000 0000 0000 ................
0000010: 2450 5331 c0e1 0000 0100 0000 0000 0000 $PS1............
0000020: 5c0a ddb8 b279 4846 e154 aa4c ed7d 414d \....yHF.T.L.}AM
0000030: 0100 0000 0000 0000 60bb a67e 1a43 4c6b ........`..~.CLk
0000040: 9807 bc8d fdb4 1f40 0000 0000 0000 0000 .......@........
0000050: 0000 0000 0000 0000 0000 0000 0000 0000 ................
0000060: 7401 0800 ffff ffff 0001 0000 c0e3 0000 t...............
0000070: 0000 0000 0000 0000 0000 0000 0100 0000 ................
0000080: 4766 9186 9d5f e909 492d 491d d9ee 8e6c Gf..._..I-I....l
0000090: 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000a0: 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000b0: 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000c0: 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000d0: 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000e0: 0000 0000 0000 0000 0000 0000 0000 0000 ................
00000f0: 0000 0000 0000 0000 0000 0000 0000 0000 ................
The PSP BootLoader version is 00.08.01.74.
Note that only Firmware binary images have versions. Key tokens are not
versioned, as there will not be multiple keys. Keys are unique to processor
family.
### BIOS Directory Table Entry Types
All x86 accessible components (both executable and data blobs) are found via
the BIOS Directory Table. A second level table may be generated to allow for
updates without the risk of corrupting the primary table.
The BIOS Directory table structure is slightly different from the PSP Directory:
* Multiple instances of firmware components are allowed for one specific type
* The type field is further structured to reflect attributes of BIOS
components such as "Region Type", "Reset Image", "Copy Image", "Read Only",
allowing design flexibility
* The "Destination Address" field is added for specific entries that are
expected to be copied from boot media to specific memory location
### BIOS Directory Table Header
+--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+
| BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to |
| | | | recognize the header. |
| | | | Cookie “$BL2” for level 2 |
|--------------|---------------|------------------|----------------------------|
| Checksum | 0x04 | 4 | 32 bit CRC value of header |
| | | | below this field and |
| | | | including all entries |
|--------------|---------------|------------------|----------------------------|
| Total Entries| 0x08 | 4 | Number of BIOS Directory |
| | | | entries in the table |
|--------------|---------------|------------------|----------------------------|
| Reserved | 0x0C | 4 | Reserved - Set to zero |
+--------------+---------------+------------------+----------------------------+
### BIOS Directory Table Entries
+--------------+---------------+------------------+----------------------------+
| Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose |
+--------------+---------------+------------------+----------------------------+
| Type | 0x00 | 8 | Entry type (see below) |
|--------------|---------------|------------------|----------------------------|
| Region Type | 0x01 | 8 | Setup the memory region's |
| | | | security attribute for the |
| | | | BIOS entry |
|--------------|---------------|------------------|----------------------------|
| Reset Image | 0x02[0] | 1 | Boolean value to define the|
| | | | BIOS entry is a reset |
| | | | binary image |
|--------------|---------------|------------------|----------------------------|
| Copy Image | 0x02[1] | 1 | Define the binary image of |
| | | | the BIOS entry is for |
| | | | copying over to the memory |
| | | | region |
|--------------|---------------|------------------|----------------------------|
| Read Only | 0x02[2] | 1 | Setup the memory region for|
| | | | the BIOS entry to read only|
|--------------|---------------|------------------|----------------------------|
| Compressed | 0x02[3] | 1 | Compressed using zlib |
| | | | |
|--------------|---------------|------------------|----------------------------|
| Instance | 0x02[7:4] | 4 | Specify the Instance of an |
| | | | entry |
|--------------|---------------|------------------|----------------------------|
| SubProgram | 0x03[2:0] | 3 | Specify the SubProgram |
|--------------|---------------|------------------|----------------------------|
| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero |
|--------------|---------------|------------------|----------------------------|
| Size | 0x04 | 32 | Memory Region Size |
|--------------|---------------|------------------|----------------------------|
| Source | 0x08 | 64 | Physical Address of SPIROM |
| Address | | | location where the data for|
| | | | the corresponding entry is |
| | | | located |
|--------------|---------------|------------------|----------------------------|
| Destination | 0x10 | 64 | Destination Address of |
| Address | | | memory location where the |
| | | | data for the corresponding |
| | | | BIOS Entry is copied |
+--------------+---------------+------------------+----------------------------+
### BIOS Directory Table Entry Types
**0x60**: APCB data
* Source field points to the AGESA PSP Customization Block (APCB) data.
**0x68**: Backup copy of APCB data
* Source field points to the backup copy of the AGESA PSP Customization Block
(APCB) data.
**0x61**: APOB data
* Location field points to the AGESA PSP Output Block (APOB) data.
**0x62**: BIOS reset image
* Source field points to BIOS binary image in flash. Destination points to
DRAM.
**0x63**: APOB data NV
* Source field points to the AGESA PSP Output Block (APOB) data NV copy.
This data is written by coreboot and replayed by PSP ABLs during S3 resume
and in certain S5 boots.
**0x64**: PMU firmware (instruction)
* Source field points to the instruction portion of Phy Microcontroller Unit
firmware.
**0x65**: PMU firmware (data)
* Source field points to the data portion of Phy Microcontroller Unit
firmware.
**0x66**: x86 microcode patch
* Source field points to the microcode patch.
**0x6a**: MP2 FW config file
* Source field points to the MP2 FW configuration file.
**0x70**: Pointer to secondary table
* Pointer to BIOS Directory Table level 2.
## Tools
### amdcompress
`cbfstool/amdcompress` is a helper for creating the BIOS Reset Image (BIOS
Directory Table type 0x62). This is the code the PSP uncompresses into DRAM
at the location where the x86 begins execution when released from reset.
Typical usage is for amdcompress to convert an ELF file’s program section
into a zlib compressed image.
### amdfwtool
All images requiring PSP functionality rely on the amdfwtool utility.
amdfwtool takes image names as command-line arguments, as well as the size of
the flash device, and intended location of the Embedded Firmware Structure.
Its output is a monolithic image with correctly positioned headers, pointers,
structures, and the firmware images added. The file, typically named
`amdfw.rom`, may then be added directly into the coreboot image.
## External Reference
* NDA document #55758: *AMD Platform Security Processor BIOS Architecture
Design Guide for AMD Family 17h Processors*
* NDA document #54267 *AMD Platform Security Processor BIOS Architecture
Design Guide*: For all devices earlier than Family 17h

47
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@@ -1,14 +1,18 @@
Tutorial, part 1: Starting from scratch
===========================================
From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for
a very basic build:
This tutorial will guide you through the process of setting up a working
coreboot toolchain. In same cases you will find specific instructions for Debian (apt-get),
Fedora (dnf) and Arch Linux (pacman) based package management systems. Use the
instructions according to your system.
Download, configure, and build coreboot
---------------------------------------
### Step 1 - Install tools and libraries needed for coreboot
$ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev
$ sudo pacman -S base-devel curl git gcc-ada ncurses zlib
$ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel
### Step 2 - Download coreboot source tree
$ git clone https://review.coreboot.org/coreboot
@@ -78,6 +82,8 @@ Test the image using QEMU
### Step 7 - Install QEMU
$ sudo apt-get install -y qemu
$ sudo pacman -S qemu
$ sudo dnf install qemu
### Step 8 - Run QEMU
Start QEMU, and point it to the ROM you just built:
@@ -91,20 +97,24 @@ Summary
-------
### Step 1 summary - Install tools and libraries needed for coreboot
You installed the minimum additional requirements for ubuntu to download and
build coreboot. Ubuntu already has most of the other tools that would be
required installed by default.
Depending on your distribution you have installed the minimum additional
software requirements to continue with downloading and building coreboot.
Not every distribution has the tools, that would be required,
installed by default. In the following we shortly introduce the purpose of the
installed packages:
* `build-essential` is the basic tools for doing builds. It comes pre-installed
on some Ubuntu flavors, and not on others.
* `build-essential` or `base-devel` are the basic tools for building software.
* `git` is needed to download coreboot from the coreboot git repository.
* `libncurses5-dev` is needed to build the menu for 'make menuconfig'
* `libncurses5-dev` or `ncurses` is needed to build the menu for 'make menuconfig'
* `m4, bison, curl, flex, zlib1g-dev, gcc, gnat` and `g++` or `clang`
are needed to build the coreboot toolchain. `gcc` and `gnat` have to be
of the same version.
If you started with a different distribution, you might need to install many
other items which vary by distribution.
If you started with a different distribution or package management system you
might need to install other packages. Most likely they are named sightly
different. If that is the case for you, we'd like to encourage you to contribute
to the project and submit a pull request with an update for this documentation
for your system.
### Step 2 summary - Download coreboot source tree
This will download a 'read-only' copy of the coreboot tree. This just means
@@ -124,12 +134,12 @@ system during the build process.
### Step 4 summary - Build the payload
To actually do anything useful with coreboot, you need to build a payload to
include in the rom. The idea behind coreboot is that it does the minimum amount
include into the rom. The idea behind coreboot is that it does the minimum amount
possible before passing control of the machine to a payload. There are various
payloads such as grub or SeaBIOS that are typically used to boot the operating
system. Instead, we used coreinfo, a small demonstration payload that allows the
user to look at various things such as memory and the contents of coreboot's
cbfs - the pieces that make up the coreboot rom.
user to look at various things such as memory and the contents of the coreboot
file system (CBFS) - the pieces that make up the coreboot rom.
### Step 5 summary - Configure the build
This step configures coreboot's build options using the menuconfig interface to
@@ -154,16 +164,17 @@ build directory as 'coreboot.rom'. At the end of the build process, the build
displayed the contents of the rom file.
### Step 7 summary - Install QEMU
QEMU is a processor emulator which we can use to show coreboot
QEMU is a processor emulator which we can use to show the coreboot boot
process in a virtualised environment.
### Step 8 summary - Run QEMU
Here's the command line broken down:
Here's the command line instruction broken down:
* `qemu-system-x86_64`
This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
ISA bridge.
* `-bios build/coreboot.rom`
Use the bios rom image that we just built. If this is left off, the standard
SeaBIOS image that comes with QEMU is used.
Use the bios rom image that we just built. If this flag is left out, the
standard SeaBIOS image that comes with QEMU is used.
* `-serial stdio`
Send the serial output to the console. This allows you to view the coreboot
debug output.
boot log.

119
Documentation/vendorcode/eltan/security.md
View File

@@ -1,38 +1,111 @@
# Eltan Security
## Security
This code enables measured boot and verified boot support.
Verified boot is available in coreboot, but based on ChromeOS. This vendorcode
uses a small encryption library and leave much more space in flash for the
payload.
Verified boot is available in coreboot, but based on ChromeOS. This vendorcode security
solution is intended to be used for system without ChromeOS support.
This solution allows implementing verified boot support for systems that do not contain a TPM.
## Hashing Library
The library suppports SHA-1, SHA-256 and SHA-512. The required routines of
`3rdparty/vboot/firmware/2lib` are used.
The API functions of `3rdparty/vboot/firmware` are used.
## Measured boot
measured boot support will use TPM2 device if available. The items specified
in `mb_log_list[]` will be measured.
Measured boot support requires a TPM2 device.
The items specified in `mb_log_list[]` and `*_verify_list[]` will be measured.
The `mb_log_list[]` should only contain items that are not contained in one of the verify_lists
below (except for the `bootblock_verify_list[]`).
The list can contain the following items: `config`, `revision`, `cmos_layout.bin`.
`oemmanifest.bin` should be added to the list when Verified boot is enabled.
## Verified boot
verified boot support will use TPM2 device if available. The items specified
in the next table will be verified:
* `bootblock_verify_list[]`
* `verify_item_t romstage_verify_list[]`
* `ram_stage_additional_list[]`
* `ramstage_verify_list[]`
* `payload_verify_list[]`
* `oprom_verify_list[]`
Verified boot support will use the OEM manifest to verify the items.
The verification process is controlled using the following verify lists:
* `bootblock_verify_list[]` (will not be measured, verified in bootblock)
* `romstage_verify_list[]` (verified in early romstage)
* `postcar_verify_list[]` (verified in just before postcar loading)
* `ramstage_verify_list[]` (verified in just before ramstage loading)
* `payload_verify_list[]` (verified in just before payload loading)
* `oprom_verify_list[]` (verified before option rom execution)
A verify_list entry contains a `related_items` member. This can point to an additional `verify_list`
which will be verified before the specified item is verified. As an example the `grub` entry in
`payload_verify_list[]` can point to the `grub_additional_list[]` that contains the items used by
the grub payload and the `seabios` entry in `payload_verify_list[]` can point to the
`seabios_additional_list[]` that contains the items used by the seabios payload. By doing this the
entries that are verified (and measured) depend on the payload selected at runtime.
## Creating private and public keys
Create private key in RSA2048 format: `openssl genrsa -F4 -out <private_key_file> 2048`
Create public key using private key:
`futility --vb1 create <private_key_file> <public_key_file_without_extension>`
The public key will be included into coreboot and used for verified boot only.
## Enabling support
To enable measured boot support:
* Enabled *VENDORCODE_ELTAN_MBOOT*
* Create `mb_log_list` table with list of items to measure
* Measured boot can be enabled using **CONFIG_MBOOT**
* Create mb_log_list table with list of item to measure
* Create tables bootblock_verify_list[], verify_item_t romstage_verify_list[],
ram_stage_additional_list[], ramstage_verify_list[], payload_verify_list[],
oprom_verify_list[]
* Verified boot can be enabled using **CONFIG_VERIFIED_BOOT**
* Added Kconfig values for verbose console output
To enable verified boot support:
* Enable *VENDORCODE_ELTAN_VBOOT*
* Create the verify lists `*_verify_list[]`
* *VENDORCODE_ELTAN_VBOOT_KEY_FILE* must point to location of the public key file created with `futility`
## Creating signed binary
During build of coreboot binary an empty `oemmanifest.bin` is added to the binary.
This binary must be replaced by a correct (signed) binary when *VENDORCODE_ELTAN_VBOOT* is enabled
The `oemmanifest.bin` file contains the SHA-256 (or SHA-512) hashes of all the different parts
contained in verify_lists.
When *VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST* is enabled the manifest should be signed and the
signature should appended to the manifest.
Please make sure the public key is in the RO part of the coreboot image. The `oemmanifest.bin` file
should be in the RW part of the coreboot image.
### Hashing
The `oemmanifest.bin` file contains the hashes of different binaries parts of the binary e.g.:
bootblock, romstage, postcar, ramstage, fsp etc.
The total number of items must match `VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS`.
For every part the SHA (SHA-256) must be calculated. First extract the binary from the coreboot
image using: `cbfstool <coreboot_file_name> extract -n <cbfs_name> -f <item_binary_file_name>`
followed by: `openssl dgst -sha256 -binary -out <hash_file_name> <item_binary_file_name>`
Replace -sha256 with -sha512 when `VENDORCODE_ELTAN_VBOOT_USE_SHA512` is enabled.
All the hashes must be combined to a hash binary. The hashes need to be placed in the same order as
defined by the `HASH_IDX_XXX` values.
### Signing
The oemmanifest needs to be signed when `VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST` is enabled.
This can be done with the following command:
`openssl dgst -sign <private_key_file_name> -sha256 -out <signature_binary> <hash_binary>`
The signed manifest can be created by adding the signature to the manifest:
`cat <hash_binary> <signature_binary> >hash_table.bin`
## Create binary
The `oemmanifest.bin` file must be replaced in the coreboot binary by the generated
`hash_table.bin`.
To replace the binary: Remove using:
`cbfstool <coreboot_file_name> remove -n oemmanifest.bin`
Then add the new image using:
`cbfstool coreboot.bin add -f <hash_table_file_name> -n oemmanifest.bin -t raw \`
`-b <CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC>`
## Debugging

2
MAINTAINERS
View File

@@ -490,7 +490,7 @@ F: src/device/oprom/
CBFS
F: src/include/cbfs.h
F: src/include/cbfs_serialized.h
F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
F: util/cbfstool/
CBMEM

21
Makefile.inc
View File

@@ -159,7 +159,7 @@ ws_to_under=$(shell echo '$1' | tr ' \t' '_')
#######################################################################
# Helper functions for ramstage postprocess
spc :=
spc +=
spc := $(spc) $(spc)
comma := ,
# Returns all files and dirs below `dir` (recursively).
@@ -261,7 +261,16 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
# Redundant offset remarks are not useful in any way and are masking useful
# ones that might indicate an issue so it is better to hide them.
REDUNDANT_OFFSET_REMARK = 2158
# Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code.
# See cb:38803 & cb:38802
# "Multiple types (Device object requires either a _HID or _ADR, but not both)"
MULTIPLE_TYPES_WARNING = 3073
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y)
IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING)
else
IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK)
endif
define asl_template
$(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
@@ -307,15 +316,16 @@ cbfs-files-processor-vsa= \
# Reduce a .config file to its minimal representation
# arg1: input
# arg2: output
cbfs-files-processor-defconfig= \
define cbfs-files-processor-defconfig
$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
+printf " CREATE $(2) (from $(1))\n"; \
printf "\# This image was built using coreboot " > $(2).tmp && \
printf "# This image was built using coreboot " > $(2).tmp && \
grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
$(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \
cat $(2).tmp2 >> $(2).tmp && \
rm -f $(2).tmp2 && \
\mv -f $(2).tmp $(2))
endef
#######################################################################
# Compile a C file with a bare struct definition into binary
@@ -394,12 +404,12 @@ COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION))
COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION
endif
CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj)
CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -I$(obj)
VBOOT_SOURCE ?= 3rdparty/vboot
CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include
CPPFLAGS_common += -include $(src)/include/kconfig.h
CPPFLAGS_common += -include $(src)/include/rules.h
CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h
CPPFLAGS_common += -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h
CPPFLAGS_common += -I3rdparty
CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\"
@@ -414,7 +424,6 @@ CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla
CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie
ifeq ($(CONFIG_COMPILER_GCC),y)
CFLAGS_common += -fno-delete-null-pointer-checks
# Don't add these GCC specific flags when running scan-build
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
CFLAGS_common += -Wno-packed-not-aligned

4
configs/config.stm Normal file
View File

@@ -0,0 +1,4 @@
CONFIG_VENDOR_PURISM=y
CONFIG_BOARD_PURISM_LIBREM15_V4=y
CONFIG_STM=y
CONFIG_IED_REGION_SIZE=0

5
payloads/coreinfo/coreinfo.c
View File

@@ -290,8 +290,11 @@ static void loop(void)
}
}
int main(void)
int main(int argc, char **argv)
{
(void)argc;
(void)argv;
int j;
if (CONFIG(LP_USB))

2
payloads/libpayload/drivers/usb/xhci_devconf.c
View File

@@ -227,7 +227,7 @@ xhci_set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr)
}
dev->endpoints[0].maxpacketsize = usb_decode_mps0(speed, buf[7]);
if (dev->endpoints[0].maxpacketsize != 8) {
if (dev->endpoints[0].maxpacketsize != speed_to_default_mps(speed)) {
memset((void *)ic->dev.ep0, 0x00, ctxsize);
*ic->add = (1 << 1); /* EP0 Context */
EC_SET(MPS, ic->dev.ep0, dev->endpoints[0].maxpacketsize);

10
payloads/libpayload/include/endian.h
View File

@@ -86,28 +86,30 @@ static inline uint16_t be16dec(const void *pp)
{
uint8_t const *p = (uint8_t const *)pp;
return ((p[0] << 8) | p[1]);
return (uint16_t)((p[0] << 8) | p[1]);
}
static inline uint32_t be32dec(const void *pp)
{
uint8_t const *p = (uint8_t const *)pp;
return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]);
return (((uint32_t)p[0] << 24) | (uint32_t)(p[1] << 16) |
(uint32_t)(p[2] << 8) | p[3]);
}
static inline uint16_t le16dec(const void *pp)
{
uint8_t const *p = (uint8_t const *)pp;
return ((p[1] << 8) | p[0]);
return (uint16_t)((p[1] << 8) | p[0]);
}
static inline uint32_t le32dec(const void *pp)
{
uint8_t const *p = (uint8_t const *)pp;
return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]);
return ((uint32_t)(p[3] << 24) | (uint32_t)(p[2] << 16) |
(uint32_t)(p[1] << 8) | p[0]);
}
static inline void bebitenc(void *pp, uint32_t u, uint8_t b)

8
payloads/libpayload/include/pci.h
View File

@@ -91,11 +91,11 @@ typedef u32 pcidev_t;
#define HEADER_TYPE_CARDBUS 2
#define HEADER_TYPE_MULTIFUNCTION 0x80
#define PCI_ADDR(_bus, _dev, _fn, _reg) \
(0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8) | (_reg & ~3))
#define PCI_DEV(_bus, _dev, _fn) (0x80000000 | \
(uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8))
#define PCI_DEV(_bus, _dev, _fn) \
(0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8))
#define PCI_ADDR(_bus, _dev, _fn, _reg) \
(PCI_DEV(_bus, _dev, _fn) | (uint8_t)(_reg & ~3))
#define PCI_BUS(_d) ((_d >> 16) & 0xff)
#define PCI_SLOT(_d) ((_d >> 11) & 0x1f)

40
payloads/libpayload/libpci/libpci.c
View File

@@ -40,34 +40,34 @@ static pcidev_t libpci_to_lb(struct pci_dev *dev)
/* libpci interface */
u8 pci_read_byte(struct pci_dev *dev, int pos)
{
return pci_read_config8(libpci_to_lb(dev), pos);
return pci_read_config8(libpci_to_lb(dev), (uint16_t)pos);
}
u16 pci_read_word(struct pci_dev *dev, int pos)
{
return pci_read_config16(libpci_to_lb(dev), pos);
return pci_read_config16(libpci_to_lb(dev), (uint16_t)pos);
}
u32 pci_read_long(struct pci_dev *dev, int pos)
{
return pci_read_config32(libpci_to_lb(dev), pos);
return pci_read_config32(libpci_to_lb(dev), (uint16_t)pos);
}
int pci_write_byte(struct pci_dev *dev, int pos, u8 data)
{
pci_write_config8(libpci_to_lb(dev), pos, data);
pci_write_config8(libpci_to_lb(dev), (uint16_t)pos, data);
return 1; /* success */
}
int pci_write_word(struct pci_dev *dev, int pos, u16 data)
{
pci_write_config16(libpci_to_lb(dev), pos, data);
pci_write_config16(libpci_to_lb(dev), (uint16_t)pos, data);
return 1; /* success */
}
int pci_write_long(struct pci_dev *dev, int pos, u32 data)
{
pci_write_config32(libpci_to_lb(dev), pos, data);
pci_write_config32(libpci_to_lb(dev), (uint16_t)pos, data);
return 1; /* success */
}
@@ -110,29 +110,29 @@ char *pci_filter_parse_slot(struct pci_filter* filter, const char* id)
char *funcp = strrchr(id, '.');
if (funcp) {
filter->func = strtoul(funcp+1, &endptr, 0);
filter->func = strtol(funcp+1, &endptr, 0);
if (endptr[0] != '\0') return invalid_pci_device_string;
}
char *devp = strrchr(id, ':');
if (!devp) {
filter->dev = strtoul(id, &endptr, 0);
filter->dev = strtol(id, &endptr, 0);
} else {
filter->dev = strtoul(devp+1, &endptr, 0);
filter->dev = strtol(devp+1, &endptr, 0);
}
if (endptr != funcp) return invalid_pci_device_string;
if (!devp) return NULL;
char *busp = strchr(id, ':');
if (busp == devp) {
filter->bus = strtoul(id, &endptr, 0);
filter->bus = strtol(id, &endptr, 0);
} else {
filter->bus = strtoul(busp+1, &endptr, 0);
filter->bus = strtol(busp+1, &endptr, 0);
}
if (endptr != funcp) return invalid_pci_device_string;
if (busp == devp) return NULL;
filter->domain = strtoul(id, &endptr, 0);
filter->domain = strtol(id, &endptr, 0);
if (endptr != busp) return invalid_pci_device_string;
return NULL;
@@ -155,15 +155,15 @@ int pci_filter_match(struct pci_filter* pf, struct pci_dev* dev)
return 1;
}
static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus)
static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, uint8_t bus)
{
int devfn;
u32 val;
unsigned char hdr;
for (devfn = 0; devfn < 0x100; devfn++) {
int func = devfn & 0x7;
int slot = (devfn >> 3) & 0x1f;
uint8_t func = devfn & 0x7;
uint8_t slot = (devfn >> 3) & 0x1f;
val = pci_read_config32(PCI_DEV(bus, slot, func),
REG_VENDOR_ID);
@@ -179,7 +179,7 @@ static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus)
dev->dev = slot;
dev->func = func;
dev->vendor_id = val & 0xffff;
dev->device_id = val >> 16;
dev->device_id = (uint16_t)(val >> 16);
dev->next = 0;
hdr = pci_read_config8(PCI_DEV(bus, slot, func),
@@ -187,10 +187,10 @@ static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus)
hdr &= 0x7F;
if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) {
unsigned int busses;
busses = pci_read_config32(PCI_DEV(bus, slot, func),
REG_PRIMARY_BUS);
busses = (busses >> 8) & 0xFF;
uint8_t busses;
busses = (uint8_t)(pci_read_config32(
PCI_DEV(bus, slot, func),
REG_PRIMARY_BUS) >> 8);
/* Avoid recursion if the new bus is the same as
* the old bus (insert lame The Who joke here) */

19
src/Kconfig
View File

@@ -354,6 +354,25 @@ config RAMPAYLOAD
Skip PCI enumeration logic and only allocate BAR for fixed devices
(bootable devices, TPM over GSPI).
config HAVE_CONFIGURABLE_RAMSTAGE
bool
config CONFIGURABLE_RAMSTAGE
bool "Enable a configurable ramstage."
default y if ARCH_X86
depends on HAVE_CONFIGURABLE_RAMSTAGE
help
A configurable ramstage allows you to select which parts of the ramstage
to run. Currently, we can only select a minimal PCI scanning step.
The minimal PCI scanning will only check those parts that are enabled
in the devicetree.cb. By convention none of those devices should be bridges.
config MINIMAL_PCI_SCANNING
bool "Enable minimal PCI scanning"
depends on CONFIGURABLE_RAMSTAGE && PCI
help
If this option is enabled, coreboot will scan only PCI devices
marked as mandatory in devicetree.cb
endmenu
menu "Mainboard"

5
src/arch/arm64/Makefile.inc
View File

@@ -184,10 +184,7 @@ BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
BL31_MAKEARGS += IS_ANYTHING_TO_BUILD=1
# Set a consistent build timestamp: the same coreboot has
# The \# \" complications exist to satisfy both gnu make's parser and editors
# with non-semantic quote-handling (that would assume that this line starts a
# multi line string.
BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell grep "\#define COREBOOT_BUILD\>" $(obj)/build.h |cut -d\" -f2 \# \")"'
BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell sed -n 's/^.define COREBOOT_BUILD\>.*"\(.*\)".*/\1/p' $(obj)/build.h)"'
BL31_CFLAGS := -fno-pic -fno-stack-protector -Wno-deprecated-declarations -Wno-unused-function
BL31_LDFLAGS := --emit-relocs

5
src/arch/arm64/fit_payload.c
View File

@@ -12,13 +12,12 @@
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <commonlib/bsd/compression.h>
#include <console/console.h>
#include <bootmem.h>
#include <program_loading.h>
#include <string.h>
#include <commonlib/compression.h>
#include <commonlib/cbfs_serialized.h>
#include <commonlib/helpers.h>
#include <lib.h>
#include <fit.h>
#include <endian.h>

2
src/arch/riscv/boot.c
View File

@@ -19,7 +19,7 @@
#include <arch/encoding.h>
#include <arch/smp/smp.h>
#include <mcall.h>
#include <commonlib/cbfs_serialized.h>
#include <cbfs.h>
#include <console/console.h>
struct arch_prog_run_args {

4
src/arch/riscv/fit_payload.c
View File

@@ -14,11 +14,11 @@
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <commonlib/bsd/compression.h>
#include <console/console.h>
#include <bootmem.h>
#include <program_loading.h>
#include <commonlib/compression.h>
#include <commonlib/cbfs_serialized.h>
#include <lib.h>
#include <fit.h>
#include <endian.h>

1
src/arch/riscv/sbi.c
View File

@@ -15,7 +15,6 @@
#include <mcall.h>
#include <stdint.h>
#include <commonlib/compiler.h>
#include <arch/exception.h>
#include <sbi.h>
#include <vm.h>

1
src/arch/riscv/smp.c
View File

@@ -18,7 +18,6 @@
#include <arch/smp/smp.h>
#include <arch/smp/spinlock.h>
#include <mcall.h>
#include <commonlib/compiler.h>
#include <console/console.h>
void smp_pause(int working_hartid)

2
src/arch/x86/acpi.c
View File

@@ -946,7 +946,7 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current,
acpi_addr_t address;
if (!dev) {
printk(BIOS_ERR, "%s: Device not found\n", __func__);
printk(BIOS_DEBUG, "%s: Device not found\n", __func__);
return current;
}
if (!dev->enabled) {

6
src/arch/x86/acpi_device.c
View File

@@ -537,9 +537,9 @@ void acpi_device_write_spi(const struct acpi_spi *spi)
void acpi_device_add_power_res(const struct acpi_power_res_params *params)
{
static const char *power_res_dev_states[] = { "_PR0", "_PR3" };
unsigned int reset_gpio = params->reset_gpio->pins[0];
unsigned int enable_gpio = params->enable_gpio->pins[0];
unsigned int stop_gpio = params->stop_gpio->pins[0];
unsigned int reset_gpio = params->reset_gpio ? params->reset_gpio->pins[0] : 0;
unsigned int enable_gpio = params->enable_gpio ? params->enable_gpio->pins[0] : 0;
unsigned int stop_gpio = params->stop_gpio ? params->stop_gpio->pins[0] : 0;
if (!reset_gpio && !enable_gpio && !stop_gpio)
return;

75
src/arch/x86/acpigen.c
View File

@@ -1758,3 +1758,78 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio)
else
return acpigen_soc_clear_tx_gpio(gpio->pins[0]);
}
/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */
void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran,
u16 range_min, u16 range_max, u16 translation, u16 length)
{
acpigen_emit_byte(0x88);
/* Byte 1+2: length (0x000d) */
acpigen_emit_byte(0x0d);
acpigen_emit_byte(0x00);
/* resource type */
acpigen_emit_byte(res_type); // 0 - mem, 1 - io, 2 - bus
/* general flags */
acpigen_emit_byte(gen_flags);
/* type flags */
// refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
acpigen_emit_byte(type_flags);
/* granularity, min, max, translation, length */
acpigen_emit_word(gran);
acpigen_emit_word(range_min);
acpigen_emit_word(range_max);
acpigen_emit_word(translation);
acpigen_emit_word(length);
}
/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */
void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags,
u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length)
{
acpigen_emit_byte(0x87);
/* Byte 1+2: length (0023) */
acpigen_emit_byte(23);
acpigen_emit_byte(0x00);
/* resource type */
acpigen_emit_byte(res_type); // 0 - mem, 1 - io, 2 - bus
/* general flags */
acpigen_emit_byte(gen_flags);
/* type flags */
// refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
acpigen_emit_byte(type_flags);
/* granularity, min, max, translation, length */
acpigen_emit_dword(gran);
acpigen_emit_dword(range_min);
acpigen_emit_dword(range_max);
acpigen_emit_dword(translation);
acpigen_emit_dword(length);
}
static void acpigen_emit_qword(u64 data)
{
acpigen_emit_dword(data & 0xffffffff);
acpigen_emit_dword((data >> 32) & 0xffffffff);
}
/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */
void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags,
u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length)
{
acpigen_emit_byte(0x8a);
/* Byte 1+2: length (0x002b) */
acpigen_emit_byte(0x2b);
acpigen_emit_byte(0x00);
/* resource type */
acpigen_emit_byte(res_type); // 0 - mem, 1 - io, 2 - bus
/* general flags */
acpigen_emit_byte(gen_flags);
/* type flags */
// refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details
acpigen_emit_byte(type_flags);
/* granularity, min, max, translation, length */
acpigen_emit_qword(gran);
acpigen_emit_qword(range_min);
acpigen_emit_qword(range_max);
acpigen_emit_qword(translation);
acpigen_emit_qword(length);
}

9
src/arch/x86/include/arch/acpigen.h
View File

@@ -472,4 +472,13 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num);
int acpigen_enable_tx_gpio(struct acpi_gpio *gpio);
int acpigen_disable_tx_gpio(struct acpi_gpio *gpio);
/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */
void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran,
u16 range_min, u16 range_max, u16 translation, u16 length);
/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */
void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags,
u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length);
/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */
void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags,
u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length);
#endif

7
src/arch/x86/include/arch/rom_segs.h
View File

@@ -18,4 +18,11 @@
#define ROM_DATA_SEG 0x10
#define ROM_CODE_SEG64 0x18
/*
* This define is placed here to make sure future romstage programmers
* know about it.
* It is used for STM setup code.
*/
#define SMM_TASK_STATE_SEG 0x20
#endif /* ROM_SEGS_H */

12
src/commonlib/Makefile.inc
View File

@@ -30,11 +30,11 @@ ramstage-y += cbfs.c
smm-y += cbfs.c
postcar-y += cbfs.c
decompressor-y += lz4_wrapper.c
bootblock-y += lz4_wrapper.c
verstage-y += lz4_wrapper.c
romstage-y += lz4_wrapper.c
ramstage-y += lz4_wrapper.c
postcar-y += lz4_wrapper.c
decompressor-y += bsd/lz4_wrapper.c
bootblock-y += bsd/lz4_wrapper.c
verstage-y += bsd/lz4_wrapper.c
romstage-y += bsd/lz4_wrapper.c
ramstage-y += bsd/lz4_wrapper.c
postcar-y += bsd/lz4_wrapper.c
ramstage-y += sort.c

42
src/commonlib/bsd/include/commonlib/bsd/cb_err.h Normal file
View File

@@ -0,0 +1,42 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
#ifndef _COMMONLIB_BSD_CB_ERR_H_
#define _COMMONLIB_BSD_CB_ERR_H_
#include <stdint.h>
/**
* coreboot error codes
*
* Common error definitions that can be used for any function. All error values
* should be negative -- when useful, positive values can also be used to denote
* success. Allocate a new group or errors every 100 values.
*/
enum cb_err {
CB_SUCCESS = 0, /**< Call completed successfully */
CB_ERR = -1, /**< Generic error code */
CB_ERR_ARG = -2, /**< Invalid argument */
/* NVRAM/CMOS errors */
CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */
CB_CMOS_LAYOUT_NOT_FOUND = -101, /**< Layout file not found */
CB_CMOS_OPTION_NOT_FOUND = -102, /**< Option string not found */
CB_CMOS_ACCESS_ERROR = -103, /**< CMOS access error */
CB_CMOS_CHECKSUM_INVALID = -104, /**< CMOS checksum is invalid */
/* Keyboard test failures */
CB_KBD_CONTROLLER_FAILURE = -200,
CB_KBD_INTERFACE_FAILURE = -201,
/* I2C controller failures */
CB_I2C_NO_DEVICE = -300, /**< Device is not responding */
CB_I2C_BUSY = -301, /**< Device tells it's busy */
CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave
device response, try again? */
CB_I2C_TIMEOUT = -303, /**< Transmission timed out */
};
/* Don't typedef the enum directly, so the size is unambiguous for serialization. */
typedef int32_t cb_err_t;
#endif /* _COMMONLIB_BSD_CB_ERR_H_ */

46
src/commonlib/include/commonlib/cbfs_serialized.h → src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h
View File

@@ -1,48 +1,4 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
* Copyright (C) 2012 Google, Inc.
* Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
*
* This file is dual-licensed. You can choose between:
* - The GNU GPL, version 2, as published by the Free Software Foundation
* - The revised BSD license (without advertising clause)
*
* ---------------------------------------------------------------------------
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* ---------------------------------------------------------------------------
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* ---------------------------------------------------------------------------
*/
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#ifndef _CBFS_SERIALIZED_H_
#define _CBFS_SERIALIZED_H_

17
src/commonlib/include/commonlib/compiler.h → src/commonlib/bsd/include/commonlib/bsd/compiler.h
View File

@@ -1,18 +1,7 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#ifndef _COMMONLIB_COMPILER_H_
#define _COMMONLIB_COMPILER_H_
#ifndef _COMMONLIB_BSD_COMPILER_H_
#define _COMMONLIB_BSD_COMPILER_H_
#ifndef __packed
#if defined(__WIN32) || defined(__WIN64)

13
src/commonlib/include/commonlib/compression.h → src/commonlib/bsd/include/commonlib/bsd/compression.h
View File

@@ -1,15 +1,4 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#ifndef _COMMONLIB_COMPRESSION_H_
#define _COMMONLIB_COMPRESSION_H_

41
src/commonlib/bsd/include/commonlib/bsd/fmap_serialized.h Normal file
View File

@@ -0,0 +1,41 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#ifndef FLASHMAP_SERIALIZED_H__
#define FLASHMAP_SERIALIZED_H__
#include <stdint.h>
#define FMAP_SIGNATURE "__FMAP__"
#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
#define FMAP_STRLEN 32 /* maximum length for strings, */
/* including null-terminator */
enum fmap_flags {
FMAP_AREA_STATIC = 1 << 0,
FMAP_AREA_COMPRESSED = 1 << 1,
FMAP_AREA_RO = 1 << 2,
FMAP_AREA_PRESERVE = 1 << 3,
};
/* Mapping of volatile and static regions in firmware binary */
struct fmap_area {
uint32_t offset; /* offset relative to base */
uint32_t size; /* size in bytes */
uint8_t name[FMAP_STRLEN]; /* descriptive name */
uint16_t flags; /* flags for this area */
} __packed;
struct fmap {
uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
uint8_t ver_major; /* major version */
uint8_t ver_minor; /* minor version */
uint64_t base; /* address of the firmware binary */
uint32_t size; /* size of firmware binary in bytes */
uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
uint16_t nareas; /* number of areas described by
fmap_areas[] below */
struct fmap_area areas[];
} __packed;
#endif /* FLASHMAP_SERIALIZED_H__ */

89
src/commonlib/bsd/include/commonlib/bsd/helpers.h Normal file
View File

@@ -0,0 +1,89 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#ifndef COMMONLIB_BSD_HELPERS_H
#define COMMONLIB_BSD_HELPERS_H
#ifndef __ASSEMBLER__
#include <commonlib/bsd/compiler.h>
#include <stddef.h>
#endif
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#endif
#define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL)
#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
#define ALIGN_UP(x, a) ALIGN((x), (a))
#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL))
#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0)
/* Double-evaluation unsafe min/max, for bitfields and outside of functions */
#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b))
#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <)
#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >)
#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \
__TYPEOF_UNLESS_CONST(a, b) var_a = (a); \
__TYPEOF_UNLESS_CONST(b, a) var_b = (b); \
var_a op var_b ? var_a : var_b; \
})
#define __CMP(a, b, op) __builtin_choose_expr( \
__builtin_constant_p(a) && __builtin_constant_p(b), \
__CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME))
#ifndef MIN
#define MIN(a, b) __CMP(a, b, <)
#endif
#ifndef MAX
#define MAX(a, b) __CMP(a, b, >)
#endif
#ifndef ABS
#define ABS(a) ({ \
__typeof__(a) _abs_local_a = (a); \
(_abs_local_a < 0) ? (-_abs_local_a) : _abs_local_a; \
})
#endif
#define IS_POWER_OF_2(x) ({ \
__typeof__(x) _power_local_x = (x); \
(_power_local_x & (_power_local_x - 1)) == 0; \
})
#define DIV_ROUND_UP(x, y) ({ \
__typeof__(x) _div_local_x = (x); \
__typeof__(y) _div_local_y = (y); \
(_div_local_x + _div_local_y - 1) / _div_local_y; \
})
#define SWAP(a, b) do { \
__typeof__(&(a)) _swap_local_a = &(a); \
__typeof__(&(b)) _swap_local_b = &(b); \
__typeof__(a) _swap_local_tmp = *_swap_local_a; \
*_swap_local_a = *_swap_local_b; \
*_swap_local_b = _swap_local_tmp; \
} while (0)
/* Standard units. */
#define KiB (1<<10)
#define MiB (1<<20)
#define GiB (1<<30)
#define KHz (1000)
#define MHz (1000 * KHz)
#define GHz (1000 * MHz)
#ifndef offsetof
#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER)
#endif
#define check_member(structure, member, offset) _Static_assert( \
offsetof(struct structure, member) == offset, \
"`struct " #structure "` offset for `" #member "` is not " #offset)
/* Calculate size of structure member. */
#define member_size(type, member) (sizeof(((type *)0)->member))
#endif /* COMMONLIB_BSD_HELPERS_H */

0
src/commonlib/lz4.c.inc → src/commonlib/bsd/lz4.c.inc
View File

45
src/commonlib/lz4_wrapper.c → src/commonlib/bsd/lz4_wrapper.c
View File

@@ -1,37 +1,8 @@
/*
* Copyright 2015-2016 Google Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */
#include <commonlib/compression.h>
#include <commonlib/endian.h>
#include <commonlib/helpers.h>
#include <commonlib/bsd/compression.h>
#include <commonlib/bsd/helpers.h>
#include <endian.h>
#include <stdint.h>
#include <string.h>
@@ -41,7 +12,7 @@
* access support), we can easily write the ones we need ourselves. */
static uint16_t LZ4_readLE16(const void *src)
{
return read_le16(src);
return le16toh(*(const uint16_t *)src);
}
static void LZ4_copy8(void *dst, const void *src)
{
@@ -143,7 +114,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
return 0; /* input overrun */
/* We assume there's always only a single, standard frame. */
if (read_le32(&h->magic) != LZ4F_MAGICNUMBER || h->version != 1)
if (le32toh(h->magic) != LZ4F_MAGICNUMBER || h->version != 1)
return 0; /* unknown format */
if (h->reserved0 || h->reserved1 || h->reserved2)
return 0; /* reserved must be zero */
@@ -158,7 +129,9 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn)
}
while (1) {
struct lz4_block_header b = { { .raw = read_le32(in) } };
struct lz4_block_header b = {
{ .raw = le32toh(*(const uint32_t *)in) }
};
in += sizeof(struct lz4_block_header);
if ((size_t)(in - src) + b.size > srcn)

4
src/commonlib/include/commonlib/cbfs.h
View File

@@ -14,7 +14,7 @@
#ifndef _COMMONLIB_CBFS_H_
#define _COMMONLIB_CBFS_H_
#include <commonlib/cbfs_serialized.h>
#include <commonlib/bsd/cbfs_serialized.h>
#include <commonlib/region.h>
#include <vb2_api.h>
@@ -24,7 +24,7 @@ struct cbfsf {
struct region_device data;
};
/* Locate file by name and optional type. Returns 0 on succcess else < 0 on
/* Locate file by name and optional type. Returns 0 on success else < 0 on
* error.*/
int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs,
const char *name, uint32_t *type);

74
src/commonlib/include/commonlib/fmap_serialized.h
View File

@@ -1,74 +0,0 @@
/*
* Copyright 2010, Google Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following disclaimer
* in the documentation and/or other materials provided with the
* distribution.
* * Neither the name of Google Inc. nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Alternatively, this software may be distributed under the terms of the
* GNU General Public License ("GPL") version 2 as published by the Free
* Software Foundation.
*/
#ifndef FLASHMAP_SERIALIZED_H__
#define FLASHMAP_SERIALIZED_H__
#include <stdint.h>
#define FMAP_SIGNATURE "__FMAP__"
#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
#define FMAP_STRLEN 32 /* maximum length for strings, */
/* including null-terminator */
enum fmap_flags {
FMAP_AREA_STATIC = 1 << 0,
FMAP_AREA_COMPRESSED = 1 << 1,
FMAP_AREA_RO = 1 << 2,
FMAP_AREA_PRESERVE = 1 << 3,
};
/* Mapping of volatile and static regions in firmware binary */
struct fmap_area {
uint32_t offset; /* offset relative to base */
uint32_t size; /* size in bytes */
uint8_t name[FMAP_STRLEN]; /* descriptive name */
uint16_t flags; /* flags for this area */
} __packed;
struct fmap {
uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
uint8_t ver_major; /* major version */
uint8_t ver_minor; /* minor version */
uint64_t base; /* address of the firmware binary */
uint32_t size; /* size of firmware binary in bytes */
uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
uint16_t nareas; /* number of areas described by
fmap_areas[] below */
struct fmap_area areas[];
} __packed;
#endif /* FLASHMAP_SERIALIZED_H__ */

89
src/commonlib/include/commonlib/helpers.h
View File

@@ -13,71 +13,12 @@
#ifndef COMMONLIB_HELPERS_H
#define COMMONLIB_HELPERS_H
/* This file is for helpers for both coreboot firmware and its utilities. */
#ifndef __ASSEMBLER__
#include <commonlib/compiler.h>
#include <stddef.h>
#endif
/* This file is for helpers for both coreboot firmware and its utilities. Most
of this has moved into <commonlib/bsd/helpers.h> now, this wrapper is just
for the stuff that nobody bothered to confirm BSD-licensability of yet. */
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#endif
#define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL)
#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask))
#define ALIGN_UP(x, a) ALIGN((x), (a))
#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL))
#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0)
/* Double-evaluation unsafe min/max, for bitfields and outside of functions */
#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b))
#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <)
#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >)
#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \
__TYPEOF_UNLESS_CONST(a, b) var_a = (a); \
__TYPEOF_UNLESS_CONST(b, a) var_b = (b); \
var_a op var_b ? var_a : var_b; \
})
#define __CMP(a, b, op) __builtin_choose_expr( \
__builtin_constant_p(a) && __builtin_constant_p(b), \
__CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME))
#ifndef MIN
#define MIN(a, b) __CMP(a, b, <)
#endif
#ifndef MAX
#define MAX(a, b) __CMP(a, b, >)
#endif
#ifndef ABS
#define ABS(a) ({ \
__typeof__(a) _abs_local_a = (a); \
(_abs_local_a < 0) ? (-_abs_local_a) : _abs_local_a; \
})
#endif
#define IS_POWER_OF_2(x) ({ \
__typeof__(x) _power_local_x = (x); \
(_power_local_x & (_power_local_x - 1)) == 0; \
})
#define DIV_ROUND_UP(x, y) ({ \
__typeof__(x) _div_local_x = (x); \
__typeof__(y) _div_local_y = (y); \
(_div_local_x + _div_local_y - 1) / _div_local_y; \
})
#define SWAP(a, b) do { \
__typeof__(&(a)) _swap_local_a = &(a); \
__typeof__(&(b)) _swap_local_b = &(b); \
__typeof__(a) _swap_local_tmp = *_swap_local_a; \
*_swap_local_a = *_swap_local_b; \
*_swap_local_b = _swap_local_tmp; \
} while (0)
#include <commonlib/bsd/helpers.h>
/*
* Divide positive or negative dividend by positive divisor and round
@@ -93,25 +34,6 @@
((_div_local_x - (_div_local_d / 2)) / _div_local_d); \
})
/* Standard units. */
#define KiB (1<<10)
#define MiB (1<<20)
#define GiB (1<<30)
/* Could we ever run into this one? I hope we get this much memory! */
#define TiB (1<<40)
#define KHz (1000)
#define MHz (1000 * KHz)
#define GHz (1000 * MHz)
#ifndef offsetof
#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER)
#endif
#define check_member(structure, member, offset) _Static_assert( \
offsetof(struct structure, member) == offset, \
"`struct " #structure "` offset for `" #member "` is not " #offset)
/**
* container_of - cast a member of a structure out to the containing structure
* @param ptr: the pointer to the member.
@@ -123,9 +45,6 @@
const __typeof__(((type *)0)->member) *__mptr = (ptr); \
(type *)((char *)__mptr - offsetof(type, member)); })
/* Calculate size of structure member. */
#define member_size(type, member) (sizeof(((type *)0)->member))
#ifndef __unused
#define __unused __attribute__((unused))
#endif

16
src/cpu/intel/thermal_monitoring/thermal_monitoring.h
View File

@@ -1,16 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define THERMAL_MONITORING_OFF 0
#define THERMAL_MONITORING_SET 0x00000008
#define MISC_ENABLE 0x01a0

49
src/cpu/x86/mp_init.c
View File

@@ -13,6 +13,7 @@
*/
#include <console/console.h>
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <rmodule.h>
@@ -37,6 +38,8 @@
#include <timer.h>
#include <thread.h>
#include <security/intel/stm/SmmStm.h>
#define MAX_APIC_IDS 256
struct mp_callback {
@@ -518,11 +521,12 @@ static int bsp_do_flight_plan(struct mp_params *mp_params)
int i;
int ret = 0;
/*
* Set time-out to wait for APs to a huge value (=1 second) since it
* could take a longer time for APs to check-in as the number of APs
* increases (contention for resources like UART also increases).
* Set time out for flight plan to a huge minimum value (>=1 second).
* CPUs with many APs may take longer if there is contention for
* resources such as UART, so scale the time out up by increments of
* 100ms if needed.
*/
const int timeout_us = 1000000;
const int timeout_us = MAX(1000000, 100000 * mp_params->num_cpus);
const int step_us = 100;
int num_aps = mp_params->num_cpus - 1;
struct stopwatch sw;
@@ -741,6 +745,23 @@ static void asmlinkage smm_do_relocation(void *arg)
/* Setup code checks this callback for validity. */
mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase);
if (CONFIG(STM)) {
if (is_smm_enabled()) {
uintptr_t mseg;
mseg = mp_state.perm_smbase +
(mp_state.perm_smsize - CONFIG_MSEG_SIZE);
stm_setup(mseg, p->cpu, runtime->num_cpus,
perm_smbase,
mp_state.perm_smbase,
runtime->start32_offset);
} else {
printk(BIOS_DEBUG,
"STM not loaded because SMM is not enabled!\n");
}
}
}
static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params)
@@ -1020,6 +1041,26 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops)
ops->get_smm_info(&state->perm_smbase, &state->perm_smsize,
&state->smm_save_state_size);
/*
* Make sure there is enough room for the SMM descriptor
*/
if (CONFIG(STM)) {
state->smm_save_state_size +=
sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR);
/* Currently, the CPU SMM save state size is based on a simplistic
* algorithm. (align on 4K)
* note: In the future, this will need to handle newer x86 processors
* that require alignment of the save state on 32K boundaries.
* The alignment is done here because coreboot has a hard coded
* value of 0x400 for this value.
* Also, this alignment only works on CPUs less than 5 threads
*/
if (CONFIG(STM))
state->smm_save_state_size =
ALIGN_UP(state->smm_save_state_size, 0x1000);
}
/*
* Default to smm_initiate_relocation() if trigger callback isn't
* provided.

21
src/cpu/x86/smm/smm_module_loader.c
View File

@@ -17,6 +17,7 @@
#include <cpu/x86/cache.h>
#include <commonlib/helpers.h>
#include <console/console.h>
#include <security/intel/stm/SmmStm.h>
#define FXSAVE_SIZE 512
@@ -201,6 +202,8 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params,
/* Adjust remaining size to account for save state. */
total_save_state_size = params->per_cpu_save_state_size *
params->num_concurrent_save_states;
if (total_save_state_size > size)
return -1;
size -= total_save_state_size;
/* The save state size encroached over the first SMM entry point. */
@@ -267,6 +270,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params,
stub_params->fxsave_area_size = FXSAVE_SIZE;
stub_params->runtime.smbase = (uintptr_t)smbase;
stub_params->runtime.save_state_size = params->per_cpu_save_state_size;
stub_params->runtime.num_cpus = params->num_concurrent_stacks;
/* Initialize the APIC id to CPU number table to be 1:1 */
for (i = 0; i < params->num_concurrent_stacks; i++)
@@ -313,6 +317,11 @@ int smm_setup_relocation_handler(struct smm_loader_params *params)
* +-----------------+ <- smram + size
* | stacks |
* +-----------------+ <- smram + size - total_stack_size
* | fxsave area |
* +-----------------+ <- smram + size - total_stack_size - fxsave_size
* | BIOS resource |
* | list (STM) |
* +-----------------+ <- .. - CONFIG_BIOS_RESOURCE_LIST_SIZE
* | ... |
* +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE
* | handler |
@@ -353,7 +362,12 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
/* Stacks start at the top of the region. */
base = smram;
base += size;
if (CONFIG(STM))
base += size - CONFIG_MSEG_SIZE; // take out the mseg
else
base += size;
params->stack_top = base;
/* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment
@@ -382,6 +396,11 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params)
/* Does the required amount of memory exceed the SMRAM region size? */
total_size = total_stack_size + handler_size;
total_size += fxsave_size + SMM_DEFAULT_SIZE;
// account for the bios resource list
if (CONFIG(STM))
total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE;
if (total_size > size)
return -1;

13
src/cpu/x86/smm/smm_stub.S
View File

@@ -44,6 +44,11 @@ smbase:
.long 0
save_state_size:
.long 0
num_cpus:
.long 0
/* allows the STM to bring up SMM in 32-bit mode */
start32_offset:
.long smm_trampoline32 - _start
/* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the
* APIC id is found at the given index, the contiguous CPU number is index
* into the table. */
@@ -90,6 +95,14 @@ smm_relocate_gdt:
/* gdt selector 0x10, flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
/* gdt selector 0x18, flat code segment (64-bit) */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00
/* gdt selector 0x20 tss segment */
.word 0xffff, 0x0000
.byte 0x00, 0x8b, 0x80, 0x00
smm_relocate_gdt_end:
.align 4

6
src/device/pci_device.c
View File

@@ -1195,6 +1195,12 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn,
* non-existence and single function devices.
*/
for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
if (CONFIG(MINIMAL_PCI_SCANNING)) {
dev = pcidev_path_behind(bus, devfn);
if (!dev || !dev->mandatory)
continue;
}
/* First thing setup the device structure. */
dev = pci_scan_get_dev(bus, devfn);

4
src/device/pnp_device.c
View File

@@ -129,12 +129,12 @@ static void pnp_set_resource(struct device *dev, struct resource *resource)
(resource->index != PNP_IDX_IRQ0) &&
(resource->index != PNP_IDX_IRQ1))
printk(BIOS_WARNING, "WARNING: %s %02lx %s size: "
"0x%010llx not assigned\n", dev_path(dev),
"0x%010llx not assigned in devicetree\n", dev_path(dev),
resource->index, resource_type(resource),
resource->size);
else
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx "
"not assigned\n", dev_path(dev), resource->index,
"not assigned in devicetree\n", dev_path(dev), resource->index,
resource_type(resource), resource->size);
return;
}

3
src/drivers/generic/gfx/gfx.c
View File

@@ -69,6 +69,9 @@ static void gfx_fill_ssdt_generator(struct device *dev)
const char *scope = acpi_device_scope(dev);
if (!scope)
return;
acpigen_write_scope(scope);
/* Method (_DOD, 0) */

18
src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
View File

@@ -17,6 +17,20 @@
#include <stddef.h>
#pragma pack(push)
/**
* These includes are required to include headers that are missing in
* the FSP headers. Import order matter for the correct PiHob definition
* to be found.
*/
#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION
#include <PiPei.h>
#include <Ppi/MpServices.h>
#include <Uefi/UefiMultiPhase.h>
#include <Pi/PiBootMode.h>
#include <Pi/PiHob.h>
#endif
/*
* This file is a implementation specific header. i.e. different
* FSP implementations for different chipsets.
@@ -28,10 +42,6 @@
#include <FirmwareVersionInfoHob.h>
#endif
#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION
#include <PiPei.h>
#include <Ppi/MpServices.h>
#endif
#pragma pack(pop)

12
src/drivers/net/chip.h
View File

@@ -15,10 +15,22 @@
#define __DRIVERS_R8168_CHIP_H__
#include <stdint.h>
#include <arch/acpi_device.h>
struct drivers_net_config {
uint16_t customized_leds;
unsigned int wake; /* Wake pin for ACPI _PRW */
/* Does the device have a power resource? */
bool has_power_resource;
/* GPIO used to stop operation of device. */
struct acpi_gpio stop_gpio;
/* Delay to be inserted after disabling stop. */
unsigned int stop_delay_ms;
/* Delay to be inserted after enabling stop. */
unsigned int stop_off_delay_ms;
/*
* There maybe many NIC cards in a system.
* This parameter is for driver to identify what

10
src/drivers/net/r8168.c
View File

@@ -317,6 +317,16 @@ static void r8168_net_fill_ssdt(struct device *dev)
if (dev->chip_ops)
acpigen_write_name_string("_DDN", dev->chip_ops->name);
/* Power Resource */
if (config->has_power_resource) {
const struct acpi_power_res_params power_res_params = {
.stop_gpio = &config->stop_gpio,
.stop_delay_ms = config->stop_delay_ms,
.stop_off_delay_ms = config->stop_off_delay_ms
};
acpi_device_add_power_res(&power_res_params);
}
/* Address */
address = PCI_SLOT(dev->path.pci.devfn) & 0xffff;
address <<= 16;

50
src/drivers/spi/adesto.c
View File

@@ -41,63 +41,63 @@
static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x4218,
.name = "AT25SL128A",
/* AT25SL128A */
.id[0] = 0x4218,
.nr_sectors_shift = 12,
},
{
.id = 0x4501,
.name = "AT25DF081A", /* Yes, 81A id < 81 */
/* AT25DF081A Yes, 81A id < 81 */
.id[0] = 0x4501,
.nr_sectors_shift = 8,
},
{
.id = 0x4502,
.name = "AT25DF081",
/* AT25DF081 */
.id[0] = 0x4502,
.nr_sectors_shift = 8,
},
{
.id = 0x4602,
.name = "AT25DF161",
/* AT25DF161 */
.id[0] = 0x4602,
.nr_sectors_shift = 9,
},
{
.id = 0x4603,
.name = "AT25DL161",
/* AT25DL161 */
.id[0] = 0x4603,
.nr_sectors_shift = 9,
},
{
.id = 0x4700,
.name = "AT25DF321",
/* AT25DF321 */
.id[0] = 0x4700,
.nr_sectors_shift = 10,
},
{
.id = 0x4701,
.name = "AT25DF321A",
/* AT25DF321A */
.id[0] = 0x4701,
.nr_sectors_shift = 10,
},
{
.id = 0x4800,
.name = "AT25DF641",
/* AT25DF641 */
.id[0] = 0x4800,
.nr_sectors_shift = 11,
},
{
.id = 0x8501,
.name = "AT25SF081",
/* AT25SF081 */
.id[0] = 0x8501,
.nr_sectors_shift = 8,
},
{
.id = 0x8600,
.name = "AT25DQ161",
/* AT25DQ161 */
.id[0] = 0x8600,
.nr_sectors_shift = 9,
},
{
.id = 0x8601,
.name = "AT25SF161",
/* AT25SF161 */
.id[0] = 0x8601,
.nr_sectors_shift = 9,
},
{
.id = 0x8700,
.name = "AT25DQ321",
/* AT25DQ321 */
.id[0] = 0x8700,
.nr_sectors_shift = 10,
},
};
@@ -106,7 +106,7 @@ const struct spi_flash_vendor_info spi_flash_adesto_vi = {
.id = VENDOR_ID_ADESTO,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

38
src/drivers/spi/amic.c
View File

@@ -36,48 +36,48 @@
static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x2015,
.name = "A25L16PU",
/* A25L16PU */
.id[0] = 0x2015,
.nr_sectors_shift = 9,
},
{
.id = 0x2025,
.name = "A25L16PT",
/* A25L16PT */
.id[0] = 0x2025,
.nr_sectors_shift = 9,
},
{
.id = 0x3014,
.name = "A25L080",
/* A25L080 */
.id[0] = 0x3014,
.nr_sectors_shift = 8,
},
{
.id = 0x3015,
.name = "A25L016",
/* A25L016 */
.id[0] = 0x3015,
.nr_sectors_shift = 9,
},
{
.id = 0x3016,
.name = "A25L032",
/* A25L032 */
.id[0] = 0x3016,
.nr_sectors_shift = 10,
},
{
.id = 0x4014,
.name = "A25LQ080",
/* A25LQ080 */
.id[0] = 0x4014,
.nr_sectors_shift = 8,
},
{
.id = 0x4015,
.name = "A25LQ16",
/* A25LQ16 */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
},
{
.id = 0x4016,
.name = "A25LQ032",
/* A25LQ032 */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
},
{
.id = 0x4017,
.name = "A25LQ64",
/* A25LQ64 */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
},
};
@@ -86,7 +86,7 @@ const struct spi_flash_vendor_info spi_flash_amic_vi = {
.id = VENDOR_ID_AMIC,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

30
src/drivers/spi/atmel.c
View File

@@ -36,38 +36,38 @@
static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x3015,
.name = "AT25X16",
/* AT25X16 */
.id[0] = 0x3015,
.nr_sectors_shift = 9,
},
{
.id = 0x47,
.name = "AT25DF32",
/* AT25DF32 */
.id[0] = 0x47,
.nr_sectors_shift = 10,
},
{
.id = 0x3017,
.name = "AT25X64",
/* AT25X64 */
.id[0] = 0x3017,
.nr_sectors_shift = 11,
},
{
.id = 0x4015,
.name = "AT25Q16",
/* AT25Q16 */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
},
{
.id = 0x4016,
.name = "AT25Q32",
/* AT25Q32 */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
},
{
.id = 0x4017,
.name = "AT25Q64",
/* AT25Q64 */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
},
{
.id = 0x4018,
.name = "AT25Q128",
/* AT25Q128 */
.id[0] = 0x4018,
.nr_sectors_shift = 12,
},
};
@@ -76,7 +76,7 @@ const struct spi_flash_vendor_info spi_flash_atmel_vi = {
.id = VENDOR_ID_ATMEL,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

86
src/drivers/spi/eon.c
View File

@@ -57,108 +57,108 @@
static const struct spi_flash_part_id flash_table[] = {
{
.id = EON_ID_EN25B80,
.name = "EN25B80",
/* EN25B80 */
.id[0] = EON_ID_EN25B80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25B16,
.name = "EN25B16",
/* EN25B16 */
.id[0] = EON_ID_EN25B16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25B32,
.name = "EN25B32",
/* EN25B32 */
.id[0] = EON_ID_EN25B32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25B64,
.name = "EN25B64",
/* EN25B64 */
.id[0] = EON_ID_EN25B64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25F80,
.name = "EN25F80",
/* EN25F80 */
.id[0] = EON_ID_EN25F80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25F16,
.name = "EN25F16",
/* EN25F16 */
.id[0] = EON_ID_EN25F16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25F32,
.name = "EN25F32",
/* EN25F32 */
.id[0] = EON_ID_EN25F32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25F64,
.name = "EN25F64",
/* EN25F64 */
.id[0] = EON_ID_EN25F64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25Q80,
.name = "EN25Q80(A)",
/* EN25Q80(A) */
.id[0] = EON_ID_EN25Q80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25Q16,
.name = "EN25Q16(D16)",
/* EN25Q16(D16) */
.id[0] = EON_ID_EN25Q16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25Q32,
.name = "EN25Q32(A/B)",
/* EN25Q32(A/B) */
.id[0] = EON_ID_EN25Q32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25Q64,
.name = "EN25Q64",
/* EN25Q64 */
.id[0] = EON_ID_EN25Q64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25Q128,
.name = "EN25Q128",
/* EN25Q128 */
.id[0] = EON_ID_EN25Q128,
.nr_sectors_shift = 12,
},
{
.id = EON_ID_EN25QH16,
.name = "EN25QH16",
/* EN25QH16 */
.id[0] = EON_ID_EN25QH16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25QH32,
.name = "EN25QH32",
/* EN25QH32 */
.id[0] = EON_ID_EN25QH32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25QH64,
.name = "EN25QH64",
/* EN25QH64 */
.id[0] = EON_ID_EN25QH64,
.nr_sectors_shift = 11,
},
{
.id = EON_ID_EN25QH128,
.name = "EN25QH128",
/* EN25QH128 */
.id[0] = EON_ID_EN25QH128,
.nr_sectors_shift = 12,
},
{
.id = EON_ID_EN25S80,
.name = "EN25S80",
/* EN25S80 */
.id[0] = EON_ID_EN25S80,
.nr_sectors_shift = 8,
},
{
.id = EON_ID_EN25S16,
.name = "EN25S16",
/* EN25S16 */
.id[0] = EON_ID_EN25S16,
.nr_sectors_shift = 9,
},
{
.id = EON_ID_EN25S32,
.name = "EN25S32",
/* EN25S32 */
.id[0] = EON_ID_EN25S32,
.nr_sectors_shift = 10,
},
{
.id = EON_ID_EN25S64,
.name = "EN25S64",
/* EN25S64 */
.id[0] = EON_ID_EN25S64,
.nr_sectors_shift = 11,
},
};
@@ -167,7 +167,7 @@ const struct spi_flash_vendor_info spi_flash_eon_vi = {
.id = VENDOR_ID_EON,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

54
src/drivers/spi/gigadevice.c
View File

@@ -36,79 +36,79 @@
static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x3114,
.name = "GD25T80",
/* GD25T80 */
.id[0] = 0x3114,
.nr_sectors_shift = 8,
},
{
.id = 0x4014,
.name = "GD25Q80",
/* GD25Q80 */
.id[0] = 0x4014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
}, /* also GD25Q80B */
{
.id = 0x4015,
.name = "GD25Q16",
/* GD25Q16 */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
}, /* also GD25Q16B */
{
.id = 0x4016,
.name = "GD25Q32B",
/* GD25Q32B */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
}, /* also GD25Q32B */
{
.id = 0x4017,
.name = "GD25Q64",
/* GD25Q64 */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
}, /* also GD25Q64B, GD25B64C */
{
.id = 0x4018,
.name = "GD25Q128",
/* GD25Q128 */
.id[0] = 0x4018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
}, /* also GD25Q128B */
{
.id = 0x4214,
.name = "GD25VQ80C",
/* GD25VQ80C */
.id[0] = 0x4214,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x4215,
.name = "GD25VQ16C",
/* GD25VQ16C */
.id[0] = 0x4215,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6014,
.name = "GD25LQ80",
/* GD25LQ80 */
.id[0] = 0x6014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6015,
.name = "GD25LQ16",
/* GD25LQ16 */
.id[0] = 0x6015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6016,
.name = "GD25LQ32",
/* GD25LQ32 */
.id[0] = 0x6016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
},
{
.id = 0x6017,
.name = "GD25LQ64C",
/* GD25LQ64C */
.id[0] = 0x6017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
}, /* also GD25LB64C */
{
.id = 0x6018,
.name = "GD25LQ128",
/* GD25LQ128 */
.id[0] = 0x6018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
},
@@ -118,7 +118,7 @@ const struct spi_flash_vendor_info spi_flash_gigadevice_vi = {
.id = VENDOR_ID_GIGADEVICE,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

78
src/drivers/spi/macronix.c
View File

@@ -38,98 +38,98 @@
static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x2014,
.name = "MX25L8005",
/* MX25L8005 */
.id[0] = 0x2014,
.nr_sectors_shift = 8,
},
{
.id = 0x2015,
.name = "MX25L1605D",
/* MX25L1605D */
.id[0] = 0x2015,
.nr_sectors_shift = 9,
},
{
.id = 0x2016,
.name = "MX25L3205D",
/* MX25L3205D */
.id[0] = 0x2016,
.nr_sectors_shift = 10,
},
{
.id = 0x2017,
.name = "MX25L6405D",
/* MX25L6405D */
.id[0] = 0x2017,
.nr_sectors_shift = 11,
},
{
.id = 0x2018,
.name = "MX25L12805D",
/* MX25L12805D */
.id[0] = 0x2018,
.nr_sectors_shift = 12,
},
{
.id = 0x2019,
.name = "MX25L25635F",
/* MX25L25635F */
.id[0] = 0x2019,
.nr_sectors_shift = 13,
},
{
.id = 0x201a,
.name = "MX66L51235F",
/* MX66L51235F */
.id[0] = 0x201a,
.nr_sectors_shift = 14,
},
{
.id = 0x2415,
.name = "MX25L1635D",
/* MX25L1635D */
.id[0] = 0x2415,
.nr_sectors_shift = 9,
},
{
.id = 0x2515,
.name = "MX25L1635E",
/* MX25L1635E */
.id[0] = 0x2515,
.nr_sectors_shift = 9,
},
{
.id = 0x2534,
.name = "MX25U8032E",
/* MX25U8032E */
.id[0] = 0x2534,
.nr_sectors_shift = 8,
},
{
.id = 0x2535,
.name = "MX25U1635E",
/* MX25U1635E */
.id[0] = 0x2535,
.nr_sectors_shift = 9,
},
{
.id = 0x2536,
.name = "MX25U3235E",
/* MX25U3235E */
.id[0] = 0x2536,
.nr_sectors_shift = 10,
},
{
.id = 0x2537,
.name = "MX25U6435F",
/* MX25U6435F */
.id[0] = 0x2537,
.nr_sectors_shift = 11,
},
{
.id = 0x2538,
.name = "MX25U12835F",
/* MX25U12835F */
.id[0] = 0x2538,
.nr_sectors_shift = 12,
},
{
.id = 0x2539,
.name = "MX25U25635F",
/* MX25U25635F */
.id[0] = 0x2539,
.nr_sectors_shift = 13,
},
{
.id = 0x253a,
.name = "MX25U51245G",
/* MX25U51245G */
.id[0] = 0x253a,
.nr_sectors_shift = 14,
},
{
.id = 0x2618,
.name = "MX25L12855E",
/* MX25L12855E */
.id[0] = 0x2618,
.nr_sectors_shift = 12,
},
{
.id = 0x5e16,
.name = "MX25L3235D", /* MX25L3225D/MX25L3236D/MX25L3237D */
/* MX25L3235D/MX25L3225D/MX25L3236D/MX25L3237D */
.id[0] = 0x5e16,
.nr_sectors_shift = 10,
},
{
.id = 0x9517,
.name = "MX25L6495F",
/* MX25L6495F */
.id[0] = 0x9517,
.nr_sectors_shift = 11,
},
};
@@ -138,7 +138,7 @@ const struct spi_flash_vendor_info spi_flash_macronix_vi = {
.id = VENDOR_ID_MACRONIX,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

65
src/drivers/spi/spansion.c
View File

@@ -51,74 +51,79 @@
static const struct spi_flash_part_id flash_table_ext[] = {
{
.id = SPSN_ID_S25FL008A,
.name = "S25FL008A",
/* S25FL008A */
.id[0] = SPSN_ID_S25FL008A,
.nr_sectors_shift = 4,
},
{
.id = SPSN_ID_S25FL016A,
.name = "S25FL016A",
/* S25FL016A */
.id[0] = SPSN_ID_S25FL016A,
.nr_sectors_shift = 5,
},
{
.id = SPSN_ID_S25FL032A,
.name = "S25FL032A",
/* S25FL032A */
.id[0] = SPSN_ID_S25FL032A,
.nr_sectors_shift = 6,
},
{
.id = SPSN_ID_S25FL064A,
.name = "S25FL064A",
/* S25FL064A */
.id[0] = SPSN_ID_S25FL064A,
.nr_sectors_shift = 7,
},
{
.id = (SPSN_EXT_ID_S25FL128P_64KB << 16) | SPSN_ID_S25FL128P,
.name = "S25FL128P_64K",
/* S25FL128P_64K */
.id[0] = SPSN_ID_S25FL128P,
.id[1] = SPSN_EXT_ID_S25FL128P_64KB,
.nr_sectors_shift = 8,
},
{
.id = (SPSN_EXT_ID_S25FLXXS_64KB << 16) | SPSN_ID_S25FL128S,
.name = "S25FL128S_256K",
/* S25FL128S_256K */
.id[0] = SPSN_ID_S25FL128S,
.id[1] = SPSN_EXT_ID_S25FLXXS_64KB,
.nr_sectors_shift = 9,
},
{
.id = (SPSN_EXT_ID_S25FL032P << 16) | SPSN_ID_S25FL032A,
.name = "S25FL032P",
/* S25FL032P */
.id[0] = SPSN_ID_S25FL032A,
.id[1] = SPSN_EXT_ID_S25FL032P,
.nr_sectors_shift = 6,
},
{
.id = (SPSN_EXT_ID_S25FLXXS_64KB << 16) | SPSN_ID_S25FL128P,
.name = "S25FS128S",
/* S25FS128S */
.id[0] = SPSN_ID_S25FL128P,
.id[1] = SPSN_EXT_ID_S25FLXXS_64KB,
.nr_sectors_shift = 8,
},
};
static const struct spi_flash_part_id flash_table_256k_sector[] = {
{
.id = (SPSN_EXT_ID_S25FL128P_256KB << 16) | SPSN_ID_S25FL128P,
.name = "S25FL128P_256K",
/* S25FL128P_256K */
.id[0] = SPSN_ID_S25FL128P,
.id[1] = SPSN_EXT_ID_S25FL128P_256KB,
.nr_sectors_shift = 6,
},
};
static const struct spi_flash_part_id flash_table[] = {
{
.id = SPSN_ID_S25FL208K,
.name = "S25FL208K",
/* S25FL208K */
.id[0] = SPSN_ID_S25FL208K,
.nr_sectors_shift = 4,
},
{
.id = SPSN_ID_S25FL116K,
.name = "S25FL116K_16M",
/* S25FL116K_16M */
.id[0] = SPSN_ID_S25FL116K,
.nr_sectors_shift = 5,
},
{
.id = SPSN_ID_S25FL132K,
.name = "S25FL132K",
/* S25FL132K */
.id[0] = SPSN_ID_S25FL132K,
.nr_sectors_shift = 6,
},
{
.id = SPSN_ID_S25FL164K,
.name = "S25FL164K",
/* S25FL164K */
.id[0] = SPSN_ID_S25FL164K,
.nr_sectors_shift = 7,
},
};
@@ -127,7 +132,8 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi = {
.id = VENDOR_ID_SPANSION,
.page_size_shift = 8,
.sector_size_kib_shift = 6,
.match_id_mask = 0xffffffff,
.match_id_mask[0] = 0xffff,
.match_id_mask[1] = 0xffff,
.ids = flash_table_ext,
.nr_part_ids = ARRAY_SIZE(flash_table_ext),
.desc = &spi_flash_pp_0xd8_sector_desc,
@@ -137,7 +143,8 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi = {
.id = VENDOR_ID_SPANSION,
.page_size_shift = 8,
.sector_size_kib_shift = 8,
.match_id_mask = 0xffffffff,
.match_id_mask[0] = 0xffff,
.match_id_mask[1] = 0xffff,
.ids = flash_table_256k_sector,
.nr_part_ids = ARRAY_SIZE(flash_table_256k_sector),
.desc = &spi_flash_pp_0xd8_sector_desc,
@@ -147,7 +154,7 @@ const struct spi_flash_vendor_info spi_flash_spansion_vi = {
.id = VENDOR_ID_SPANSION,
.page_size_shift = 8,
.sector_size_kib_shift = 6,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0xd8_sector_desc,

25
src/drivers/spi/spi_flash.c
View File

@@ -355,8 +355,7 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash,
{
memcpy(&flash->spi, spi, sizeof(*spi));
flash->vendor = vi->id;
flash->model = part->id;
flash->name = part->name;
flash->model = part->id[0];
flash->page_size = 1U << vi->page_size_shift;
flash->sector_size = (1U << vi->sector_size_kib_shift) * KiB;
@@ -379,14 +378,19 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash,
}
static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_info *vi,
uint32_t id)
uint16_t id[2])
{
size_t i;
const uint16_t lid[2] = {
[0] = id[0] & vi->match_id_mask[0],
[1] = id[1] & vi->match_id_mask[1],
};
for (i = 0; i < vi->nr_part_ids; i++) {
const struct spi_flash_part_id *part = &vi->ids[i];
if (part->id == id)
if (part->id[0] == lid[0] && part->id[1] == lid[1])
return part;
}
@@ -394,7 +398,7 @@ static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_i
}
static int find_match(const struct spi_slave *spi, struct spi_flash *flash,
uint8_t manuf_id, uint32_t id)
uint8_t manuf_id, uint16_t id[2])
{
int i;
@@ -407,7 +411,7 @@ static int find_match(const struct spi_slave *spi, struct spi_flash *flash,
if (manuf_id != vi->id)
continue;
part = find_part(vi, id & vi->match_id_mask);
part = find_part(vi, id);
if (part == NULL)
continue;
@@ -424,7 +428,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi,
int ret, i;
u8 idcode[IDCODE_LEN];
u8 manuf_id;
u32 id;
u16 id[2];
/* Read the ID codes */
ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
@@ -450,7 +454,8 @@ int spi_flash_generic_probe(const struct spi_slave *spi,
manuf_id = idcode[0];
}
id = (idcode[3] << 24) | (idcode[4] << 16) | (idcode[1] << 8) | idcode[2];
id[0] = (idcode[1] << 8) | idcode[2];
id[1] = (idcode[3] << 8) | idcode[4];
return find_match(spi, flash, manuf_id, id);
}
@@ -483,8 +488,8 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
if (flash->flags.dual_spi && spi.ctrlr->xfer_dual)
mode_string = " (Dual SPI mode)";
printk(BIOS_INFO,
"SF: Detected %s with sector size 0x%x, total 0x%x%s\n",
flash->name, flash->sector_size, flash->size, mode_string);
"SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n",
flash->vendor, flash->model, flash->sector_size, flash->size, mode_string);
if (bus == CONFIG_BOOT_DEVICE_SPI_FLASH_BUS
&& flash->size != CONFIG_ROM_SIZE) {
printk(BIOS_ERR, "SF size 0x%x does not correspond to"

12
src/drivers/spi/spi_flash_internal.h
View File

@@ -73,10 +73,12 @@ int spi_flash_cmd_read(const struct spi_flash *flash, u32 offset, size_t len, vo
int stmicro_release_deep_sleep_identify(const struct spi_slave *spi, u8 *idcode);
struct spi_flash_part_id {
/* rdid command constructs a 32-bit id using the following method
* for matching: 31 | id[3] | id[4] | id[1] | id[2] | 0 */
uint32_t id;
const char *name;
/* rdid command constructs 2x 16-bit id using the following method
* for matching after reading 5 bytes (1st byte is manuf id):
* id[0] = (id[1] << 8) | id[2]
* id[1] = (id[3] << 8) | id[4]
*/
uint16_t id[2];
/* Log based 2 total number of sectors. */
uint16_t nr_sectors_shift: 4;
uint16_t fast_read_dual_output_support : 1;
@@ -104,7 +106,7 @@ struct spi_flash_vendor_info {
uint8_t sector_size_kib_shift : 4;
uint16_t nr_part_ids;
const struct spi_flash_part_id *ids;
uint32_t match_id_mask; /* matching bytes of the id for this set*/
uint16_t match_id_mask[2]; /* matching bytes of the id for this set*/
const struct spi_flash_ops_descriptor *desc;
const struct spi_flash_protection_ops *prot_ops;
/* Returns 0 on success. !0 otherwise. */

52
src/drivers/spi/sst.c
View File

@@ -46,56 +46,56 @@
static const struct spi_flash_part_id flash_table_ai[] = {
{
.id = 0x8d,
.name = "SST25VF040B",
/* SST25VF040B */
.id[0] = 0x8d,
.nr_sectors_shift = 7,
},{
.id = 0x8e,
.name = "SST25VF080B",
/* SST25VF080B */
.id[0] = 0x8e,
.nr_sectors_shift = 8,
},{
.id = 0x80,
.name = "SST25VF080",
/* SST25VF080 */
.id[0] = 0x80,
.nr_sectors_shift = 8,
},{
.id = 0x41,
.name = "SST25VF016B",
/* SST25VF016B */
.id[0] = 0x41,
.nr_sectors_shift = 9,
},{
.id = 0x4a,
.name = "SST25VF032B",
/* SST25VF032B */
.id[0] = 0x4a,
.nr_sectors_shift = 10,
},{
.id = 0x01,
.name = "SST25WF512",
/* SST25WF512 */
.id[0] = 0x01,
.nr_sectors_shift = 4,
},{
.id = 0x02,
.name = "SST25WF010",
/* SST25WF010 */
.id[0] = 0x02,
.nr_sectors_shift = 5,
},{
.id = 0x03,
.name = "SST25WF020",
/* SST25WF020 */
.id[0] = 0x03,
.nr_sectors_shift = 6,
},{
.id = 0x04,
.name = "SST25WF040",
/* SST25WF040 */
.id[0] = 0x04,
.nr_sectors_shift = 7,
},{
.id = 0x05,
.name = "SST25WF080",
/* SST25WF080 */
.id[0] = 0x05,
.nr_sectors_shift = 8,
},{
.id = 0x14,
.name = "SST25WF080B",
/* SST25WF080B */
.id[0] = 0x14,
.nr_sectors_shift = 8,
},
};
static const struct spi_flash_part_id flash_table_pp256[] = {
{
.id = 0x4b,
.name = "SST25VF064C",
/* SST25VF064C */
.id[0] = 0x4b,
.nr_sectors_shift = 11,
},
};
@@ -254,7 +254,7 @@ static const struct spi_flash_ops_descriptor descai = {
const struct spi_flash_vendor_info spi_flash_sst_ai_vi = {
.id = VENDOR_ID_SST,
.sector_size_kib_shift = 2,
.match_id_mask = 0xff,
.match_id_mask[0] = 0xff,
.ids = flash_table_ai,
.nr_part_ids = ARRAY_SIZE(flash_table_ai),
.desc = &descai,
@@ -265,7 +265,7 @@ const struct spi_flash_vendor_info spi_flash_sst_vi = {
.id = VENDOR_ID_SST,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xff,
.match_id_mask[0] = 0xff,
.ids = flash_table_pp256,
.nr_part_ids = ARRAY_SIZE(flash_table_pp256),
.desc = &spi_flash_pp_0x20_sector_desc,

112
src/drivers/spi/stmicro.c
View File

@@ -66,142 +66,142 @@
static const struct spi_flash_part_id flash_table_se32k[] = {
{
.id = STM_ID_M25P10,
.name = "M25P10",
/* M25P10 */
.id[0] = STM_ID_M25P10,
.nr_sectors_shift = 2,
},
};
static const struct spi_flash_part_id flash_table_se64k[] = {
{
.id = STM_ID_M25P16,
.name = "M25P16",
/* M25P16 */
.id[0] = STM_ID_M25P16,
.nr_sectors_shift = 5,
},
{
.id = STM_ID_M25P20,
.name = "M25P20",
/* M25P20 */
.id[0] = STM_ID_M25P20,
.nr_sectors_shift = 2,
},
{
.id = STM_ID_M25P32,
.name = "M25P32",
/* M25P32 */
.id[0] = STM_ID_M25P32,
.nr_sectors_shift = 6,
},
{
.id = STM_ID_M25P40,
.name = "M25P40",
/* M25P40 */
.id[0] = STM_ID_M25P40,
.nr_sectors_shift = 3,
},
{
.id = STM_ID_M25P64,
.name = "M25P64",
/* M25P64 */
.id[0] = STM_ID_M25P64,
.nr_sectors_shift = 7,
},
{
.id = STM_ID_M25P80,
.name = "M25P80",
/* M25P80 */
.id[0] = STM_ID_M25P80,
.nr_sectors_shift = 4,
},
{
.id = STM_ID_M25PX80,
.name = "M25PX80",
/* M25PX80 */
.id[0] = STM_ID_M25PX80,
.nr_sectors_shift = 4,
},
{
.id = STM_ID_M25PX16,
.name = "M25PX16",
/* M25PX16 */
.id[0] = STM_ID_M25PX16,
.nr_sectors_shift = 5,
},
{
.id = STM_ID_M25PX32,
.name = "M25PX32",
/* M25PX32 */
.id[0] = STM_ID_M25PX32,
.nr_sectors_shift = 6,
},
{
.id = STM_ID_M25PX64,
.name = "M25PX64",
/* M25PX64 */
.id[0] = STM_ID_M25PX64,
.nr_sectors_shift = 7,
},
{
.id = STM_ID_M25PE80,
.name = "M25PE80",
/* M25PE80 */
.id[0] = STM_ID_M25PE80,
.nr_sectors_shift = 4,
},
{
.id = STM_ID_M25PE16,
.name = "M25PE16",
/* M25PE16 */
.id[0] = STM_ID_M25PE16,
.nr_sectors_shift = 5,
},
{
.id = STM_ID_M25PE32,
.name = "M25PE32",
/* M25PE32 */
.id[0] = STM_ID_M25PE32,
.nr_sectors_shift = 6,
},
{
.id = STM_ID_M25PE64,
.name = "M25PE64",
/* M25PE64 */
.id[0] = STM_ID_M25PE64,
.nr_sectors_shift = 7,
},
};
static const struct spi_flash_part_id flash_table_se256k[] = {
{
.id = STM_ID_M25P128,
.name = "M25P128",
/* M25P128 */
.id[0] = STM_ID_M25P128,
.nr_sectors_shift = 6,
},
};
static const struct spi_flash_part_id flash_table_sse[] = {
{
.id = STM_ID_N25Q016__3E,
.name = "N25Q016..3E",
/* N25Q016..3E */
.id[0] = STM_ID_N25Q016__3E,
.nr_sectors_shift = 9,
},
{
.id = STM_ID_N25Q032__3E,
.name = "N25Q032..3E",
/* N25Q032..3E */
.id[0] = STM_ID_N25Q032__3E,
.nr_sectors_shift = 10,
},
{
.id = STM_ID_N25Q064__3E,
.name = "N25Q064..3E",
/* N25Q064..3E */
.id[0] = STM_ID_N25Q064__3E,
.nr_sectors_shift = 11,
},
{
.id = STM_ID_N25Q128__3E,
.name = "N25Q128..3E",
/* N25Q128..3E */
.id[0] = STM_ID_N25Q128__3E,
.nr_sectors_shift = 12,
},
{
.id = STM_ID_N25Q256__3E,
.name = "N25Q256..3E",
/* N25Q256..3E */
.id[0] = STM_ID_N25Q256__3E,
.nr_sectors_shift = 13,
},
{
.id = STM_ID_N25Q016__1E,
.name = "N25Q016..1E",
/* N25Q016..1E */
.id[0] = STM_ID_N25Q016__1E,
.nr_sectors_shift = 9,
},
{
.id = STM_ID_N25Q032__1E,
.name = "N25Q032..1E",
/* N25Q032..1E */
.id[0] = STM_ID_N25Q032__1E,
.nr_sectors_shift = 10,
},
{
.id = STM_ID_N25Q064__1E,
.name = "N25Q064..1E",
/* N25Q064..1E */
.id[0] = STM_ID_N25Q064__1E,
.nr_sectors_shift = 11,
},
{
.id = STM_ID_N25Q128__1E,
.name = "N25Q128..1E",
/* N25Q128..1E */
.id[0] = STM_ID_N25Q128__1E,
.nr_sectors_shift = 12,
},
{
.id = STM_ID_N25Q256__1E,
.name = "N25Q256..1E",
/* N25Q256..1E */
.id[0] = STM_ID_N25Q256__1E,
.nr_sectors_shift = 13,
},
};
@@ -228,7 +228,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro1_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 5,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_se32k,
.nr_part_ids = ARRAY_SIZE(flash_table_se32k),
.desc = &spi_flash_pp_0xd8_sector_desc,
@@ -238,7 +238,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro2_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 6,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_se64k,
.nr_part_ids = ARRAY_SIZE(flash_table_se64k),
.desc = &spi_flash_pp_0xd8_sector_desc,
@@ -248,7 +248,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro3_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 8,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_se256k,
.nr_part_ids = ARRAY_SIZE(flash_table_se256k),
.desc = &spi_flash_pp_0xd8_sector_desc,
@@ -258,7 +258,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro4_vi = {
.id = VENDOR_ID_STMICRO,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table_sse,
.nr_part_ids = ARRAY_SIZE(flash_table_sse),
.desc = &spi_flash_pp_0x20_sector_desc,

82
src/drivers/spi/winbond.c
View File

@@ -81,141 +81,141 @@ struct status_regs {
static const struct spi_flash_part_id flash_table[] = {
{
.id = 0x2014,
.name = "W25P80",
/* W25P80 */
.id[0] = 0x2014,
.nr_sectors_shift = 8,
},
{
.id = 0x2015,
.name = "W25P16",
/* W25P16 */
.id[0] = 0x2015,
.nr_sectors_shift = 9,
},
{
.id = 0x2016,
.name = "W25P32",
/* W25P32 */
.id[0] = 0x2016,
.nr_sectors_shift = 10,
},
{
.id = 0x3014,
.name = "W25X80",
/* W25X80 */
.id[0] = 0x3014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x3015,
.name = "W25X16",
/* W25X16 */
.id[0] = 0x3015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
},
{
.id = 0x3016,
.name = "W25X32",
/* W25X32 */
.id[0] = 0x3016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
},
{
.id = 0x3017,
.name = "W25X64",
/* W25X64 */
.id[0] = 0x3017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
},
{
.id = 0x4014,
.name = "W25Q80_V",
/* W25Q80_V */
.id[0] = 0x4014,
.nr_sectors_shift = 8,
.fast_read_dual_output_support = 1,
},
{
.id = 0x4015,
.name = "W25Q16_V",
/* W25Q16_V */
.id[0] = 0x4015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x6015,
.name = "W25Q16DW",
/* W25Q16DW */
.id[0] = 0x6015,
.nr_sectors_shift = 9,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x4016,
.name = "W25Q32_V",
/* W25Q32_V */
.id[0] = 0x4016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x6016,
.name = "W25Q32DW",
/* W25Q32DW */
.id[0] = 0x6016,
.nr_sectors_shift = 10,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 3,
},
{
.id = 0x4017,
.name = "W25Q64_V",
/* W25Q64_V */
.id[0] = 0x4017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 17,
.bp_bits = 3,
},
{
.id = 0x6017,
.name = "W25Q64DW",
/* W25Q64DW */
.id[0] = 0x6017,
.nr_sectors_shift = 11,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 17,
.bp_bits = 3,
},
{
.id = 0x4018,
.name = "W25Q128_V",
/* W25Q128_V */
.id[0] = 0x4018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x6018,
.name = "W25Q128FW",
/* W25Q128FW */
.id[0] = 0x6018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x7018,
.name = "W25Q128J",
/* W25Q128J */
.id[0] = 0x7018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x8018,
.name = "W25Q128JW",
/* W25Q128JW */
.id[0] = 0x8018,
.nr_sectors_shift = 12,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 18,
.bp_bits = 3,
},
{
.id = 0x4019,
.name = "W25Q256_V",
/* W25Q256_V */
.id[0] = 0x4019,
.nr_sectors_shift = 13,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
.bp_bits = 4,
},
{
.id = 0x7019,
.name = "W25Q256J",
/* W25Q256J */
.id[0] = 0x7019,
.nr_sectors_shift = 13,
.fast_read_dual_output_support = 1,
.protection_granularity_shift = 16,
@@ -551,7 +551,7 @@ const struct spi_flash_vendor_info spi_flash_winbond_vi = {
.id = VENDOR_ID_WINBOND,
.page_size_shift = 8,
.sector_size_kib_shift = 2,
.match_id_mask = 0xffff,
.match_id_mask[0] = 0xffff,
.ids = flash_table,
.nr_part_ids = ARRAY_SIZE(flash_table),
.desc = &spi_flash_pp_0x20_sector_desc,

59
src/ec/google/chromeec/ec.c
View File

@@ -15,16 +15,18 @@
#include <stdint.h>
#include <string.h>
#include <cbmem.h>
#include <console/console.h>
#include <assert.h>
#include <bootmode.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <device/path.h>
#include <elog.h>
#include <rtc.h>
#include <stdlib.h>
#include <security/vboot/vboot_common.h>
#include <stdlib.h>
#include <timer.h>
#include "chip.h"
@@ -1419,6 +1421,57 @@ enum ec_current_image google_chromeec_get_current_image(void)
return ec_image_type;
}
int google_chromeec_get_num_pd_ports(int *num_ports)
{
struct ec_response_charge_port_count resp = {};
struct chromeec_command cmd = {
.cmd_code = EC_CMD_CHARGE_PORT_COUNT,
.cmd_version = 0,
.cmd_data_out = &resp,
.cmd_size_in = 0,
.cmd_size_out = sizeof(resp),
.cmd_dev_index = 0,
};
int rv;
rv = google_chromeec_command(&cmd);
if (rv)
return rv;
*num_ports = resp.port_count;
return 0;
}
int google_chromeec_get_pd_port_caps(int port,
struct usb_pd_port_caps *port_caps)
{
struct ec_params_get_pd_port_caps params = {
.port = port,
};
struct ec_response_get_pd_port_caps resp = {};
struct chromeec_command cmd = {
.cmd_code = EC_CMD_GET_PD_PORT_CAPS,
.cmd_version = 0,
.cmd_data_in = &params,
.cmd_size_in = sizeof(params),
.cmd_data_out = &resp,
.cmd_size_out = sizeof(resp),
.cmd_dev_index = 0,
};
int rv;
rv = google_chromeec_command(&cmd);
if (rv)
return rv;
port_caps->power_role_cap = resp.pd_power_role_cap;
port_caps->try_power_role_cap = resp.pd_try_power_role_cap;
port_caps->data_role_cap = resp.pd_data_role_cap;
port_caps->port_location = resp.pd_port_location;
return 0;
}
void google_chromeec_init(void)
{
google_chromeec_log_uptimeinfo();

30
src/ec/google/chromeec/ec.h
View File

@@ -299,4 +299,34 @@ int google_chromeec_get_protocol_info(
*/
int google_chromeec_get_cmd_versions(int command, uint32_t *pmask);
/**
* Get number of PD-capable USB ports from EC.
*
* @param *num_ports If successful, num_ports is the number
* of PD-capable USB ports according to the EC.
* @return 0 on success, -1 on error
*/
int google_chromeec_get_num_pd_ports(int *num_ports);
/* Structure representing the capabilities of a USB-PD port */
struct usb_pd_port_caps {
enum ec_pd_power_role_caps power_role_cap;
enum ec_pd_try_power_role_caps try_power_role_cap;
enum ec_pd_data_role_caps data_role_cap;
enum ec_pd_port_location port_location;
};
/**
* Get role-based capabilities for a USB-PD port
*
* @param port Which port to get information about
* @param *power_role_cap The power-role capabillity of the port
* @param *try_power_role_cap The Try-power-role capability of the port
* @param *data_role_cap The data role capability of the port
* @param *port_location Location of the port on the device
* @return 0 on success, -1 on error
*/
int google_chromeec_get_pd_port_caps(int port,
struct usb_pd_port_caps *port_caps);
#endif /* _EC_GOOGLE_CHROMEEC_EC_H */

68
src/ec/google/chromeec/ec_commands.h
View File

@@ -5852,6 +5852,74 @@ struct ec_response_locate_chip {
*/
#define EC_CMD_REBOOT_AP_ON_G3 0x0127
/*****************************************************************************/
/* Get PD port capabilities
*
* Returns the following static *capabilities* of the given port:
* 1) Power role: source, sink, or dual. It is not anticipated that
* future CrOS devices would ever be only a source, so the options are
* sink or dual.
* 2) Try-power role: source, sink, or none (practically speaking, I don't
* believe any CrOS device would support Try.SNK, so this would be source
* or none).
* 3) Data role: dfp, ufp, or dual. This will probably only be DFP or dual
* for CrOS devices.
*/
#define EC_CMD_GET_PD_PORT_CAPS 0x0128
enum ec_pd_power_role_caps {
EC_PD_POWER_ROLE_SOURCE = 0,
EC_PD_POWER_ROLE_SINK = 1,
EC_PD_POWER_ROLE_DUAL = 2,
};
enum ec_pd_try_power_role_caps {
EC_PD_TRY_POWER_ROLE_NONE = 0,
EC_PD_TRY_POWER_ROLE_SINK = 1,
EC_PD_TRY_POWER_ROLE_SOURCE = 2,
};
enum ec_pd_data_role_caps {
EC_PD_DATA_ROLE_DFP = 0,
EC_PD_DATA_ROLE_UFP = 1,
EC_PD_DATA_ROLE_DUAL = 2,
};
/* From: power_manager/power_supply_properties.proto */
enum ec_pd_port_location {
/* The location of the port is unknown, or there's only one port. */
EC_PD_PORT_LOCATION_UNKNOWN = 0,
/*
* Various positions on the device. The first word describes the side of
* the device where the port is located while the second clarifies the
* position. For example, LEFT_BACK means the farthest-back port on the
* left side, while BACK_LEFT means the leftmost port on the back of the
* device.
*/
EC_PD_PORT_LOCATION_LEFT = 1,
EC_PD_PORT_LOCATION_RIGHT = 2,
EC_PD_PORT_LOCATION_BACK = 3,
EC_PD_PORT_LOCATION_FRONT = 4,
EC_PD_PORT_LOCATION_LEFT_FRONT = 5,
EC_PD_PORT_LOCATION_LEFT_BACK = 6,
EC_PD_PORT_LOCATION_RIGHT_FRONT = 7,
EC_PD_PORT_LOCATION_RIGHT_BACK = 8,
EC_PD_PORT_LOCATION_BACK_LEFT = 9,
EC_PD_PORT_LOCATION_BACK_RIGHT = 10,
};
struct ec_params_get_pd_port_caps {
uint8_t port; /* Which port to interrogate */
} __ec_align1;
struct ec_response_get_pd_port_caps {
uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */
uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */
uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */
uint8_t pd_port_location; /* enum ec_pd_port_location */
} __ec_align1;
/*****************************************************************************/
/* The command range 0x200-0x2FF is reserved for Rotor. */

15
src/ec/google/wilco/chip.c
View File

@@ -16,10 +16,13 @@
#include <arch/acpi.h>
#include <arch/acpi_device.h>
#include <arch/acpigen.h>
#include <arch/cpu.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/pnp.h>
#include <ec/acpi/ec.h>
#include <intelblocks/cpulib.h>
#include <pc80/keyboard.h>
#include <stdint.h>
@@ -124,6 +127,14 @@ static void wilco_ec_resume(void *unused)
}
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, wilco_ec_resume, NULL);
static int wilco_set_cpu_id(void)
{
uint32_t cpu_phy_cores, cpu_virtual_cores;
cpu_read_topology(&cpu_phy_cores, &cpu_virtual_cores);
return wilco_ec_set_cpuid(cpu_get_cpuid(), cpu_phy_cores, 0);
}
static void wilco_ec_init(struct device *dev)
{
if (!dev->enabled)
@@ -153,6 +164,10 @@ static void wilco_ec_init(struct device *dev)
/* Turn on camera power */
wilco_ec_send(KB_CAMERA, CAMERA_ON);
/* Set cpu id and phy cores */
if (wilco_set_cpu_id())
printk(BIOS_ERR, "EC: use default cpu power table\n");
}
static void wilco_ec_resource(struct device *dev, int index,

10
src/include/cpu/x86/msr.h
View File

@@ -16,6 +16,7 @@
/* Page attribute type MSR */
#define TSC_MSR 0x10
#define IA32_PLATFORM_ID 0x17
#define IA32_APIC_BASE_MSR_INDEX 0x1B
#define IA32_FEATURE_CONTROL 0x3a
#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
#define FEATURE_ENABLE_VMX (1 << 2)
@@ -30,6 +31,10 @@
#define IA32_BIOS_SIGN_ID 0x8b
#define IA32_MPERF 0xe7
#define IA32_APERF 0xe8
/* STM */
#define IA32_SMM_MONITOR_CTL_MSR 0x9B
#define SMBASE_RO_MSR 0x98
#define IA32_SMM_MONITOR_VALID (1 << 0)
#define IA32_MCG_CAP 0x179
#define MCG_CTL_P (1 << 3)
#define MCA_BANKS_MASK 0xff
@@ -45,6 +50,9 @@
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define SMRR_PHYSBASE_MSR 0x1F2
#define SMRR_PHYSMASK_MSR 0x1F3
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_PAT 0x277
#define IA32_MC0_CTL 0x400
#define IA32_MC0_STATUS 0x401
@@ -65,6 +73,8 @@
#define MCA_STATUS_LO_ERRCODE_EXT_SH 16
#define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH)
#define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0)
#define IA32_VMX_BASIC_MSR 0x480
#define IA32_VMX_MISC_MSR 0x485
#define MC0_ADDR 0x402
#define MC0_MISC 0x403
#define MC0_CTL_MASK 0xC0010044

3
src/include/cpu/x86/smm.h
View File

@@ -64,6 +64,9 @@ extern unsigned char _binary_smm_end[];
struct smm_runtime {
u32 smbase;
u32 save_state_size;
u32 num_cpus;
/* STM's 32bit entry into SMI handler */
u32 start32_offset;
/* The apic_id_to_cpu provides a mapping from APIC id to CPU number.
* The CPU number is indicated by the index into the array by matching
* the default APIC id and value at the index. The stub loader

7
src/include/device/device.h
View File

@@ -119,9 +119,12 @@ struct device {
unsigned int initialized : 1; /* 1 if we have initialized the device */
unsigned int on_mainboard : 1;
unsigned int disable_pcie_aspm : 1;
unsigned int hidden : 1; /* set if we should hide from UI */
/* set if we should hide from UI */
unsigned int hidden : 1;
/* set if this device is used even in minimum PCI cases */
unsigned int mandatory : 1;
u8 command;
uint16_t hotplug_buses; /* hotplug buses to allocate */
uint16_t hotplug_buses; /* Number of hotplug buses to allocate */
/* Base registers for this device. I/O, MEM and Expansion ROM */
DEVTREE_CONST struct resource *resource_list;

2
src/include/fmap.h
View File

@@ -16,8 +16,8 @@
#ifndef _FMAP_H_
#define _FMAP_H_
#include <commonlib/bsd/fmap_serialized.h>
#include <commonlib/region.h>
#include <commonlib/fmap_serialized.h>
/* Locate the named area in the fmap and fill in a region device representing
* that area. The region is a sub-region of the readonly boot media. Return

1
src/include/spi_flash.h
View File

@@ -104,7 +104,6 @@ struct spi_flash {
};
} flags;
u16 model;
const char *name;
u32 size;
u32 sector_size;
u32 page_size;

33
src/include/types.h
View File

@@ -17,6 +17,7 @@
#define __TYPES_H
/* types.h is supposed to provide the standard headers defined in here: */
#include <commonlib/bsd/cb_err.h>
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
@@ -30,36 +31,4 @@
#define BIT(x) (1ul << (x))
#endif
/**
* coreboot error codes
*
* When building functions that return a status or an error code, use cb_err as
* the return type. When failure reason needs to be communicated by the return
* value, define a it here. Start new enum groups with values in decrements of
* 100.
*/
enum cb_err {
CB_SUCCESS = 0, /**< Call completed successfully */
CB_ERR = -1, /**< Generic error code */
CB_ERR_ARG = -2, /**< Invalid argument */
/* NVRAM/CMOS errors */
CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */
CB_CMOS_LAYOUT_NOT_FOUND = -101, /**< Layout file not found */
CB_CMOS_OPTION_NOT_FOUND = -102, /**< Option string not found */
CB_CMOS_ACCESS_ERROR = -103, /**< CMOS access error */
CB_CMOS_CHECKSUM_INVALID = -104, /**< CMOS checksum is invalid */
/* Keyboard test failures */
CB_KBD_CONTROLLER_FAILURE = -200,
CB_KBD_INTERFACE_FAILURE = -201,
/* I2C controller failures */
CB_I2C_NO_DEVICE = -300, /**< Device is not responding */
CB_I2C_BUSY = -301, /**< Device tells it's busy */
CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave
device response, try again? */
CB_I2C_TIMEOUT = -303, /**< Transmission timed out */
};
#endif /* __TYPES_H */

2
src/lib/cbfs.c
View File

@@ -20,7 +20,7 @@
#include <stdlib.h>
#include <boot_device.h>
#include <cbfs.h>
#include <commonlib/compression.h>
#include <commonlib/bsd/compression.h>
#include <endian.h>
#include <lib.h>
#include <symbols.h>

2
src/lib/decompressor.c
View File

@@ -15,7 +15,7 @@
*/
#include <bootblock_common.h>
#include <commonlib/compression.h>
#include <commonlib/bsd/compression.h>
#include <delay.h>
#include <program_loading.h>
#include <symbols.h>

2
src/lib/fit.c
View File

@@ -16,6 +16,7 @@
*/
#include <assert.h>
#include <cbfs.h>
#include <console/console.h>
#include <ctype.h>
#include <endian.h>
@@ -27,7 +28,6 @@
#include <memrange.h>
#include <fit.h>
#include <boardid.h>
#include <commonlib/cbfs_serialized.h>
#include <commonlib/stdlib.h>
static struct list_node image_nodes;

4
src/lib/fit_payload.c
View File

@@ -15,6 +15,8 @@
* GNU General Public License for more details.
*/
#include <cbfs.h>
#include <commonlib/bsd/compression.h>
#include <console/console.h>
#include <bootmem.h>
#include <cbmem.h>
@@ -25,8 +27,6 @@
#include <program_loading.h>
#include <timestamp.h>
#include <string.h>
#include <commonlib/cbfs_serialized.h>
#include <commonlib/compression.h>
#include <lib.h>
#include <fit_payload.h>
#include <boardid.h>

1
src/lib/fmap.c
View File

@@ -17,7 +17,6 @@
#include <cbmem.h>
#include <console/console.h>
#include <fmap.h>
#include <commonlib/fmap_serialized.h>
#include <stddef.h>
#include <string.h>
#include <symbols.h>

2
src/lib/selfboot.c
View File

@@ -15,7 +15,7 @@
* GNU General Public License for more details.
*/
#include <commonlib/compression.h>
#include <commonlib/bsd/compression.h>
#include <commonlib/endian.h>
#include <console/console.h>
#include <stdint.h>

16
src/mainboard/amd/olivehill/BiosCallOuts.c
View File

@@ -95,13 +95,13 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] =
/* Olivehill Hardware Monitor Fan Control
* Hardware limitation:
* HWM failed to read the input temperture vi I2C,
* if other software switch the I2C switch by mistake or intention.
* We recommend to using IMC to control Fans, instead of HWM.
* HWM failed to read the input temperature via I2C,
* if other software switches the I2C switch by mistake or intention.
* We recommend using IMC to control Fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
/* Enable IMC fan control, the recommended way */
if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
@@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
* so we remove it from AGESA code. Please Seee FchInitLateHwm.
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
* So we remove it from AGESA code. Please See FchInitLateHwm.
*/
} else {
/* HWM fan control, the way not recommand */
/* HWM fan control, the way not recommended */
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */

16
src/mainboard/amd/parmer/BiosCallOuts.c
View File

@@ -95,13 +95,13 @@ static const CODEC_TBL_LIST CodecTableList[] =
/* Parmer Hardware Monitor Fan Control
* Hardware limitation:
* HWM failed to read the input temperture vi I2C,
* if other software switch the I2C switch by mistake or intention.
* We recommend to using IMC to control Fans, instead of HWM.
* HWM failed to read the input temperature via I2C,
* if other software switches the I2C switch by mistake or intention.
* We recommend using IMC to control Fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
/* Enable IMC fan control, the recommended way */
if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
@@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
* so we remove it from AGESA code. Please Seee FchInitLateHwm.
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
* So we remove it from AGESA code. Please See FchInitLateHwm.
*/
} else {
/* HWM fan control, the way not recommand */
/* HWM fan control, the way not recommended */
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */

18
src/mainboard/amd/thatcher/BiosCallOuts.c
View File

@@ -93,15 +93,15 @@ static const CODEC_TBL_LIST CodecTableList[] =
#define FREQ_14HZ 0xFE
#define FREQ_11HZ 0xFF
/* Parmer Hardware Monitor Fan Control
/* Hardware Monitor Fan Control
* Hardware limitation:
* HWM failed to read the input temperture vi I2C,
* if other software switch the I2C switch by mistake or intention.
* We recommend to using IMC to control Fans, instead of HWM.
* HWM failed to read the input temperature via I2C,
* if other software switches the I2C switch by mistake or intention.
* We recommend using IMC to control Fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
/* Enable IMC fan control, the recommended way */
if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
@@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
* so we remove it from AGESA code. Please Seee FchInitLateHwm.
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
* So we remove it from AGESA code. Please See FchInitLateHwm.
*/
} else {
/* HWM fan control, the way not recommand */
/* HWM fan control, the way not recommended */
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */

18
src/mainboard/bap/ode_e20XX/BiosCallOuts.c
View File

@@ -97,15 +97,15 @@ static const CODEC_TBL_LIST CodecTableList[] =
#define FREQ_14HZ 0xFE
#define FREQ_11HZ 0xFF
/* Hardware Monitor Fan Control
/* Hardware Monitor Fan Control
* Hardware limitation:
* HWM failed to read the input temperture vi I2C,
* if other software switch the I2C switch by mistake or intention.
* We recommend to using IMC to control Fans, instead of HWM.
* HWM failed to read the input temperature via I2C,
* if other software switches the I2C switch by mistake or intention.
* We recommend using IMC to control Fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
/* Enable IMC fan control, the recommended way */
if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
@@ -160,12 +160,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
* so we remove it from AGESA code. Please Seee FchInitLateHwm.
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
* So we remove it from AGESA code. Please See FchInitLateHwm.
*/
} else {
/* HWM fan control, the way not recommand */
/* HWM fan control, the way not recommended */
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */

18
src/mainboard/biostar/a68n_5200/BiosCallOuts.c
View File

@@ -93,15 +93,15 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] =
#define FREQ_14HZ 0xFE
#define FREQ_11HZ 0xFF
/* Olivehill Hardware Monitor Fan Control
/* Hardware Monitor Fan Control
* Hardware limitation:
* HWM failed to read the input temperture vi I2C,
* if other software switch the I2C switch by mistake or intention.
* We recommend to using IMC to control Fans, instead of HWM.
* HWM failed to read the input temperature via I2C,
* if other software switches the I2C switch by mistake or intention.
* We recommend using IMC to control Fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
/* Enable IMC fan control, the recommended way */
if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
@@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
* so we remove it from AGESA code. Please Seee FchInitLateHwm.
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
* So we remove it from AGESA code. Please See FchInitLateHwm.
*/
} else {
/* HWM fan control, the way not recommand */
/* HWM fan control, the way not recommended */
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */

4
src/mainboard/emulation/qemu-q35/devicetree.cb
View File

@@ -5,10 +5,10 @@ chip mainboard/emulation/qemu-q35
end
end
device domain 0 on
device pci 0.0 on end # northbridge (q35)
device pci 0.0 mandatory end # northbridge (q35)
chip southbridge/intel/i82801ix
# present unconditionally
device pci 1f.0 on end # LPC
device pci 1f.0 mandatory end # LPC
device pci 1f.2 on end # SATA
device pci 1f.3 on end # SMBus

1
src/mainboard/facebook/monolith/Kconfig
View File

@@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_TPM2
select MAINBOARD_USES_IFD_GBE_REGION
select INTEL_GMA_HAVE_VBT
select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE
config CBFS_SIZE
hex "CBFS_SIZE"

25
src/mainboard/facebook/monolith/acpi/superio.asl
View File

@@ -43,3 +43,28 @@ Device (COM1) {
EndDependentFn ()
})
}
Device (COM2) {
Name (_HID, EISAID ("PNP0501"))
Name (_UID, 2)
Method (_STA, 0, NotSerialized)
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate ()
{
FixedIO (0x02F8, 0x08)
IRQNoFlags () {3}
})
Name (_PRS, ResourceTemplate ()
{
StartDependentFn (0, 0) {
FixedIO (0x02F8, 0x08)
IRQNoFlags () {3}
}
EndDependentFn ()
})
}

11
src/mainboard/facebook/monolith/com_init.c
View File

@@ -19,11 +19,14 @@
#include <device/pnp_ops.h>
#include "onboard.h"
#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
#define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */
#define SERIAL_DEV2 PNP_DEV(ITE8528_CMD_PORT, 2) /* ITE8528 UART2 */
void bootblock_mainboard_early_init(void)
{
/* Enable the serial port inside the EC */
pnp_set_logical_device(SERIAL_DEV);
pnp_set_enable(SERIAL_DEV, 1);
/* Enable the serial ports inside the EC */
pnp_set_logical_device(SERIAL_DEV1);
pnp_set_enable(SERIAL_DEV1, 1);
pnp_set_logical_device(SERIAL_DEV2);
pnp_set_enable(SERIAL_DEV2, 1);
}

18
src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c
View File

@@ -93,15 +93,15 @@ static const CODEC_TBL_LIST CodecTableList[] =
#define FREQ_14HZ 0xFE
#define FREQ_11HZ 0xFF
/* Hardware Monitor Fan Control
/* Hardware Monitor Fan Control
* Hardware limitation:
* HWM failed to read the input temperture vi I2C,
* if other software switch the I2C switch by mistake or intention.
* We recommend to using IMC to control Fans, instead of HWM.
* HWM failed to read the input temperature via I2C,
* if other software switches the I2C switch by mistake or intention.
* We recommend using IMC to control Fans, instead of HWM.
*/
static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
{
/* Enable IMC fan control. the recommand way */
/* Enable IMC fan control, the recommended way */
if (CONFIG(HUDSON_IMC_FWM)) {
imc_reg_init();
@@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
* AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it.
* so we remove it from AGESA code. Please Seee FchInitLateHwm.
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage,
* AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it.
* So we remove it from AGESA code. Please See FchInitLateHwm.
*/
} else {
/* HWM fan control, the way not recommand */
/* HWM fan control, the way not recommended */
FchParams->Imc.ImcEnable = FALSE;
FchParams->Hwm.HwMonitorEnable = TRUE;
FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */

1
src/mainboard/google/dedede/Kconfig
View File

@@ -1,6 +1,7 @@
config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES

1
src/mainboard/google/dedede/Makefile.inc
View File

@@ -8,6 +8,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-y += ec.c
ramstage-y += board_info.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c

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