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mb/,sb/intel/i82801gx: Merge ide_legacy_combined into sata_mode

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Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.

Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber 2019-07-20 17:03:56 +02:00 committed by Patrick Georgi
parent 0db6e7569d
commit ae317695e3
9 changed files with 3 additions and 9 deletions
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1
src/mainboard/asus/p5gc-mx/devicetree.cb
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@ -50,7 +50,6 @@ chip northbridge/intel/i945
register "gpe0_en" = "0"
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"

2
src/mainboard/getac/p470/devicetree.cb
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@ -54,7 +54,7 @@ chip northbridge/intel/i945
register "gpe0_en" = "0x00800106"
register "alt_gp_smi_en" = "0x0100"
register "ide_legacy_combined" = "0x1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"

1
src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
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@ -73,7 +73,6 @@ chip northbridge/intel/i945
register "gpe0_en" = "0"
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "c3_latency" = "85"

1
src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
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@ -45,7 +45,6 @@ chip northbridge/intel/x4x # Northbridge
register "pirqf_routing" = "0x0b"
register "pirqg_routing" = "0x0b"
register "pirqh_routing" = "0x0b"
register "ide_legacy_combined" = "0x0" # Combined mode broken
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "sata_ports_implemented" = "0x3"

1
src/mainboard/ibase/mb899/devicetree.cb
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@ -33,7 +33,6 @@ chip northbridge/intel/i945
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"

1
src/mainboard/intel/d945gclf/devicetree.cb
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@ -47,7 +47,6 @@ chip northbridge/intel/i945
register "gpi13_routing" = "1"
register "gpe0_en" = "0x20000601"
register "ide_legacy_combined" = "0x0"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"
register "c3_latency" = "85"

2
src/mainboard/kontron/986lcd-m/devicetree.cb
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@ -33,7 +33,7 @@ chip northbridge/intel/i945
# 2 SCI (if corresponding GPIO_EN bit is also set)
register "gpi13_routing" = "1"
register "ide_legacy_combined" = "0x1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x1"
register "c3_latency" = "85"

2
src/mainboard/roda/rk886ex/devicetree.cb
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@ -58,7 +58,7 @@ chip northbridge/intel/i945
register "docking_supported" = "1"
register "p_cnt_throttling_supported" = "1"
register "ide_legacy_combined" = "0x1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED"
register "ide_enable_primary" = "0x1"
register "ide_enable_secondary" = "0x0"

1
src/southbridge/intel/i82801gx/chip.h
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@ -68,7 +68,6 @@ struct southbridge_intel_i82801gx_config {
uint16_t alt_gp_smi_en;
/* IDE configuration */
uint32_t ide_legacy_combined;
uint32_t ide_enable_primary;
uint32_t ide_enable_secondary;
enum sata_mode sata_mode;