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mb/system76/tgl-u: lemp10: Re-add CPU PCIe RTD3

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Tested with the following drives:

- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E-00BCA0)
- WD Blue SN580 (WDS500G2B0C-00PXH0)
- WD Green SN350 (WDS240G2G0C-00AJM0)

Test:

- PCH asserts `SLP_S0#` during suspend (power LED blinks)
- `slp_s0_residency_usec` increases after suspend

Change-Id: I8e2d23fff9c89aa1364c5f982d227ec52e3ac8a2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-12-29 13:07:30 -07:00
committed by Tim Crawford
parent ddfd79d8c7
commit b3e9fbe971
1 changed files with 7 additions and 1 deletions
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8
src/mainboard/system76/tgl-u/variants/lemp10/overridetree.cb
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@@ -22,6 +22,12 @@ chip soc/intel/tigerlake
# Despite the name, SSD2_CLKREQ# is used for SSD1
register "PcieClkSrcUsage[3]" = "0x40"
register "PcieClkSrcClkReq[3]" = "3"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C13)" # SSD1_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # GPP_C12_RTD3 (labeled incorrectly)
register "srcclk_pin" = "3" # SSD2_CLKREQ#
device generic 0 on end
end
end
device ref north_xhci on # J_TYPEC1
register "UsbTcPortEn" = "1"
@@ -135,7 +141,7 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_DN#
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" # GPP_D13_RTD3 (labeled incorrectly)
register "srcclk_pin" = "0"
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end