src/southbridge: Code formating

Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)

src/southbridge/amd/agesa/hudson/acpi/fch.asl

@@ -183,9 +183,9 @@ Method(_INI, 0) {
 
 Method(OSFL, 0){
 
-	if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
+	if (LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
 
-	if(CondRefOf(\_OSI))
+	if (CondRefOf(\_OSI))
 	{
 		Store(1, OSVR)					/* Assume some form of XP */
 		if (\_OSI("Windows 2006"))		/* Vista */

src/southbridge/amd/amd8111/acpi.c

@@ -152,7 +152,7 @@ static void acpi_init(struct device *dev)
 	/* Throttle the CPU speed down for testing */
 	on = SLOW_CPU_OFF;
 	get_option(&on, "slow_cpu");
-	if(on) {
+	if (on) {
 		pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
 		outl(((on<<1)+0x10)  ,(pm10_bar + 0x10));
 		inl(pm10_bar + 0x10);

src/southbridge/amd/amd8111/amd8111_smbus.h

@@ -26,11 +26,11 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 		if ((val & 0x800) == 0) {
 			break;
 		}
-		if(loops == (SMBUS_TIMEOUT / 2)) {
+		if (loops == (SMBUS_TIMEOUT / 2)) {
 			outw(inw(smbus_io_base + SMBGSTATUS),
 				smbus_io_base + SMBGSTATUS);
 		}
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
@@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 		if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
 			break;
 		}
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
 
@@ -267,11 +267,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned
 	}
 
 	/* read data block */
-	for(i=0; i<msglen && i<bytes; i++) {
+	for (i=0; i<msglen && i<bytes; i++) {
 		buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
 	}
 	/* empty fifo */
-	while(bytes++<msglen) {
+	while (bytes++<msglen) {
 		inw(smbus_io_base + SMBHSTFIFO);
 	}
 
@@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne
 	outw(bytes, smbus_io_base + SMBHSTDAT);
 
 	/* set the data block */
-	for(i=0; i<bytes; i++) {
+	for (i=0; i<bytes; i++) {
 		outw(buf[i], smbus_io_base + SMBHSTFIFO);
 	}
 

src/southbridge/amd/amd8111/early_ctrl.c

@@ -4,16 +4,16 @@
 /* by yhlu 2005.10 */
 static unsigned get_sbdn(unsigned bus)
 {
-        device_t dev;
+	device_t dev;
 
-        /* Find the device.
+	/* Find the device.
-         * There can only be one 8111 on a hypertransport chain/bus.
+	 * There can only be one 8111 on a hypertransport chain/bus.
-         */
+	 */
-        dev = pci_locate_device_on_bus(
+	dev = pci_locate_device_on_bus(
-                PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
+		PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
-                bus);
+		bus);
 
-        return (dev>>15) & 0x1f;
+	return (dev>>15) & 0x1f;
 
 }
 
@@ -40,34 +40,34 @@ static void enable_cf9(void)
 
 void hard_reset(void)
 {
-        set_bios_reset();
+	set_bios_reset();
-        /* reset */
+	/* reset */
-        enable_cf9();
+	enable_cf9();
-        outb(0x0e, 0x0cf9); // make sure cf9 is enabled
+	outb(0x0e, 0x0cf9); // make sure cf9 is enabled
 }
 
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 {
-        device_t dev;
+	device_t dev;
 
 	dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
 
-        pci_write_config8(dev, 0x74, 4);
+	pci_write_config8(dev, 0x74, 4);
 
-        /* set VFSMAF ( VID/FID System Management Action Field) to 2 */
+	/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
-        pci_write_config32(dev, 0x70, 2<<12);
+	pci_write_config32(dev, 0x70, 2<<12);
 
 }
 
 static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
 {
-        device_t dev;
+	device_t dev;
 
 	dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
 
-        /* Reset */
+	/* Reset */
-        set_bios_reset();
+	set_bios_reset();
-        pci_write_config8(dev, 0x47, 1);
+	pci_write_config8(dev, 0x47, 1);
 
 }
 

src/southbridge/amd/amd8111/ide.c

@@ -33,8 +33,8 @@ static void ide_init(struct device *dev)
 	pci_write_config16(dev, 0x40, word);
 
 
-        byte = 0x20 ; // Latency: 64-->32
+	byte = 0x20 ; // Latency: 64-->32
-        pci_write_config8(dev, 0xd, byte);
+	pci_write_config8(dev, 0xd, byte);
 
 	word = 0x0f;
 	pci_write_config16(dev, 0x42, word);

src/southbridge/amd/amd8111/reset.c

@@ -12,26 +12,26 @@
 
 static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
 {
-        unsigned addr;
+	unsigned addr;
-        addr = (dev>>4) | where;
+	addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(0x80000000 | (addr & ~3), 0xCF8);
-        outb(value, 0xCFC + (addr & 3));
+	outb(value, 0xCFC + (addr & 3));
 }
 
 static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
 {
 	unsigned addr;
-        addr = (dev>>4) | where;
+	addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(0x80000000 | (addr & ~3), 0xCF8);
-        outl(value, 0xCFC);
+	outl(value, 0xCFC);
 }
 
 static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
 {
 	unsigned addr;
-        addr = (dev>>4) | where;
+	addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(0x80000000 | (addr & ~3), 0xCF8);
-        return inl(0xCFC);
+	return inl(0xCFC);
 }
 
 #define PCI_DEV_INVALID (0xffffffffU)
@@ -40,7 +40,7 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
 	pci_devfn_t dev, last;
 	dev = PCI_DEV(bus, 0, 0);
 	last = PCI_DEV(bus, 31, 7);
-	for(; dev <= last; dev += PCI_DEV(0,0,1)) {
+	for (; dev <= last; dev += PCI_DEV(0,0,1)) {
 		unsigned int id;
 		id = pci_read_config32(dev, 0);
 		if (id == pci_id) {

src/southbridge/amd/amd8131/bridge.c

@@ -19,8 +19,7 @@ static void amd8131_walk_children(struct bus *bus,
 	void (*visit)(device_t dev, void *ptr), void *ptr)
 {
 	device_t child;
-	for(child = bus->children; child; child = child->sibling)
+	for (child = bus->children; child; child = child->sibling) {
-	{
 		if (child->path.type != DEVICE_PATH_PCI) {
 			continue;
 		}
@@ -72,7 +71,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
 	sibs = info->master_devices - 1;
 	/* Count how many sibling functions this device has */
 	sib_funcs = 0;
-	for(sib = dev->bus->children; sib; sib = sib->sibling) {
+	for (sib = dev->bus->children; sib; sib = sib->sibling) {
 		if (sib == dev) {
 			continue;
 		}
@@ -258,7 +257,7 @@ static void amd8131_scan_bus(struct bus *bus,
 	/* Don't allow the 8131 or any of it's parent busses to
 	 * implement relaxed ordering.  Errata #58
 	 */
-	for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
+	for (pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
 		printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
 			bus_path(pbus));
 		pbus->disable_relaxed_ordering = 1;
@@ -280,57 +279,57 @@ static void amd8131_pcix_init(device_t dev)
 
 	/* Enable memory write and invalidate ??? */
 	byte = pci_read_config8(dev, 0x04);
-        byte |= 0x10;
+	byte |= 0x10;
-        pci_write_config8(dev, 0x04, byte);
+	pci_write_config8(dev, 0x04, byte);
 
 	/* Set drive strength */
 	word = pci_read_config16(dev, 0xe0);
-        word = 0x0404;
+	word = 0x0404;
-        pci_write_config16(dev, 0xe0, word);
+	pci_write_config16(dev, 0xe0, word);
 	word = pci_read_config16(dev, 0xe4);
-        word = 0x0404;
+	word = 0x0404;
-        pci_write_config16(dev, 0xe4, word);
+	pci_write_config16(dev, 0xe4, word);
 
 	/* Set impedance */
 	word = pci_read_config16(dev, 0xe8);
-        word = 0x0404;
+	word = 0x0404;
-        pci_write_config16(dev, 0xe8, word);
+	pci_write_config16(dev, 0xe8, word);
 
 	/* Set discard unrequested prefetch data */
 	/* Errata #51 */
 	word = pci_read_config16(dev, 0x4c);
-        word |= 1;
+	word |= 1;
-        pci_write_config16(dev, 0x4c, word);
+	pci_write_config16(dev, 0x4c, word);
 
 	/* Set split transaction limits */
 	word = pci_read_config16(dev, 0xa8);
-        pci_write_config16(dev, 0xaa, word);
+	pci_write_config16(dev, 0xaa, word);
 	word = pci_read_config16(dev, 0xac);
-        pci_write_config16(dev, 0xae, word);
+	pci_write_config16(dev, 0xae, word);
 
 	/* Set up error reporting, enable all */
 	/* system error enable */
 	dword = pci_read_config32(dev, 0x04);
-        dword |= (1<<8);
+	dword |= (1<<8);
-        pci_write_config32(dev, 0x04, dword);
+	pci_write_config32(dev, 0x04, dword);
 
 	/* system and error parity enable */
 	dword = pci_read_config32(dev, 0x3c);
-        dword |= (3<<16);
+	dword |= (3<<16);
-        pci_write_config32(dev, 0x3c, dword);
+	pci_write_config32(dev, 0x3c, dword);
 
 	/* NMI enable */
 	nmi_option = NMI_OFF;
 	get_option(&nmi_option, "nmi");
-	if(nmi_option) {
+	if (nmi_option) {
 		dword = pci_read_config32(dev, 0x44);
-        	dword |= (1<<0);
+		dword |= (1<<0);
-        	pci_write_config32(dev, 0x44, dword);
+		pci_write_config32(dev, 0x44, dword);
 	}
 
 	/* Set up CRC flood enable */
 	dword = pci_read_config32(dev, 0xc0);
-	if(dword) {  /* do device A only */
+	if (dword) {  /* do device A only */
 		dword = pci_read_config32(dev, 0xc4);
 		dword |= (1<<1);
 		pci_write_config32(dev, 0xc4, dword);
@@ -377,22 +376,22 @@ static void bridge_set_resources(struct device *dev)
 
 static struct device_operations pcix_ops  = {
 #if BRIDGE_40_BIT_SUPPORT
-        .read_resources   = bridge_read_resources,
+	.read_resources   = bridge_read_resources,
-        .set_resources    = bridge_set_resources,
+	.set_resources    = bridge_set_resources,
 #else
-        .read_resources   = pci_bus_read_resources,
+	.read_resources   = pci_bus_read_resources,
-        .set_resources    = pci_dev_set_resources,
+	.set_resources    = pci_dev_set_resources,
 #endif
 	.enable_resources = pci_bus_enable_resources,
-        .init             = amd8131_pcix_init,
+	.init             = amd8131_pcix_init,
-        .scan_bus         = amd8131_scan_bridge,
+	.scan_bus         = amd8131_scan_bridge,
 	.reset_bus        = pci_bus_reset,
 };
 
 static const struct pci_driver pcix_driver __pci_driver = {
-        .ops    = &pcix_ops,
+	.ops    = &pcix_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = 0x7450,
+	.device = 0x7450,
 };
 
 

src/southbridge/amd/amd8132/bridge.c

@@ -32,8 +32,7 @@ static void amd8132_walk_children(struct bus *bus,
 	void (*visit)(device_t dev, void *ptr), void *ptr)
 {
 	device_t child;
-	for(child = bus->children; child; child = child->sibling)
+	for (child = bus->children; child; child = child->sibling) {
-	{
 		if (child->path.type != DEVICE_PATH_PCI) {
 			continue;
 		}
@@ -126,11 +125,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
 		cmd |= max_tran << 4;
 	}
 
-        /* Don't attempt to handle PCI-X errors */
+	/* Don't attempt to handle PCI-X errors */
-        cmd &= ~PCI_X_CMD_DPERR_E;
+	cmd &= ~PCI_X_CMD_DPERR_E;
-        if (orig_cmd != cmd) {
+	if (orig_cmd != cmd) {
-                pci_write_config16(dev, cap + PCI_X_CMD, cmd);
+		pci_write_config16(dev, cap + PCI_X_CMD, cmd);
-        }
+	}
 
 
 }
@@ -203,18 +202,18 @@ static void amd8132_pcix_init(device_t dev)
 	unsigned chip_rev;
 
 	/* Find the revision of the 8132 */
-        chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+	chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
 
 	/* Enable memory write and invalidate ??? */
 	dword = pci_read_config32(dev, 0x04);
-        dword |= 0x10;
+	dword |= 0x10;
 	dword &= ~(1<<6); // PERSP Parity Error Response
-        pci_write_config32(dev, 0x04, dword);
+	pci_write_config32(dev, 0x04, dword);
 
 	if (chip_rev == 0x01) {
 		/* Errata #37 */
 		byte = pci_read_config8(dev, 0x0c);
-		if(byte == 0x08 )
+		if (byte == 0x08 )
 			pci_write_config8(dev, 0x0c, 0x10);
 
 #if 0
@@ -229,58 +228,58 @@ static void amd8132_pcix_init(device_t dev)
 	/* Set up error reporting, enable all */
 	/* system error enable */
 	dword = pci_read_config32(dev, 0x04);
-        dword |= (1<<8);
+	dword |= (1<<8);
-        pci_write_config32(dev, 0x04, dword);
+	pci_write_config32(dev, 0x04, dword);
 
 	/* system and error parity enable */
 	dword = pci_read_config32(dev, 0x3c);
-        dword |= (3<<16);
+	dword |= (3<<16);
-        pci_write_config32(dev, 0x3c, dword);
+	pci_write_config32(dev, 0x3c, dword);
 
-        dword = pci_read_config32(dev, 0x40);
+	dword = pci_read_config32(dev, 0x40);
-//        dword &= ~(1<<31); /* WriteChainEnable */
+//	dword &= ~(1<<31); /* WriteChainEnable */
 	dword |= (1<<31);
 	dword |= (1<<7);// must set to 1
 	dword |= (3<<21); //PCIErrorSerrDisable
-        pci_write_config32(dev, 0x40, dword);
+	pci_write_config32(dev, 0x40, dword);
 
-        /* EXTARB = 1, COMPAT = 0 */
+	/* EXTARB = 1, COMPAT = 0 */
-        dword = pci_read_config32(dev, 0x48);
+	dword = pci_read_config32(dev, 0x48);
-        dword |= (1<<3);
+	dword |= (1<<3);
 	dword &= ~(1<<0);
 	dword |= (1<<15); //CLEARPCILOG_L
 	dword |= (1<<19); //PERR FATAL Enable
 	dword |= (1<<22); // SERR FATAL Enable
 	dword |= (1<<23); // LPMARBENABLE
 	dword |= (0x61<<24); //LPMARBCOUNT
-        pci_write_config32(dev, 0x48, dword);
+	pci_write_config32(dev, 0x48, dword);
 
-        dword = pci_read_config32(dev, 0x4c);
+	dword = pci_read_config32(dev, 0x4c);
-        dword |= (1<<6); //Initial prefetch for memory read line request
+	dword |= (1<<6); //Initial prefetch for memory read line request
 	dword |= (1<<9); //continuous prefetch Enable for memory read line request
-        pci_write_config32(dev, 0x4c, dword);
+	pci_write_config32(dev, 0x4c, dword);
 
 
-       /* Disable Single-Bit-Error Correction [30] = 0 */
+	/* Disable Single-Bit-Error Correction [30] = 0 */
-        dword = pci_read_config32(dev, 0x70);
+	dword = pci_read_config32(dev, 0x70);
-        dword &= ~(1<<30);
+	dword &= ~(1<<30);
-        pci_write_config32(dev, 0x70, dword);
+	pci_write_config32(dev, 0x70, dword);
 
 	//link
-        dword = pci_read_config32(dev, 0xd4);
+	dword = pci_read_config32(dev, 0xd4);
-        dword |= (0x5c<<16);
+	dword |= (0x5c<<16);
-        pci_write_config32(dev, 0xd4, dword);
+	pci_write_config32(dev, 0xd4, dword);
 
-        /* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
+	/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
-        dword = pci_read_config32(dev, 0xdc);
+	dword = pci_read_config32(dev, 0xdc);
 	dword |= (1<<1) |  (1<<4); // stream disable 1 to 0 , DBLINSRATE
-        dword |= (1<<18)|(1<<26);
+	dword |= (1<<18)|(1<<26);
-        dword &= ~((3<<16)|(3<<24));
+	dword &= ~((3<<16)|(3<<24));
-        pci_write_config32(dev, 0xdc, dword);
+	pci_write_config32(dev, 0xdc, dword);
 
 	/* Set up CRC flood enable */
 	dword = pci_read_config32(dev, 0xc0);
-	if(dword) {  /* do device A only */
+	if (dword) {  /* do device A only */
 #if 0
 		dword = pci_read_config32(dev, 0xc4);
 		dword |= (1<<1);
@@ -290,12 +289,12 @@ static void amd8132_pcix_init(device_t dev)
 		pci_write_config32(dev, 0xc8, dword);
 #endif
 
-	        if (chip_rev == 0x11) {
+		if (chip_rev == 0x11) {
-        	        /* [18] Clock Gate Enable = 1 */
+			/* [18] Clock Gate Enable = 1 */
-                	dword = pci_read_config32(dev, 0xf0);
+			dword = pci_read_config32(dev, 0xf0);
-	                dword |= 0x00040008;
+			dword |= 0x00040008;
-        	        pci_write_config32(dev, 0xf0, dword);
+			pci_write_config32(dev, 0xf0, dword);
-	        }
+		}
 
 	}
 	return;
@@ -337,22 +336,22 @@ static void bridge_set_resources(struct device *dev)
 
 static struct device_operations pcix_ops  = {
 #if BRIDGE_40_BIT_SUPPORT
-        .read_resources   = bridge_read_resources,
+	.read_resources   = bridge_read_resources,
-        .set_resources    = bridge_set_resources,
+	.set_resources    = bridge_set_resources,
 #else
-        .read_resources   = pci_bus_read_resources,
+	.read_resources   = pci_bus_read_resources,
-        .set_resources    = pci_dev_set_resources,
+	.set_resources    = pci_dev_set_resources,
 #endif
 	.enable_resources = pci_bus_enable_resources,
-        .init             = amd8132_pcix_init,
+	.init             = amd8132_pcix_init,
-        .scan_bus         = amd8132_scan_bridge,
+	.scan_bus         = amd8132_scan_bridge,
 	.reset_bus        = pci_bus_reset,
 };
 
 static const struct pci_driver pcix_driver __pci_driver = {
-        .ops    = &pcix_ops,
+	.ops    = &pcix_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = 0x7458,
+	.device = 0x7458,
 };
 
 static void ioapic_enable(device_t dev)
@@ -369,39 +368,39 @@ static void ioapic_enable(device_t dev)
 }
 static void amd8132_ioapic_init(device_t dev)
 {
-        uint32_t dword;
+	uint32_t dword;
-        unsigned chip_rev;
+	unsigned chip_rev;
 
-        /* Find the revision of the 8132 */
+	/* Find the revision of the 8132 */
-        chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
+	chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
 
-        if (chip_rev == 0x01) {
+	if (chip_rev == 0x01) {
 #if 0
-                /* Errata #43 */
+		/* Errata #43 */
-                dword = pci_read_config32(dev, 0xc8);
+		dword = pci_read_config32(dev, 0xc8);
 		dword |= (0x3<<23);
 		pci_write_config32(dev, 0xc8, dword);
 #endif
 
-        }
+	}
 
 
-        if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
+	if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
-                //for b1 b2
+		//for b1 b2
-                /* Errata #73 */
+		/* Errata #73 */
-                dword = pci_read_config32(dev, 0x80);
+		dword = pci_read_config32(dev, 0x80);
-                dword |= (0x1f<<5);
+		dword |= (0x1f<<5);
-                pci_write_config32(dev, 0x80, dword);
+		pci_write_config32(dev, 0x80, dword);
-                dword = pci_read_config32(dev, 0x88);
+		dword = pci_read_config32(dev, 0x88);
-                dword |= (0x1f<<5);
+		dword |= (0x1f<<5);
-                pci_write_config32(dev, 0x88, dword);
+		pci_write_config32(dev, 0x88, dword);
 
-                /* Errata #74 */
+		/* Errata #74 */
-                dword = pci_read_config32(dev, 0x7c);
+		dword = pci_read_config32(dev, 0x7c);
-                dword &= ~(0x3<<30);
+		dword &= ~(0x3<<30);
-                dword |= (0x01<<30);
+		dword |= (0x01<<30);
-                pci_write_config32(dev, 0x7c, dword);
+		pci_write_config32(dev, 0x7c, dword);
-        }
+	}
 
 }
 

src/southbridge/amd/amd8151/agp3.c

@@ -66,7 +66,7 @@ static void agp3dev_enable(device_t dev)
 }
 
 static struct pci_operations pci_ops_pci_dev = {
-        .set_subsystem    = pci_dev_set_subsystem,
+	.set_subsystem    = pci_dev_set_subsystem,
 };
 
 static struct device_operations agp3dev_ops = {

src/southbridge/amd/cimx/sb700/Platform.h

@@ -62,7 +62,7 @@ void    TraceCode ( UINT32 Level, UINT32 Code);
 	#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
 		#define TRACE(Arguments) printk Arguments
 	#else
-		#define TRACE(Arguments) do {} while(0)
+		#define TRACE(Arguments) do {} while (0)
 	#endif
 	#define TRACECODE(Arguments)
 #endif

src/southbridge/amd/cimx/sb700/reset.c

@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for(i = 0; i < nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 0);
 		htic = pci_read_config32(dev, HT_INIT_CONTROL);
 		htic &= ~HTIC_BIOSR_Detect;

src/southbridge/amd/cimx/sb800/early.c

@@ -66,6 +66,6 @@ void sb800_clk_output_48Mhz(void)
 	/* AcpiMMioDecodeEn */
 	RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
 
-        *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
+	*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
-        *(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
+	*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
 }

src/southbridge/amd/cimx/sb800/late.c

@@ -151,21 +151,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 }
 
 static struct device_operations lpc_ops = {
-        .read_resources = lpc_read_resources,
+	.read_resources = lpc_read_resources,
-        .set_resources = lpc_set_resources,
+	.set_resources = lpc_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	.write_acpi_tables = acpi_write_hpet,
 #endif
-        .init = lpc_init,
+	.init = lpc_init,
-        .scan_bus = scan_lpc_bus,
+	.scan_bus = scan_lpc_bus,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver lpc_driver __pci_driver = {
-        .ops = &lpc_ops,
+	.ops = &lpc_ops,
-        .vendor = PCI_VENDOR_ID_ATI,
+	.vendor = PCI_VENDOR_ID_ATI,
-        .device = PCI_DEVICE_ID_ATI_SB800_LPC,
+	.device = PCI_DEVICE_ID_ATI_SB800_LPC,
 };
 
 static struct device_operations sata_ops = {
@@ -226,34 +226,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
 
 
 static struct device_operations azalia_ops = {
-        .read_resources = pci_dev_read_resources,
+	.read_resources = pci_dev_read_resources,
-        .set_resources = pci_dev_set_resources,
+	.set_resources = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
-        .init = 0,
+	.init = 0,
-        .scan_bus = 0,
+	.scan_bus = 0,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver azalia_driver __pci_driver = {
-        .ops = &azalia_ops,
+	.ops = &azalia_ops,
-        .vendor = PCI_VENDOR_ID_ATI,
+	.vendor = PCI_VENDOR_ID_ATI,
-        .device = PCI_DEVICE_ID_ATI_SB800_HDA,
+	.device = PCI_DEVICE_ID_ATI_SB800_HDA,
 };
 
 
 static struct device_operations gec_ops = {
-        .read_resources = pci_dev_read_resources,
+	.read_resources = pci_dev_read_resources,
-        .set_resources = pci_dev_set_resources,
+	.set_resources = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
-        .init = 0,
+	.init = 0,
-        .scan_bus = 0,
+	.scan_bus = 0,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver gec_driver __pci_driver = {
-        .ops = &gec_ops,
+	.ops = &gec_ops,
-        .vendor = PCI_VENDOR_ID_ATI,
+	.vendor = PCI_VENDOR_ID_ATI,
-        .device = PCI_DEVICE_ID_ATI_SB800_GEC,
+	.device = PCI_DEVICE_ID_ATI_SB800_GEC,
 };
 
 /**

src/southbridge/amd/cimx/sb800/reset.c

@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for(i = 0; i < nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 0);
 		htic = pci_read_config32(dev, HT_INIT_CONTROL);
 		htic &= ~HTIC_BIOSR_Detect;

src/southbridge/amd/cimx/sb800/smbus.c

@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
+	printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
 		return -2;	/* not ready */
 	}
 
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
+	printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
 		return -2;	/* not ready */
 	}
 
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
+	printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
 		return -2;	/* not ready */
 	}
 
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
+	printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
 		return -2;	/* not ready */
 	}
 

src/southbridge/amd/cimx/sb900/cfg.c

@@ -28,7 +28,7 @@
 void sb900_cimx_config(AMDSBCFG *sb_config)
 {
 	if (!sb_config) {
-        printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
+	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
 		return;
 	}
     printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
@@ -257,7 +257,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
 void SbPowerOnInit_Config(AMDSBCFG *sb_config)
 {
 	if (!sb_config) {
-        printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
+	printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
 		return;
 	}
     printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");

src/southbridge/amd/cimx/sb900/early.c

@@ -60,7 +60,7 @@ void sb_poweron_init(void)
 	outb(0xEA, 0xCD6);
 	data = inb(0xCD7);
 	data &= !BIT0;
-	if(!CONFIG_PCIB_ENABLE) {
+	if (!CONFIG_PCIB_ENABLE) {
 		data |= BIT0;
 	}
 	outb(data, 0xCD7);

src/southbridge/amd/cimx/sb900/late.c

@@ -121,21 +121,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 }
 
 static struct device_operations lpc_ops = {
-        .read_resources = lpc_read_resources,
+	.read_resources = lpc_read_resources,
-        .set_resources = lpc_set_resources,
+	.set_resources = lpc_set_resources,
-        .enable_resources = lpc_enable_resources,
+	.enable_resources = lpc_enable_resources,
-        .init = lpc_init,
+	.init = lpc_init,
 #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
 	.write_acpi_tables = acpi_write_hpet,
 #endif
-        .scan_bus = scan_lpc_bus,
+	.scan_bus = scan_lpc_bus,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver lpc_driver __pci_driver = {
-        .ops = &lpc_ops,
+	.ops = &lpc_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_LPC,
+	.device = PCI_DEVICE_ID_ATI_SB900_LPC,
 };
 
 
@@ -239,18 +239,18 @@ static void azalia_init(struct device *dev)
 }
 
 static struct device_operations azalia_ops = {
-        .read_resources = pci_dev_read_resources,
+	.read_resources = pci_dev_read_resources,
-        .set_resources = pci_dev_set_resources,
+	.set_resources = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
-        .init = azalia_init,
+	.init = azalia_init,
-        .scan_bus = 0,
+	.scan_bus = 0,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver azalia_driver __pci_driver = {
-        .ops = &azalia_ops,
+	.ops = &azalia_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_HDA,
+	.device = PCI_DEVICE_ID_ATI_SB900_HDA,
 };
 
 
@@ -263,18 +263,18 @@ static void gec_init(struct device *dev)
 }
 
 static struct device_operations gec_ops = {
-        .read_resources = pci_dev_read_resources,
+	.read_resources = pci_dev_read_resources,
-        .set_resources = pci_dev_set_resources,
+	.set_resources = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
-        .init = gec_init,
+	.init = gec_init,
-        .scan_bus = 0,
+	.scan_bus = 0,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver gec_driver __pci_driver = {
-        .ops = &gec_ops,
+	.ops = &gec_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_GEC,
+	.device = PCI_DEVICE_ID_ATI_SB900_GEC,
 };
 
 
@@ -286,19 +286,19 @@ static void pcie_init(device_t dev)
 }
 
 static struct device_operations pci_ops = {
-        .read_resources = pci_bus_read_resources,
+	.read_resources = pci_bus_read_resources,
-        .set_resources = pci_dev_set_resources,
+	.set_resources = pci_dev_set_resources,
-        .enable_resources = pci_bus_enable_resources,
+	.enable_resources = pci_bus_enable_resources,
-        .init = pcie_init,
+	.init = pcie_init,
-        .scan_bus = pci_scan_bridge,
+	.scan_bus = pci_scan_bridge,
-        .reset_bus = pci_bus_reset,
+	.reset_bus = pci_bus_reset,
-        .ops_pci = &lops_pci,
+	.ops_pci = &lops_pci,
 };
 
 static const struct pci_driver pci_driver __pci_driver = {
-        .ops = &pci_ops,
+	.ops = &pci_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_PCI,
+	.device = PCI_DEVICE_ID_ATI_SB900_PCI,
 };
 
 
@@ -315,30 +315,30 @@ struct device_operations bridge_ops = {
 
 /* 0:15:0 PCIe PortA */
 static const struct pci_driver PORTA_driver __pci_driver = {
-        .ops = &bridge_ops,
+	.ops = &bridge_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
+	.device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
 };
 
 /* 0:15:1 PCIe PortB */
 static const struct pci_driver PORTB_driver __pci_driver = {
-        .ops = &bridge_ops,
+	.ops = &bridge_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
+	.device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
 };
 
 /* 0:15:2 PCIe PortC */
 static const struct pci_driver PORTC_driver __pci_driver = {
-        .ops = &bridge_ops,
+	.ops = &bridge_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
+	.device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
 };
 
 /* 0:15:3 PCIe PortD */
 static const struct pci_driver PORTD_driver __pci_driver = {
-        .ops = &bridge_ops,
+	.ops = &bridge_ops,
-        .vendor = PCI_VENDOR_ID_AMD,
+	.vendor = PCI_VENDOR_ID_AMD,
-        .device = PCI_DEVICE_ID_ATI_SB900_PCIED,
+	.device = PCI_DEVICE_ID_ATI_SB900_PCIED,
 };
 
 

src/southbridge/amd/cimx/sb900/reset.c

@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for(i = 0; i < nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 0);
 		htic = pci_read_config32(dev, HT_INIT_CONTROL);
 		htic &= ~HTIC_BIOSR_Detect;

src/southbridge/amd/cimx/sb900/smbus.c

@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
+	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
 		return -2;	/* not ready */
 	}
 
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
+	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
 		return -2;	/* not ready */
 	}
 
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
+	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
 		return -2;	/* not ready */
 	}
 
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
 	u8 byte;
 
 	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-        printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
+	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
 		return -2;	/* not ready */
 	}
 

src/southbridge/amd/common/amd_pci_util.c

@@ -58,7 +58,7 @@ void write_pci_int_table (void)
 {
 	u8 byte;
 
-	if(picr_data_ptr == NULL || intr_data_ptr == NULL){
+	if (picr_data_ptr == NULL || intr_data_ptr == NULL){
 		printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n"
 				"'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n");
 		return;

src/southbridge/amd/cs5535/chipsetinit.c

@@ -328,7 +328,7 @@ chipsetinit(void)
 	i = 0;
 
 	csi = &SB_MASTER_CONF_TABLE[i];
-	for(; csi->msrnum; csi++){
+	for (; csi->msrnum; csi++){
 		msr.lo = csi->msr.lo;
 		msr.hi = csi->msr.hi;
 		wrmsr(csi->msrnum, msr); // MSR - see table above
@@ -347,7 +347,7 @@ chipsetinit(void)
 	{
 		csi = CS5535_CLOCK_GATING_TABLE;
 
-		for(; csi->msrnum; csi++){
+		for (; csi->msrnum; csi++){
 			msr.lo = csi->msr.lo;
 			msr.hi = csi->msr.hi;
 			wrmsr(csi->msrnum, msr);	// MSR - see table above

src/southbridge/amd/cs5535/cs5535.c

@@ -56,9 +56,9 @@ static void dump_south(struct device *dev)
 {
 	int i, j;
 
-	for(i=0; i<256; i+=16) {
+	for (i=0; i<256; i+=16) {
 		printk(BIOS_DEBUG, "0x%02x: ", i);
-		for(j=0; j<16; j++)
+		for (j=0; j<16; j++)
 			printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
 		printk(BIOS_DEBUG, "\n");
 	}
@@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = {
 };
 
 struct chip_operations southbridge_amd_cs5535_ops = {
-        CHIP_NAME("AMD Geode CS5535 Southbridge")
+	CHIP_NAME("AMD Geode CS5535 Southbridge")
-            /* This is only called when this device is listed in the
+	    /* This is only called when this device is listed in the
-             * static device tree.
+	     * static device tree.
-             */
+	     */
-            .enable_dev = southbridge_enable,
+	    .enable_dev = southbridge_enable,
 };

src/southbridge/amd/cs5535/early_setup.c

@@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void)
 	outl(0x1 << (CS5535_DEV_NUM + 10), 0);
 }
 
-static void cs5535_usb_swapsif(void)
+static void cs5535_usb_swapsif (void)
 {
 	msr_t msr;
 
@@ -133,7 +133,7 @@ static void cs5535_early_setup(void)
 	printk(BIOS_DEBUG, "Setup idsel\n");
 	cs5535_setup_idsel();
 	printk(BIOS_DEBUG, "Setup iobase\n");
-	cs5535_usb_swapsif();
+	cs5535_usb_swapsif ();
 	cs5535_setup_iobase();
 	printk(BIOS_DEBUG, "Setup gpio\n");
 	cs5535_setup_gpio();

src/southbridge/amd/cs5536/early_setup.c

@@ -42,7 +42,7 @@ static void cs5536_setup_idsel(void)
 	outl(0x1 << (CS5536_DEV_NUM + 10), 0);
 }
 
-static void cs5536_usb_swapsif(void)
+static void cs5536_usb_swapsif (void)
 {
 	msr_t msr;
 
@@ -260,7 +260,7 @@ static void cs5536_early_setup(void)
 	//printk(BIOS_DEBUG, "Setup idsel\n");
 	cs5536_setup_idsel();
 	//printk(BIOS_DEBUG, "Setup iobase\n");
-	cs5536_usb_swapsif();
+	cs5536_usb_swapsif ();
 	cs5536_setup_iobase();
 	//printk(BIOS_DEBUG, "Setup gpio\n");
 	cs5536_setup_gpio();

src/southbridge/amd/pi/hudson/acpi/fch.asl

@@ -165,9 +165,9 @@ Method(_INI, 0) {
 
 Method(OSFL, 0){
 
-	if(LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
+	if (LNotEqual(OSVR, Ones)) {Return(OSVR)}	/* OS version was already detected */
 
-	if(CondRefOf(\_OSI))
+	if (CondRefOf(\_OSI))
 	{
 		Store(1, OSVR)					/* Assume some form of XP */
 		if (\_OSI("Windows 2006"))		/* Vista */

src/southbridge/amd/rs690/gfx.c

@@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
 	/* done by enable_pci_bar3() before */
 
 	/* step 6 SBIOS compile flags */
-        if (cfg->gfx_tmds) {
+	if (cfg->gfx_tmds) {
-                /* step 6.2.2 Clock-Muxing Control */
+		/* step 6.2.2 Clock-Muxing Control */
-                /* step 6.2.2.1 */
+		/* step 6.2.2.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
 
-                /* step 6.2.2.2 */
+		/* step 6.2.2.2 */
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
 
-                /* step 6.2.2.3 */
+		/* step 6.2.2.3 */
-                set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
+		set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
 
-                /* step 6.2.3 Lane-Muxing Control */
+		/* step 6.2.3 Lane-Muxing Control */
-                /* step 6.2.3.1 */
+		/* step 6.2.3.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
+		set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
 
-                /* step 6.2.4 Received Data Control */
+		/* step 6.2.4 Received Data Control */
-                /* step 6.2.4.1 */
+		/* step 6.2.4.1 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
 
-                /* step 6.2.4.2 */
+		/* step 6.2.4.2 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
 
-                /* step 6.2.4.3 */
+		/* step 6.2.4.3 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
 
-                /* step 6.2.4.4 */
+		/* step 6.2.4.4 */
-                set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
+		set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
 
-                /* step 6.2.5 PLL Power Down Control */
+		/* step 6.2.5 PLL Power Down Control */
-                /* step 6.2.5.1 */
+		/* step 6.2.5.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
+		set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
 
-                /* step 6.2.6 Driving Strength Control */
+		/* step 6.2.6 Driving Strength Control */
-                /* step 6.2.6.1 */
+		/* step 6.2.6.1 */
-                set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
+		set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
 
-                /* step 6.2.6.2 */
+		/* step 6.2.6.2 */
-                set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
+		set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
-        }
+	}
 
-        printk(BIOS_INFO, "rs690_gfx_init step6.\n");
+	printk(BIOS_INFO, "rs690_gfx_init step6.\n");
 
 	/* step 7 compliance state, (only need if CMOS option is enabled) */
 	/* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */

src/southbridge/amd/rs690/ht.c

@@ -52,12 +52,12 @@ static void ht_dev_set_resources(device_t dev)
 		printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
 		k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
 		// find a not assigned resource
-		for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
+		for ( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
 			base = pci_read_config32(k8_f1,reg);
 			limit = pci_read_config32(k8_f1,reg+4);
-			if( !(base & 3) ) break; // found a not assigned resource
+			if ( !(base & 3) ) break; // found a not assigned resource
 		}
-		if( !(base & 3) ) {
+		if ( !(base & 3) ) {
 			u32 sblk;
 			device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
 			/* Remember this resource has been stored. */
@@ -90,7 +90,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
 	// we report mmconf base
 	res = probe_resource(dev, 0x1C);
-	if( res )
+	if ( res )
 		mmconf_base = res->base;
 
 	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?

src/southbridge/amd/rs690/pcie.c

@@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
 			   PCIE_GFX_COMPLIANCE))) {
 	}
 
-        if (!cfg->gfx_tmds){
+	if (!cfg->gfx_tmds){
 		/* step 3 Power Down Control for Southbridge */
 		reg = nbpcie_p_read_index(dev, 0xa2);
 

src/southbridge/amd/rs780/early_setup.c

@@ -335,7 +335,7 @@ static void k8_optimization(void)
 	wrmsr(0xC001001F, msr);
 }
 #else
-#define k8_optimization() do{}while(0)
+#define k8_optimization() do {} while (0)
 #endif	/* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
 
 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
@@ -400,7 +400,7 @@ static void fam10_optimization(void)
 	}
 }
 #else
-#define fam10_optimization() do{}while(0)
+#define fam10_optimization() do {} while (0)
 #endif	/* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
 
 /*****************************************

src/southbridge/amd/rs780/gfx.c

@@ -127,12 +127,10 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 {
 	int i;
 	MMIORANGE * TempRange;
-	for(i=0; i<8; i++)
+	for (i=0; i<8; i++) {
-	{
+		if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) {
-		if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
-		{
 			TempRange = AllocMMIO(pMMIO);
-			if(TempRange == 0) return 0x80000000;
+			if (TempRange == 0) return 0x80000000;
 			TempRange->Base = Limit;
 			TempRange->Limit = pMMIO[i].Limit;
 			TempRange->Attribute = pMMIO[i].Attribute;
@@ -140,7 +138,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 		}
 	}
 	TempRange = AllocMMIO(pMMIO);
-	if(TempRange == 0) return 0x80000000;
+	if (TempRange == 0) return 0x80000000;
 	TempRange->Base = Base;
 	TempRange->Limit = Limit;
 	TempRange->Attribute = Attribute;
@@ -150,32 +148,25 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
 static u8 FinalizeMMIO(MMIORANGE *pMMIO)
 {
 	int i, j, n = 0;
-	for(i=0; i<8; i++)
+	for (i=0; i<8; i++) {
-	{
+		if (pMMIO[i].Base == pMMIO[i].Limit) {
-		if (pMMIO[i].Base == pMMIO[i].Limit)
-		{
 			FreeMMIO(&pMMIO[i]);
 			continue;
 		}
-		for(j=0; j<i; j++)
+		for (j=0; j<i; j++) {
-		{
+			if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) {
-			if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
+				if (pMMIO[i].Base == pMMIO[j].Limit) {
-			{
-				if (pMMIO[i].Base == pMMIO[j].Limit)
-				{
 					pMMIO[j].Limit = pMMIO[i].Limit;
 					 FreeMMIO(&pMMIO[i]);
 				}
-				if (pMMIO[i].Limit == pMMIO[j].Base)
+				if (pMMIO[i].Limit == pMMIO[j].Base) {
-				{
 					pMMIO[j].Base = pMMIO[i].Base;
 				   FreeMMIO(&pMMIO[i]);
 				}
 			}
 		}
 	}
-	for (i=0; i<8; i++)
+	for (i=0; i<8; i++) {
-	{
 		if (pMMIO[i].Limit != 0) n++;
 	}
 	return n;
@@ -191,29 +182,23 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 	Value = pci_read_config32(dev0x14, 0x18);
 	BusStart = (Value >> 8) & 0xFF;
 	BusEnd = (Value >> 16) & 0xFF;
-	for(Bus = BusStart; Bus <= BusEnd; Bus++)
+	for (Bus = BusStart; Bus <= BusEnd; Bus++) {
-	{
+		for (Dev = 0; Dev <= 0x1f; Dev++) {
-		for(Dev = 0; Dev <= 0x1f; Dev++)
-		{
 			tempdev = dev_find_slot(Bus, Dev << 3);
 			Value = pci_read_config32(tempdev, 0);
 			printk(BIOS_DEBUG, "Dev ID %x\n", Value);
-			if((Value & 0xffff) == 0x1102)
+			if ((Value & 0xffff) == 0x1102) {//Creative
-			{//Creative
 				//Found Creative SB
 			 	u32	MMIOStart = 0xffffffff;
 				u32 MMIOLimit = 0;
-				for(Reg = 0x10; Reg < 0x20; Reg+=4)
+				for (Reg = 0x10; Reg < 0x20; Reg+=4) {
-				{
 					u32	BaseA, LimitA;
 					BaseA = pci_read_config32(tempdev, Reg);
 					Value = BaseA;
-					if(!(Value & 0x01))
+					if (!(Value & 0x01)) {
-					{
 						Value = Value & 0xffffff00;
-						if(Value !=  0)
+						if (Value !=  0) {
-						{
+							if (MMIOStart > Value)
-							if(MMIOStart > Value)
 								MMIOStart = Value;
 							LimitA = 0xffffffff;
 							//WritePCI(PciAddress,AccWidthUint32,&LimitA);
@@ -232,16 +217,14 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 				if (MMIOStart < MMIOLimit)
 				{
 					Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
-					if(Status == CIM_ERROR) return Status;
+					if (Status == CIM_ERROR) return Status;
 				}
 			}
 		}
 	}
-	if(Status == CIM_SUCCESS)
+	if (Status == CIM_SUCCESS) {
-	{
 		//Lets optimize MMIO
-		if(FinalizeMMIO(pMMIO) > 4)
+		if (FinalizeMMIO(pMMIO) > 4) {
-		{
 			Status = CIM_ERROR;
 		}
 	}
@@ -256,23 +239,18 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
 
 	k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 
-	for(i = 0; i < 8; i++)
+	for (i = 0; i < 8; i++) {
-	{
 		int k = 0, MmioReg;
 		u32 Base = 0;
 		u32 Limit = 0;
-		for(j = 0; j < 8; j++)
+		for (j = 0; j < 8; j++) {
-		{
+			if (Base < pMMIO[j].Base) {
-			if (Base < pMMIO[j].Base)
-			{
 				Base = pMMIO[j].Base;
 				k = j;
 			}
 		}
-		if(pMMIO[k].Limit != 0)
+		if (pMMIO[k].Limit != 0) {
-		{
+			if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
-			if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
-			{
 				Base = 0;
 			}
 			else
@@ -366,8 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* Clear vgainfo. */
 	bpointer = (unsigned char *) &vgainfo;
-	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
+	for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
-	{
 		*bpointer = 0;
 		bpointer++;
 	}
@@ -651,8 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* Transfer the Table to VBIOS. */
 	pointer = (u32 *)&vgainfo;
-	for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
+	for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
-	{
 #if CONFIG_GFXUMA
 		*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
 #else
@@ -686,14 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 
 	/* clear MMIO and CreativeMMIO. */
 	bpointer = (unsigned char *)MMIO;
-	for(i=0; i<sizeof(MMIO); i++)
+	for (i=0; i<sizeof(MMIO); i++) {
-	{
 		*bpointer = 0;
 		bpointer++;
 	}
 	bpointer = (unsigned char *)CreativeMMIO;
-	for(i=0; i<sizeof(CreativeMMIO); i++)
+	for (i=0; i<sizeof(CreativeMMIO); i++) {
-	{
 		*bpointer = 0;
 		bpointer++;
 	}
@@ -708,20 +682,18 @@ static void internal_gfx_pci_dev_init(struct device *dev)
 	temp = pci_read_config32(dev0x14, 0x20);
 	Base32 = (temp & 0x0fff0) << 8;
 	Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
-	if(Base32 < Limit32)
+	if (Base32 < Limit32) {
-	{
 		Status = GetCreativeMMIO(&CreativeMMIO[0]);
-		if(Status != CIM_ERROR)
+		if (Status != CIM_ERROR)
 			SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
 	}
 	/* Set MMIO for prefetchable P2P. */
-	if(Status != CIM_ERROR)
+	if (Status != CIM_ERROR) {
-	{
 		temp = pci_read_config32(dev0x14, 0x24);
 
 		Base32 = (temp & 0x0fff0) <<8;
 		Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
-		if(Base32 < Limit32)
+		if (Base32 < Limit32)
 			SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
 	}
 
@@ -835,8 +807,7 @@ static void rs780_internal_gfx_enable(device_t dev)
 	device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
 	device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
 	device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
-	for (i = 0; i < 12; i++)
+	for (i = 0; i < 12; i++) {
-	{
 		l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
 		nbmc_write_index(nb_dev, 0x30 + i, l_dword);
 	}
@@ -848,10 +819,8 @@ static void rs780_internal_gfx_enable(device_t dev)
 	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
 	l_dword = pci_read_config32(k8_f2, 0x90);
 	set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
-   if (is_family10h())
+   if (is_family10h()) {
-   {
+	   for (i = 0; i < 12; i++) {
-	   for (i = 0; i < 12; i++)
-	   {
 		   l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
 		   nbmc_write_index(nb_dev, 0x3d + i, l_dword);
 	   }
@@ -974,13 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev)
 	/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
 
 	/* Init PM timing. */
-	for(i=0; i<4; i++)
+	for (i=0; i<4; i++) {
-	{
 		l_dword = nbmc_read_index(nb_dev, 0xa0+i);
 		nbmc_write_index(nb_dev, 0xc8+i, l_dword);
 	}
-	for(i=0; i<4; i++)
+	for (i=0; i<4; i++) {
-	{
 		l_dword = nbmc_read_index(nb_dev, 0xa8+i);
 		nbmc_write_index(nb_dev, 0xcc+i, l_dword);
 	}
@@ -1538,7 +1505,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 		printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
 
 		printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
-		if((dev->path.pci.devfn >> 3) == 2) {
+		if ((dev->path.pci.devfn >> 3) == 2) {
 			single_port_configuration(nb_dev, dev);
 		} else {
 			set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
@@ -1565,7 +1532,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 		break;
 
 	case 2:
-		if(is_dev3_present()){
+		if (is_dev3_present()) {
 			/* step 1, lane reversal (only need if CMOS option is enabled) */
 			if (cfg->gfx_lane_reversal) {
 				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
@@ -1583,7 +1550,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 			printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
 			dual_port_configuration(nb_dev, dev);
 
-		}else{
+		} else {
 			if (cfg->gfx_lane_reversal) {
 				set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
 				set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
@@ -1591,9 +1558,9 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
 			}
 			printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
 
-			if((dev->path.pci.devfn >> 3) == 2)
+			if ((dev->path.pci.devfn >> 3) == 2)
 				single_port_configuration(nb_dev, dev);
-			else{
+			else {
 				set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
 				printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
 			    }

src/southbridge/amd/rs780/rs780.h

@@ -101,7 +101,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
 	ULONG                      ulDockingPinCFGInfo;
 	ULONG                      ulCPUCapInfo;
 	USHORT                     usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform
-                                                       //                               1 - non inverted waveform
+	                                                     //                               1 - non inverted waveform
 	USHORT                     usMaxNBVoltage;
 	USHORT                     usMinNBVoltage;
 	USHORT                     usBootUpNBVoltage;

src/southbridge/amd/sb600/early_setup.c

@@ -137,7 +137,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
 	pmio_write(0x8b, 0x01);
 	pmio_write(0x8a, 0x90);
 
-	if(get_sb600_revision() > 0x13)
+	if (get_sb600_revision() > 0x13)
 		pmio_write(0x88, 0x10);
 	else
 		pmio_write(0x88, 0x06);

src/southbridge/amd/sb600/hda.c

@@ -175,7 +175,7 @@ static int wait_for_ready(void *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 dword=read32(base +  HDA_ICII_REG);
 		if (!(dword & HDA_ICII_BUSY))
 			return 0;
@@ -196,7 +196,7 @@ static int wait_for_valid(void *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		u32 dword = read32(base + HDA_ICII_REG);
 		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/amd/sb600/sata.c

@@ -182,7 +182,7 @@ static void sata_init(struct device *dev)
 		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 		byte &= 0xF;
 
-		if( byte == 0x1 ) {
+		if ( byte == 0x1 ) {
 			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 			/* Try to do something about it. */
 			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");

src/southbridge/amd/sb700/Kconfig

@@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select HAVE_HARD_RESET
 	select SMBUS_HAS_AUX_CHANNELS
 
-config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
-	bool "Enable high speed SPI clock"
-	default n
-	help
-	  When set, the SPI clock will run at 33MHz instead
-	  of the compatibility mode 16.5MHz.  Note that not
-	  all ROMs are capable of 33MHz operation, so you
-	  will need to verify this option is appropriate for
-	  the ROM you are using.
-
 # Set for southbridge SP5100 which also uses SB700 driver
 config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
 	bool

src/southbridge/amd/sb700/bootblock.c

@@ -20,10 +20,6 @@
 
 #define IO_MEM_PORT_DECODE_ENABLE_5	0x48
 #define IO_MEM_PORT_DECODE_ENABLE_6	0x4a
-#define SPI_BASE_ADDRESS		0xa0
-
-#define SPI_CONTROL_1			0xc
-#define TEMPORARY_SPI_BASE_ADDRESS	0xfec10000
 
 /*
  * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -96,37 +92,7 @@ static void sb700_enable_rom(void)
 	pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
 }
 
-static void sb700_configure_rom(void)
-{
-	pci_devfn_t dev;
-	uint32_t dword;
-
-	dev = PCI_DEV(0, 0x14, 3);
-
-	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
-		uint32_t prev_spi_cfg;
-		volatile uint32_t *spi_mmio;
-
-		/* Temporarily set up SPI access to change SPI speed */
-		prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
-		dword &= ~(0x7ffffff << 5);		/* SPI_BaseAddr */
-		dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
-		dword |= (0x1 << 1);			/* SpiRomEnable = 1 */
-		pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
-
-		spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
-		dword = *spi_mmio;
-		dword &= ~(0x3 << 12);	/* NormSpeed = 0x1 */
-		dword |= (0x1 << 12);
-		*spi_mmio = dword;
-
-		/* Restore previous SPI access */
-		pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
-	}
-}
-
 static void bootblock_southbridge_init(void)
 {
 	sb700_enable_rom();
-	sb700_configure_rom();
 }

src/southbridge/amd/sb700/hda.c

@@ -97,7 +97,7 @@ static int wait_for_ready(void *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 dword=read32(base +  HDA_ICII_REG);
 		if (!(dword & HDA_ICII_BUSY))
 			return 0;
@@ -118,7 +118,7 @@ static int wait_for_valid(void *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		u32 dword = read32(base + HDA_ICII_REG);
 		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/amd/sb700/reset.c

@@ -36,7 +36,7 @@ static void set_bios_reset(void)
 	int i;
 
 	nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for(i = 0; i < nodes; i++) {
+	for (i = 0; i < nodes; i++) {
 		dev = NODE_PCI(i, 0);
 		htic = pci_read_config32(dev, HT_INIT_CONTROL);
 		htic &= ~HTIC_BIOSR_Detect;

src/southbridge/amd/sb700/sm.c

@@ -213,7 +213,7 @@ static void sm_init(device_t dev)
 	}
 
 	/*rpr v2.13  2.22 SMBUS PCI Config */
- 	byte = pci_read_config8(dev, 0xE1);
+	byte = pci_read_config8(dev, 0xE1);
 	if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
 		byte |= 1 << 0;
 	}
@@ -222,7 +222,7 @@ static void sm_init(device_t dev)
 	 */
 	//byte |= 1 << 2 | 1 << 3 | 1 << 4;
 	byte |= 1 << 3 | 1 << 4;
- 	pci_write_config8(dev, 0xE1, byte);
+	pci_write_config8(dev, 0xE1, byte);
 
 	/* 2.5 Enabling Non-Posted Memory Write */
        	axindxc_reg(0x10, 1 << 9, 1 << 9);
@@ -278,7 +278,7 @@ static void sm_init(device_t dev)
 		u16 word;
 
 		/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
-        	axindxc_reg(0x02, 1 << 9, 1 << 9);
+		axindxc_reg(0x02, 1 << 9, 1 << 9);
 		abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
 		abcfg_reg(0x1009C, 0x00000030, 0x00000030);
 		abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
@@ -287,19 +287,19 @@ static void sm_init(device_t dev)
 		abcfg_reg(0x58, 0x0000F800, 0x0000E800);
 
 		/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
-        	axindxc_reg(0x02, 1 << 10, 1 << 10);
+		axindxc_reg(0x02, 1 << 10, 1 << 10);
 
 		/* rpr v2.13 2.38 Unconditional Shutdown */
- 		byte = pci_read_config8(dev, 0x43);
+		byte = pci_read_config8(dev, 0x43);
 		byte &= ~(1 << 3);
- 		pci_write_config8(dev, 0x43, byte);
+		pci_write_config8(dev, 0x43, byte);
 
 		word = pci_read_config16(dev, 0x38);
 		word |= 1 << 12;
- 		pci_write_config16(dev, 0x38, word);
+		pci_write_config16(dev, 0x38, word);
 
 		byte |= 1 << 3;
- 		pci_write_config8(dev, 0x43, byte);
+		pci_write_config8(dev, 0x43, byte);
 
 		/* Enable southbridge MMIO decode */
 		dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
@@ -308,12 +308,12 @@ static void sm_init(device_t dev)
 		dword |= 0x1;
 		pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
 	}
- 	byte = pci_read_config8(dev, 0xAE);
+	byte = pci_read_config8(dev, 0xAE);
- 	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
+	if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
- 		byte |= 1 << 4;
+	byte |= 1 << 4;
 	byte |= 1 << 5;	/* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
 	byte |= 1 << 6;	/* Enable arbiter between APIC and PIC interrupts */
- 	pci_write_config8(dev, 0xAE, byte);
+	pci_write_config8(dev, 0xAE, byte);
 
 	/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
 	/* 4.12: Enabling AB and BIF Clock Gating */

src/southbridge/amd/sb800/hda.c

@@ -99,7 +99,7 @@ static int wait_for_ready(void *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 dword=read32(base +  HDA_ICII_REG);
 		if (!(dword & HDA_ICII_BUSY))
 			return 0;
@@ -120,7 +120,7 @@ static int wait_for_valid(void *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		u32 dword = read32(base + HDA_ICII_REG);
 		if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/amd/sb800/sata.c

@@ -177,7 +177,7 @@ static void sata_init(struct device *dev)
 		byte = read8(sata_bar5 + 0x128 + 0x80 * i);
 		printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
 		byte &= 0xF;
-		if( byte == 0x1 ) {
+		if ( byte == 0x1 ) {
 			/* If the drive status is 0x1 then we see it but we aren't talking to it. */
 			/* Try to do something about it. */
 			printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");

src/southbridge/amd/sr5650/early_setup.c

@@ -30,22 +30,22 @@
  */
 static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
 {
-        u32 tmp;
+	u32 tmp;
 
-        /* read axindc to tmp */
+	/* read axindc to tmp */
-        outl(space << 30 | space << 3 | 0x30, AB_INDX);
+	outl(space << 30 | space << 3 | 0x30, AB_INDX);
-        outl(axindc, AB_DATA);
+	outl(axindc, AB_DATA);
-        outl(space << 30 | space << 3 | 0x34, AB_INDX);
+	outl(space << 30 | space << 3 | 0x34, AB_INDX);
-        tmp = inl(AB_DATA);
+	tmp = inl(AB_DATA);
 
-        tmp &= ~mask;
+	tmp &= ~mask;
-        tmp |= val;
+	tmp |= val;
 
-        /* write tmp */
+	/* write tmp */
-        outl(space << 30 | space << 3 | 0x30, AB_INDX);
+	outl(space << 30 | space << 3 | 0x30, AB_INDX);
-        outl(axindc, AB_DATA);
+	outl(axindc, AB_DATA);
-        outl(space << 30 | space << 3 | 0x34, AB_INDX);
+	outl(space << 30 | space << 3 | 0x34, AB_INDX);
-        outl(tmp, AB_DATA);
+	outl(tmp, AB_DATA);
 }
 
 
@@ -327,7 +327,7 @@ void fam10_optimization(void)
 	/* rpr Table 5-11, 5-12 */
 }
 #else
-#define fam10_optimization() do{}while(0)
+#define fam10_optimization() do {} while (0)
 #endif	/* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
 
 /*****************************************

src/southbridge/amd/sr5650/sr5650.c

@@ -817,8 +817,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
 
 	if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
-        	res = sr5650_retrieve_cpu_mmio_resource();
+		res = sr5650_retrieve_cpu_mmio_resource();
-        	if (res)
+		if (res)
 			mmconf_base = res->base;
 
 		current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f);

src/southbridge/broadcom/bcm21000/pcie.c

@@ -43,7 +43,7 @@ static void pcie_init(struct device *dev)
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = 0,
+	.set_subsystem = 0,
 };
 
 static struct device_operations pcie_ops  = {

src/southbridge/broadcom/bcm5780/nic.c

@@ -23,12 +23,12 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
+	pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations nic_ops  = {
@@ -47,7 +47,7 @@ static const struct pci_driver nic_driver __pci_driver = {
 };
 
 static const struct pci_driver nic1_driver __pci_driver = {
-        .ops    = &nic_ops,
+	.ops    = &nic_ops,
-        .vendor = PCI_VENDOR_ID_BROADCOM,
+	.vendor = PCI_VENDOR_ID_BROADCOM,
-        .device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
+	.device = PCI_DEVICE_ID_BROADCOM_BCM5780_NIC1,
 };

src/southbridge/broadcom/bcm5780/pcie.c

@@ -35,17 +35,17 @@ static void pcie_init(struct device *dev)
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = 0,
+	.set_subsystem = 0,
 };
 
 static struct device_operations pcie_ops  = {
-        .read_resources   = pci_bus_read_resources,
+	.read_resources   = pci_bus_read_resources,
-        .set_resources    = pci_dev_set_resources,
+	.set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_bus_enable_resources,
+	.enable_resources = pci_bus_enable_resources,
-        .init             = pcie_init,
+	.init             = pcie_init,
-        .scan_bus         = pci_scan_bridge,
+	.scan_bus         = pci_scan_bridge,
-        .reset_bus        = pci_bus_reset,
+	.reset_bus        = pci_bus_reset,
-        .ops_pci          = &lops_pci,
+	.ops_pci          = &lops_pci,
 
 };
 

src/southbridge/broadcom/bcm5780/pcix.c

@@ -22,22 +22,22 @@
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
+	pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations ht_ops  = {
-        .read_resources   = pci_bus_read_resources,
+	.read_resources   = pci_bus_read_resources,
-        .set_resources    = pci_dev_set_resources,
+	.set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_bus_enable_resources,
+	.enable_resources = pci_bus_enable_resources,
-        .init             = 0 ,
+	.init             = 0 ,
-        .scan_bus         = pci_scan_bridge,
+	.scan_bus         = pci_scan_bridge,
-        .reset_bus        = pci_bus_reset,
+	.reset_bus        = pci_bus_reset,
-        .ops_pci          = &lops_pci,
+	.ops_pci          = &lops_pci,
 
 };
 

src/southbridge/broadcom/bcm5785/bcm5785.c

@@ -36,17 +36,17 @@ void bcm5785_enable(device_t dev)
 		sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn);
 		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
 	} else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
-                (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
+		(bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X )
-        {
+	{
-                unsigned devfn;
+		unsigned devfn;
-                devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
+		devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3);
-                sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
+		sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn);
 		// index = ((dev->path.pci.devfn & ~7) >> 3) + 8;
-        }
+	}
 	else { // same bus
 		unsigned devfn;
 		devfn = (dev->path.pci.devfn) & ~7;
-		if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
+		if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
 			if (dev->device == 0x0036) //PCI-X Bridge
 			{ devfn += (1<<3); }
 			else if (dev->device == 0x0223) // USB

src/southbridge/broadcom/bcm5785/chip.h

@@ -19,10 +19,10 @@
 
 struct southbridge_broadcom_bcm5785_config
 {
-        unsigned int ide0_enable : 1;
+	unsigned int ide0_enable : 1;
-        unsigned int ide1_enable : 1;
+	unsigned int ide1_enable : 1;
-        unsigned int sata0_enable : 1;
+	unsigned int sata0_enable : 1;
-        unsigned int sata1_enable : 1;
+	unsigned int sata1_enable : 1;
 };
 
 #endif /* BCM5785_CHIP_H */

src/southbridge/broadcom/bcm5785/early_setup.c

@@ -19,62 +19,62 @@
 
 static void bcm5785_enable_lpc(void)
 {
-        uint8_t byte;
+	uint8_t byte;
-        device_t dev;
+	device_t dev;
 
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
-        /* LPC Control 0 */
+	/* LPC Control 0 */
-        byte = pci_read_config8(dev, 0x44);
+	byte = pci_read_config8(dev, 0x44);
-        /* Serial 0 */
+	/* Serial 0 */
-        byte |= (1<<6);
+	byte |= (1<<6);
-        pci_write_config8(dev, 0x44, byte);
+	pci_write_config8(dev, 0x44, byte);
 
-        /* LPC Control 4 */
+	/* LPC Control 4 */
-        byte = pci_read_config8(dev, 0x48);
+	byte = pci_read_config8(dev, 0x48);
-        /* superio port 0x2e/4e enable */
+	/* superio port 0x2e/4e enable */
-        byte |=(1<<1)|(1<<0);
+	byte |=(1<<1)|(1<<0);
-        pci_write_config8(dev, 0x48, byte);
+	pci_write_config8(dev, 0x48, byte);
 }
 
 static void bcm5785_enable_wdt_port_cf9(void)
 {
-        device_t dev;
+	device_t dev;
-        uint32_t dword;
+	uint32_t dword;
-        uint32_t dword_old;
+	uint32_t dword_old;
 
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
 
-        dword_old = pci_read_config32(dev, 0x4c);
+	dword_old = pci_read_config32(dev, 0x4c);
-        dword = dword_old | (1<<4); //enable Timer Func
+	dword = dword_old | (1<<4); //enable Timer Func
-        if (dword != dword_old ) {
+	if (dword != dword_old ) {
-                pci_write_config32(dev, 0x4c, dword);
+		pci_write_config32(dev, 0x4c, dword);
-        }
+	}
 
-        dword_old = pci_read_config32(dev, 0x6c);
+	dword_old = pci_read_config32(dev, 0x6c);
-        dword = dword_old | (1<<9); //unhide Timer Func in pci space
+	dword = dword_old | (1<<9); //unhide Timer Func in pci space
-        if (dword != dword_old ) {
+	if (dword != dword_old ) {
-                pci_write_config32(dev, 0x6c, dword);
+		pci_write_config32(dev, 0x6c, dword);
-        }
+	}
 
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0);
 
-        /* enable cf9 */
+	/* enable cf9 */
-        pci_write_config8(dev, 0x40, (1<<2));
+	pci_write_config8(dev, 0x40, (1<<2));
 }
 
 unsigned get_sbdn(unsigned bus)
 {
-        device_t dev;
+	device_t dev;
 
-        /* Find the device.
+	/* Find the device.
-         * There can only be one bcm5785 on a hypertransport chain/bus.
+	 * There can only be one bcm5785 on a hypertransport chain/bus.
-         */
+	 */
-        dev = pci_locate_device_on_bus(
+	dev = pci_locate_device_on_bus(
-                PCI_ID(0x1166, 0x0036),
+		PCI_ID(0x1166, 0x0036),
-                bus);
+		bus);
 
-        return (dev>>15) & 0x1f;
+	return (dev>>15) & 0x1f;
 
 }
 
@@ -89,8 +89,8 @@ void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
 	// set port to 0x2060
 	outb(0x67, 0xcd6);
 	outb(0x60, 0xcd7);
-        outb(0x68, 0xcd6);
+	outb(0x68, 0xcd6);
-        outb(0x20, 0xcd7);
+	outb(0x20, 0xcd7);
 
 	outb(0x69, 0xcd6);
 	outb(7, 0xcd7);
@@ -107,113 +107,113 @@ void ldtstop_sb(void)
 
 void hard_reset(void)
 {
-        bcm5785_enable_wdt_port_cf9();
+	bcm5785_enable_wdt_port_cf9();
 
-        set_bios_reset();
+	set_bios_reset();
 
-        /* full reset */
+	/* full reset */
-        outb(0x0a, 0x0cf9);
+	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
+	outb(0x0e, 0x0cf9);
 }
 
 void soft_reset(void)
 {
-        bcm5785_enable_wdt_port_cf9();
+	bcm5785_enable_wdt_port_cf9();
 
-        set_bios_reset();
+	set_bios_reset();
 #if 1
-        /* link reset */
+	/* link reset */
-//        outb(0x02, 0x0cf9);
+//	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
+	outb(0x06, 0x0cf9);
 #endif
 }
 
 static void bcm5785_enable_msg(void)
 {
-        device_t dev;
+	device_t dev;
-        uint32_t dword;
+	uint32_t dword;
-        uint32_t dword_old;
+	uint32_t dword_old;
-        uint8_t byte;
+	uint8_t byte;
 
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
 
-        byte = pci_read_config8(dev, 0x42);
+	byte = pci_read_config8(dev, 0x42);
-        byte = (1<<1); //enable a20
+	byte = (1<<1); //enable a20
-        pci_write_config8(dev, 0x42, byte);
+	pci_write_config8(dev, 0x42, byte);
 
-        dword_old = pci_read_config32(dev, 0x6c);
+	dword_old = pci_read_config32(dev, 0x6c);
-        // bit 5: enable A20 Message
+	// bit 5: enable A20 Message
-        // bit 4: enable interrupt messages
+	// bit 4: enable interrupt messages
-        // bit 3: enable reset init message
+	// bit 3: enable reset init message
-        // bit 2: enable keyboard init message
+	// bit 2: enable keyboard init message
-        // bit 1: enable upsteam messages
+	// bit 1: enable upsteam messages
-        // bit 0: enable shutdowm message to init generation
+	// bit 0: enable shutdowm message to init generation
-        dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
+	dword = dword_old | (1<<5) | (1<<3) | (1<<2) | (1<<1) | (1<<0); // bit 1 and bit 4 must be set, otherwise interrupt msg will not be delivered to the processor
-        if (dword != dword_old ) {
+	if (dword != dword_old ) {
-                pci_write_config32(dev, 0x6c, dword);
+		pci_write_config32(dev, 0x6c, dword);
-        }
+	}
 }
 
 static void bcm5785_early_setup(void)
 {
-        uint8_t byte;
+	uint8_t byte;
-        uint32_t dword;
+	uint32_t dword;
-        device_t dev;
+	device_t dev;
 
 //F0
-        // enable device on bcm5785 at first
+	// enable device on bcm5785 at first
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0);
-        dword = pci_read_config32(dev, 0x64);
+	dword = pci_read_config32(dev, 0x64);
-        dword |=  (1<<15) | (1<<11) | (1<<3); // ioapci enable
+	dword |=  (1<<15) | (1<<11) | (1<<3); // ioapci enable
-        dword |= (1<<8); // USB enable
+	dword |= (1<<8); // USB enable
-        dword |= /* (1<<27)|*/(1<<14); // IDE enable
+	dword |= /* (1<<27)|*/(1<<14); // IDE enable
-        pci_write_config32(dev, 0x64, dword);
+	pci_write_config32(dev, 0x64, dword);
 
-        byte = pci_read_config8(dev, 0x84);
+	byte = pci_read_config8(dev, 0x84);
-        byte |= (1<<0); // SATA enable
+	byte |= (1<<0); // SATA enable
-        pci_write_config8(dev, 0x84, byte);
+	pci_write_config8(dev, 0x84, byte);
 
 // WDT and cf9 for later in ramstage to call hard_reset
-        bcm5785_enable_wdt_port_cf9();
+	bcm5785_enable_wdt_port_cf9();
 
-        bcm5785_enable_msg();
+	bcm5785_enable_msg();
 
 
 // IDE related
 	//F0
-        byte = pci_read_config8(dev, 0x4e);
+	byte = pci_read_config8(dev, 0x4e);
-        byte |= (1<<4); //enable IDE ext regs
+	byte |= (1<<4); //enable IDE ext regs
-        pci_write_config8(dev, 0x4e, byte);
+	pci_write_config8(dev, 0x4e, byte);
 
 	//F1
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0214), 0);
-        byte = pci_read_config8(dev, 0x48);
+	byte = pci_read_config8(dev, 0x48);
-        byte &= ~1; // disable pri channel
+	byte &= ~1; // disable pri channel
-        pci_write_config8(dev, 0x48, byte);
+	pci_write_config8(dev, 0x48, byte);
-        pci_write_config8(dev, 0xb0, 0x01);
+	pci_write_config8(dev, 0xb0, 0x01);
-        pci_write_config8(dev, 0xb2, 0x02);
+	pci_write_config8(dev, 0xb2, 0x02);
-        byte = pci_read_config8(dev, 0x06);
+	byte = pci_read_config8(dev, 0x06);
-        byte |= (1<<4); // so b0, b2 can not be changed from now
+	byte |= (1<<4); // so b0, b2 can not be changed from now
-        pci_write_config8(dev, 0x06, byte);
+	pci_write_config8(dev, 0x06, byte);
-        byte = pci_read_config8(dev, 0x49);
+	byte = pci_read_config8(dev, 0x49);
-        byte |= 1; // enable second channel
+	byte |= 1; // enable second channel
-        pci_write_config8(dev, 0x49, byte);
+	pci_write_config8(dev, 0x49, byte);
 
 	//F2
-        dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
+	dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0);
 
-        byte = pci_read_config8(dev, 0x40);
+	byte = pci_read_config8(dev, 0x40);
-        byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
+	byte |= (1<<3)|(1<<2); // LPC Retry, LPC to PCI DMA enable
-        pci_write_config8(dev, 0x40, byte);
+	pci_write_config8(dev, 0x40, byte);
 
-        pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
+	pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end
 
 // USB related
-        pci_write_config8(dev, 0x90, 0x40);
+	pci_write_config8(dev, 0x90, 0x40);
-        pci_write_config8(dev, 0x92, 0x06);
+	pci_write_config8(dev, 0x92, 0x06);
-        pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
+	pci_write_config8(dev, 0x9c, 0x7c); //PHY timinig register
-        pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
+	pci_write_config8(dev, 0xa4, 0x02); //mask reg - low/full speed func
-        pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
+	pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func
-        pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
+	pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func
-        pci_write_config8(dev, 0xb4, 0x40);
+	pci_write_config8(dev, 0xb4, 0x40);
 }

src/southbridge/broadcom/bcm5785/early_smbus.c

@@ -38,20 +38,20 @@ static void enable_smbus(void)
 
 static inline int smbus_recv_byte(unsigned device)
 {
-        return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+	return do_smbus_recv_byte(SMBUS_IO_BASE, device);
 }
 
 static inline int smbus_send_byte(unsigned device, unsigned char val)
 {
-        return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+	return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
 }
 
 static inline int smbus_read_byte(unsigned device, unsigned address)
 {
-        return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
 
 static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
 {
-        return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
+	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
 }

src/southbridge/broadcom/bcm5785/ide.c

@@ -23,13 +23,13 @@
 
 static void bcm5785_ide_read_resources(device_t dev)
 {
-        /* Get the normal pci resources of this device */
+	/* Get the normal pci resources of this device */
-        pci_dev_read_resources(dev);
+	pci_dev_read_resources(dev);
 
-        /* BAR */
+	/* BAR */
-        pci_get_resource(dev, 0x64);
+	pci_get_resource(dev, 0x64);
 
-        compact_resources(dev);
+	compact_resources(dev);
 }
 
 static void ide_init(struct device *dev)
@@ -38,12 +38,12 @@ static void ide_init(struct device *dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
+	pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations ide_ops  = {

src/southbridge/broadcom/bcm5785/lpc.c

@@ -74,15 +74,15 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
 	reg = pci_read_config8(dev, 0x44);
 
 	for (link = dev->link_list; link; link = link->next) {
-                device_t child;
+		device_t child;
-                for (child = link->children; child; child = child->sibling) {
+		for (child = link->children; child; child = child->sibling) {
-			if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
+			if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
 				struct resource *res;
-				for(res = child->resource_list; res; res = res->next) {
+				for (res = child->resource_list; res; res = res->next) {
-			                unsigned long base, end; // don't need long long
+					unsigned long base, end; // don't need long long
-					if(!(res->flags & IORESOURCE_IO)) continue;
+					if (!(res->flags & IORESOURCE_IO)) continue;
-		        	        base = res->base;
+					base = res->base;
-                			end = resource_end(res);
+					end = resource_end(res);
 					printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
 					switch(base) {
 					case 0x60: //KBC
@@ -103,8 +103,8 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
 					}
 				}
 			}
-                }
+		}
-        }
+	}
 	pci_write_config32(dev, 0x44, reg);
 
 
@@ -112,18 +112,18 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
 
 static void bcm5785_lpc_enable_resources(device_t dev)
 {
-        pci_dev_enable_resources(dev);
+	pci_dev_enable_resources(dev);
-        bcm5785_lpc_enable_childrens_resources(dev);
+	bcm5785_lpc_enable_childrens_resources(dev);
 }
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
+	pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations lpc_ops  = {

src/southbridge/broadcom/bcm5785/reset.c

@@ -18,24 +18,24 @@
 #include <reset.h>
 
 #define PCI_DEV(BUS, DEV, FN) ( \
-        (((BUS) & 0xFFF) << 20) | \
+	(((BUS) & 0xFFF) << 20) | \
-        (((DEV) & 0x1F) << 15) | \
+	(((DEV) & 0x1F) << 15) | \
-        (((FN)  & 0x7) << 12))
+	(((FN)  & 0x7) << 12))
 
 static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
 {
-        unsigned addr;
+	unsigned addr;
-        addr = (dev>>4) | where;
+	addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(0x80000000 | (addr & ~3), 0xCF8);
-        outl(value, 0xCFC);
+	outl(value, 0xCFC);
 }
 
 static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
 {
-        unsigned addr;
+	unsigned addr;
-        addr = (dev>>4) | where;
+	addr = (dev>>4) | where;
-        outl(0x80000000 | (addr & ~3), 0xCF8);
+	outl(0x80000000 | (addr & ~3), 0xCF8);
-        return inl(0xCFC);
+	return inl(0xCFC);
 }
 
 #include "../../../northbridge/amd/amdk8/reset_test.c"
@@ -43,7 +43,7 @@ static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
 void hard_reset(void)
 {
 	set_bios_reset();
-        /* Try rebooting through port 0xcf9 */
+	/* Try rebooting through port 0xcf9 */
 	/* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */
 	outb((0 <<3)|(0<<2)|(1<<1), 0xcf9);
       	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);

src/southbridge/broadcom/bcm5785/sata.c

@@ -28,41 +28,41 @@ static void sata_init(struct device *dev)
 	uint8_t byte;
 
 	u8 *mmio;
-        struct resource *res;
+	struct resource *res;
-        u8 *mmio_base;
+	u8 *mmio_base;
 	int i;
 
-	if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
+	if (!(dev->path.pci.devfn & 7)) { // only set it in Func0
 		byte = pci_read_config8(dev, 0x78);
 		byte |= (1<<7);
-        	pci_write_config8(dev, 0x78, byte);
+		pci_write_config8(dev, 0x78, byte);
 
 	        res = find_resource(dev, 0x24);
-                mmio_base = res2mmio(res, 0, 3);
+		mmio_base = res2mmio(res, 0, 3);
 
 		write32(mmio_base + 0x10f0, 0x40000001);
 		write32(mmio_base + 0x8c, 0x00ff2007);
-                mdelay( 10 );
+		mdelay( 10 );
 		write32(mmio_base + 0x8c, 0x78592009);
-                mdelay( 10 );
+		mdelay( 10 );
 		write32(mmio_base + 0x8c, 0x00082004);
-                mdelay( 10 );
+		mdelay( 10 );
 		write32(mmio_base + 0x8c, 0x00002004);
-                mdelay( 10 );
+		mdelay( 10 );
 
 		//init PHY
 
 		printk(BIOS_DEBUG, "init PHY...\n");
-		for(i=0; i<4; i++) {
+		for (i=0; i<4; i++) {
 			mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
 			byte = read8(mmio + 0x40);
 			printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
-			if(byte & 0x4) {// bit 2 is set
+			if (byte & 0x4) {// bit 2 is set
 				byte = read8(mmio+0x48);
 				write8(mmio + 0x48, byte | 1);
 				write8(mmio + 0x48, byte & (~1));
-	                        byte = read8(mmio + 0x40);
+				byte = read8(mmio + 0x40);
-	                        printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
+				printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte);
 			}
 		}
 	}
@@ -70,12 +70,12 @@ static void sata_init(struct device *dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
+	pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations sata_ops  = {

src/southbridge/broadcom/bcm5785/sb_pci_main.c

@@ -45,7 +45,7 @@ static void sb_init(device_t dev)
 	} else {
 		byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
 	}
-	if( byte != byte_old) {
+	if ( byte != byte_old) {
 		outb(byte, 0x70);
 	}
 
@@ -63,101 +63,101 @@ static void bcm5785_sb_read_resources(device_t dev)
 
 	compact_resources(dev);
 
-        /* Add an extra subtractive resource for both memory and I/O */
+	/* Add an extra subtractive resource for both memory and I/O */
-        res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-        res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
-        res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-        res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
 
 }
 
 static int lsmbus_recv_byte(device_t dev)
 {
-        unsigned device;
+	unsigned device;
-        struct resource *res;
+	struct resource *res;
 	struct bus *pbus;
 
-        device = dev->path.i2c.device;
+	device = dev->path.i2c.device;
 	pbus = get_pbus_smbus(dev);
 
-        res = find_resource(pbus->dev, 0x90);
+	res = find_resource(pbus->dev, 0x90);
 
-        return do_smbus_recv_byte(res->base, device);
+	return do_smbus_recv_byte(res->base, device);
 }
 
 static int lsmbus_send_byte(device_t dev, uint8_t val)
 {
-        unsigned device;
+	unsigned device;
-        struct resource *res;
+	struct resource *res;
-        struct bus *pbus;
+	struct bus *pbus;
 
-        device = dev->path.i2c.device;
+	device = dev->path.i2c.device;
-        pbus = get_pbus_smbus(dev);
+	pbus = get_pbus_smbus(dev);
 
-        res = find_resource(pbus->dev, 0x90);
+	res = find_resource(pbus->dev, 0x90);
 
-        return do_smbus_send_byte(res->base, device, val);
+	return do_smbus_send_byte(res->base, device, val);
 }
 
 static int lsmbus_read_byte(device_t dev, uint8_t address)
 {
-        unsigned device;
+	unsigned device;
-        struct resource *res;
+	struct resource *res;
-        struct bus *pbus;
+	struct bus *pbus;
 
-        device = dev->path.i2c.device;
+	device = dev->path.i2c.device;
-        pbus = get_pbus_smbus(dev);
+	pbus = get_pbus_smbus(dev);
 
-        res = find_resource(pbus->dev, 0x90);
+	res = find_resource(pbus->dev, 0x90);
 
-        return do_smbus_read_byte(res->base, device, address);
+	return do_smbus_read_byte(res->base, device, address);
 }
 
 static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
 {
-        unsigned device;
+	unsigned device;
-        struct resource *res;
+	struct resource *res;
-        struct bus *pbus;
+	struct bus *pbus;
 
-        device = dev->path.i2c.device;
+	device = dev->path.i2c.device;
-        pbus = get_pbus_smbus(dev);
+	pbus = get_pbus_smbus(dev);
 
-        res = find_resource(pbus->dev, 0x90);
+	res = find_resource(pbus->dev, 0x90);
 
-        return do_smbus_write_byte(res->base, device, address, val);
+	return do_smbus_write_byte(res->base, device, address, val);
 }
 
 static struct smbus_bus_operations lops_smbus_bus = {
-        .recv_byte  = lsmbus_recv_byte,
+	.recv_byte  = lsmbus_recv_byte,
-        .send_byte  = lsmbus_send_byte,
+	.send_byte  = lsmbus_send_byte,
-        .read_byte  = lsmbus_read_byte,
+	.read_byte  = lsmbus_read_byte,
-        .write_byte = lsmbus_write_byte,
+	.write_byte = lsmbus_write_byte,
 };
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x2c,
+	pci_write_config32(dev, 0x2c,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations sb_ops = {
-        .read_resources   = bcm5785_sb_read_resources,
+	.read_resources   = bcm5785_sb_read_resources,
-        .set_resources    = pci_dev_set_resources,
+	.set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
-        .init             = sb_init,
+	.init             = sb_init,
-        .scan_bus         = scan_smbus,
+	.scan_bus         = scan_smbus,
 //        .enable           = bcm5785_enable,
-        .ops_pci          = &lops_pci,
+	.ops_pci          = &lops_pci,
-        .ops_smbus_bus    = &lops_smbus_bus,
+	.ops_smbus_bus    = &lops_smbus_bus,
 };
 
 static const struct pci_driver sb_driver __pci_driver = {
-        .ops    = &sb_ops,
+	.ops    = &sb_ops,
-        .vendor = PCI_VENDOR_ID_SERVERWORKS,
+	.vendor = PCI_VENDOR_ID_SERVERWORKS,
-        .device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
+	.device = PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN,
 };

src/southbridge/broadcom/bcm5785/smbus.h

@@ -53,7 +53,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 			return 0;
 		}
 		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while(--loops);
+	} while (--loops);
 	return -2; // time out
 }
 
@@ -73,7 +73,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 			outb(val, smbus_io_base + SMBHSTSTAT); // clear status
 			return 0; //
 		}
-	} while(--loops);
+	} while (--loops);
 	return -3; // timeout
 }
 
@@ -81,54 +81,54 @@ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)
 {
 	uint8_t byte;
 
-        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-                return -2; // not ready
+		return -2; // not ready
-        }
+	}
 
-        /* set the device I'm talking too */
+	/* set the device I'm talking too */
-        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
 
-        byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte = inb(smbus_io_base + SMBHSTCTRL);
-        byte &= 0xe3; // Clear [4:2]
+	byte &= 0xe3; // Clear [4:2]
-        byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+	byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
-        outb(byte, smbus_io_base + SMBHSTCTRL);
+	outb(byte, smbus_io_base + SMBHSTCTRL);
 
-        /* poll for transaction completion */
+	/* poll for transaction completion */
-        if (smbus_wait_until_done(smbus_io_base) < 0) {
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
-                return -3; // timeout or error
+		return -3; // timeout or error
-        }
+	}
 
-        /* read results of transaction */
+	/* read results of transaction */
-        byte = inb(smbus_io_base + SMBHSTCMD);
+	byte = inb(smbus_io_base + SMBHSTCMD);
 
 	return byte;
 }
 
 static int do_smbus_send_byte(unsigned smbus_io_base, unsigned device, unsigned char val)
 {
-        uint8_t byte;
+	uint8_t byte;
 
-        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-                return -2; // not ready
+		return -2; // not ready
-        }
+	}
 
-        /* set the command... */
+	/* set the command... */
-        outb(val, smbus_io_base + SMBHSTCMD);
+	outb(val, smbus_io_base + SMBHSTCMD);
 
-        /* set the device I'm talking too */
+	/* set the device I'm talking too */
-        outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+	outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
 
-        byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte = inb(smbus_io_base + SMBHSTCTRL);
-        byte &= 0xe3; // Clear [4:2]
+	byte &= 0xe3; // Clear [4:2]
-        byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
+	byte |= (1<<2) | (1<<6); // Byte data read/write command, start the command
-        outb(byte, smbus_io_base + SMBHSTCTRL);
+	outb(byte, smbus_io_base + SMBHSTCTRL);
 
-        /* poll for transaction completion */
+	/* poll for transaction completion */
-        if (smbus_wait_until_done(smbus_io_base) < 0) {
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
-                return -3; // timeout or error
+		return -3; // timeout or error
-        }
+	}
 
-        return 0;
+	return 0;
 }
 
 static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address)
@@ -142,8 +142,8 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
 	/* set the command/address... */
 	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
 
-        /* set the device I'm talking too */
+	/* set the device I'm talking too */
-        outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
+	outb(((device & 0x7f) << 1)|1 , smbus_io_base + SMBHSTADDR);
 
 	byte = inb(smbus_io_base + SMBHSTCTRL);
 	byte &= 0xe3; // Clear [4:2]
@@ -163,30 +163,30 @@ static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned
 
 static int do_smbus_write_byte(unsigned smbus_io_base, unsigned device, unsigned address, unsigned char val)
 {
-        uint8_t byte;
+	uint8_t byte;
 
-        if (smbus_wait_until_ready(smbus_io_base) < 0) {
+	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-                return -2; // not ready
+		return -2; // not ready
-        }
+	}
 
-        /* set the command/address... */
+	/* set the command/address... */
-        outb(address & 0xff, smbus_io_base + SMBHSTCMD);
+	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
 
-        /* set the device I'm talking too */
+	/* set the device I'm talking too */
-        outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
+	outb(((device & 0x7f) << 1)|0 , smbus_io_base + SMBHSTADDR);
 
-        /* output value */
+	/* output value */
-        outb(val, smbus_io_base + SMBHSTDAT0);
+	outb(val, smbus_io_base + SMBHSTDAT0);
 
-        byte = inb(smbus_io_base + SMBHSTCTRL);
+	byte = inb(smbus_io_base + SMBHSTCTRL);
-        byte &= 0xe3; // Clear [4:2]
+	byte &= 0xe3; // Clear [4:2]
-        byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
+	byte |= (1<<3) | (1<<6); // Byte data read/write command, start the command
-        outb(byte, smbus_io_base + SMBHSTCTRL);
+	outb(byte, smbus_io_base + SMBHSTCTRL);
 
-        /* poll for transaction completion */
+	/* poll for transaction completion */
-        if (smbus_wait_until_done(smbus_io_base) < 0) {
+	if (smbus_wait_until_done(smbus_io_base) < 0) {
-                return -3; // timeout or error
+		return -3; // timeout or error
-        }
+	}
 
-        return 0;
+	return 0;
 }

src/southbridge/broadcom/bcm5785/usb.c

@@ -23,7 +23,7 @@
 
 static void usb_init(struct device *dev)
 {
-        uint32_t dword;
+	uint32_t dword;
 
 	dword = pci_read_config32(dev, 0x04);
 	dword |= (1<<2)|(1<<1)|(1<<0);
@@ -35,12 +35,12 @@ static void usb_init(struct device *dev)
 
 static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
-        pci_write_config32(dev, 0x40,
+	pci_write_config32(dev, 0x40,
-                ((device & 0xffff) << 16) | (vendor & 0xffff));
+		((device & 0xffff) << 16) | (vendor & 0xffff));
 }
 
 static struct pci_operations lops_pci = {
-        .set_subsystem = lpci_set_subsystem,
+	.set_subsystem = lpci_set_subsystem,
 };
 
 static struct device_operations usb_ops  = {

src/southbridge/intel/bd82x6x/azalia.c

@@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 1000;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -145,7 +145,7 @@ static int wait_for_valid(u8 *base)
 	/* Use a 1msec timeout */
 
 	int timeout = 1000;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/intel/bd82x6x/lpc.c

@@ -125,7 +125,7 @@ static void pch_pirq_init(device_t dev)
 	pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
 	pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

src/southbridge/intel/bd82x6x/me.c

@@ -445,7 +445,7 @@ static int mkhi_get_fwcaps(void)
 	print_cap("IntelR Power Sharing Technology (MPC)",
 		  cap.caps_sku.intel_mpc);
 	print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
 	print_cap("IPV6", cap.caps_sku.ipv6);
 	print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);

src/southbridge/intel/bd82x6x/me_8.x.c

@@ -703,7 +703,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-		if(intel_me_read_mbp(&mbp_data))
+		if (intel_me_read_mbp(&mbp_data))
 			break;
 
 #if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -893,7 +893,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 		default:
 			printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n",
 			       mbp_item_id);
-			while(copy_size--)
+			while (copy_size--)
 				read_cb();
 			continue;
 		}
@@ -904,7 +904,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 			       buffer_room, copy_size, mbp_item_id);
 			return -1;
 		}
-		while(copy_size--)
+		while (copy_size--)
 			*copy_addr++ = read_cb();
 	}
 
@@ -914,7 +914,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	{
 		int cntr = 0;
-		while(host.interrupt_generate) {
+		while (host.interrupt_generate) {
 			read_host_csr(&host);
 			cntr++;
 		}

src/southbridge/intel/bd82x6x/reset.c

@@ -19,10 +19,10 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }

src/southbridge/intel/bd82x6x/smihandler.c

@@ -271,37 +271,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
+	int slot, func;
-        unsigned int val;
+	unsigned int val;
-        unsigned char hdr;
+	unsigned char hdr;
 
-        for (slot = 0; slot < 0x20; slot++) {
+	for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
+		for (func = 0; func < 8; func++) {
-                        u32 reg32;
+			u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
+			device_t dev = PCI_DEV(bus, slot, func);
 
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
-                        if (val == 0xffffffff || val == 0x00000000 ||
+			if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
+			    val == 0x0000ffff || val == 0xffff0000)
-                                continue;
+				continue;
 
-                        /* Disable Bus Mastering for this one device */
+			/* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
+			reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+			pci_write_config32(dev, PCI_COMMAND, reg32);
 
-                        /* If this is a bridge, then follow it. */
+			/* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
+			hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
+				unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
+			}
-                }
+		}
-        }
+	}
 }
 
 static void southbridge_gate_memory_reset_real(int offset,
@@ -863,7 +863,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 

src/southbridge/intel/fsp_bd82x6x/azalia.c

@@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/intel/fsp_bd82x6x/lpc.c

@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

src/southbridge/intel/fsp_bd82x6x/me.c

@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
 	print_cap("IntelR Power Sharing Technology (MPC)",
 		  cap.caps_sku.intel_mpc);
 	print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
 	print_cap("IPV6", cap.caps_sku.ipv6);
 	print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);

src/southbridge/intel/fsp_bd82x6x/me_8.x.c

@@ -385,11 +385,10 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap)
 	};
 
 	/* Send request and wait for response */
-	if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg))
+	if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) {
-	    < 0) {
 		printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
 		return -1;
-        }
+	}
 	*cap = cap_msg.caps_sku;
 	return 0;
 }
@@ -413,7 +412,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
 	print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
 	print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
 	print_cap("ICC Over Clocking", cap->icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
 	print_cap("IPV6", cap->ipv6);
 	print_cap("KVM Remote Control (KVM)", cap->kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -702,7 +701,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-		if(intel_me_read_mbp(&mbp_data))
+		if (intel_me_read_mbp(&mbp_data))
 			break;
 
 #if CONFIG_CHROMEOS && 0 /* DISABLED */
@@ -901,7 +900,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 			       buffer_room, copy_size, mbp_item_id);
 			return -1;
 		}
-		while(copy_size--)
+		while (copy_size--)
 			*copy_addr++ = read_cb();
 	}
 
@@ -911,7 +910,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	{
 		int cntr = 0;
-		while(host.interrupt_generate) {
+		while (host.interrupt_generate) {
 			read_host_csr(&host);
 			cntr++;
 		}

src/southbridge/intel/fsp_bd82x6x/reset.c

@@ -20,10 +20,10 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 void hard_reset(void)
 {
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }

src/southbridge/intel/fsp_bd82x6x/smihandler.c

@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
+	int slot, func;
-        unsigned int val;
+	unsigned int val;
-        unsigned char hdr;
+	unsigned char hdr;
 
-        for (slot = 0; slot < 0x20; slot++) {
+	for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
+		for (func = 0; func < 8; func++) {
-                        u32 reg32;
+			u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
+			device_t dev = PCI_DEV(bus, slot, func);
 
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
-                        if (val == 0xffffffff || val == 0x00000000 ||
+			if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
+			    val == 0x0000ffff || val == 0xffff0000)
-                                continue;
+				continue;
 
-                        /* Disable Bus Mastering for this one device */
+			/* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
+			reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+			pci_write_config32(dev, PCI_COMMAND, reg32);
 
-                        /* If this is a bridge, then follow it. */
+			/* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
+			hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
+				unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
+			}
-                }
+		}
-        }
+	}
 }
 
 /*
@@ -749,7 +749,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 

src/southbridge/intel/fsp_i89xx/lpc.c

@@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

src/southbridge/intel/fsp_i89xx/me.c

@@ -444,7 +444,7 @@ static int mkhi_get_fwcaps(void)
 	print_cap("IntelR Power Sharing Technology (MPC)",
 		  cap.caps_sku.intel_mpc);
 	print_cap("ICC Over Clocking", cap.caps_sku.icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap.caps_sku.pavp);
 	print_cap("IPV6", cap.caps_sku.ipv6);
 	print_cap("KVM Remote Control (KVM)", cap.caps_sku.kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap.caps_sku.och);

src/southbridge/intel/fsp_i89xx/me_8.x.c

@@ -413,7 +413,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section)
 	print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls);
 	print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc);
 	print_cap("ICC Over Clocking", cap->icc_over_clocking);
-        print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
+	print_cap("Protected Audio Video Path (PAVP)", cap->pavp);
 	print_cap("IPV6", cap->ipv6);
 	print_cap("KVM Remote Control (KVM)", cap->kvm);
 	print_cap("Outbreak Containment Heuristic (OCH)", cap->och);
@@ -670,7 +670,7 @@ static void intel_me_init(device_t dev)
 		if (intel_mei_setup(dev) < 0)
 			break;
 
-		if(intel_me_read_mbp(&mbp_data))
+		if (intel_me_read_mbp(&mbp_data))
 			break;
 
 #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
@@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 			       buffer_room, copy_size, mbp_item_id);
 			return -1;
 		}
-		while(copy_size--)
+		while (copy_size--)
 			*copy_addr++ = read_cb();
 	}
 
@@ -865,7 +865,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
 
 	{
 		int cntr = 0;
-		while(host.interrupt_generate) {
+		while (host.interrupt_generate) {
 			read_host_csr(&host);
 			cntr++;
 		}

src/southbridge/intel/fsp_i89xx/romstage.c

@@ -203,7 +203,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 
 	cbmem_was_initted = !cbmem_recovery(0);
 
-	if(cbmem_was_initted) {
+	if (cbmem_was_initted) {
 		reset_system();
 	}
 

src/southbridge/intel/fsp_i89xx/smihandler.c

@@ -235,37 +235,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
+	int slot, func;
-        unsigned int val;
+	unsigned int val;
-        unsigned char hdr;
+	unsigned char hdr;
 
-        for (slot = 0; slot < 0x20; slot++) {
+	for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
+		for (func = 0; func < 8; func++) {
-                        u32 reg32;
+			u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
+			device_t dev = PCI_DEV(bus, slot, func);
 
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
-                        if (val == 0xffffffff || val == 0x00000000 ||
+			if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
+			    val == 0x0000ffff || val == 0xffff0000)
-                                continue;
+				continue;
 
-                        /* Disable Bus Mastering for this one device */
+			/* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
+			reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+			pci_write_config32(dev, PCI_COMMAND, reg32);
 
-                        /* If this is a bridge, then follow it. */
+			/* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
+			hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
+				unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
+			}
-                }
+		}
-        }
+	}
 }
 
 /*
@@ -746,7 +746,7 @@ void southbridge_smi_handler(void)
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 

src/southbridge/intel/fsp_rangeley/gpio.c

@@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
 	/* CFIO Core Well Set 1 */
 	if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
 		write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
-		for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
+		for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
 			if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
 				continue;
 			write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
@@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
 	/* CFIO SUS Well Set 1 */
 	if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
 		write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
-		for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
+		for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
 			if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
 				continue;
 			write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);

src/southbridge/intel/fsp_rangeley/lpc.c

@@ -137,7 +137,7 @@ static void write_pci_config_irqs(void)
 	 * the Interrupt Route registers in the ILB
 	 */
 	printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 
 		if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
 			(!irq_dev->enabled))
@@ -225,7 +225,7 @@ static void soc_pirq_init(device_t dev)
 		write16(ir_base + i, ir->pcidev[i]);
 
 		/* If the entry is more than just 0, print it out */
-		if(ir->pcidev[i]) {
+		if (ir->pcidev[i]) {
 			printk(BIOS_SPEW, " %d: ", i);
 			for (j = 0; j < 4; j++) {
 				pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;

src/southbridge/intel/i3100/early_smbus.c

@@ -27,7 +27,7 @@ static void enable_smbus(void)
 	pci_write_config8(dev, 0x40, 1);
 	pci_write_config8(dev, 0x4, 1);
 	/* SMBALERT_DIS */
-        outb(4, SMBUS_IO_BASE + SMBSLVCMD);
+	outb(4, SMBUS_IO_BASE + SMBSLVCMD);
 
 	/* Disable interrupt generation */
 	outb(0, SMBUS_IO_BASE + SMBHSTCTL);

src/southbridge/intel/i3100/lpc.c

@@ -206,19 +206,19 @@ static void i3100_pirq_init(device_t dev)
 	if (config->pirq_e_h)
 		pci_write_config32(dev, 0x68, config->pirq_e_h);
 
-        for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
-                u8 int_pin=0, int_line=0;
+		u8 int_pin=0, int_line=0;
 
-                if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
-                        continue;
+			continue;
 
-                int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+		int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
-                switch (int_pin) {
+		switch (int_pin) {
-                case 1: /* INTA# */
+		case 1: /* INTA# */
 			int_line = config->pirq_a_d & 0xff;
 			break;
 
-                case 2: /* INTB# */
+		case 2: /* INTB# */
 			int_line = (config->pirq_a_d >> 8) & 0xff;
 			break;
 
@@ -226,17 +226,17 @@ static void i3100_pirq_init(device_t dev)
 			int_line = (config->pirq_a_d >> 16) & 0xff;
 			break;
 
-                case 4: /* INTD# */
+		case 4: /* INTD# */
 			int_line = (config->pirq_a_d >> 24) & 0xff;
 			break;
-                }
+		}
 
-                if (!int_line)
+		if (!int_line)
-                        continue;
+			continue;
 
 		printk(BIOS_DEBUG, "%s: irq pin %d, irq line %d\n", dev_path(irq_dev), int_pin, int_line);
-                pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+		pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
-        }
+	}
 
 
 }

src/southbridge/intel/i3100/sata.c

@@ -42,7 +42,7 @@ static void sata_init(struct device *dev)
 	/* Enable SATA devices */
 	printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
 
-	if(ahci) {
+	if (ahci) {
 	  /* AHCI mode */
 	  pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
 

src/southbridge/intel/i82371eb/acpi_tables.c

@@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void)
 {
 	device_t cpu;
 	int count = 0;
-	for(cpu = all_devices; cpu; cpu = cpu->next) {
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
 		if ((cpu->path.type != DEVICE_PATH_APIC) ||
 			(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
 			continue;

src/southbridge/intel/i82371eb/smbus.h

@@ -35,12 +35,12 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 			break;
 		}
 #if 0
-		if(loops == (SMBUS_TIMEOUT / 2)) {
+		if (loops == (SMBUS_TIMEOUT / 2)) {
 			outw(inw(smbus_io_base + SMBHST_STATUS),
 				smbus_io_base + SMBHST_STATUS);
 		}
 #endif
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
@@ -62,7 +62,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 		if (val & 0xfe) {
 			break;
 		}
-	} while(--loops);
+	} while (--loops);
 	return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
 }
 

src/southbridge/intel/i82801dx/smihandler.c

@@ -233,37 +233,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
+	int slot, func;
-        unsigned int val;
+	unsigned int val;
-        unsigned char hdr;
+	unsigned char hdr;
 
-        for (slot = 0; slot < 0x20; slot++) {
+	for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
+		for (func = 0; func < 8; func++) {
-                        u32 reg32;
+			u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
+			device_t dev = PCI_DEV(bus, slot, func);
 
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
-                        if (val == 0xffffffff || val == 0x00000000 ||
+			if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
+			    val == 0x0000ffff || val == 0xffff0000)
-                                continue;
+				continue;
 
-                        /* Disable Bus Mastering for this one device */
+			/* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
+			reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+			pci_write_config32(dev, PCI_COMMAND, reg32);
 
-                        /* If this is a bridge, then follow it. */
+			/* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
+			hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
+				unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
+			}
-                }
+		}
-        }
+	}
 }
 
 
@@ -636,7 +636,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 

src/southbridge/intel/i82801ex/early_smbus.c

@@ -81,7 +81,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 	/* setup transaction */
 	/* Obtain ownership */
 	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	for(stat=0;(stat&0x40)==0;) {
+	for (stat=0;(stat&0x40)==0;) {
 	stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
 	}
 	/* clear the done bit */
@@ -105,7 +105,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 	outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
 			SMBUS_IO_BASE + SMBHSTCTL);
 
-	for(i=0;i<length;i++) {
+	for (i=0;i<length;i++) {
 
 		/* poll for transaction completion */
 		if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
@@ -113,7 +113,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
 		}
 
 		/* load the next byte */
-		if(i>3)
+		if (i>3)
 			byte=(data2>>(i%4))&0x0ff;
 		else
 			byte=(data1>>(i))&0x0ff;

src/southbridge/intel/i82801ex/lpc.c

@@ -78,8 +78,8 @@ static void i82801ex_pci_dma_cfg(device_t dev)
 #define LPC_EN 0xe6
 static void i82801ex_enable_lpc(device_t dev)
 {
-        /* lpc i/f enable */
+	/* lpc i/f enable */
-        pci_write_config8(dev, LPC_EN, 0x0d);
+	pci_write_config8(dev, LPC_EN, 0x0d);
 }
 
 typedef struct southbridge_intel_i82801ex_config config_t;
@@ -92,7 +92,7 @@ static void set_i82801ex_gpio_use_sel(
 
 	gpio_use_sel  = 0x1A003180;
 	gpio_use_sel2 = 0x00000007;
-	for(i = 0; i < 64; i++) {
+	for (i = 0; i < 64; i++) {
 		int val;
 		switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
 		case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
@@ -121,7 +121,7 @@ static void set_i82801ex_gpio_direction(
 
 	gpio_io_sel  = 0x0000ffff;
 	gpio_io_sel2 = 0x00000300;
-	for(i = 0; i < 64; i++) {
+	for (i = 0; i < 64; i++) {
 		int val;
 		switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
 		case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
@@ -152,7 +152,7 @@ static void set_i82801ex_gpio_level(
 	gpio_lvl   = 0x1b3f0000;
 	gpio_blink = 0x00040000;
 	gpio_lvl2  = 0x00030207;
-	for(i = 0; i < 64; i++) {
+	for (i = 0; i < 64; i++) {
 		int val, blink;
 		switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
 		case ICH5R_GPIO_LVL_LOW:   val = 0; blink = 0; break;
@@ -184,7 +184,7 @@ static void set_i82801ex_gpio_inv(
 	int i;
 
 	gpio_inv   = 0x00000000;
-	for(i = 0; i < 32; i++) {
+	for (i = 0; i < 32; i++) {
 		int val;
 		switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
 		case ICH5R_GPIO_INV_OFF: val = 0; break;
@@ -205,10 +205,10 @@ static void i82801ex_pirq_init(device_t dev)
 	/* Get the chip configuration */
 	config = dev->chip_info;
 
-	if(config->pirq_a_d) {
+	if (config->pirq_a_d) {
 		pci_write_config32(dev, 0x60, config->pirq_a_d);
 	}
-	if(config->pirq_e_h) {
+	if (config->pirq_e_h) {
 		pci_write_config32(dev, 0x68, config->pirq_e_h);
 	}
 }
@@ -292,7 +292,7 @@ static void lpc_init(struct device *dev)
 	/* Clear SATA to non raid */
 	pci_write_config8(dev, 0xae, 0x00);
 
-        get_option(&pwr_on, "power_on_after_fail");
+	get_option(&pwr_on, "power_on_after_fail");
 	byte = pci_read_config8(dev, 0xa4);
 	byte &= 0xfe;
 	if (!pwr_on) {

src/southbridge/intel/i82801ex/reset.c

@@ -3,6 +3,6 @@
 
 void hard_reset(void)
 {
-        /* Try rebooting through port 0xcf9 */
+	/* Try rebooting through port 0xcf9 */
-        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+	outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
 }

src/southbridge/intel/i82801ex/smbus.h

@@ -29,7 +29,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
 		if (--loops == 0)
 			break;
 		byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while(byte & 1);
+	} while (byte & 1);
 	return loops?0:-1;
 }
 
@@ -42,7 +42,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
 	        if (--loops == 0)
 	               break;
 	        byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
+	} while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
 	return loops?0:-1;
 }
 
@@ -55,7 +55,7 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
 	        if (--loops == 0)
 	               break;
 	        byte = inb(smbus_io_base + SMBHSTSTAT);
-	} while((byte&(1<<7)) == 0);
+	} while ((byte&(1<<7)) == 0);
 	return loops?0:-1;
 }
 

src/southbridge/intel/i82801ex/watchdog.c

@@ -6,23 +6,23 @@
 
 void watchdog_off(void)
 {
-        device_t dev;
+	device_t dev;
-        unsigned long value,base;
+	unsigned long value,base;
 
 	/* turn off the ICH5 watchdog */
-        dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
-        /* Enable I/O space */
+	/* Enable I/O space */
-        value = pci_read_config16(dev, 0x04);
+	value = pci_read_config16(dev, 0x04);
-        value |= (1 << 10);
+	value |= (1 << 10);
-        pci_write_config16(dev, 0x04, value);
+	pci_write_config16(dev, 0x04, value);
-        /* Get TCO base */
+	/* Get TCO base */
-        base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
-        /* Disable the watchdog timer */
+	/* Disable the watchdog timer */
-        value = inw(base + 0x08);
+	value = inw(base + 0x08);
-        value |= 1 << 11;
+	value |= 1 << 11;
-        outw(value, base + 0x08);
+	outw(value, base + 0x08);
-        /* Clear TCO timeout status */
+	/* Clear TCO timeout status */
-        outw(0x0008, base + 0x04);
+	outw(0x0008, base + 0x04);
-        outw(0x0002, base + 0x06);
+	outw(0x0002, base + 0x06);
-        printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
+	printk(BIOS_DEBUG, "Watchdog ICH5 disabled\n");
 }

src/southbridge/intel/i82801gx/azalia.c

@@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -146,7 +146,7 @@ static int wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/intel/i82801gx/bootblock.c

@@ -30,22 +30,22 @@ static void store_initial_timestamp(void)
 
 static void enable_spi_prefetch(void)
 {
-        u8 reg8;
+	u8 reg8;
-        pci_devfn_t dev;
+	pci_devfn_t dev;
 
-        dev = PCI_DEV(0, 0x1f, 0);
+	dev = PCI_DEV(0, 0x1f, 0);
 
-        reg8 = pci_read_config8(dev, 0xdc);
+	reg8 = pci_read_config8(dev, 0xdc);
-        reg8 &= ~(3 << 2);
+	reg8 &= ~(3 << 2);
-        reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-        pci_write_config8(dev, 0xdc, reg8);
+	pci_write_config8(dev, 0xdc, reg8);
 }
 
 static void bootblock_southbridge_init(void)
 {
 	store_initial_timestamp();
 
-        enable_spi_prefetch();
+	enable_spi_prefetch();
 
 	/* Enable RCBA */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);

src/southbridge/intel/i82801gx/lpc.c

@@ -108,7 +108,7 @@ static void i82801gx_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

src/southbridge/intel/i82801gx/reset.c

@@ -19,7 +19,7 @@
 
 void soft_reset(void)
 {
-        outb(0x04, 0xcf9);
+	outb(0x04, 0xcf9);
 }
 
 #if 0
@@ -32,6 +32,6 @@ void hard_reset(void)
 
 void hard_reset(void)
 {
-        outb(0x02, 0xcf9);
+	outb(0x02, 0xcf9);
-        outb(0x06, 0xcf9);
+	outb(0x06, 0xcf9);
 }

src/southbridge/intel/i82801gx/smbus.c

@@ -123,7 +123,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
 	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
 	     smbus_base + SMBHSTCTL);
 
-	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	while (!(inb(smbus_base + SMBHSTSTAT) & 1));
 	/* Poll for transaction completion */
 	do {
 		status = inb(smbus_base + SMBHSTSTAT);
@@ -136,7 +136,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
 			outb(*buf++, smbus_base + SMBBLKDAT);
 			outb(status, smbus_base + SMBHSTSTAT);
 		}
-	} while(status & 0x01);
+	} while (status & 0x01);
 
 	return 0;
 }
@@ -180,7 +180,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
 	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
 	     smbus_base + SMBHSTCTL);
 
-	while(!(inb(smbus_base + SMBHSTSTAT) & 1));
+	while (!(inb(smbus_base + SMBHSTSTAT) & 1));
 	/* Poll for transaction completion */
 	do {
 		status = inb(smbus_base + SMBHSTSTAT);
@@ -200,7 +200,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
 					 smbus_base + SMBHSTCTL);
 			}
 		}
-	} while(status & 0x01);
+	} while (status & 0x01);
 
 	return bytes_read;
 }

src/southbridge/intel/i82801gx/smihandler.c

@@ -269,37 +269,37 @@ void southbridge_smi_set_eos(void)
 
 static void busmaster_disable_on_bus(int bus)
 {
-        int slot, func;
+	int slot, func;
-        unsigned int val;
+	unsigned int val;
-        unsigned char hdr;
+	unsigned char hdr;
 
-        for (slot = 0; slot < 0x20; slot++) {
+	for (slot = 0; slot < 0x20; slot++) {
-                for (func = 0; func < 8; func++) {
+		for (func = 0; func < 8; func++) {
-                        u32 reg32;
+			u32 reg32;
-                        device_t dev = PCI_DEV(bus, slot, func);
+			device_t dev = PCI_DEV(bus, slot, func);
 
-                        val = pci_read_config32(dev, PCI_VENDOR_ID);
+			val = pci_read_config32(dev, PCI_VENDOR_ID);
 
-                        if (val == 0xffffffff || val == 0x00000000 ||
+			if (val == 0xffffffff || val == 0x00000000 ||
-                            val == 0x0000ffff || val == 0xffff0000)
+			    val == 0x0000ffff || val == 0xffff0000)
-                                continue;
+				continue;
 
-                        /* Disable Bus Mastering for this one device */
+			/* Disable Bus Mastering for this one device */
-                        reg32 = pci_read_config32(dev, PCI_COMMAND);
+			reg32 = pci_read_config32(dev, PCI_COMMAND);
-                        reg32 &= ~PCI_COMMAND_MASTER;
+			reg32 &= ~PCI_COMMAND_MASTER;
-                        pci_write_config32(dev, PCI_COMMAND, reg32);
+			pci_write_config32(dev, PCI_COMMAND, reg32);
 
-                        /* If this is a bridge, then follow it. */
+			/* If this is a bridge, then follow it. */
-                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+			hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
-                        hdr &= 0x7f;
+			hdr &= 0x7f;
-                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+			if (hdr == PCI_HEADER_TYPE_BRIDGE ||
-                            hdr == PCI_HEADER_TYPE_CARDBUS) {
+			    hdr == PCI_HEADER_TYPE_CARDBUS) {
-                                unsigned int buses;
+				unsigned int buses;
-                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+				buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
-                                busmaster_disable_on_bus((buses >> 8) & 0xff);
+				busmaster_disable_on_bus((buses >> 8) & 0xff);
-                        }
+			}
-                }
+		}
-        }
+	}
 }
 
 
@@ -673,7 +673,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 

src/southbridge/intel/i82801ix/bootblock.c

@@ -17,18 +17,18 @@
 
 static void enable_spi_prefetch(void)
 {
-        u8 reg8;
+	u8 reg8;
-        pci_devfn_t dev;
+	pci_devfn_t dev;
 
-        dev = PCI_DEV(0, 0x1f, 0);
+	dev = PCI_DEV(0, 0x1f, 0);
 
-        reg8 = pci_read_config8(dev, 0xdc);
+	reg8 = pci_read_config8(dev, 0xdc);
-        reg8 &= ~(3 << 2);
+	reg8 &= ~(3 << 2);
-        reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
-        pci_write_config8(dev, 0xdc, reg8);
+	pci_write_config8(dev, 0xdc, reg8);
 }
 
 static void bootblock_southbridge_init(void)
 {
-        enable_spi_prefetch();
+	enable_spi_prefetch();
 }

src/southbridge/intel/i82801ix/hdaudio.c

@@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
 
 	int timeout = 50;
 
-	while(timeout--) {
+	while (timeout--) {
 		u32 reg32 = read32(base + HDA_ICII_REG);
 		if (!(reg32 & HDA_ICII_BUSY))
 			return 0;
@@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
 	 * same duration */
 
 	int timeout = 50;
-	while(timeout--) {
+	while (timeout--) {
 		reg32 = read32(base + HDA_ICII_REG);
 		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
 			HDA_ICII_VALID)

src/southbridge/intel/i82801ix/lpc.c

@@ -110,7 +110,7 @@ static void i82801ix_pirq_init(device_t dev)
 	 * I am not so sure anymore he was right.
 	 */
 
-	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
 		u8 int_pin=0, int_line=0;
 
 		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

src/southbridge/intel/i82801ix/smihandler.c

@@ -518,7 +518,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
 		}
 	}
 
-	if(dump) {
+	if (dump) {
 		dump_smi_status(smi_sts);
 	}
 

src/southbridge/intel/i82870/ioapic.c

@@ -11,11 +11,10 @@ static int num_p64h2_ioapics = 0;
 
 static void p64h2_ioapic_enable(device_t dev)
 {
-    /* We have to enable MEM and Bus Master for IOAPIC */
+	/* We have to enable MEM and Bus Master for IOAPIC */
-    uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 
-
+	pci_write_config16(dev, PCI_COMMAND, command);
-    pci_write_config16(dev, PCI_COMMAND, command);
 }
 
 /**
@@ -29,70 +28,70 @@ static void p64h2_ioapic_enable(device_t dev)
  */
 static void p64h2_ioapic_init(device_t dev)
 {
-    uint32_t memoryBase;
+	uint32_t memoryBase;
-    int apic_index, apic_id;
+	int apic_index, apic_id;
 
-    volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
+	volatile uint32_t* pIndexRegister;    /* io apic io memory space command address */
-    volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
+	volatile uint32_t* pWindowRegister;    /* io apic io memory space data address */
 
-    apic_index = num_p64h2_ioapics;
+	apic_index = num_p64h2_ioapics;
-    num_p64h2_ioapics++;
+	num_p64h2_ioapics++;
 
-    // A note on IOAPIC addresses:
+	// A note on IOAPIC addresses:
-    //  0 and 1 are used for the local APICs of the dual virtual
+	//  0 and 1 are used for the local APICs of the dual virtual
-    //  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
+	//  (hyper-threaded) CPUs of physical CPU 0 (devicetree.cb).
-    //  6 and 7 are used for the local APICs of the dual virtual
+	//  6 and 7 are used for the local APICs of the dual virtual
-    //  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
+	//  (hyper-threaded) CPUs of physical CPU 1 (devicetree.cb).
-    //  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
+	//  2 is used for the IOAPIC in the 82801 southbridge (hard-coded in i82801xx_lpc.c)
 
-    // Map APIC index into APIC ID
+	// Map APIC index into APIC ID
-    // IDs 3, 4, 5, and 8+ are available (see above note)
+	// IDs 3, 4, 5, and 8+ are available (see above note)
 
-    if (apic_index < 3)
+	if (apic_index < 3)
-        apic_id = apic_index + 3;
+		apic_id = apic_index + 3;
-    else
+	else
-        apic_id = apic_index + 5;
+		apic_id = apic_index + 5;
 
-    ASSERT(apic_id < 16);       // ID is only 4 bits
+	ASSERT(apic_id < 16);       // ID is only 4 bits
 
-    // Read the MBAR address for setting up the IOAPIC in memory space
+	// Read the MBAR address for setting up the IOAPIC in memory space
-    // NOTE: this address was assigned during enumeration of the bus
+	// NOTE: this address was assigned during enumeration of the bus
 
-    memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+	memoryBase = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-    pIndexRegister  = (volatile uint32_t*) memoryBase;
+	pIndexRegister  = (volatile uint32_t*) memoryBase;
-    pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
+	pWindowRegister = (volatile uint32_t*)(memoryBase + 0x10);
 
-    printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
+	printk(BIOS_DEBUG, "IOAPIC %d at %02x:%02x.%01x  MBAR = %p DataAddr = %p\n",
-                 apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
+		apic_id, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn),
-                 PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
+		PCI_FUNC(dev->path.pci.devfn), pIndexRegister, pWindowRegister);
 
-    apic_id <<= 24;             // Convert ID to bitmask
+	apic_id <<= 24;             // Convert ID to bitmask
 
-    *pIndexRegister = 0;        // Select APIC ID register
+	*pIndexRegister = 0;        // Select APIC ID register
-    *pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
+	*pWindowRegister = (*pWindowRegister & ~(0xF<<24)) | apic_id;   // Set the ID
 
-    if ((*pWindowRegister & (0xF<<24)) != apic_id)
+	if ((*pWindowRegister & (0xF<<24)) != apic_id)
-        die("p64h2_ioapic_init failed");
+		die("p64h2_ioapic_init failed");
 
-    *pIndexRegister  = 3;   // Select Boot Configuration register
+	*pIndexRegister  = 3;   // Select Boot Configuration register
-    *pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
+	*pWindowRegister |= 1;  // Use Processor System Bus to deliver interrupts
 
-    if (!(*pWindowRegister & 1))
+	if (!(*pWindowRegister & 1))
-        die("p64h2_ioapic_init failed");
+		die("p64h2_ioapic_init failed");
 }
 
 static struct device_operations ioapic_ops = {
-        .read_resources   = pci_dev_read_resources,
+	.read_resources   = pci_dev_read_resources,
-        .set_resources    = pci_dev_set_resources,
+	.set_resources    = pci_dev_set_resources,
-        .enable_resources = pci_dev_enable_resources,
+	.enable_resources = pci_dev_enable_resources,
-        .init     = p64h2_ioapic_init,
+	.init     = p64h2_ioapic_init,
-        .scan_bus = 0,
+	.scan_bus = 0,
-        .enable   = p64h2_ioapic_enable,
+	.enable   = p64h2_ioapic_enable,
 };
 
 static const struct pci_driver ioapic_driver __pci_driver = {
-        .ops    = &ioapic_ops,
+	.ops    = &ioapic_ops,
-        .vendor = PCI_VENDOR_ID_INTEL,
+	.vendor = PCI_VENDOR_ID_INTEL,
-        .device = PCI_DEVICE_ID_INTEL_82870_1E0,
+	.device = PCI_DEVICE_ID_INTEL_82870_1E0,
 
 };