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src/southbridge: Code formating

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Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Elyes HAOUAS
2016-08-31 19:22:16 +02:00
committed by Martin Roth
parent 2e4d80687d
commit ba28e8d73b
130 changed files with 1484 additions and 1589 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/southbridge/amd/agesa/hudson/acpi/fch.asl
View File

@ -183,9 +183,9 @@ Method(_INI, 0) {
Method(OSFL, 0){
if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if(CondRefOf(\_OSI))
if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */

2
src/southbridge/amd/amd8111/acpi.c
View File

@ -152,7 +152,7 @@ static void acpi_init(struct device *dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
if (on) {
pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
inl(pm10_bar + 0x10);

12
src/southbridge/amd/amd8111/amd8111_smbus.h
View File

@ -26,11 +26,11 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if ((val & 0x800) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
if (loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
} while(--loops);
} while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
break;
}
} while(--loops);
} while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
@ -267,11 +267,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned
}
/* read data block */
for(i=0; i<msglen && i<bytes; i++) {
for (i=0; i<msglen && i<bytes; i++) {
buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
}
/* empty fifo */
while(bytes++<msglen) {
while (bytes++<msglen) {
inw(smbus_io_base + SMBHSTFIFO);
}
@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne
outw(bytes, smbus_io_base + SMBHSTDAT);
/* set the data block */
for(i=0; i<bytes; i++) {
for (i=0; i<bytes; i++) {
outw(buf[i], smbus_io_base + SMBHSTFIFO);
}

2
src/southbridge/amd/amd8111/reset.c
View File

@ -40,7 +40,7 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for(; dev <= last; dev += PCI_DEV(0,0,1)) {
for (; dev <= last; dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id) {

11
src/southbridge/amd/amd8131/bridge.c
View File

@ -19,8 +19,7 @@ static void amd8131_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
for(child = bus->children; child; child = child->sibling)
{
for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
@ -72,7 +71,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
sibs = info->master_devices - 1;
/* Count how many sibling functions this device has */
sib_funcs = 0;
for(sib = dev->bus->children; sib; sib = sib->sibling) {
for (sib = dev->bus->children; sib; sib = sib->sibling) {
if (sib == dev) {
continue;
}
@ -258,7 +257,7 @@ static void amd8131_scan_bus(struct bus *bus,
/* Don't allow the 8131 or any of it's parent busses to
* implement relaxed ordering. Errata #58
*/
for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
for (pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
bus_path(pbus));
pbus->disable_relaxed_ordering = 1;
@ -322,7 +321,7 @@ static void amd8131_pcix_init(device_t dev)
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if(nmi_option) {
if (nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
@ -330,7 +329,7 @@ static void amd8131_pcix_init(device_t dev)
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
if (dword) { /* do device A only */
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
pci_write_config32(dev, 0xc4, dword);

7
src/southbridge/amd/amd8132/bridge.c
View File

@ -32,8 +32,7 @@ static void amd8132_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
for(child = bus->children; child; child = child->sibling)
{
for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
@ -214,7 +213,7 @@ static void amd8132_pcix_init(device_t dev)
if (chip_rev == 0x01) {
/* Errata #37 */
byte = pci_read_config8(dev, 0x0c);
if(byte == 0x08 )
if (byte == 0x08 )
pci_write_config8(dev, 0x0c, 0x10);
#if 0
@ -280,7 +279,7 @@ static void amd8132_pcix_init(device_t dev)
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
if (dword) { /* do device A only */
#if 0
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);

2
src/southbridge/amd/cimx/sb700/Platform.h
View File

@ -62,7 +62,7 @@ void TraceCode ( UINT32 Level, UINT32 Code);
#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
#define TRACE(Arguments) printk Arguments
#else
#define TRACE(Arguments) do {} while(0)
#define TRACE(Arguments) do {} while (0)
#endif
#define TRACECODE(Arguments)
#endif

2
src/southbridge/amd/cimx/sb700/reset.c
View File

@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

2
src/southbridge/amd/cimx/sb800/reset.c
View File

@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

2
src/southbridge/amd/cimx/sb900/early.c
View File

@ -60,7 +60,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
if(!CONFIG_PCIB_ENABLE) {
if (!CONFIG_PCIB_ENABLE) {
data |= BIT0;
}
outb(data, 0xCD7);

2
src/southbridge/amd/cimx/sb900/reset.c
View File

@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

2
src/southbridge/amd/common/amd_pci_util.c
View File

@ -58,7 +58,7 @@ void write_pci_int_table (void)
{
u8 byte;
if(picr_data_ptr == NULL || intr_data_ptr == NULL){
if (picr_data_ptr == NULL || intr_data_ptr == NULL){
printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n"
"'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n");
return;

4
src/southbridge/amd/cs5535/chipsetinit.c
View File

@ -328,7 +328,7 @@ chipsetinit(void)
i = 0;
csi = &SB_MASTER_CONF_TABLE[i];
for(; csi->msrnum; csi++){
for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above
@ -347,7 +347,7 @@ chipsetinit(void)
{
csi = CS5535_CLOCK_GATING_TABLE;
for(; csi->msrnum; csi++){
for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above

4
src/southbridge/amd/cs5535/cs5535.c
View File

@ -56,9 +56,9 @@ static void dump_south(struct device *dev)
{
int i, j;
for(i=0; i<256; i+=16) {
for (i=0; i<256; i+=16) {
printk(BIOS_DEBUG, "0x%02x: ", i);
for(j=0; j<16; j++)
for (j=0; j<16; j++)
printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
printk(BIOS_DEBUG, "\n");
}

4
src/southbridge/amd/cs5535/early_setup.c
View File

@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void)
outl(0x1 << (CS5535_DEV_NUM + 10), 0);
}
static void cs5535_usb_swapsif(void)
static void cs5535_usb_swapsif (void)
{
msr_t msr;
@ -133,7 +133,7 @@ static void cs5535_early_setup(void)
printk(BIOS_DEBUG, "Setup idsel\n");
cs5535_setup_idsel();
printk(BIOS_DEBUG, "Setup iobase\n");
cs5535_usb_swapsif();
cs5535_usb_swapsif ();
cs5535_setup_iobase();
printk(BIOS_DEBUG, "Setup gpio\n");
cs5535_setup_gpio();

4
src/southbridge/amd/cs5536/early_setup.c
View File

@ -42,7 +42,7 @@ static void cs5536_setup_idsel(void)
outl(0x1 << (CS5536_DEV_NUM + 10), 0);
}
static void cs5536_usb_swapsif(void)
static void cs5536_usb_swapsif (void)
{
msr_t msr;
@ -260,7 +260,7 @@ static void cs5536_early_setup(void)
//printk(BIOS_DEBUG, "Setup idsel\n");
cs5536_setup_idsel();
//printk(BIOS_DEBUG, "Setup iobase\n");
cs5536_usb_swapsif();
cs5536_usb_swapsif ();
cs5536_setup_iobase();
//printk(BIOS_DEBUG, "Setup gpio\n");
cs5536_setup_gpio();

4
src/southbridge/amd/pi/hudson/acpi/fch.asl
View File

@ -165,9 +165,9 @@ Method(_INI, 0) {
Method(OSFL, 0){
if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if(CondRefOf(\_OSI))
if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */

8
src/southbridge/amd/rs690/ht.c
View File

@ -52,12 +52,12 @@ static void ht_dev_set_resources(device_t dev)
printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
// find a not assigned resource
for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
for ( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
base = pci_read_config32(k8_f1,reg);
limit = pci_read_config32(k8_f1,reg+4);
if( !(base & 3) ) break; // found a not assigned resource
if ( !(base & 3) ) break; // found a not assigned resource
}
if( !(base & 3) ) {
if ( !(base & 3) ) {
u32 sblk;
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
/* Remember this resource has been stored. */
@ -90,7 +90,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
// we report mmconf base
res = probe_resource(dev, 0x1C);
if( res )
if ( res )
mmconf_base = res->base;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?

4
src/southbridge/amd/rs780/early_setup.c
View File

@ -335,7 +335,7 @@ static void k8_optimization(void)
wrmsr(0xC001001F, msr);
}
#else
#define k8_optimization() do{}while(0)
#define k8_optimization() do {} while (0)
#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
@ -400,7 +400,7 @@ static void fam10_optimization(void)
}
}
#else
#define fam10_optimization() do{}while(0)
#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
/*****************************************

121
src/southbridge/amd/rs780/gfx.c
View File

@ -127,12 +127,10 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
{
int i;
MMIORANGE * TempRange;
for(i=0; i<8; i++)
{
if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) {
TempRange = AllocMMIO(pMMIO);
if(TempRange == 0) return 0x80000000;
if (TempRange == 0) return 0x80000000;
TempRange->Base = Limit;
TempRange->Limit = pMMIO[i].Limit;
TempRange->Attribute = pMMIO[i].Attribute;
@ -140,7 +138,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
}
}
TempRange = AllocMMIO(pMMIO);
if(TempRange == 0) return 0x80000000;
if (TempRange == 0) return 0x80000000;
TempRange->Base = Base;
TempRange->Limit = Limit;
TempRange->Attribute = Attribute;
@ -150,32 +148,25 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
static u8 FinalizeMMIO(MMIORANGE *pMMIO)
{
int i, j, n = 0;
for(i=0; i<8; i++)
{
if (pMMIO[i].Base == pMMIO[i].Limit)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Base == pMMIO[i].Limit) {
FreeMMIO(&pMMIO[i]);
continue;
}
for(j=0; j<i; j++)
{
if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
{
if (pMMIO[i].Base == pMMIO[j].Limit)
{
for (j=0; j<i; j++) {
if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) {
if (pMMIO[i].Base == pMMIO[j].Limit) {
pMMIO[j].Limit = pMMIO[i].Limit;
FreeMMIO(&pMMIO[i]);
}
if (pMMIO[i].Limit == pMMIO[j].Base)
{
if (pMMIO[i].Limit == pMMIO[j].Base) {
pMMIO[j].Base = pMMIO[i].Base;
FreeMMIO(&pMMIO[i]);
}
}
}
}
for (i=0; i<8; i++)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Limit != 0) n++;
}
return n;
@ -191,29 +182,23 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
Value = pci_read_config32(dev0x14, 0x18);
BusStart = (Value >> 8) & 0xFF;
BusEnd = (Value >> 16) & 0xFF;
for(Bus = BusStart; Bus <= BusEnd; Bus++)
{
for(Dev = 0; Dev <= 0x1f; Dev++)
{
for (Bus = BusStart; Bus <= BusEnd; Bus++) {
for (Dev = 0; Dev <= 0x1f; Dev++) {
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
if ((Value & 0xffff) == 0x1102) {//Creative
//Found Creative SB
u32 MMIOStart = 0xffffffff;
u32 MMIOLimit = 0;
for(Reg = 0x10; Reg < 0x20; Reg+=4)
{
for (Reg = 0x10; Reg < 0x20; Reg+=4) {
u32 BaseA, LimitA;
BaseA = pci_read_config32(tempdev, Reg);
Value = BaseA;
if(!(Value & 0x01))
{
if (!(Value & 0x01)) {
Value = Value & 0xffffff00;
if(Value != 0)
{
if(MMIOStart > Value)
if (Value != 0) {
if (MMIOStart > Value)
MMIOStart = Value;
LimitA = 0xffffffff;
//WritePCI(PciAddress,AccWidthUint32,&LimitA);
@ -232,16 +217,14 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
if(Status == CIM_ERROR) return Status;
if (Status == CIM_ERROR) return Status;
}
}
}
}
if(Status == CIM_SUCCESS)
{
if (Status == CIM_SUCCESS) {
//Lets optimize MMIO
if(FinalizeMMIO(pMMIO) > 4)
{
if (FinalizeMMIO(pMMIO) > 4) {
Status = CIM_ERROR;
}
}
@ -256,23 +239,18 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i = 0; i < 8; i++)
{
for (i = 0; i < 8; i++) {
int k = 0, MmioReg;
u32 Base = 0;
u32 Limit = 0;
for(j = 0; j < 8; j++)
{
if (Base < pMMIO[j].Base)
{
for (j = 0; j < 8; j++) {
if (Base < pMMIO[j].Base) {
Base = pMMIO[j].Base;
k = j;
}
}
if(pMMIO[k].Limit != 0)
{
if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
{
if (pMMIO[k].Limit != 0) {
if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
Base = 0;
}
else
@ -366,8 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Clear vgainfo. */
bpointer = (unsigned char *) &vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
{
for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
*bpointer = 0;
bpointer++;
}
@ -651,8 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
{
for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
#if CONFIG_GFXUMA
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
@ -686,14 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* clear MMIO and CreativeMMIO. */
bpointer = (unsigned char *)MMIO;
for(i=0; i<sizeof(MMIO); i++)
{
for (i=0; i<sizeof(MMIO); i++) {
*bpointer = 0;
bpointer++;
}
bpointer = (unsigned char *)CreativeMMIO;
for(i=0; i<sizeof(CreativeMMIO); i++)
{
for (i=0; i<sizeof(CreativeMMIO); i++) {
*bpointer = 0;
bpointer++;
}
@ -708,20 +682,18 @@ static void internal_gfx_pci_dev_init(struct device *dev)
temp = pci_read_config32(dev0x14, 0x20);
Base32 = (temp & 0x0fff0) << 8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
if(Base32 < Limit32)
{
if (Base32 < Limit32) {
Status = GetCreativeMMIO(&CreativeMMIO[0]);
if(Status != CIM_ERROR)
if (Status != CIM_ERROR)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
/* Set MMIO for prefetchable P2P. */
if(Status != CIM_ERROR)
{
if (Status != CIM_ERROR) {
temp = pci_read_config32(dev0x14, 0x24);
Base32 = (temp & 0x0fff0) <<8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
if(Base32 < Limit32)
if (Base32 < Limit32)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
@ -835,8 +807,7 @@ static void rs780_internal_gfx_enable(device_t dev)
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
for (i = 0; i < 12; i++)
{
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
nbmc_write_index(nb_dev, 0x30 + i, l_dword);
}
@ -848,10 +819,8 @@ static void rs780_internal_gfx_enable(device_t dev)
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
l_dword = pci_read_config32(k8_f2, 0x90);
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
if (is_family10h())
{
for (i = 0; i < 12; i++)
{
if (is_family10h()) {
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
nbmc_write_index(nb_dev, 0x3d + i, l_dword);
}
@ -974,13 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev)
/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
/* Init PM timing. */
for(i=0; i<4; i++)
{
for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa0+i);
nbmc_write_index(nb_dev, 0xc8+i, l_dword);
}
for(i=0; i<4; i++)
{
for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa8+i);
nbmc_write_index(nb_dev, 0xcc+i, l_dword);
}
@ -1538,7 +1505,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
if((dev->path.pci.devfn >> 3) == 2) {
if ((dev->path.pci.devfn >> 3) == 2) {
single_port_configuration(nb_dev, dev);
} else {
set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
@ -1565,7 +1532,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
break;
case 2:
if(is_dev3_present()){
if (is_dev3_present()) {
/* step 1, lane reversal (only need if CMOS option is enabled) */
if (cfg->gfx_lane_reversal) {
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
@ -1583,7 +1550,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
dual_port_configuration(nb_dev, dev);
}else{
} else {
if (cfg->gfx_lane_reversal) {
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
@ -1591,9 +1558,9 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
}
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
if((dev->path.pci.devfn >> 3) == 2)
if ((dev->path.pci.devfn >> 3) == 2)
single_port_configuration(nb_dev, dev);
else{
else {
set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
}

2
src/southbridge/amd/sb600/early_setup.c
View File

@ -137,7 +137,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x8b, 0x01);
pmio_write(0x8a, 0x90);
if(get_sb600_revision() > 0x13)
if (get_sb600_revision() > 0x13)
pmio_write(0x88, 0x10);
else
pmio_write(0x88, 0x06);

4
src/southbridge/amd/sb600/hda.c
View File

@ -175,7 +175,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@ -196,7 +196,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/amd/sb600/sata.c
View File

@ -182,7 +182,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
if( byte == 0x1 ) {
if ( byte == 0x1 ) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");

10
src/southbridge/amd/sb700/Kconfig
View File

@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select SMBUS_HAS_AUX_CHANNELS
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
bool "Enable high speed SPI clock"
default n
help
When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz. Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.
# Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool

34
src/southbridge/amd/sb700/bootblock.c
View File

@ -20,10 +20,6 @@
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
#define SPI_BASE_ADDRESS 0xa0
#define SPI_CONTROL_1 0xc
#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@ -96,37 +92,7 @@ static void sb700_enable_rom(void)
pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
}
static void sb700_configure_rom(void)
{
pci_devfn_t dev;
uint32_t dword;
dev = PCI_DEV(0, 0x14, 3);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
uint32_t prev_spi_cfg;
volatile uint32_t *spi_mmio;
/* Temporarily set up SPI access to change SPI speed */
prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */
dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
dword |= (0x1 << 1); /* SpiRomEnable = 1 */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
dword = *spi_mmio;
dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */
dword |= (0x1 << 12);
*spi_mmio = dword;
/* Restore previous SPI access */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
}
}
static void bootblock_southbridge_init(void)
{
sb700_enable_rom();
sb700_configure_rom();
}

4
src/southbridge/amd/sb700/hda.c
View File

@ -97,7 +97,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@ -118,7 +118,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/amd/sb700/reset.c
View File

@ -36,7 +36,7 @@ static void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

4
src/southbridge/amd/sb800/hda.c
View File

@ -99,7 +99,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@ -120,7 +120,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/amd/sb800/sata.c
View File

@ -177,7 +177,7 @@ static void sata_init(struct device *dev)
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
if( byte == 0x1 ) {
if ( byte == 0x1 ) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");

2
src/southbridge/amd/sr5650/early_setup.c
View File

@ -327,7 +327,7 @@ void fam10_optimization(void)
/* rpr Table 5-11, 5-12 */
}
#else
#define fam10_optimization() do{}while(0)
#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
/*****************************************

2
src/southbridge/broadcom/bcm5785/bcm5785.c
View File

@ -46,7 +46,7 @@ void bcm5785_enable(device_t dev)
else { // same bus
unsigned devfn;
devfn = (dev->path.pci.devfn) & ~7;
if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
if ( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) {
if (dev->device == 0x0036) //PCI-X Bridge
{ devfn += (1<<3); }
else if (dev->device == 0x0223) // USB

6
src/southbridge/broadcom/bcm5785/lpc.c
View File

@ -76,11 +76,11 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
for (link = dev->link_list; link; link = link->next) {
device_t child;
for (child = link->children; child; child = child->sibling) {
if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for(res = child->resource_list; res; res = res->next) {
for (res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long
if(!(res->flags & IORESOURCE_IO)) continue;
if (!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "bcm5785lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);

6
src/southbridge/broadcom/bcm5785/sata.c
View File

@ -32,7 +32,7 @@ static void sata_init(struct device *dev)
u8 *mmio_base;
int i;
if(!(dev->path.pci.devfn & 7)) { // only set it in Func0
if (!(dev->path.pci.devfn & 7)) { // only set it in Func0
byte = pci_read_config8(dev, 0x78);
byte |= (1<<7);
pci_write_config8(dev, 0x78, byte);
@ -53,11 +53,11 @@ static void sata_init(struct device *dev)
//init PHY
printk(BIOS_DEBUG, "init PHY...\n");
for(i=0; i<4; i++) {
for (i=0; i<4; i++) {
mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i);
byte = read8(mmio + 0x40);
printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte);
if(byte & 0x4) {// bit 2 is set
if (byte & 0x4) {// bit 2 is set
byte = read8(mmio+0x48);
write8(mmio + 0x48, byte | 1);
write8(mmio + 0x48, byte & (~1));

2
src/southbridge/broadcom/bcm5785/sb_pci_main.c
View File

@ -45,7 +45,7 @@ static void sb_init(device_t dev)
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW
}
if( byte != byte_old) {
if ( byte != byte_old) {
outb(byte, 0x70);
}

4
src/southbridge/broadcom/bcm5785/smbus.h
View File

@ -53,7 +53,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
return 0;
}
outb(val, smbus_io_base + SMBHSTSTAT);
} while(--loops);
} while (--loops);
return -2; // time out
}
@ -73,7 +73,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
outb(val, smbus_io_base + SMBHSTSTAT); // clear status
return 0; //
}
} while(--loops);
} while (--loops);
return -3; // timeout
}

4
src/southbridge/intel/bd82x6x/azalia.c
View File

@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
int timeout = 1000;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -145,7 +145,7 @@ static int wait_for_valid(u8 *base)
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -125,7 +125,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

8
src/southbridge/intel/bd82x6x/me_8.x.c
View File

@ -703,7 +703,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
if(intel_me_read_mbp(&mbp_data))
if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
@ -893,7 +893,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
default:
printk(BIOS_ERR, "ME: unknown mbp item id 0x%x! Skipping\n",
mbp_item_id);
while(copy_size--)
while (copy_size--)
read_cb();
continue;
}
@ -904,7 +904,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
while(copy_size--)
while (copy_size--)
*copy_addr++ = read_cb();
}
@ -914,7 +914,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
while(host.interrupt_generate) {
while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}

2
src/southbridge/intel/bd82x6x/smihandler.c
View File

@ -863,7 +863,7 @@ void southbridge_smi_handler(void)
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

4
src/southbridge/intel/fsp_bd82x6x/azalia.c
View File

@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/fsp_bd82x6x/lpc.c
View File

@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

9
src/southbridge/intel/fsp_bd82x6x/me_8.x.c
View File

@ -385,8 +385,7 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap)
};
/* Send request and wait for response */
if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg))
< 0) {
if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
}
@ -702,7 +701,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
if(intel_me_read_mbp(&mbp_data))
if (intel_me_read_mbp(&mbp_data))
break;
#if CONFIG_CHROMEOS && 0 /* DISABLED */
@ -901,7 +900,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
while(copy_size--)
while (copy_size--)
*copy_addr++ = read_cb();
}
@ -911,7 +910,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
while(host.interrupt_generate) {
while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}

2
src/southbridge/intel/fsp_bd82x6x/smihandler.c
View File

@ -749,7 +749,7 @@ void southbridge_smi_handler(void)
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

2
src/southbridge/intel/fsp_i89xx/lpc.c
View File

@ -132,7 +132,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

6
src/southbridge/intel/fsp_i89xx/me_8.x.c
View File

@ -670,7 +670,7 @@ static void intel_me_init(device_t dev)
if (intel_mei_setup(dev) < 0)
break;
if(intel_me_read_mbp(&mbp_data))
if (intel_me_read_mbp(&mbp_data))
break;
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
@ -855,7 +855,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
buffer_room, copy_size, mbp_item_id);
return -1;
}
while(copy_size--)
while (copy_size--)
*copy_addr++ = read_cb();
}
@ -865,7 +865,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data)
{
int cntr = 0;
while(host.interrupt_generate) {
while (host.interrupt_generate) {
read_host_csr(&host);
cntr++;
}

2
src/southbridge/intel/fsp_i89xx/romstage.c
View File

@ -203,7 +203,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
cbmem_was_initted = !cbmem_recovery(0);
if(cbmem_was_initted) {
if (cbmem_was_initted) {
reset_system();
}

2
src/southbridge/intel/fsp_i89xx/smihandler.c
View File

@ -746,7 +746,7 @@ void southbridge_smi_handler(void)
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

4
src/southbridge/intel/fsp_rangeley/gpio.c
View File

@ -64,7 +64,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* CFIO Core Well Set 1 */
if ((gpio->core.cfio_init != NULL) || (gpio->core.cfio_entrynum != 0)) {
write32(cfiobase + (0x0700 / sizeof(u32)), (u32)0x01001002);
for(cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
for (cfio_cnt = 0; cfio_cnt < gpio->core.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0))
continue;
write32(cfiobase + ((CFIO_PAD_CONF0 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->core.cfio_init[cfio_cnt].pad_conf_0);
@ -78,7 +78,7 @@ void setup_soc_gpios(const struct soc_gpio_map *gpio)
/* CFIO SUS Well Set 1 */
if ((gpio->sus.cfio_init != NULL) || (gpio->sus.cfio_entrynum != 0)) {
write32(cfiobase + (0x1700 / sizeof(u32)), (u32)0x01001002);
for(cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
for (cfio_cnt = 0; cfio_cnt < gpio->sus.cfio_entrynum; cfio_cnt++) {
if (!((u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0))
continue;
write32(cfiobase + ((CFIO_PAD_CONF0 + 0x1000 + (16*cfio_cnt))/sizeof(u32)), (u32)gpio->sus.cfio_init[cfio_cnt].pad_conf_0);

4
src/southbridge/intel/fsp_rangeley/lpc.c
View File

@ -137,7 +137,7 @@ static void write_pci_config_irqs(void)
* the Interrupt Route registers in the ILB
*/
printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n");
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
(!irq_dev->enabled))
@ -225,7 +225,7 @@ static void soc_pirq_init(device_t dev)
write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
if (ir->pcidev[i]) {
printk(BIOS_SPEW, " %d: ", i);
for (j = 0; j < 4; j++) {
pirq = (ir->pcidev[i] >> (j * 4)) & 0xF;

2
src/southbridge/intel/i3100/sata.c
View File

@ -42,7 +42,7 @@ static void sata_init(struct device *dev)
/* Enable SATA devices */
printk(BIOS_INFO, "SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
if(ahci) {
if (ahci) {
/* AHCI mode */
pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));

2
src/southbridge/intel/i82371eb/acpi_tables.c
View File

@ -28,7 +28,7 @@ static int determine_total_number_of_cores(void)
{
device_t cpu;
int count = 0;
for(cpu = all_devices; cpu; cpu = cpu->next) {
for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
(cpu->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) {
continue;

6
src/southbridge/intel/i82371eb/smbus.h
View File

@ -35,12 +35,12 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
break;
}
#if 0
if(loops == (SMBUS_TIMEOUT / 2)) {
if (loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBHST_STATUS),
smbus_io_base + SMBHST_STATUS);
}
#endif
} while(--loops);
} while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
@ -62,7 +62,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (val & 0xfe) {
break;
}
} while(--loops);
} while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}

2
src/southbridge/intel/i82801dx/smihandler.c
View File

@ -636,7 +636,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

6
src/southbridge/intel/i82801ex/early_smbus.c
View File

@ -81,7 +81,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
/* setup transaction */
/* Obtain ownership */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
for(stat=0;(stat&0x40)==0;) {
for (stat=0;(stat&0x40)==0;) {
stat = inb(SMBUS_IO_BASE + SMBHSTSTAT);
}
/* clear the done bit */
@ -105,7 +105,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x5 << 2) | 0x40,
SMBUS_IO_BASE + SMBHSTCTL);
for(i=0;i<length;i++) {
for (i=0;i<length;i++) {
/* poll for transaction completion */
if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) {
@ -113,7 +113,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
}
/* load the next byte */
if(i>3)
if (i>3)
byte=(data2>>(i%4))&0x0ff;
else
byte=(data1>>(i))&0x0ff;

12
src/southbridge/intel/i82801ex/lpc.c
View File

@ -92,7 +92,7 @@ static void set_i82801ex_gpio_use_sel(
gpio_use_sel = 0x1A003180;
gpio_use_sel2 = 0x00000007;
for(i = 0; i < 64; i++) {
for (i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_USE_MASK) {
case ICH5R_GPIO_USE_AS_NATIVE: val = 0; break;
@ -121,7 +121,7 @@ static void set_i82801ex_gpio_direction(
gpio_io_sel = 0x0000ffff;
gpio_io_sel2 = 0x00000300;
for(i = 0; i < 64; i++) {
for (i = 0; i < 64; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_SEL_MASK) {
case ICH5R_GPIO_SEL_OUTPUT: val = 0; break;
@ -152,7 +152,7 @@ static void set_i82801ex_gpio_level(
gpio_lvl = 0x1b3f0000;
gpio_blink = 0x00040000;
gpio_lvl2 = 0x00030207;
for(i = 0; i < 64; i++) {
for (i = 0; i < 64; i++) {
int val, blink;
switch(config->gpio[i] & ICH5R_GPIO_LVL_MASK) {
case ICH5R_GPIO_LVL_LOW: val = 0; blink = 0; break;
@ -184,7 +184,7 @@ static void set_i82801ex_gpio_inv(
int i;
gpio_inv = 0x00000000;
for(i = 0; i < 32; i++) {
for (i = 0; i < 32; i++) {
int val;
switch(config->gpio[i] & ICH5R_GPIO_INV_MASK) {
case ICH5R_GPIO_INV_OFF: val = 0; break;
@ -205,10 +205,10 @@ static void i82801ex_pirq_init(device_t dev)
/* Get the chip configuration */
config = dev->chip_info;
if(config->pirq_a_d) {
if (config->pirq_a_d) {
pci_write_config32(dev, 0x60, config->pirq_a_d);
}
if(config->pirq_e_h) {
if (config->pirq_e_h) {
pci_write_config32(dev, 0x68, config->pirq_e_h);
}
}

6
src/southbridge/intel/i82801ex/smbus.h
View File

@ -29,7 +29,7 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
} while(byte & 1);
} while (byte & 1);
return loops?0:-1;
}
@ -42,7 +42,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
} while((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
} while ((byte & 1) || (byte & ~((1<<6)|(1<<0))) == 0);
return loops?0:-1;
}
@ -55,7 +55,7 @@ static inline int smbus_wait_until_blk_done(unsigned smbus_io_base)
if (--loops == 0)
break;
byte = inb(smbus_io_base + SMBHSTSTAT);
} while((byte&(1<<7)) == 0);
} while ((byte&(1<<7)) == 0);
return loops?0:-1;
}

4
src/southbridge/intel/i82801gx/azalia.c
View File

@ -117,7 +117,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -146,7 +146,7 @@ static int wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/i82801gx/lpc.c
View File

@ -108,7 +108,7 @@ static void i82801gx_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

8
src/southbridge/intel/i82801gx/smbus.c
View File

@ -123,7 +123,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
while(!(inb(smbus_base + SMBHSTSTAT) & 1));
while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@ -136,7 +136,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb(*buf++, smbus_base + SMBBLKDAT);
outb(status, smbus_base + SMBHSTSTAT);
}
} while(status & 0x01);
} while (status & 0x01);
return 0;
}
@ -180,7 +180,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
while(!(inb(smbus_base + SMBHSTSTAT) & 1));
while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@ -200,7 +200,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
smbus_base + SMBHSTCTL);
}
}
} while(status & 0x01);
} while (status & 0x01);
return bytes_read;
}

2
src/southbridge/intel/i82801gx/smihandler.c
View File

@ -673,7 +673,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

4
src/southbridge/intel/i82801ix/hdaudio.c
View File

@ -118,7 +118,7 @@ static int wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -147,7 +147,7 @@ static int wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/i82801ix/lpc.c
View File

@ -110,7 +110,7 @@ static void i82801ix_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

2
src/southbridge/intel/i82801ix/smihandler.c
View File

@ -518,7 +518,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

1
src/southbridge/intel/i82870/ioapic.c
View File

@ -14,7 +14,6 @@ static void p64h2_ioapic_enable(device_t dev)
/* We have to enable MEM and Bus Master for IOAPIC */
uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, command);
}

4
src/southbridge/intel/ibexpeak/azalia.c
View File

@ -115,7 +115,7 @@ static int wait_for_ready(u8 *base)
int timeout = 1000;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -143,7 +143,7 @@ static int wait_for_valid(u8 *base)
/* Use a 1msec timeout */
int timeout = 1000;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -120,7 +120,7 @@ static void pch_pirq_init(device_t dev)
pci_write_config8(dev, PIRQG_ROUT, pirq_routing);
pci_write_config8(dev, PIRQH_ROUT, pirq_routing);
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

8
src/southbridge/intel/ibexpeak/smbus.h
View File

@ -171,7 +171,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
while(!(inb(smbus_base + SMBHSTSTAT) & 1));
while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@ -184,7 +184,7 @@ static int do_smbus_block_write(unsigned smbus_base, unsigned device,
outb(*buf++, smbus_base + SMBBLKDAT);
outb(status, smbus_base + SMBHSTSTAT);
}
} while(status & 0x01);
} while (status & 0x01);
return 0;
}
@ -214,7 +214,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
outb((inb(smbus_base + SMBHSTCTL) | 0x40),
smbus_base + SMBHSTCTL);
while(!(inb(smbus_base + SMBHSTSTAT) & 1));
while (!(inb(smbus_base + SMBHSTSTAT) & 1));
/* Poll for transaction completion */
do {
status = inb(smbus_base + SMBHSTSTAT);
@ -234,7 +234,7 @@ static int do_smbus_block_read(unsigned smbus_base, unsigned device,
smbus_base + SMBHSTCTL);
}
}
} while(status & 0x01);
} while (status & 0x01);
return bytes_read;
}

2
src/southbridge/intel/ibexpeak/smihandler.c
View File

@ -849,7 +849,7 @@ void southbridge_smi_handler(void)
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}

4
src/southbridge/intel/lynxpoint/hda_verb.c
View File

@ -94,7 +94,7 @@ static int hda_wait_for_ready(u8 *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 reg32 = read32(base + HDA_ICII_REG);
if (!(reg32 & HDA_ICII_BUSY))
return 0;
@ -122,7 +122,7 @@ static int hda_wait_for_valid(u8 *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
reg32 = read32(base + HDA_ICII_REG);
if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -124,7 +124,7 @@ static void pch_pirq_init(device_t dev)
* I am not so sure anymore he was right.
*/
for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
u8 int_pin=0, int_line=0;
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)

2
src/southbridge/intel/lynxpoint/smihandler.c
View File

@ -459,7 +459,7 @@ static void southbridge_smi_monitor(void)
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
trap_cycle & 0xfffc);
for (i=0; i < 4; i++)
if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
printk(BIOS_DEBUG, " read/write: %s\n",

2
src/southbridge/nvidia/mcp55/early_setup_car.c
View File

@ -381,7 +381,7 @@ static int mcp55_early_setup_x(void)
device_t dev;
dev = PCI_DEV(busnx, devnx, 0);
id = pci_read_config32(dev, PCI_VENDOR_ID);
if(id == 0x036910de) {
if (id == 0x036910de) {
busn[mcp55_num] = busnx;
devn[mcp55_num] = devnx;

16
src/southbridge/nvidia/mcp55/nic.c
View File

@ -127,26 +127,26 @@ static void nic_init(struct device *dev)
struct device *dev_eeprom;
dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr);
if(dev_eeprom) {
if (dev_eeprom) {
// if that is valid we will use that
unsigned char dat[6];
int status;
int i;
for(i=0;i<6;i++) {
for (i=0;i<6;i++) {
status = smbus_read_byte(dev_eeprom, i);
if(status < 0) break;
if (status < 0) break;
dat[i] = status & 0xff;
}
if(status >= 0) {
if (status >= 0) {
mac_l = 0;
for(i=3;i>=0;i--) {
for (i=3;i>=0;i--) {
mac_l <<= 8;
mac_l += dat[i];
}
if(mac_l != 0xffffffff) {
if (mac_l != 0xffffffff) {
mac_l += nic_index;
mac_h = 0;
for(i=5;i>=4;i--) {
for (i=5;i>=4;i--) {
mac_h <<= 8;
mac_h += dat[i];
}
@ -156,7 +156,7 @@ static void nic_init(struct device *dev)
}
}
// if that is invalid we will read that from romstrap
if(!eeprom_valid) {
if (!eeprom_valid) {
u32 *mac_pos;
mac_pos = (u32 *)0xffffffd0; // refer to romstrap.inc and romstrap.ld
mac_l = read32(mac_pos) + nic_index; // overflow?

2
src/southbridge/nvidia/mcp55/sata.c
View File

@ -35,7 +35,7 @@ static void sata_init(struct device *dev)
dword = pci_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
if(conf) {
if (conf) {
if (conf->sata1_enable) {
/* Enable secondary SATA interface */
dword |= (1<<0);

2
src/southbridge/nvidia/mcp55/smbus.h
View File

@ -48,7 +48,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if ( (val & 0xff) != 0) {
return 0;
}
} while(--loops);
} while (--loops);
return -3;
}
static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device)

6
src/southbridge/ricoh/rl5c476/rl5c476.c
View File

@ -166,7 +166,7 @@ static void rl5c476_read_resources(device_t dev)
/* For CF socket we need an extra memory window for
* the control structure of the CF itself
*/
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
/* fake index as it isn't in PCI config space */
resource = new_resource(dev, 1);
resource->flags |= IORESOURCE_MEM;
@ -181,9 +181,9 @@ static void rl5c476_set_resources(device_t dev)
{
struct resource *resource;
printk(BIOS_DEBUG, "%s In set resources\n",dev_path(dev));
if( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
if ( enable_cf_boot && (PCI_FUNC(dev->path.pci.devfn) == 1)){
resource = find_resource(dev,1);
if( !(resource->flags & IORESOURCE_STORED) ){
if ( !(resource->flags & IORESOURCE_STORED) ){
resource->flags |= IORESOURCE_STORED ;
printk(BIOS_DEBUG, "%s 1 ==> %llx\n", dev_path(dev), resource->base);
cf_base = resource->base;

16
src/southbridge/sis/sis966/aza.c
View File

@ -56,7 +56,7 @@ static int set_bits(void *port, u32 mask, u32 val)
udelay(100);
} while ((dword != val) && --count);
if(!count) return -1;
if (!count) return -1;
udelay(500);
return 0;
@ -98,9 +98,9 @@ static int codec_detect(u8 *base)
set_bits(base + 0x08, 1, 1);
do{
do {
dword = read32(base + 0x08)&0x1;
if(idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
if (idx++>1000) { printk(BIOS_DEBUG, "controller reset fail !!!\n"); break;}
} while (dword !=1);
dword=send_verb(base,0x000F0000); // get codec VendorId and DeviceId
@ -215,14 +215,14 @@ static void codec_init(u8 *base, int addr)
printk(BIOS_DEBUG, "codec viddid: %08x\n", dword);
verb_size = find_verb(dword, &verb);
if(!verb_size) {
if (!verb_size) {
printk(BIOS_DEBUG, "No verb!\n");
return;
}
printk(BIOS_DEBUG, "verb_size: %d\n", verb_size);
/* 3 */
for(i=0; i<verb_size; i++) {
for (i=0; i<verb_size; i++) {
send_verb(base,verb[i]);
}
printk(BIOS_DEBUG, "verb loaded!\n");
@ -246,7 +246,7 @@ static void aza_init(struct device *dev)
{
u8 temp8;
int i=0;
while(SiS_SiS7502_init[i][0] != 0)
while (SiS_SiS7502_init[i][0] != 0)
{
temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]);
temp8 &= SiS_SiS7502_init[i][1];
@ -279,7 +279,7 @@ static void aza_init(struct device *dev)
#endif
res = find_resource(dev, 0x10);
if(!res)
if (!res)
return;
base = res2mmio(res, 0, 0);
@ -287,7 +287,7 @@ static void aza_init(struct device *dev)
codec_mask = codec_detect(base);
if(codec_mask) {
if (codec_mask) {
printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask);
codecs_init(base, codec_mask);
}

2
src/southbridge/sis/sis966/early_setup_car.c
View File

@ -29,7 +29,7 @@ void sis966_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io
dword |= 0x3f0; // disable it at first
pci_write_config32(dev, 0xe4, dword);
for(i=0; i<3; i++) {
for (i=0; i<3; i++) {
tgio_ctrl = inl(anactrl_io_base + 0xcc);
tgio_ctrl &= ~(3<<9);
tgio_ctrl |= (i<<9);

65
src/southbridge/sis/sis966/early_smbus.c
View File

@ -37,7 +37,7 @@ int smbus_wait_until_ready(unsigned smbus_io_base)
return 0;
}
outb(val,smbus_io_base + SMBHSTSTAT);
} while(--loops);
} while (--loops);
return -2;
}
@ -53,7 +53,7 @@ int smbus_wait_until_done(unsigned smbus_io_base)
if ( (val & 0xff) != 0x02) {
return 0;
}
} while(--loops);
} while (--loops);
return -3;
}
@ -135,11 +135,10 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un
smbus_delay();
int i, j;
for(i = 0;i < 0x1000; i++)
{
if (inb(smbus_io_base + 0x00) != 0x08)
{ smbus_delay();
for(j=0;j<0xFFFF;j++);
for (i = 0;i < 0x1000; i++) {
if (inb(smbus_io_base + 0x00) != 0x08) {
smbus_delay();
for (j=0;j<0xFFFF;j++);
}
}
@ -502,12 +501,13 @@ static const uint8_t SiS_SiS1183_init[44][3]={
};
/* In => Share Memory size
=> 00h : 0MBytes
=> 02h : 32MBytes
=> 03h : 64MBytes
=> 04h : 128MBytes
=> Others: Reserved
*/
* => 00h : 0MBytes
* => 02h : 32MBytes
* => 03h : 64MBytes
* => 03h : 64MBytes
* => 04h : 128MBytes
* => Others: Reserved
*/
static void Init_Share_Memory(uint8_t ShareSize)
{
device_t dev;
@ -517,13 +517,13 @@ static void Init_Share_Memory(uint8_t ShareSize)
}
/* In: => Aperture size
=> 00h : 32MBytes
=> 01h : 64MBytes
=> 02h : 128MBytes
=> 03h : 256MBytes
=> 04h : 512MBytes
=> Others: Reserved
*/
* => 00h : 32MBytes
* => 01h : 64MBytes
* => 02h : 128MBytes
* => 03h : 256MBytes
* => 04h : 512MBytes
* => Others: Reserved
*/
static void Init_Aper_Size(uint8_t AperSize)
{
device_t dev;
@ -547,8 +547,8 @@ static void sis_init_stage1(void)
// ========================== NB =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
i=0;
while(SiS_NB_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
while (SiS_NB_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
temp8 &= SiS_NB_init[i][1];
temp8 |= SiS_NB_init[i][2];
pci_write_config8(dev, SiS_NB_init[i][0], temp8);
@ -558,8 +558,8 @@ static void sis_init_stage1(void)
// ========================== LPC =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
i=0;
while(SiS_LPC_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
while (SiS_LPC_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
temp8 &= SiS_LPC_init[i][1];
temp8 |= SiS_LPC_init[i][2];
pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
@ -567,8 +567,8 @@ static void sis_init_stage1(void)
};
// ========================== ACPI =============================
i=0;
while(SiS_ACPI_init[i][0] != 0)
{ temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
while (SiS_ACPI_init[i][0] != 0) {
temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
temp8 &= SiS_ACPI_init[i][1];
temp8 |= SiS_ACPI_init[i][2];
outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
@ -582,8 +582,8 @@ static void sis_init_stage1(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
i=0;
while(SiS_NBPCIE_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
while (SiS_NBPCIE_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
temp8 &= SiS_NBPCIE_init[i][1];
temp8 |= SiS_NBPCIE_init[i][2];
pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
@ -614,8 +614,7 @@ static void sis_init_stage2(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
i=0;
while(SiS_NBAGP_init[i][0] != 0)
{
while (SiS_NBAGP_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
temp8 &= SiS_NBAGP_init[i][1];
temp8 |= SiS_NBAGP_init[i][2];
@ -662,13 +661,13 @@ static void sis_init_stage2(void)
// ========================== ACPI =============================
i=0;
printk(BIOS_DEBUG, "Init ACPI -------->\n");
do
{ temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
do {
temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
temp8 &= SiS_ACPI_2_init[i][1];
temp8 |= SiS_ACPI_2_init[i][2];
outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);
i++;
}while(SiS_ACPI_2_init[i][0] != 0);
} while (SiS_ACPI_2_init[i][0] != 0);
// ========================== Misc =============================
printk(BIOS_DEBUG, "Init Misc -------->\n");

5
src/southbridge/sis/sis966/ide.c
View File

@ -103,8 +103,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
{
uint8_t temp8;
int i=0;
while(SiS_SiS5513_init[i][0] != 0)
{
while (SiS_SiS5513_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
temp8 &= SiS_SiS5513_init[i][1];
temp8 |= SiS_SiS5513_init[i][2];
@ -148,7 +147,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
printk(BIOS_DEBUG, "****** IDE PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for (i=0;i<0xff;i+=4){
for (i=0;i<0xff;i+=4) {
if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));

14
src/southbridge/sis/sis966/lpc.c
View File

@ -112,7 +112,7 @@ static void lpc_init(device_t dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
if (on) {
uint16_t pm10_bar;
uint32_t dword;
pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
@ -195,11 +195,11 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
for (link = dev->link_list; link; link = link->next) {
device_t child;
for (child = link->children; child; child = child->sibling) {
if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
struct resource *res;
for(res = child->resource_list; res; res = res->next) {
for (res = child->resource_list; res; res = res->next) {
unsigned long base, end; // don't need long long
if(!(res->flags & IORESOURCE_IO)) continue;
if (!(res->flags & IORESOURCE_IO)) continue;
base = res->base;
end = resource_end(res);
printk(BIOS_DEBUG, "sis966 lpc decode:%s, base=0x%08lx, end=0x%08lx\n",dev_path(child),base, end);
@ -217,8 +217,8 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
case 0x300: // Midi 0
reg |= (1<<12); break;
}
if( (base == 0x290) || (base >= 0x400)) {
if(var_num>=4) continue; // only 4 var ; compact them ?
if ( (base == 0x290) || (base >= 0x400)) {
if (var_num>=4) continue; // only 4 var ; compact them ?
reg |= (1<<(28+var_num));
reg_var[var_num++] = (base & 0xffff)|((end & 0xffff)<<16);
}
@ -227,7 +227,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
}
}
pci_write_config32(dev, 0xa0, reg);
for(i=0;i<var_num;i++) {
for (i=0;i<var_num;i++) {
pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
}

50
src/southbridge/sis/sis966/nic.c
View File

@ -73,8 +73,7 @@ static void readApcMacAddr(void)
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
printk(BIOS_DEBUG, "MAC addr in APC = ");
for (i = 0x9 ; i <=0xe ; i++)
{
for (i = 0x9 ; i <=0xe ; i++) {
printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
}
printk(BIOS_DEBUG, "\n");
@ -98,8 +97,7 @@ static void set_apc(struct device *dev)
outl(0x80001048,0xcf8);
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
for (i = 0 ; i <3; i++)
{
for (i = 0 ; i <3; i++) {
addr=0x9+2*i;
writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
@ -135,15 +133,13 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
u32 i;
u32 ulValue;
ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
write32(base + 0x3c, ulValue);
mdelay(10);
for (i=0 ; i <= LoopNum; i++)
{
for (i=0 ; i <= LoopNum; i++) {
ulValue=read32(base + 0x3c);
if (!(ulValue & 0x0080)) //BIT_7
@ -155,7 +151,7 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
mdelay(50);
if (i==LoopNum) data=0x10000;
else{
else {
ulValue=read32(base + 0x3c);
data = ((ulValue & 0xffff0000) >> 16);
}
@ -169,8 +165,6 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
u32 Read_Cmd;
u16 usData;
Read_Cmd = ((phy_reg << 11) |
(phy_addr << 6) |
SMI_READ |
@ -180,19 +174,15 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
write32(base + 0x44, Read_Cmd);
// Polling SMI_REQ bit to be deasserted indicated read command completed
do
{
do {
// Wait 20 usec before checking status
mdelay(20);
ulValue = read32(base + 0x44);
} while((ulValue & SMI_REQUEST) != 0);
} while ((ulValue & SMI_REQUEST) != 0);
//printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
usData=(ulValue>>16);
return usData;
}
// Detect a valid PHY
@ -205,22 +195,18 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
// Scan all PHY address(0 ~ 31) to find a valid PHY
for (PhyAddress = 0; PhyAddress < 32; PhyAddress++)
{
for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) {
usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
// Found a valid PHY
if ((usData != 0x0) && (usData != 0xffff))
{
if ((usData != 0x0) && (usData != 0xffff)) {
bFoundPhy = TRUE;
break;
}
}
if (!bFoundPhy)
{
if (!bFoundPhy) {
printk(BIOS_DEBUG, "PHY not found !!!!\n");
}
@ -243,8 +229,7 @@ static void nic_init(struct device *dev)
{
u8 temp8;
int i=0;
while(SiS_SiS191_init[i][0] != 0)
{
while (SiS_SiS191_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
temp8 &= SiS_SiS191_init[i][1];
temp8 |= SiS_SiS191_init[i][2];
@ -260,31 +245,28 @@ static void nic_init(struct device *dev)
res = find_resource(dev, 0x10);
if (!res)
{
if (!res) {
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "NIC base address %p\n",base);
if (!(val=phy_detect(base,&PhyAddr)))
{
if (!(val=phy_detect(base,&PhyAddr))) {
printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
return;
}
ulValue=read32(base + 0x38L); // check EEPROM existing
if ((ulValue & 0x0002))
{
if ((ulValue & 0x0002)) {
// read MAC address from EEPROM at first
// if that is valid we will use that
printk(BIOS_DEBUG, "EEPROM contents %lx\n",ReadEEprom( dev, base, 0LL));
for(i=0;i<3;i++) {
for (i=0;i<3;i++) {
//status = smbus_read_byte(dev_eeprom, i);
ulValue=ReadEEprom( dev, base, i+3L);
if (ulValue ==0x10000) break; // error
@ -292,7 +274,7 @@ static void nic_init(struct device *dev)
MacAddr[i] =ulValue & 0xFFFF;
}
}else{
} else {
// read MAC address from firmware
printk(BIOS_DEBUG, "EEPROM invalid!!\nReg 0x38h=%.8lx\n",ulValue);
MacAddr[0]=read16((u16 *)0xffffffc0); // mac address store at here
@ -311,7 +293,7 @@ static void nic_init(struct device *dev)
printk(BIOS_DEBUG, "****** NIC PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for (i=0;i<0xff;i+=4){
for (i=0;i<0xff;i+=4) {
if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));

9
src/southbridge/sis/sis966/sata.c
View File

@ -109,8 +109,6 @@ static void sata_init(struct device *dev)
{
struct southbridge_sis_sis966_config *conf;
conf = dev->chip_info;
printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
@ -118,8 +116,7 @@ static void sata_init(struct device *dev)
{
uint8_t temp8;
int i=0;
while(SiS_SiS1183_init[i][0] != 0)
{
while (SiS_SiS1183_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
temp8 &= SiS_SiS1183_init[i][1];
temp8 |= SiS_SiS1183_init[i][2];
@ -133,7 +130,7 @@ static void sata_init(struct device *dev)
uint32_t i,j;
uint32_t temp32;
for (i=0;i<10;i++){
for (i=0;i<10;i++) {
temp32=0;
temp32= pci_read_config32(dev, 0xC0);
for ( j=0;j<0xFFFF;j++);
@ -150,7 +147,7 @@ for (i=0;i<10;i++){
printk(BIOS_DEBUG, "****** SATA PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for (i=0;i<0xff;i+=4){
for (i=0;i<0xff;i+=4) {
if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));

22
src/southbridge/sis/sis966/sis966.c
View File

@ -70,7 +70,7 @@ void sis966_enable(device_t dev)
conf = dev->chip_info;
int i;
if(dev->device==0x0000) {
if (dev->device==0x0000) {
reg = pci_read_config32(dev, PCI_VENDOR_ID);
deviceid = (reg >> 16) & 0xffff;
vendorid = reg & 0xffff;
@ -92,9 +92,9 @@ void sis966_enable(device_t dev)
case PCI_DEVICE_ID_SIS_SIS966_NIC:
devfn -= (7<<3);
index = 10;
for(i=0;i<2;i++) {
for (i=0;i<2;i++) {
lpc_dev = find_lpc_dev(dev, devfn - (i<<3));
if(!lpc_dev) continue;
if (!lpc_dev) continue;
index -= i;
devfn -= (i<<3);
break;
@ -112,7 +112,7 @@ void sis966_enable(device_t dev)
devfn -= (4<<3);
index = 22;
i = (dev->path.pci.devfn) & 7;
if(i>0) {
if (i>0) {
index -= (i+3);
}
break;
@ -124,14 +124,14 @@ void sis966_enable(device_t dev)
index = 0;
}
if(!lpc_dev)
if (!lpc_dev)
lpc_dev = find_lpc_dev(dev, devfn);
if ( !lpc_dev ) return;
if(index2!=0) {
if (index2!=0) {
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
if (!sm_dev) return;
if ( sm_dev ) {
reg_old = reg = pci_read_config32(sm_dev, 0xe4);
@ -165,9 +165,9 @@ void sis966_enable(device_t dev)
}
if( index == 16) {
if ( index == 16) {
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
if (!sm_dev) return;
final_reg = pci_read_config32(sm_dev, 0xe8);
final_reg &= ~0x0057cf00;
@ -184,9 +184,9 @@ void sis966_enable(device_t dev)
*/
}
if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
if (index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
if (!sm_dev) return;
reg_old = pci_read_config32(sm_dev, 0xe8);
if (final_reg != reg_old) {
pci_write_config32(sm_dev, 0xe8, final_reg);

6
src/southbridge/sis/sis966/usb.c
View File

@ -58,8 +58,8 @@ static void usb_init(struct device *dev)
uint8_t temp8;
int i=0;
while(SiS_SiS7001_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
while (SiS_SiS7001_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
temp8 &= SiS_SiS7001_init[i][1];
temp8 |= SiS_SiS7001_init[i][2];
pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);
@ -75,7 +75,7 @@ static void usb_init(struct device *dev)
printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for (i=0;i<0xff;i+=4){
for (i=0;i<0xff;i+=4) {
if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));

5
src/southbridge/sis/sis966/usb2.c
View File

@ -72,8 +72,7 @@ static void usb2_init(struct device *dev)
//-------------- enable USB2.0 (SiS7002) ----------------------
i = 0;
while (SiS_SiS7002_init[i][0] != 0)
{
while (SiS_SiS7002_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
temp8 &= SiS_SiS7002_init[i][1];
temp8 |= SiS_SiS7002_init[i][2];
@ -94,7 +93,7 @@ static void usb2_init(struct device *dev)
printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for (i=0;i<0xff;i+=4){
for (i=0;i<0xff;i+=4) {
if ((i%16)==0)
printk(BIOS_DEBUG, "\n%02x: ", i);
printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));

2
src/southbridge/via/k8t890/dram.c
View File

@ -107,7 +107,7 @@ k8m890_host_fb_size_get(void)
{
struct device *dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M800_DRAM, 0);
if(!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
if (!dev) dev = dev_find_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_K8M890CE_3, 0);
unsigned char tmp;

2
src/southbridge/via/vt8237r/smihandler.c
View File

@ -245,7 +245,7 @@ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_sav
}
}
if(dump) {
if (dump) {
dump_smi_status(smi_sts);
}