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Merge remote-tracking branch 'upstream/master' into galp5

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Change-Id: Ic25f3dba2af53111bca9e7762a2690c518c35fe1
This commit is contained in:
Jeremy Soller
2020-11-23 08:52:59 -07:00
parent 3cdc454b18 93859e319e
commit bd6bbc3655
346 changed files with 8729 additions and 9797 deletions
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2
3rdparty/vboot vendored

Submodule 3rdparty/vboot updated: 4c523ed10f...9d4053df76

4
Documentation/mainboard/index.md
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@@ -76,6 +76,10 @@ The boards in this section are not real mainboards, but emulators.
- [IceLake RVP](intel/icelake_rvp.md)
- [KBLRVP11](intel/kblrvp11.md)
## Kontron
- [mAL-10](kontron/mal10.md)
## Lenovo
- [Mainboard codenames](lenovo/codenames.md)

106
Documentation/mainboard/kontron/mal10.md Normal file
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@@ -0,0 +1,106 @@
# Kontron mAL10 Computer-on-Modules platform
The Kontron [mAL10] COMe is a credit card sized Computer-on-Modules
platform based on the Intel Atom E3900 Series, Pentium and Celeron
processors.
## Technology
```eval_rst
+------------------+----------------------------------+
| COMe Type | mini pin-out type 10 |
+------------------+----------------------------------+
| SoC | Intel Atom x5-E3940 (4 core) |
+------------------+----------------------------------+
| GPU | Intel HD Graphics 500 |
+------------------+----------------------------------+
| Coprocessor | Intel TXE 3.0 |
+------------------+----------------------------------+
| RAM | 8GB DDR3L |
+------------------+----------------------------------+
| eMMC Flash | 32GB eMMC pSLC |
+------------------+----------------------------------+
| USB3 | x2 |
+------------------+----------------------------------+
| USB2 | x6 |
+------------------+----------------------------------+
| SATA | x2 |
+------------------+----------------------------------+
| LAN | Intel I210IT, I211AT |
+------------------+----------------------------------+
| Super IO/EC | Kontron CPLD/EC |
+------------------+----------------------------------+
| HWM | NCT7802 |
+------------------+----------------------------------+
```
## Building coreboot
The following commands will build a working image:
```bash
make distclean
make defconfig KBUILD_DEFCONFIG=configs/config.kontron_mal10
make
```
## Payloads
- SeaBIOS
- Tianocore
- Linux as payload
## Flashing coreboot
The SPI flash can be accessed internally using [flashrom].
The following command is used to flash BIOS region.
```bash
$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
```
## Hardware Monitor
The Nuvoton [NCT7802Y] is a hardware monitoring IC, capable of monitor critical
system parameters including power supply voltages, fan speeds, and temperatures.
The remote inputs can be connected to CPU/GPU thermal diode or any thermal diode
sensors and thermistor.
- 6 temperature sensors;
- 5 voltage sensors;
- 3 fan speed sensors;
- 4 sets of temperature setting points.
PECI is not supported by Apollo Lake Pentium/Celeron/Atom processors and the CPU
temperature value is taken from a thermal resistor (NTC) that is placed very
close to the CPU.
## Known issues
- Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91
Booting with the "CorebootPayload" [crashes].
- Tianocore outputs video through an external GPU only.
## Untested
- IGD/LVDS
- SDIO
## Tested and working
- Kontron CPLD/EC (Serial ports, I2C port)
- NCT7802 [HWM](#Hardware Monitor)
- USB2/3
- Gigabit Ethernet ports
- eMMC
- SATA
- PCIe ports
- IGD/DP
## TODO
- Onboard audio (codec IDT 92HD73C1X5, currently disabled)
- S3 suspend/resume
[mAL10]: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html
[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf
[flashrom]: https://flashrom.org/Flashrom
[NCT7802Y]: https://www.nuvoton.com/products/cloud-computing/hardware-monitors/desktop-server-series/nct7802y/?__locale=en
[crashes]: https://pastebin.com/cpCfrPCL

13
Documentation/releases/checklist.md
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@@ -75,7 +75,8 @@ be more frequent than was needed, so we scaled it back to twice a year.
- [ ] Test the release from the actual release tarballs.
- [ ] Push signed Tag to repo.
- [ ] Announce that the release tag is done on IRC.
- [ ] Upload release files to web server
- [ ] Upload release files to web server.
- [ ] Also extract the release notes and place them on the web server.
- [ ] Upload crossgcc sources to web server.
- [ ] Update download page to point to files, push to repo.
- [ ] Write and publish blog post with release notes.
@@ -197,16 +198,16 @@ the coreboot server, and put them in the release directory at
````
People can now see the release tarballs on the website at
https://www.coreboot.org/releases/
<https://www.coreboot.org/releases/>
The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at https://review.coreboot.org/cgit/homepage.git/tree/downloads.html
The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
Here is an example commit to change it: https://review.coreboot.org/#/c/19515/
Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515>
## Upload crossgcc sources
Sometimes the source files for older revisions of
crossgcc disappear. To deal with that we maintain a mirror at
https://www.coreboot.org/releases/crossgcc-sources/ where we host the
<https://www.coreboot.org/releases/crossgcc-sources/> where we host the
sources used by the crossgcc scripts that are part of coreboot releases.
Run
@@ -220,7 +221,7 @@ sources. Download them yourself and copy them into the crossgcc-sources
directory on the server.
## After the release is complete
Post the release notes on https://blogs.coreboot.org
Post the release notes on <https://blogs.coreboot.org>
## Making a branch
At times we will need to create a branch, generally for patch fixes.

24
Documentation/releases/coreboot-4.13-relnotes.md
View File

@@ -234,3 +234,27 @@ to ensure that the platforms listed above are fixed before the next release. If
is interest in maintaining support for these platforms beyond the next release,
please ensure that the platforms are fixed to conform to the expectations of resource
allocation.
Notes
-----
### Intel microcode updates
Intel microcode updates tagged *microcode-20200616* are still included in our
builds. Note, [Intel released new microcode updates]
(https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md)
tagged
1. *microcode-20201110*
2. *microcode-20201112*
3. *microcode-20201118*
with security updates for [INTEL-SA-00381]
(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00381.html)
and [INTEL-SA-00389]
(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00389.html).
Due to too short time for rigorous testing and bad experience with botched
microcode updates in the past, these new updates are not included. Users wanting
to use those, can apply them in the operating system, or update the submodule
pointer themselves.

20
MAINTAINERS
View File

@@ -282,6 +282,14 @@ F: /src/mainboard/intel/strago/
KONTRON BSL6 MAINBOARD
M: Felix Singer <felixsinger@posteo.net>
M: Nico Huber <nico.h@gmx.de>
S: Supported
F: src/mainboard/kontron/bsl6/
LENOVO MAINBOARDS
M: Alexander Couzens <lynxis@fe80.eu>
M: Patrick Rudolph <siro@das-labor.org>
@@ -379,6 +387,12 @@ F: src/mainboard/samsung/stumpy/
SIEMENS CHILI MAINBAORD
M: Felix Singer <felixsinger@posteo.net>
M: Nico Huber <nico.h@gmx.de>
S: Supported
F: src/mainboard/siemens/chili/
SIEMENS MC_xxxx MAINBOARDS
M: Werner Zeh <werner.zeh@siemens.com>
S: Maintained
@@ -506,9 +520,11 @@ F: src/drivers/intel/
F: src/include/cpu/intel/
INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
M: Suresh Bellampalli <suresh.bellampalli@intel.com>
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
M: David Guckian <david.guckian@intel.com>
S: Odd Fixes
M: Michal Motyl <michalx.motyl@intel.com>
M: Mariusz Szafranski <mariuszx.szafranski@intel.com>
S: Maintained
F: src/mainboard/intel/harcuvar/
F: src/soc/intel/denverton_ns/

4
payloads/external/LinuxBoot/Kconfig vendored
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@@ -1,7 +1,3 @@
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## SPDX-License-Identifier: GPL-2.0-only
if PAYLOAD_LINUXBOOT

3
payloads/external/LinuxBoot/Kconfig.name vendored
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@@ -1,6 +1,3 @@
##
## Copyright (C) 2017 Facebook Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
config PAYLOAD_LINUXBOOT

4
payloads/external/LinuxBoot/Makefile vendored
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@@ -1,7 +1,3 @@
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## SPDX-License-Identifier: GPL-2.0-only
project_dir=linuxboot

4
payloads/external/LinuxBoot/targets/linux.mk vendored
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@@ -1,7 +1,3 @@
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## SPDX-License-Identifier: GPL-2.0-only
SHELL := /bin/bash

4
payloads/external/LinuxBoot/targets/u-root.mk vendored
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@@ -1,7 +1,3 @@
##
## Copyright (C) 2017 Facebook Inc.
## Copyright (C) 2018 9elements Cyber Security
##
## SPDX-License-Identifier: GPL-2.0-only
project_dir=$(shell pwd)/linuxboot

11
payloads/external/Makefile.inc vendored
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@@ -1,10 +1,3 @@
################################################################################
##
##
## Copyright (C) 2009-2010 coresystems GmbH
## Copyright (C) 2015 Google Inc.
## Copyright (C) 2017 Facebook Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
# set up payload config and version files for later inclusion
@@ -121,14 +114,14 @@ ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
INTERMEDIATE+=seabios_sercon
seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL)
@printf " SeaBIOS Add sercon-port file\n"
# $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
$(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
endif
ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
INTERMEDIATE+=seabios_thread_optionroms
seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL)
@printf " SeaBIOS Thread optionroms\n"
$(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads
$(CBFSTOOL) $< add-int -i 2 -n etc/threads
endif
# Depthcharge

4
payloads/external/Memtest86Plus/Makefile vendored
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@@ -1,7 +1,3 @@
##
##
## Copyright (C) 2016 Google Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
TAG-$(CONFIG_MEMTEST_MASTER)=origin/master

4
payloads/external/U-Boot/Makefile vendored
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@@ -1,7 +1,3 @@
##
##
## Copyright (C) 2015 Google Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
# 2019-4 tag

4
payloads/external/Yabits/Makefile vendored
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@@ -1,7 +1,3 @@
##
##
## Copyright (C) 2016 Google Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
TAG-$(CONFIG_YABITS_MASTER)=origin/master

2
payloads/external/iPXE/Kconfig vendored
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@@ -1,5 +1,3 @@
##
##
## SPDX-License-Identifier: GPL-2.0-only
config PXE

4
payloads/external/iPXE/Makefile vendored
View File

@@ -1,7 +1,3 @@
##
##
## Copyright (C) 2016 Google Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
# 2019.3 - Last commit of March 2019

4
payloads/external/tianocore/Makefile vendored
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@@ -1,7 +1,3 @@
##
##
## Copyright (C) 2017 Google Inc.
##
## SPDX-License-Identifier: GPL-2.0-only
# force the shell to bash - the edksetup.sh script doesn't work with dash

17
payloads/libpayload/drivers/usb/ehci.c
View File

@@ -28,6 +28,7 @@
//#define USB_DEBUG
#include <inttypes.h>
#include <libpayload.h>
#include <arch/barrier.h>
#include <arch/cache.h>
@@ -46,15 +47,15 @@ static void dump_td(u32 addr)
usb_debug("|..[OUT]............................................|\n");
else
usb_debug("|..[]...............................................|\n");
usb_debug("|:|============ EHCI TD at [0x%08lx] ==========|:|\n", addr);
usb_debug("|:| ERRORS = [%ld] | TOKEN = [0x%08lx] | |:|\n",
usb_debug("|:|============ EHCI TD at [0x%08"PRIx32"] ==========|:|\n", addr);
usb_debug("|:| ERRORS = [%"PRId32"] | TOKEN = [0x%08"PRIx32"] | |:|\n",
3 - ((td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT), td->token);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| Next qTD [0x%08lx] |:|\n", td->next_qtd);
usb_debug("|:| Next qTD [0x%08"PRIx32"] |:|\n", td->next_qtd);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| Alt. Next qTD [0x%08lx] |:|\n", td->alt_next_qtd);
usb_debug("|:| Alt. Next qTD [0x%08"PRIx32"] |:|\n", td->alt_next_qtd);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| | Bytes to Transfer |[%05ld] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16);
usb_debug("|:| | Bytes to Transfer |[%05"PRId32"] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16);
usb_debug("|:| | PID CODE: | [%ld] |:|\n", (td->token & (3UL << 8)) >> 8);
usb_debug("|:| | Interrupt On Complete (IOC) | [%ld] |:|\n", (td->token & (1UL << 15)) >> 15);
usb_debug("|:| | Status Active | [%ld] |:|\n", (td->token & (1UL << 7)) >> 7);
@@ -277,9 +278,11 @@ static int wait_for_tds(qtd_t *head)
if (cur->next_qtd & 1) {
break;
}
if (0) dump_td(virt_to_phys(cur));
if (0)
dump_td(virt_to_phys(cur));
/* helps debugging the TD chain */
if (0) usb_debug("\nmoving from %x to %x\n", cur, phys_to_virt(cur->next_qtd));
if (0)
usb_debug("\nmoving from %p to %p\n", cur, phys_to_virt(cur->next_qtd));
cur = phys_to_virt(cur->next_qtd);
}
return result;

19
payloads/libpayload/drivers/usb/ohci.c
View File

@@ -29,6 +29,7 @@
//#define USB_DEBUG
#include <arch/virtual.h>
#include <inttypes.h>
#include <usb/usb.h>
#include "ohci_private.h"
#include "ohci.h"
@@ -59,7 +60,7 @@ dump_td (td_t *cur)
else
usb_debug("|..[]...............................................|\n");
usb_debug("|:|============ OHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(cur));
usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08lx] | |:|\n",
usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08"PRIx32"] | |:|\n",
3 - ((cur->config & (3UL << 26)) >> 26), cur->config);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28);
@@ -69,11 +70,11 @@ dump_td (td_t *cur)
usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24);
usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| Current Buffer Pointer [0x%08lx] |:|\n", cur->current_buffer_pointer);
usb_debug("|:| Current Buffer Pointer [0x%08"PRIx32"] |:|\n", cur->current_buffer_pointer);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| Next TD [0x%08lx] |:|\n", cur->next_td);
usb_debug("|:| Next TD [0x%08"PRIx32"] |:|\n", cur->next_td);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| Current Buffer End [0x%08lx] |:|\n", cur->buffer_end);
usb_debug("|:| Current Buffer End [0x%08"PRIx32"] |:|\n", cur->buffer_end);
usb_debug("|:|-----------------------------------------------|:|\n");
usb_debug("|...................................................|\n");
usb_debug("+---------------------------------------------------+\n");
@@ -88,9 +89,9 @@ dump_ed (ed_t *cur)
usb_debug("+---------------------------------------------------+\n");
usb_debug("| Next Endpoint Descriptor [0x%08lx] |\n", cur->next_ed & ~0xFUL);
usb_debug("+---------------------------------------------------+\n");
usb_debug("| | @ 0x%08lx : |\n", cur->config);
usb_debug("| | @ 0x%08"PRIx32" : |\n", cur->config);
usb_debug("| C | Maximum Packet Length | [%04ld] |\n", ((cur->config & (0x3fffUL << 16)) >> 16));
usb_debug("| O | Function Address | [%04ld] |\n", cur->config & 0x7F);
usb_debug("| O | Function Address | [%04"PRIx32"] |\n", cur->config & 0x7F);
usb_debug("| N | Endpoint Number | [%02ld] |\n", (cur->config & (0xFUL << 7)) >> 7);
usb_debug("| F | Endpoint Direction | [%ld] |\n", ((cur->config & (3UL << 11)) >> 11));
usb_debug("| I | Endpoint Speed | [%ld] |\n", ((cur->config & (1UL << 13)) >> 13));
@@ -468,7 +469,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen,
head->tail_pointer = virt_to_phys(final_td);
head->head_pointer = virt_to_phys(first_td);
usb_debug("ohci_control(): doing transfer with %x. first_td at %x\n",
usb_debug("%s(): doing transfer with %x. first_td at %"PRIxPTR"\n", __func__,
head->config & ED_FUNC_MASK, virt_to_phys(first_td));
#ifdef USB_DEBUG
dump_ed(head);
@@ -506,7 +507,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)
td_t *cur, *next;
int remaining = dalen;
u8 *data = src;
usb_debug("bulk: %x bytes from %x, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize);
usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize);
if (!dma_coherent(src)) {
data = OHCI_INST(ep->dev->controller)->dma_buffer;
@@ -596,7 +597,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize)
head->tail_pointer = virt_to_phys(cur);
head->head_pointer = virt_to_phys(first_td) | (ep->toggle?ED_TOGGLE:0);
usb_debug("doing bulk transfer with %x(%x). first_td at %x, last %x\n",
usb_debug("doing bulk transfer with %x(%x). first_td at %"PRIxPTR", last %"PRIxPTR"\n",
head->config & ED_FUNC_MASK,
(head->config & ED_EP_MASK) >> ED_EP_SHIFT,
virt_to_phys(first_td), virt_to_phys(cur));

9
payloads/libpayload/drivers/usb/uhci.c
View File

@@ -29,6 +29,7 @@
//#define USB_DEBUG
#include <arch/virtual.h>
#include <inttypes.h>
#include <usb/usb.h>
#include "uhci.h"
#include "uhci_private.h"
@@ -79,14 +80,14 @@ static void td_dump(td_t *td)
(td->ptr & (1UL << 2)) >> 2, (td->ptr & (1UL << 1)) >> 1, td->ptr & 1UL);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| T | Maximum Length | [%04lx] |:|\n", (td->token & (0x7FFUL << 21)) >> 21);
usb_debug("|:| O | PID CODE | [%04lx] |:|\n", td->token & 0xFF);
usb_debug("|:| K | Endpoint | [%04lx] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT);
usb_debug("|:| O | PID CODE | [%04"PRIx32"] |:|\n", td->token & 0xFF);
usb_debug("|:| K | Endpoint | [%04"PRIx32"] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT);
usb_debug("|:| E | Device Address | [%04lx] |:|\n", (td->token & (0x7FUL << 8)) >> 8);
usb_debug("|:| N | Data Toggle | [%lx] |:|\n", (td->token & (1UL << 19)) >> 19);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| C | Short Packet Detector | [%lx] |:|\n", (td->ctrlsts & (1UL << 29)) >> 29);
usb_debug("|:| O | Error Counter | [%lx] |:|\n",
(td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT);
(td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT);
usb_debug("|:| N | Low Speed Device | [%lx] |:|\n", (td->ctrlsts & (1UL << 26)) >> 26);
usb_debug("|:| T | Isochronous Select | [%lx] |:|\n", (td->ctrlsts & (1UL << 25)) >> 25);
usb_debug("|:| R | Interrupt on Complete (IOC) | [%lx] |:|\n", (td->ctrlsts & (1UL << 24)) >> 24);
@@ -101,7 +102,7 @@ static void td_dump(td_t *td)
usb_debug("|:| S ----------------------------------------|:|\n");
usb_debug("|:| | Actual Length | [%04lx] |:|\n", td->ctrlsts & 0x7FFUL);
usb_debug("|:+-----------------------------------------------+:|\n");
usb_debug("|:| Buffer pointer [0x%08lx] |:|\n", td->bufptr);
usb_debug("|:| Buffer pointer [0x%08"PRIx32"] |:|\n", td->bufptr);
usb_debug("|:|-----------------------------------------------|:|\n");
usb_debug("|...................................................|\n");
usb_debug("+---------------------------------------------------+\n");

3
payloads/libpayload/drivers/usb/usb.c
View File

@@ -28,6 +28,7 @@
//#define USB_DEBUG
#include <inttypes.h>
#include <libpayload-config.h>
#include <usb/usb.h>
@@ -229,7 +230,7 @@ get_free_address (hci_t *controller)
int i = controller->latest_address + 1;
for (; i != controller->latest_address; i++) {
if (i >= ARRAY_SIZE(controller->devices) || i < 1) {
usb_debug("WARNING: Device addresses for controller %#x"
usb_debug("WARNING: Device addresses for controller %#" PRIxPTR
" wrapped around!\n", controller->reg_base);
i = 0;
continue;

12
payloads/libpayload/drivers/usb/xhci.c
View File

@@ -194,7 +194,7 @@ xhci_init (unsigned long physical_bar)
xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff;
xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff;
xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar);
xhci_debug("regbase: 0x%"PRIxPTR"\n", physical_bar);
xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg));
xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff);
xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff);
@@ -208,8 +208,8 @@ xhci_init (unsigned long physical_bar)
}
xhci_debug("context size: %dB\n", CTXSIZE(xhci));
xhci_debug("maxslots: 0x%02lx\n", CAP_GET(MAXSLOTS, xhci->capreg));
xhci_debug("maxports: 0x%02lx\n", CAP_GET(MAXPORTS, xhci->capreg));
xhci_debug("maxslots: 0x%02"PRIx32"\n", CAP_GET(MAXSLOTS, xhci->capreg));
xhci_debug("maxports: 0x%02"PRIx32"\n", CAP_GET(MAXPORTS, xhci->capreg));
const unsigned pagesize = xhci->opreg->pagesize << 12;
xhci_debug("pagesize: 0x%04x\n", pagesize);
@@ -374,7 +374,7 @@ xhci_reinit (hci_t *controller)
/* Initialize command ring */
xhci_init_cycle_ring(&xhci->cr, COMMAND_RING_SIZE);
xhci_debug("command ring @%p (0x%08x)\n",
xhci_debug("command ring @%p (0x%08"PRIxPTR")\n",
xhci->cr.ring, virt_to_phys(xhci->cr.ring));
xhci->opreg->crcr_lo = virt_to_phys(xhci->cr.ring) | CRCR_RCS;
xhci->opreg->crcr_hi = 0;
@@ -384,9 +384,9 @@ xhci_reinit (hci_t *controller)
/* Initialize event ring */
xhci_reset_event_ring(&xhci->er);
xhci_debug("event ring @%p (0x%08x)\n",
xhci_debug("event ring @%p (0x%08"PRIxPTR")\n",
xhci->er.ring, virt_to_phys(xhci->er.ring));
xhci_debug("ERST Max: 0x%lx -> 0x%lx entries\n",
xhci_debug("ERST Max: 0x%"PRIx32" -> 0x%x entries\n",
CAP_GET(ERST_MAX, xhci->capreg),
1 << CAP_GET(ERST_MAX, xhci->capreg));
memset((void*)xhci->ev_ring_table, 0x00, sizeof(erst_entry_t));

2
payloads/libpayload/include/usb/usb.h
View File

@@ -334,7 +334,7 @@ int usb_interface_check(u16 vendor, u16 device);
#define USB_QUIRK_TEST (1 << 31)
#define USB_QUIRK_NONE 0
static inline void usb_debug(const char *fmt, ...)
static inline void __attribute__((format(printf, 1, 2))) usb_debug(const char *fmt, ...)
{
#ifdef USB_DEBUG
va_list ap;

10
src/arch/x86/smbios.c
View File

@@ -493,6 +493,12 @@ unsigned int __weak smbios_cache_conf_operation_mode(u8 level)
return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */
}
/* Returns the processor voltage in 100mV units */
unsigned int __weak smbios_cpu_get_voltage(void)
{
return 0; /* Unknown */
}
static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache)
{
size_t max_logical_cpus_sharing_cache = 0;
@@ -595,6 +601,7 @@ static int smbios_write_type3(unsigned long *current, int handle)
static int smbios_write_type4(unsigned long *current, int handle)
{
unsigned int cpu_voltage;
struct cpuid_result res;
struct smbios_type4 *t = (struct smbios_type4 *)*current;
int len = sizeof(struct smbios_type4);
@@ -686,6 +693,9 @@ static int smbios_write_type4(unsigned long *current, int handle)
}
}
t->processor_characteristics = characteristics | smbios_processor_characteristics();
cpu_voltage = smbios_cpu_get_voltage();
if (cpu_voltage > 0)
t->voltage = 0x80 | cpu_voltage;
*current += len;
return len;

7
src/commonlib/Makefile.inc
View File

@@ -37,6 +37,13 @@ postcar-y += bsd/cbfs_private.c
ramstage-y += bsd/cbfs_private.c
smm-y += bsd/cbfs_private.c
bootblock-y += bsd/cbfs_mcache.c
verstage-y += bsd/cbfs_mcache.c
romstage-y += bsd/cbfs_mcache.c
postcar-y += bsd/cbfs_mcache.c
ramstage-y += bsd/cbfs_mcache.c
smm-y += bsd/cbfs_mcache.c
decompressor-y += bsd/lz4_wrapper.c
bootblock-y += bsd/lz4_wrapper.c
verstage-y += bsd/lz4_wrapper.c

143
src/commonlib/bsd/cbfs_mcache.c Normal file
View File

@@ -0,0 +1,143 @@
/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */
#include <assert.h>
#include <commonlib/bsd/cbfs_private.h>
/*
* A CBFS metadata cache is an in memory data structure storing CBFS file headers (= metadata).
* It is defined by its start pointer and size. It contains a sequence of variable-length
* union mcache_entry entries. There is no overall header structure for the cache.
*
* Each mcache_entry is the raw metadata for a CBFS file (including attributes) in the same form
* as stored on flash (i.e. values in big-endian), except that the CBFS magic signature in the
* first 8 bytes ('LARCHIVE') is overwritten with mcache-internal bookkeeping data. The first 4
* bytes are a magic number (MCACHE_MAGIC_FILE) and the next 4 bytes are the absolute offset in
* bytes on the cbfs_dev_t that this metadata blob was found at. (Note that depending on the
* implementation of cbfs_dev_t, this offset may still be relative to the start of a subregion
* of the underlying storage device.)
*
* The length of an mcache_entry (i.e. length of the underlying metadata blob) is encoded in the
* metadata (entry->file.h.offset). The next mcache_entry begins at the next
* CBFS_MCACHE_ALIGNMENT boundary after that. The cache is terminated by a special 4-byte
* mcache_entry that consists only of a magic number (MCACHE_MAGIC_END or MCACHE_MAGIC_FULL).
*/
#define MCACHE_MAGIC_FILE 0x454c4946 /* 'FILE' */
#define MCACHE_MAGIC_FULL 0x4c4c5546 /* 'FULL' */
#define MCACHE_MAGIC_END 0x444e4524 /* '$END' */
union mcache_entry {
union cbfs_mdata file;
struct { /* These fields exactly overlap file.h.magic */
uint32_t magic;
uint32_t offset;
};
};
struct cbfs_mcache_build_args {
void *mcache;
void *end;
int count;
};
static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata,
size_t already_read, void *arg)
{
struct cbfs_mcache_build_args *args = arg;
union mcache_entry *entry = args->mcache;
const uint32_t data_offset = be32toh(mdata->h.offset);
if (args->end - args->mcache < data_offset)
return CB_CBFS_CACHE_FULL;
if (cbfs_copy_fill_metadata(args->mcache, mdata, already_read, dev, offset))
return CB_CBFS_IO;
entry->magic = MCACHE_MAGIC_FILE;
entry->offset = offset;
args->mcache += ALIGN_UP(data_offset, CBFS_MCACHE_ALIGNMENT);
args->count++;
return CB_CBFS_NOT_FOUND;
}
cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size,
struct vb2_hash *metadata_hash)
{
struct cbfs_mcache_build_args args = {
.mcache = mcache,
.end = mcache + ALIGN_DOWN(size, CBFS_MCACHE_ALIGNMENT)
- sizeof(uint32_t), /* leave space for terminating magic */
.count = 0,
};
assert(size > sizeof(uint32_t) && IS_ALIGNED((uintptr_t)mcache, CBFS_MCACHE_ALIGNMENT));
cb_err_t ret = cbfs_walk(dev, build_walker, &args, metadata_hash, 0);
union mcache_entry *entry = args.mcache;
if (ret == CB_CBFS_NOT_FOUND) {
ret = CB_SUCCESS;
entry->magic = MCACHE_MAGIC_END;
} else if (ret == CB_CBFS_CACHE_FULL) {
ERROR("mcache overflow, should increase CBFS_MCACHE size!\n");
entry->magic = MCACHE_MAGIC_FULL;
}
LOG("mcache @%p built for %d files, used %#zx of %#zx bytes\n", mcache,
args.count, args.mcache + sizeof(entry->magic) - mcache, size);
return ret;
}
cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out)
{
const size_t namesize = strlen(name) + 1; /* Count trailing \0 so we can memcmp() it. */
const void *end = mcache + mcache_size;
const void *current = mcache;
while (current + sizeof(uint32_t) < end) {
const union mcache_entry *entry = current;
if (entry->magic == MCACHE_MAGIC_END)
return CB_CBFS_NOT_FOUND;
if (entry->magic == MCACHE_MAGIC_FULL)
return CB_CBFS_CACHE_FULL;
assert(entry->magic == MCACHE_MAGIC_FILE);
const uint32_t data_offset = be32toh(entry->file.h.offset);
const uint32_t data_length = be32toh(entry->file.h.len);
if (namesize <= data_offset - offsetof(union cbfs_mdata, filename) &&
memcmp(name, entry->file.filename, namesize) == 0) {
LOG("Found '%s' @%#x size %#x in mcache @%p\n",
name, entry->offset, data_length, current);
*data_offset_out = entry->offset + data_offset;
memcpy(mdata_out, &entry->file, data_offset);
return CB_SUCCESS;
}
current += ALIGN_UP(data_offset, CBFS_MCACHE_ALIGNMENT);
}
ERROR("CBFS mcache overflow!\n");
return CB_ERR;
}
size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size)
{
const void *end = mcache + mcache_size;
const void *current = mcache;
while (current + sizeof(uint32_t) < end) {
const union mcache_entry *entry = current;
if (entry->magic == MCACHE_MAGIC_FULL || entry->magic == MCACHE_MAGIC_END) {
current += sizeof(entry->magic);
break;
}
assert(entry->magic == MCACHE_MAGIC_FILE);
current += ALIGN_UP(be32toh(entry->file.h.offset), CBFS_MCACHE_ALIGNMENT);
}
return current - mcache;
}

1
src/commonlib/bsd/include/commonlib/bsd/cb_err.h
View File

@@ -39,6 +39,7 @@ enum cb_err {
CB_CBFS_IO = -400, /**< Underlying I/O error */
CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */
CB_CBFS_HASH_MISMATCH = -402, /**< Master hash validation failed */
CB_CBFS_CACHE_FULL = -403, /**< Metadata cache overflowed */
};
/* Don't typedef the enum directly, so the size is unambiguous for serialization. */

21
src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h
View File

@@ -113,4 +113,25 @@ cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata *
cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out,
size_t *data_offset_out, struct vb2_hash *metadata_hash);
/* Both base address and size of CBFS mcaches must be aligned to this value! */
#define CBFS_MCACHE_ALIGNMENT sizeof(uint32_t) /* Largest data type used in CBFS */
/* Build an in-memory CBFS metadata cache out of the CBFS on |dev| into a |mcache_size| bytes
* memory area at |mcache|. Also verify |metadata_hash| unless it is NULL. If this returns
* CB_CBFS_CACHE_FULL, the mcache is still valid and can be used, but lookups may return
* CB_CBFS_CACHE_FULL for files that didn't fit to indicate that the caller needs to fall back
* to cbfs_lookup(). */
cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size,
struct vb2_hash *metadata_hash);
/*
* Find a file named |name| in a CBFS metadata cache and copy its metadata into |mdata_out|.
* Pass out offset to the file data (on the original CBFS device used for cbfs_mcache_build()).
*/
cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name,
union cbfs_mdata *mdata_out, size_t *data_offset_out);
/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */
size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size);
#endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */

6
src/commonlib/include/commonlib/cbmem_id.h
View File

@@ -67,6 +67,8 @@
#define CBMEM_ID_ROM2 0x524f4d32
#define CBMEM_ID_ROM3 0x524f4d33
#define CBMEM_ID_FMAP 0x464d4150
#define CBMEM_ID_CBFS_RO_MCACHE 0x524d5346
#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346
#define CBMEM_ID_FSP_LOGO 0x4c4f474f
#define CBMEM_ID_SMM_COMBUFFER 0x53534d32
@@ -129,5 +131,7 @@
{ CBMEM_ID_ROM1, "VGA ROM #1 "}, \
{ CBMEM_ID_ROM2, "VGA ROM #2 "}, \
{ CBMEM_ID_ROM3, "VGA ROM #3 "}, \
{ CBMEM_ID_FMAP, "FMAP "},
{ CBMEM_ID_FMAP, "FMAP "}, \
{ CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \
{ CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "}
#endif /* _CBMEM_ID_H_ */

2
src/cpu/amd/microcode/Makefile.inc
View File

@@ -1,2 +0,0 @@
ramstage-y += microcode.c
romstage-y += microcode.c

13
src/cpu/amd/pi/00660F01/Kconfig
View File

@@ -1,13 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
config CPU_AMD_PI_00660F01
bool
select X86_AMD_FIXED_MTRRS
if CPU_AMD_PI_00660F01
config CPU_ADDR_BITS
int
default 48
endif

14
src/cpu/amd/pi/00660F01/Makefile.inc
View File

@@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-only
romstage-y += fixme.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
ramstage-y += model_15_init.c
subdirs-y += ../../mtrr
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
subdirs-y += ../../../x86/mtrr
subdirs-y += ../../../x86/pae
subdirs-y += ../../../x86/smm

48
src/cpu/amd/pi/00660F01/acpi/cpu.asl
View File

@@ -1,48 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Processor Object
*
*/
Scope (\_SB) { /* define processor scope */
Device (P000) {
Name(_HID, "ACPI0007")
Name(_UID, 0)
}
Device (P001) {
Name(_HID, "ACPI0007")
Name(_UID, 1)
}
Device (P002) {
Name(_HID, "ACPI0007")
Name(_UID, 2)
}
Device (P003) {
Name(_HID, "ACPI0007")
Name(_UID, 3)
}
Device (P004) {
Name(_HID, "ACPI0007")
Name(_UID, 4)
}
Device (P005) {
Name(_HID, "ACPI0007")
Name(_UID, 5)
}
Device (P006) {
Name(_HID, "ACPI0007")
Name(_UID, 6)
}
Device (P007) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
} /* End _SB scope */

7
src/cpu/amd/pi/00660F01/chip_name.c
View File

@@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/device.h>
struct chip_operations cpu_amd_pi_00660F01_ops = {
CHIP_NAME("AMD CPU Family 15h Model 60h-6Fh")
};

55
src/cpu/amd/pi/00660F01/fixme.c
View File

@@ -1,55 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/mtrr.h>
#include <cpu/amd/msr.h>
#include <cpu/amd/mtrr.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <Porting.h>
#include <AGESA.h>
#include <amdlib.h>
void amd_initcpuio(void)
{
UINT64 MsrReg;
UINT32 PciData;
PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* The platform BIOS needs to ensure the memory ranges of SB800 legacy
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
/* last address before processor local APIC at FEE00000 */
PciData = 0x00FEDF00;
/* set NP (non-posted) bit */
PciData |= 1 << 7;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
/* lowest NP address is HPET at FED00000 */
PciData = (0xFED00000 >> 8) | 3;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
}

119
src/cpu/amd/pi/00660F01/model_15_init.c
View File

@@ -1,119 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <device/pci.h>
#include <cpu/x86/pae.h>
#include <cpu/x86/lapic.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <amdlib.h>
#include <PspBaseLib.h>
void PSPProgBar3Msr(void *Buffer);
void PSPProgBar3Msr(void *Buffer)
{
u32 Bar3Addr;
u64 Tmp64;
/* Get Bar3 Addr */
Bar3Addr = PspLibPciReadPspConfig(0x20);
Tmp64 = Bar3Addr;
printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);
LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL);
LibAmdMsrRead(0xC00110A2, &Tmp64, NULL);
}
static void model_15_init(struct device *dev)
{
printk(BIOS_DEBUG, "Model 15 Init.\n");
u8 i;
msr_t msr;
int num_banks;
int msrno;
#if CONFIG(LOGICAL_CPUS)
u32 siblings;
#endif
disable_cache();
/* Enable access to AMD RdDram and WrDram extension bits */
msr = rdmsr(SYSCFG_MSR);
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
// BSP: make a0000-bffff UC, c0000-fffff WB
msr.lo = msr.hi = 0;
wrmsr(MTRR_FIX_16K_A0000, msr);
msr.lo = msr.hi = 0x1e1e1e1e;
wrmsr(MTRR_FIX_64K_00000, msr);
wrmsr(MTRR_FIX_16K_80000, msr);
for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
wrmsr(msrno, msr);
msr = rdmsr(SYSCFG_MSR);
msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
wrmsr(SYSCFG_MSR, msr);
x86_mtrr_check();
x86_enable_cache();
/* zero the machine check error status registers */
msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & MCA_BANKS_MASK;
msr.lo = 0;
msr.hi = 0;
for (i = 0; i < num_banks; i++)
wrmsr(IA32_MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */
setup_lapic();
#if CONFIG(LOGICAL_CPUS)
siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |= 1 << (33 - 32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
PSPProgBar3Msr(NULL);
/* DisableCf8ExtCfg */
msr = rdmsr(NB_CFG_MSR);
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
}
static struct device_operations cpu_dev_ops = {
.init = model_15_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_AMD, 0x660f00 },
{ X86_VENDOR_AMD, 0x660f01 },
{ 0, 0 },
};
static const struct cpu_driver model_15 __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

2
src/cpu/amd/pi/Kconfig
View File

@@ -4,7 +4,6 @@ config CPU_AMD_PI
bool
default y if CPU_AMD_PI_00630F01
default y if CPU_AMD_PI_00730F01
default y if CPU_AMD_PI_00660F01
default n
select ARCH_ALL_STAGES_X86_32
select DRIVERS_AMD_PI
@@ -46,4 +45,3 @@ endif # CPU_AMD_PI
source "src/cpu/amd/pi/00630F01/Kconfig"
source "src/cpu/amd/pi/00730F01/Kconfig"
source "src/cpu/amd/pi/00660F01/Kconfig"

1
src/cpu/amd/pi/Makefile.inc
View File

@@ -2,4 +2,3 @@
subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01

3
src/cpu/intel/common/Kconfig
View File

@@ -32,6 +32,9 @@ config CPU_INTEL_COMMON_TIMEBASE
endif
config CPU_INTEL_COMMON_VOLTAGE
bool
config CPU_INTEL_COMMON_SMM
bool
default y if CPU_INTEL_COMMON

1
src/cpu/intel/common/Makefile.inc
View File

@@ -1,5 +1,6 @@
ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c
ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c
ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y)
bootblock-y += fsb.c

12
src/cpu/intel/common/voltage.c Normal file
View File

@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/msr.h>
#include <smbios.h>
/* This is not an architectural MSR. */
#define MSR_PERF_STATUS 0x198
unsigned int smbios_cpu_get_voltage(void)
{
return (rdmsr(MSR_PERF_STATUS).hi & 0xffff) * 10 / 8192;
}

1
src/cpu/intel/haswell/Kconfig
View File

@@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select HAVE_ASAN_IN_ROMSTAGE
select CPU_INTEL_COMMON_VOLTAGE
config SMM_TSEG_SIZE
hex

2
src/cpu/intel/socket_441/Kconfig
View File

@@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x4000
default 0x8000
config DCACHE_RAM_BASE
hex

3
src/drivers/i2c/generic/generic.c
View File

@@ -72,7 +72,8 @@ void i2c_generic_fill_ssdt(const struct device *dev,
if (config->cid)
acpigen_write_name_string("_CID", config->cid);
acpigen_write_name_integer("_UID", config->uid);
acpigen_write_name_string("_DDN", config->desc);
if (config->desc)
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(acpi_device_status(dev));
/* Resources */

4
src/drivers/i2c/hid/hid.c
View File

@@ -28,6 +28,10 @@ static void i2c_hid_fill_ssdt_generator(const struct device *dev)
static const char *i2c_hid_acpi_name(const struct device *dev)
{
static char name[5];
struct drivers_i2c_hid_config *config = dev->chip_info;
if (config->generic.name)
return config->generic.name;
snprintf(name, sizeof(name), "H%03.3X", dev->path.i2c.device);
name[4] = '\0';
return name;

6
src/drivers/i2c/sx9324/Kconfig Normal file
View File

@@ -0,0 +1,6 @@
config DRIVERS_I2C_SX9324
bool
default n
depends on HAVE_ACPI_TABLES
help
Board has a Semtech SX9324 proximity sensor.

1
src/drivers/i2c/sx9324/Makefile.inc Normal file
View File

@@ -0,0 +1 @@
ramstage-$(CONFIG_DRIVERS_I2C_SX9324) += sx9324.c

31
src/drivers/i2c/sx9324/chip.h Normal file
View File

@@ -0,0 +1,31 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __DRIVERS_I2C_SX9324_CHIP_H__
#define __DRIVERS_I2C_SX9324_CHIP_H__
#include <acpi/acpi_device.h>
#include <device/i2c_simple.h>
#define REGISTER(NAME) uint8_t NAME
struct drivers_i2c_sx9324_config {
/* Device Description */
const char *desc;
/* ACPI _UID */
unsigned int uid;
/* Bus speed in Hz, default is I2C_SPEED_FAST */
enum i2c_speed speed;
/* Use GPIO-based interrupt instead of IO-APIC */
struct acpi_gpio irq_gpio;
/* IO-APIC interrupt */
struct acpi_irq irq;
#include "registers.h"
};
#undef REGISTER
#endif /* __DRIVERS_I2C_SX9324_CHIP_H__ */

50
src/drivers/i2c/sx9324/registers.h Normal file
View File

@@ -0,0 +1,50 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef REGISTER
#error "define REGISTER(NAME) before including this file"
#endif
REGISTER(reg_gnrl_ctrl0);
REGISTER(reg_gnrl_ctrl1);
REGISTER(reg_afe_ctrl0);
REGISTER(reg_afe_ctrl1);
REGISTER(reg_afe_ctrl2);
REGISTER(reg_afe_ctrl3);
REGISTER(reg_afe_ctrl4);
REGISTER(reg_afe_ctrl5);
REGISTER(reg_afe_ctrl6);
REGISTER(reg_afe_ctrl7);
REGISTER(reg_afe_ctrl8);
REGISTER(reg_afe_ctrl9);
REGISTER(reg_prox_ctrl0);
REGISTER(reg_prox_ctrl1);
REGISTER(reg_prox_ctrl2);
REGISTER(reg_prox_ctrl3);
REGISTER(reg_prox_ctrl4);
REGISTER(reg_prox_ctrl5);
REGISTER(reg_prox_ctrl6);
REGISTER(reg_prox_ctrl7);
REGISTER(reg_adv_ctrl0);
REGISTER(reg_adv_ctrl1);
REGISTER(reg_adv_ctrl2);
REGISTER(reg_adv_ctrl3);
REGISTER(reg_adv_ctrl4);
REGISTER(reg_adv_ctrl5);
REGISTER(reg_adv_ctrl6);
REGISTER(reg_adv_ctrl7);
REGISTER(reg_adv_ctrl8);
REGISTER(reg_adv_ctrl9);
REGISTER(reg_adv_ctrl10);
REGISTER(reg_adv_ctrl11);
REGISTER(reg_adv_ctrl12);
REGISTER(reg_adv_ctrl13);
REGISTER(reg_adv_ctrl14);
REGISTER(reg_adv_ctrl15);
REGISTER(reg_adv_ctrl16);
REGISTER(reg_adv_ctrl17);
REGISTER(reg_adv_ctrl18);
REGISTER(reg_adv_ctrl19);
REGISTER(reg_adv_ctrl20);

104
src/drivers/i2c/sx9324/sx9324.c Normal file
View File

@@ -0,0 +1,104 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi_device.h>
#include <acpi/acpigen.h>
#include <console/console.h>
#include <device/i2c_simple.h>
#include <device/device.h>
#include <device/path.h>
#include <string.h>
#include "chip.h"
#define I2C_SX9324_ACPI_ID "STH9324"
#define I2C_SX9324_CHIP_NAME "Semtech SX9324"
#define REGISTER(NAME) acpi_dp_add_integer(dsd, \
I2C_SX9324_ACPI_ID "," #NAME, \
config->NAME)
static void i2c_sx9324_fill_ssdt(const struct device *dev)
{
struct drivers_i2c_sx9324_config *config = dev->chip_info;
const char *scope = acpi_device_scope(dev);
struct acpi_i2c i2c = {
.address = dev->path.i2c.device,
.mode_10bit = dev->path.i2c.mode_10bit,
.speed = I2C_SPEED_FAST,
.resource = scope,
};
struct acpi_dp *dsd;
if (!scope || !config)
return;
if (config->speed)
i2c.speed = config->speed;
/* Device */
acpigen_write_scope(scope);
acpigen_write_device(acpi_device_name(dev));
acpigen_write_name_string("_HID", I2C_SX9324_ACPI_ID);
acpigen_write_name_integer("_UID", config->uid);
acpigen_write_name_string("_DDN", config->desc);
acpigen_write_STA(acpi_device_status(dev));
/* Resources */
acpigen_write_name("_CRS");
acpigen_write_resourcetemplate_header();
acpi_device_write_i2c(&i2c);
if (config->irq_gpio.pin_count)
acpi_device_write_gpio(&config->irq_gpio);
else
acpi_device_write_interrupt(&config->irq);
acpigen_write_resourcetemplate_footer();
/* DSD */
dsd = acpi_dp_new_table("_DSD");
#include "registers.h"
acpi_dp_write(dsd);
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */
printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev),
config->desc ? : dev->chip_ops->name, dev_path(dev));
}
#undef REGISTER
static const char *i2c_sx9324_acpi_name(const struct device *dev)
{
static char name[5];
snprintf(name, sizeof(name), "SX%02.2X", dev->path.i2c.device);
return name;
}
static struct device_operations i2c_sx9324_ops = {
.read_resources = noop_read_resources,
.set_resources = noop_set_resources,
.acpi_name = i2c_sx9324_acpi_name,
.acpi_fill_ssdt = i2c_sx9324_fill_ssdt,
};
static void i2c_sx9324_enable(struct device *dev)
{
struct drivers_i2c_sx9324_config *config = dev->chip_info;
if (!config) {
dev->enabled = 0;
return;
}
dev->ops = &i2c_sx9324_ops;
if (config->desc)
dev->name = config->desc;
}
struct chip_operations drivers_i2c_sx9324_ops = {
CHIP_NAME(I2C_SX9324_CHIP_NAME)
.enable_dev = i2c_sx9324_enable
};

1
src/drivers/intel/fsp1_1/Makefile.inc
View File

@@ -9,6 +9,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c
bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
bootblock-y += fsp_util.c
bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S
bootblock-y += fsp_report.c
romstage-y += car.c
romstage-y += fsp_util.c

24
src/drivers/intel/fsp1_1/cache_as_ram.S
View File

@@ -145,16 +145,28 @@ CAR_init_done:
* mm1: high 32-bits of TSC value
*/
/* coreboot assumes stack/heap region will be zero */
/*
* temp_memory_start/end reside in the .bss section, which gets cleared
* below. Save the FSP return value to the stack before writing those
* variables.
*/
push %ecx
push %edx
/* clear .bss section */
cld
movl %ecx, %edi
neg %ecx
/* Clear up to Temp Ram top. */
add %edx, %ecx
xor %eax, %eax
movl $(_ebss), %ecx
movl $(_bss), %edi
sub %edi, %ecx
shrl $2, %ecx
xorl %eax, %eax
rep stosl
pop %edx
movl %edx, temp_memory_end
pop %ecx
movl %ecx, temp_memory_start
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp

27
src/drivers/intel/fsp1_1/fsp_report.c Normal file
View File

@@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/symbols.h>
#include <console/console.h>
#include <fsp/util.h>
/* filled in assembly after FSP-T ran */
uintptr_t temp_memory_start;
uintptr_t temp_memory_end;
void report_fsp_output(void)
{
const struct region fsp_car_region = {
.offset = temp_memory_start,
.size = temp_memory_end - temp_memory_start,
};
const struct region coreboot_car_region = {
.offset = (uintptr_t)_car_region_start,
.size = (uintptr_t)_car_region_size,
};
printk(BIOS_DEBUG, "FSP: reported temp_mem region: [0x%08lx,0x%08lx)\n",
temp_memory_start, temp_memory_end);
if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) {
printk(BIOS_ERR, "Wrong CAR region used!\n");
printk(BIOS_ERR, "Adapt DCACHE_RAM_BASE and DCACHE_RAM_SIZE to match FSP-T\n");
}
}

1
src/drivers/intel/fsp1_1/include/fsp/util.h
View File

@@ -31,6 +31,7 @@ void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start);
void *get_first_resource_hob(const EFI_GUID *guid);
void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old,
uint64_t new);
void report_fsp_output(void);
/* Return version of FSP associated with fih. */
static inline uint32_t fsp_version(FSP_INFO_HEADER *fih)

10
src/drivers/intel/fsp2_0/header_display.c
View File

@@ -5,15 +5,7 @@
void fsp_print_header_info(const struct fsp_header *hdr)
{
union {
uint32_t val;
struct {
uint8_t bld_num;
uint8_t revision;
uint8_t minor;
uint8_t major;
} rev;
} revision;
union fsp_revision revision;
revision.val = hdr->fsp_revision;

11
src/drivers/intel/fsp2_0/include/fsp/util.h
View File

@@ -42,6 +42,16 @@ struct hob_resource {
uint64_t length;
} __packed;
union fsp_revision {
uint32_t val;
struct {
uint8_t bld_num;
uint8_t revision;
uint8_t minor;
uint8_t major;
} rev;
};
#if CONFIG_UDK_VERSION < CONFIG_UDK_2017_VERSION
enum resource_type {
EFI_RESOURCE_SYSTEM_MEMORY = 0,
@@ -90,6 +100,7 @@ void fsp_find_bootloader_tolum(struct range_entry *re);
void fsp_get_version(char *buf);
void lb_string_platform_blob_version(struct lb_header *header);
void report_fspt_output(void);
void soc_validate_fsp_version(const struct fsp_header *hdr);
/* Fill in header and validate sanity of component within region device. */
enum cb_err fsp_validate_component(struct fsp_header *hdr,

18
src/drivers/intel/fsp2_0/util.c
View File

@@ -85,6 +85,9 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr,
return CB_ERR;
}
if (ENV_ROMSTAGE)
soc_validate_fsp_version(hdr);
return CB_SUCCESS;
}
@@ -213,15 +216,7 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea
void fsp_get_version(char *buf)
{
struct fsp_header *hdr = &fsps_hdr;
union {
uint32_t val;
struct {
uint8_t bld_num;
uint8_t revision;
uint8_t minor;
uint8_t major;
} rev;
} revision;
union fsp_revision revision;
revision.val = hdr->fsp_revision;
snprintf(buf, FSP_VER_LEN, "%u.%u-%u.%u.%u.%u", (hdr->spec_version >> 4),
@@ -243,3 +238,8 @@ void lb_string_platform_blob_version(struct lb_header *header)
rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8);
memcpy(rec->string, fsp_version, len+1);
}
__weak void soc_validate_fsp_version(const struct fsp_header *hdr)
{
printk(BIOS_DEBUG, "%s not implemented.\n", __func__);
}

126
src/drivers/pc80/tpm/tis.c
View File

@@ -21,13 +21,11 @@
#include <console/console.h>
#include <security/tpm/tis.h>
#include <device/pnp.h>
#include <drivers/tpm/tpm_ppi.h>
#include "chip.h"
#define PREFIX "lpc_tpm: "
/* TCG Physical Presence Interface */
#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653"
/* TCG Memory Clear Interface */
#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d"
/* coreboot wrapper for TPM driver (start) */
#define TPM_DEBUG(fmt, args...) \
if (CONFIG(DEBUG_TPM)) { \
@@ -777,104 +775,9 @@ static void lpc_tpm_set_resources(struct device *dev)
}
#if CONFIG(HAVE_ACPI_TABLES)
static void tpm_ppi_func0_cb(void *arg)
{
/* Functions 1-8. */
u8 buf[] = {0xff, 0x01};
acpigen_write_return_byte_buffer(buf, 2);
}
static void tpm_ppi_func1_cb(void *arg)
{
if (CONFIG(TPM2))
/* Interface version: 2.0 */
acpigen_write_return_string("2.0");
else
/* Interface version: 1.2 */
acpigen_write_return_string("1.2");
}
static void tpm_ppi_func2_cb(void *arg)
{
/* Submit operations: drop on the floor and return success. */
acpigen_write_return_byte(0);
}
static void tpm_ppi_func3_cb(void *arg)
{
/* Pending operation: none. */
acpigen_emit_byte(RETURN_OP);
acpigen_write_package(2);
acpigen_write_byte(0);
acpigen_write_byte(0);
acpigen_pop_len();
}
static void tpm_ppi_func4_cb(void *arg)
{
/* Pre-OS transition method: reboot. */
acpigen_write_return_byte(2);
}
static void tpm_ppi_func5_cb(void *arg)
{
/* Operation response: no operation executed. */
acpigen_emit_byte(RETURN_OP);
acpigen_write_package(3);
acpigen_write_byte(0);
acpigen_write_byte(0);
acpigen_write_byte(0);
acpigen_pop_len();
}
static void tpm_ppi_func6_cb(void *arg)
{
/*
* Set preferred user language: deprecated and must return 3 aka
* "not implemented".
*/
acpigen_write_return_byte(3);
}
static void tpm_ppi_func7_cb(void *arg)
{
/* Submit operations: deny. */
acpigen_write_return_byte(3);
}
static void tpm_ppi_func8_cb(void *arg)
{
/* All actions are forbidden. */
acpigen_write_return_byte(1);
}
static void (*tpm_ppi_callbacks[])(void *) = {
tpm_ppi_func0_cb,
tpm_ppi_func1_cb,
tpm_ppi_func2_cb,
tpm_ppi_func3_cb,
tpm_ppi_func4_cb,
tpm_ppi_func5_cb,
tpm_ppi_func6_cb,
tpm_ppi_func7_cb,
tpm_ppi_func8_cb,
};
static void tpm_mci_func0_cb(void *arg)
{
/* Function 1. */
acpigen_write_return_singleton_buffer(0x3);
}
static void tpm_mci_func1_cb(void *arg)
{
/* Just return success. */
acpigen_write_return_byte(0);
}
static void (*tpm_mci_callbacks[])(void *) = {
tpm_mci_func0_cb,
tpm_mci_func1_cb,
};
static void lpc_tpm_fill_ssdt(const struct device *dev)
{
const char *path = acpi_device_path(dev->bus->dev);
u32 arg;
if (!path) {
path = "\\_SB_.PCI0.LPCB";
@@ -938,31 +841,12 @@ static void lpc_tpm_fill_ssdt(const struct device *dev)
acpi_device_write_interrupt(&tpm_irq);
}
acpigen_write_resourcetemplate_footer();
if (!CONFIG(CHROMEOS)) {
/*
* _DSM method
*/
struct dsm_uuid ids[] = {
/* Physical presence interface.
* This is used to submit commands like "Clear TPM" to
* be run at next reboot provided that user confirms
* them. Spec allows user to cancel all commands and/or
* configure BIOS to reject commands. So we pretend that
* user did just this: cancelled everything. If user
* really wants to clear TPM the only option now is to
* do it manually in payload.
*/
DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0],
ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg),
/* Memory clearing on boot: just a dummy. */
DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0],
ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg),
};
if (!CONFIG(CHROMEOS))
tpm_ppi_acpi_fill_ssdt(dev);
acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids));
}
acpigen_pop_len(); /* Device */
acpigen_pop_len(); /* Scope */

2
src/drivers/tpm/Makefile.inc
View File

@@ -1 +1,3 @@
ramstage-$(CONFIG_TPM_INIT) += tpm.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c

133
src/drivers/tpm/ppi_stub.c Normal file
View File

@@ -0,0 +1,133 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <types.h>
#include <stddef.h>
#include <acpi/acpi.h>
#include <acpi/acpigen.h>
#include <acpi/acpi_device.h>
#include "tpm_ppi.h"
static void tpm_ppi_func0_cb(void *arg)
{
/* Functions 1-8. */
u8 buf[] = {0xff, 0x01};
acpigen_write_return_byte_buffer(buf, sizeof(buf));
}
static void tpm_ppi_func1_cb(void *arg)
{
if (CONFIG(TPM2))
/* Interface version: 2.0 */
acpigen_write_return_string("2.0");
else
/* Interface version: 1.2 */
acpigen_write_return_string("1.2");
}
static void tpm_ppi_func2_cb(void *arg)
{
/* Submit operations: drop on the floor and return success. */
acpigen_write_return_byte(PPI2_RET_SUCCESS);
}
static void tpm_ppi_func3_cb(void *arg)
{
/* Pending operation: none. */
acpigen_emit_byte(RETURN_OP);
acpigen_write_package(2);
acpigen_write_byte(0);
acpigen_write_byte(0);
acpigen_pop_len();
}
static void tpm_ppi_func4_cb(void *arg)
{
/* Pre-OS transition method: reboot. */
acpigen_write_return_byte(2);
}
static void tpm_ppi_func5_cb(void *arg)
{
/* Operation response: no operation executed. */
acpigen_emit_byte(RETURN_OP);
acpigen_write_package(3);
acpigen_write_byte(0);
acpigen_write_byte(0);
acpigen_write_byte(0);
acpigen_pop_len();
}
static void tpm_ppi_func6_cb(void *arg)
{
/*
* Set preferred user language: deprecated and must return 3 AKA
* "not implemented".
*/
acpigen_write_return_byte(PPI6_RET_NOT_IMPLEMENTED);
}
static void tpm_ppi_func7_cb(void *arg)
{
/* Submit operations: deny. */
acpigen_write_return_byte(PPI7_RET_BLOCKED_BY_FIRMWARE);
}
static void tpm_ppi_func8_cb(void *arg)
{
/* All actions are forbidden. */
acpigen_write_return_byte(PPI8_RET_FIRMWARE_ONLY);
}
static void (*tpm_ppi_callbacks[])(void *) = {
tpm_ppi_func0_cb,
tpm_ppi_func1_cb,
tpm_ppi_func2_cb,
tpm_ppi_func3_cb,
tpm_ppi_func4_cb,
tpm_ppi_func5_cb,
tpm_ppi_func6_cb,
tpm_ppi_func7_cb,
tpm_ppi_func8_cb,
};
static void tpm_mci_func0_cb(void *arg)
{
/* Function 1. */
acpigen_write_return_singleton_buffer(0x3);
}
static void tpm_mci_func1_cb(void *arg)
{
/* Just return success. */
acpigen_write_return_byte(0);
}
static void (*tpm_mci_callbacks[])(void *) = {
tpm_mci_func0_cb,
tpm_mci_func1_cb,
};
void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
{
/*
* _DSM method
*/
struct dsm_uuid ids[] = {
/* Physical presence interface.
* This is used to submit commands like "Clear TPM" to
* be run at next reboot provided that user confirms
* them. Spec allows user to cancel all commands and/or
* configure BIOS to reject commands. So we pretend that
* user did just this: cancelled everything. If user
* really wants to clear TPM the only option now is to
* do it manually in payload.
*/
DSM_UUID(TPM_PPI_UUID, tpm_ppi_callbacks,
ARRAY_SIZE(tpm_ppi_callbacks), NULL),
/* Memory clearing on boot: just a dummy. */
DSM_UUID(TPM_MCI_UUID, tpm_mci_callbacks,
ARRAY_SIZE(tpm_mci_callbacks), NULL),
};
acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids));
}

58
src/drivers/tpm/tpm_ppi.h Normal file
View File

@@ -0,0 +1,58 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef _TPM_PPI_H_
#define _TPM_PPI_H_
#include <device/device.h>
#if CONFIG(HAVE_ACPI_TABLES)
void tpm_ppi_acpi_fill_ssdt(const struct device *dev);
#else
static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev)
{
}
#endif
/* Return codes */
/* Function 2 */
#define PPI2_RET_SUCCESS 0
#define PPI2_RET_NOT_SUPPORTED 1
#define PPI2_RET_GENERAL_FAILURE 2
/* Function 3 */
#define PPI3_RET_SUCCESS 0
#define PPI3_RET_GENERAL_FAILURE 1
/* Function 4 */
#define PPI4_RET_NONE 0
#define PPI4_RET_SHUTDOWN 1
#define PPI4_RET_REBOOT 2
#define PPI4_RET_OS_VENDOR_SPECIFIC 3
/* Function 5 */
#define PPI5_RET_SUCCESS 0
#define PPI5_RET_GENERAL_FAILURE 1
/* Function 6 */
#define PPI6_RET_NOT_IMPLEMENTED 3
/* Function 7 */
#define PPI7_RET_SUCCESS 0
#define PPI7_RET_NOT_IMPLEMENTED 1
#define PPI7_RET_GENERAL_FAILURE 2
#define PPI7_RET_BLOCKED_BY_FIRMWARE 3
/* Function 8 */
#define PPI8_RET_NOT_IMPLEMENTED 0
#define PPI8_RET_FIRMWARE_ONLY 1
#define PPI8_RET_BLOCKED_FOR_OS_BY_FW 2
#define PPI8_RET_ALLOWED_WITH_PP 3
#define PPI8_RET_ALLOWED 4
/* TCG Physical Presence Interface */
#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653"
/* TCG Memory Clear Interface */
#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d"
#endif /* _TPM_PPI_H_ */

23
src/include/cbfs.h
View File

@@ -3,10 +3,10 @@
#ifndef _CBFS_H_
#define _CBFS_H_
#include <cbmem.h>
#include <commonlib/cbfs.h>
#include <program_loading.h>
#include <stddef.h>
#include <stdint.h>
#include <types.h>
/***********************************************
* Perform CBFS operations on the boot device. *
@@ -42,8 +42,21 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset,
/* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */
int cbfs_prog_stage_load(struct prog *prog);
/* Returns the region device of the currently active CBFS.
Return < 0 on error, 0 on success. */
int cbfs_boot_region_device(struct region_device *rdev);
struct cbfs_boot_device {
struct region_device rdev;
void *mcache;
size_t mcache_size;
};
/* Helper to fill out |mcache| and |mcache_size| in a cbfs_boot_device. */
void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id);
/*
* Retrieves the currently active CBFS boot device. If |force_ro| is set, will
* always return the read-only CBFS instead (this only makes a difference when
* CONFIG(VBOOT) is enabled). May perform certain CBFS initialization tasks.
* Returns NULL on error (e.g. boot device IO error).
*/
const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro);
#endif

28
src/include/device/pci_ids.h
View File

@@ -301,11 +301,13 @@
#define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536
#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566
#define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0
#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630
#define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419
#define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423
#define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577
#define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567
#define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1
#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631
#define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D
#define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380
@@ -454,13 +456,17 @@
#define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 0x1633
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2 0x1634
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635
#define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2
#define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA
@@ -468,6 +474,22 @@
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0 0x1448
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1 0x1449
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2 0x144A
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3 0x144B
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4 0x144C
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3 0x166D
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4 0x166E
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5 0x166F
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6 0x1670
#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7 0x1671
#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901
#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904
#define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916
@@ -476,9 +498,15 @@
#define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B
#define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458
#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641
#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644
#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8
#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU 0x1636
#define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU 0x164C
#define PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU 0x1638
#define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0 0x15DE
#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_HDA0 0x1637
#define PCI_VENDOR_ID_VLSI 0x1004
#define PCI_DEVICE_ID_VLSI_82C592 0x0005

3
src/include/memlayout.h
View File

@@ -71,6 +71,9 @@
_ = ASSERT(sz >= FMAP_SIZE, \
STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE)));
#define CBFS_MCACHE(addr, sz) \
REGION(cbfs_mcache, addr, sz, 4)
#if ENV_ROMSTAGE_OR_BEFORE
#define PRERAM_CBFS_CACHE(addr, size) \
REGION(preram_cbfs_cache, addr, size, 4) \

1
src/include/smbios.h
View File

@@ -40,6 +40,7 @@ const char *smbios_system_sku(void);
unsigned int smbios_cpu_get_max_speed_mhz(void);
unsigned int smbios_cpu_get_current_speed_mhz(void);
unsigned int smbios_cpu_get_voltage(void);
const char *smbios_mainboard_manufacturer(void);
const char *smbios_mainboard_product_name(void);

1
src/include/symbols.h
View File

@@ -33,6 +33,7 @@ DECLARE_REGION(stack)
DECLARE_REGION(preram_cbfs_cache)
DECLARE_REGION(postram_cbfs_cache)
DECLARE_REGION(cbfs_cache)
DECLARE_REGION(cbfs_mcache)
DECLARE_REGION(fmap_cache)
DECLARE_REGION(tpm_tcpa_log)

21
src/lib/Kconfig
View File

@@ -80,3 +80,24 @@ config ESPI_DEBUG
help
This option enables eSPI library helper functions for displaying debug
information.
config NO_CBFS_MCACHE
bool
default y
help
Disables the CBFS metadata cache. This means that your platform does
not need to provide a CBFS_MCACHE section in memlayout and can save
the associated CAR/SRAM size. In that case every single CBFS file
lookup must re-read the same CBFS directory entries from flash to find
the respective file.
config CBFS_MCACHE_RW_PERCENTAGE
int
depends on VBOOT && !NO_CBFS_MCACHE
default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only
default 50
help
The amount of the CBFS_MCACHE area that's used for the RW CBFS, in
percent from 0 to 100. The remaining area will be used for the RO
CBFS. Default is an even 50/50 split. When VBOOT is disabled, this
will automatically be 0 (meaning the whole MCACHE is used for RO).

112
src/lib/cbfs.c
View File

@@ -3,6 +3,7 @@
#include <assert.h>
#include <boot_device.h>
#include <cbfs.h>
#include <cbmem.h>
#include <commonlib/bsd/cbfs_private.h>
#include <commonlib/bsd/compression.h>
#include <commonlib/endian.h>
@@ -16,22 +17,33 @@
#include <symbols.h>
#include <timestamp.h>
static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd,
const char *name, union cbfs_mdata *mdata, size_t *data_offset)
{
cb_err_t err = CB_CBFS_CACHE_FULL;
if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM)
err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size,
name, mdata, data_offset);
if (err == CB_CBFS_CACHE_FULL)
err = cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL);
return err;
}
int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
{
struct region_device rdev;
if (cbfs_boot_region_device(&rdev))
const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false);
if (!cbd)
return -1;
size_t data_offset;
cb_err_t err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL);
cb_err_t err = cbfs_boot_lookup(cbd, name, &fh->mdata, &data_offset);
if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) {
printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n",
name);
if (fmap_locate_area_as_rdev("COREBOOT", &rdev))
if (!(cbd = cbfs_get_boot_device(true)))
return -1;
err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL);
err = cbfs_boot_lookup(cbd, name, &fh->mdata, &data_offset);
}
if (err)
return -1;
@@ -39,7 +51,8 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type)
size_t msize = be32toh(fh->mdata.h.offset);
if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev,
(uintptr_t)&fh->mdata, msize) ||
rdev_chain(&fh->data, &rdev, data_offset, be32toh(fh->mdata.h.len)))
rdev_chain(&fh->data, &cbd->rdev, data_offset,
be32toh(fh->mdata.h.len)))
return -1;
if (type) {
if (!*type)
@@ -333,9 +346,86 @@ out:
return 0;
}
int cbfs_boot_region_device(struct region_device *rdev)
void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id)
{
boot_device_init();
return vboot_locate_cbfs(rdev) &&
fmap_locate_area_as_rdev("COREBOOT", rdev);
if (CONFIG(NO_CBFS_MCACHE) || ENV_SMM)
return;
const struct cbmem_entry *entry;
if (cbmem_possibly_online() &&
(entry = cbmem_entry_find(id))) {
cbd->mcache = cbmem_entry_start(entry);
cbd->mcache_size = cbmem_entry_size(entry);
} else if (ENV_ROMSTAGE_OR_BEFORE) {
u8 *boundary = _ecbfs_mcache - REGION_SIZE(cbfs_mcache) *
CONFIG_CBFS_MCACHE_RW_PERCENTAGE / 100;
boundary = (u8 *)ALIGN_DOWN((uintptr_t)boundary,
CBFS_MCACHE_ALIGNMENT);
if (id == CBMEM_ID_CBFS_RO_MCACHE) {
cbd->mcache = _cbfs_mcache;
cbd->mcache_size = boundary - _cbfs_mcache;
} else if (id == CBMEM_ID_CBFS_RW_MCACHE) {
cbd->mcache = boundary;
cbd->mcache_size = _ecbfs_mcache - boundary;
}
}
}
const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro)
{
static struct cbfs_boot_device ro;
/* Ensure we always init RO mcache, even if first file is from RW.
Otherwise it may not be available when needed in later stages. */
if (ENV_INITIAL_STAGE && !force_ro && !region_device_sz(&ro.rdev))
cbfs_get_boot_device(true);
if (!force_ro) {
const struct cbfs_boot_device *rw = vboot_get_cbfs_boot_device();
/* This will return NULL if vboot isn't enabled, didn't run yet
or decided to boot into recovery mode. */
if (rw)
return rw;
}
if (region_device_sz(&ro.rdev))
return &ro;
if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev))
return NULL;
cbfs_boot_device_find_mcache(&ro, CBMEM_ID_CBFS_RO_MCACHE);
if (ENV_INITIAL_STAGE && !CONFIG(NO_CBFS_MCACHE)) {
cb_err_t err = cbfs_mcache_build(&ro.rdev, ro.mcache,
ro.mcache_size, NULL);
if (err && err != CB_CBFS_CACHE_FULL)
die("Failed to build RO mcache");
}
return &ro;
}
#if !CONFIG(NO_CBFS_MCACHE)
static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id)
{
if (!cbd)
return;
size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size);
void *cbmem_mcache = cbmem_add(cbmem_id, real_size);
if (!cbmem_mcache) {
printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n",
cbmem_id, real_size);
return;
}
memcpy(cbmem_mcache, cbd->mcache, real_size);
}
static void cbfs_mcache_migrate(int unused)
{
mcache_to_cbmem(vboot_get_cbfs_boot_device(), CBMEM_ID_CBFS_RW_MCACHE);
mcache_to_cbmem(cbfs_get_boot_device(true), CBMEM_ID_CBFS_RO_MCACHE);
}
ROMSTAGE_CBMEM_INIT_HOOK(cbfs_mcache_migrate)
#endif

11
src/lib/coreboot_table.c
View File

@@ -220,11 +220,8 @@ static void lb_boot_media_params(struct lb_header *header)
{
struct lb_boot_media_params *bmp;
const struct region_device *boot_dev;
struct region_device cbfs_dev;
boot_device_init();
if (cbfs_boot_region_device(&cbfs_dev))
const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false);
if (!cbd)
return;
boot_dev = boot_device_ro();
@@ -235,8 +232,8 @@ static void lb_boot_media_params(struct lb_header *header)
bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS;
bmp->size = sizeof(*bmp);
bmp->cbfs_offset = region_device_offset(&cbfs_dev);
bmp->cbfs_size = region_device_sz(&cbfs_dev);
bmp->cbfs_offset = region_device_offset(&cbd->rdev);
bmp->cbfs_size = region_device_sz(&cbd->rdev);
bmp->boot_media_size = region_device_sz(boot_dev);
bmp->fmap_offset = get_fmap_flash_offset();

85
src/mainboard/acer/g43t-am3/cmos.layout
View File

@@ -4,68 +4,67 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
# coreboot config options: cpu
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
432 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
10 0 AHCI
10 1 Compatible
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
10 0 AHCI
10 1 Compatible
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
# -----------------------------------------------------------------
checksums

81
src/mainboard/amd/inagua/cmos.layout
View File

@@ -5,52 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

79
src/mainboard/amd/olivehill/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

79
src/mainboard/amd/parmer/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

81
src/mainboard/amd/persimmon/cmos.layout
View File

@@ -5,52 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

81
src/mainboard/amd/south_station/cmos.layout
View File

@@ -5,52 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

79
src/mainboard/amd/thatcher/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

81
src/mainboard/amd/union_station/cmos.layout
View File

@@ -5,52 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

120
src/mainboard/apple/macbook21/cmos.layout
View File

@@ -4,102 +4,76 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: cpu
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
#409 2 e 7 power_on_after_fail
408 1 e 1 nmi
#409 2 e 7 power_on_after_fail
# coreboot config options: northbridge
411 3 e 11 gfx_uma_size
411 3 e 11 gfx_uma_size
# coreboot config options: bootloader
416 512 s 0 boot_devices
928 8 h 0 boot_default
936 1 e 8 cmos_defaults_loaded
937 1 e 1 lpt
#938 46 r 0 unused
416 512 s 0 boot_devices
928 8 h 0 boot_default
936 1 e 8 cmos_defaults_loaded
937 1 e 1 lpt
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
984 16 h 0 check_sum
# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 No
8 1 Yes
9 0 Secondary
9 1 Primary
11 0 1M
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
8 0 No
8 1 Yes
9 0 Secondary
9 1 Primary
11 0 1M
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
# -----------------------------------------------------------------
checksums

88
src/mainboard/apple/macbookair4_2/cmos.layout
View File

@@ -3,73 +3,49 @@
# -----------------------------------------------------------------
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
#400 8 r 0 reserved for century byte
395 4 e 6 debug_level
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: cpu
#424 8 r 0 unused
# coreboot config options: northbridge
#432 5 e 11 gfx_uma_size
#437 3 r 0 unused
#440 8 h 0 volume
#432 5 e 11 gfx_uma_size
#440 8 h 0 volume
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums
checksum 392 447 984

2
src/mainboard/asrock/b85m_pro4/cmos.layout
View File

@@ -14,7 +14,6 @@
984 16 h 0 check_sum
# -----------------------------------------------------------------
# -----------------------------------------------------------------
enumerations
# -----------------------------------------------------------------
@@ -41,7 +40,6 @@
5 2 Keep
# -----------------------------------------------------------------
# -----------------------------------------------------------------
checksums
# -----------------------------------------------------------------

87
src/mainboard/asrock/e350m1/cmos.layout
View File

@@ -5,55 +5,52 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 2 e 3 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 2 e 3 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
3 0 Off
3 1 On
3 2 Last
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
3 0 Off
3 1 On
3 2 Last
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

93
src/mainboard/asrock/g41c-gs/cmos.layout
View File

@@ -4,84 +4,59 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 5 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: cpu
#425 7 r 0 unused
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
#435 549 r 0 unused
432 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
# -----------------------------------------------------------------
checksums

109
src/mainboard/asrock/h110m/cmos.layout
View File

@@ -3,108 +3,61 @@
# -----------------------------------------------------------------
entries
#start-bit length config config-ID name
#0 8 r 0 seconds
#8 8 r 0 alarm_seconds
#16 8 r 0 minutes
#24 8 r 0 alarm_minutes
#32 8 r 0 hours
#40 8 r 0 alarm_hours
#48 8 r 0 day_of_week
#56 8 r 0 day_of_month
#64 8 r 0 month
#72 8 r 0 year
# -----------------------------------------------------------------
# Status Register A
#80 4 r 0 rate_select
#84 3 r 0 REF_Clock
#87 1 r 0 UIP
# -----------------------------------------------------------------
# Status Register B
#88 1 r 0 auto_switch_DST
#89 1 r 0 24_hour_mode
#90 1 r 0 binary_values_enable
#91 1 r 0 square-wave_out_enable
#92 1 r 0 update_finished_enable
#93 1 r 0 alarm_interrupt_enable
#94 1 r 0 periodic_interrupt_enable
#95 1 r 0 disable_clock_updates
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
#start-bit length config config-ID name
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: cpu
400 1 e 2 hyper_threading
#401 7 r 0 unused
400 1 e 2 hyper_threading
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 5 r 0 unused
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
#544 440 r 0 unused
416 128 r 0 vbnv
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
# -----------------------------------------------------------------
checksums

76
src/mainboard/asrock/h81m-hds/cmos.layout
View File

@@ -4,75 +4,53 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 3 boot_option
388 4 h 0 reboot_counter
384 1 e 3 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 4 debug_level
#399 1 r 0 unused
395 4 e 4 debug_level
#400 8 r 0 reserved for century byte
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
2 0 Enable
2 1 Disable
3 0 Fallback
3 1 Normal
3 0 Fallback
3 1 Normal
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
5 0 Disable
5 1 Enable
5 2 Keep
5 0 Disable
5 1 Enable
5 2 Keep
# -----------------------------------------------------------------
checksums

79
src/mainboard/asrock/imb-a180/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

89
src/mainboard/asus/a88xm-e/cmos.layout
View File

@@ -2,55 +2,54 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
#456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
#456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

71
src/mainboard/asus/am1i-a/cmos.layout
View File

@@ -5,46 +5,45 @@
entries
#start-bit length config config-ID name
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 r 0 reboot_counter
#392 3 r 0 unused
#400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 r 0 boot_index
432 8 r 0 boot_countdown
440 8 e 10 sata_mode
448 8 e 11 sata_speed
#728 256 h 0 user_data
984 16 h 0 check_sum
#start-bit length config config-ID name
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 r 0 reboot_counter
#400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
420 4 e 7 boot_second
424 4 e 7 boot_third
428 4 r 0 boot_index
432 8 r 0 boot_countdown
440 8 e 10 sata_mode
448 8 e 11 sata_speed
#728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
#1 0 Disable
#1 1 Enable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
10 0 IDE
10 2 AHCI
11 1 3Gbps
11 0 6Gbps
#ID value text
#1 0 Disable
#1 1 Enable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Network
7 1 HDD
7 2 Floppy
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
10 0 IDE
10 2 AHCI
11 1 3Gbps
11 0 6Gbps
checksums

79
src/mainboard/asus/f2a85-m/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

97
src/mainboard/asus/h61m-cs/cmos.layout
View File

@@ -4,88 +4,61 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 10 r 0 unused
421 1 e 9 sata_mode
#422 2 r 0 unused
421 1 e 9 sata_mode
# coreboot config options: cpu
#425 7 r 0 unused
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
#435 549 r 0 unused
432 3 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 IDE
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 IDE
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums

104
src/mainboard/asus/maximus_iv_gene-z/cmos.layout
View File

@@ -4,95 +4,73 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 3 boot_option
388 4 h 0 reboot_counter
384 1 e 3 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 4 debug_level
#399 1 r 0 unused
395 4 e 4 debug_level
#400 8 r 0 reserved for century byte
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
411 1 e 6 sata_mode
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
411 1 e 6 sata_mode
# coreboot config options: northbridge
412 3 e 7 gfx_uma_size
412 3 e 7 gfx_uma_size
# SandyBridge MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
896 32 r 0 mrc_scrambler_seed
928 32 r 0 mrc_scrambler_seed_s3
960 16 r 0 mrc_scrambler_seed_chk
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
2 0 Enable
2 1 Disable
3 0 Fallback
3 1 Normal
3 0 Fallback
3 1 Normal
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
5 0 Disable
5 1 Enable
5 2 Keep
5 0 Disable
5 1 Enable
5 2 Keep
6 0 AHCI
6 1 Compatible
6 0 AHCI
6 1 Compatible
7 0 32M
7 1 64M
7 2 96M
7 3 128M
7 4 160M
7 5 192M
7 6 224M
7 0 32M
7 1 64M
7 2 96M
7 3 128M
7 4 160M
7 5 192M
7 6 224M
# -----------------------------------------------------------------
checksums

79
src/mainboard/asus/p5gc-mx/cmos.layout
View File

@@ -2,72 +2,65 @@
# -----------------------------------------------------------------
entries
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: cpu
#401 7 r 0 unused
# coreboot config options: southbridge
408 1 e 1 nmi
408 1 e 1 nmi
# coreboot config options: northbridge
411 3 e 11 gfx_uma_size
411 3 e 11 gfx_uma_size
# coreboot config options: bootloader
416 512 s 0 boot_devices
#928 80 r 0 unused
416 512 s 0 boot_devices
# coreboot config options: check sums
984 16 h 0 check_sum
#1000 24 r 0 amd_reserved
984 16 h 0 check_sum
# RAM initialization internal data
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
1024 8 r 0 C0WL0REOST
1032 8 r 0 C1WL0REOST
1040 8 r 0 RCVENMT
1048 4 r 0 C0DRT1
1052 4 r 0 C1DRT1
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
11 0 1M
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
11 0 1M
11 1 4M
11 2 8M
11 3 16M
11 4 32M
11 5 48M
11 6 64M
# -----------------------------------------------------------------
checksums

81
src/mainboard/asus/p5qc/cmos.layout
View File

@@ -4,77 +4,54 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 5 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
408 1 e 10 sata_mode
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
# coreboot config options: cpu
#424 8 r 0 unused
# coreboot config options: northbridge
#432 554 r 0 unused
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
10 0 AHCI
10 1 Compatible
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
10 0 AHCI
10 1 Compatible
# -----------------------------------------------------------------
checksums

73
src/mainboard/asus/p5ql-em/cmos.layout
View File

@@ -4,64 +4,59 @@
entries
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 5 r 0 unused
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
395 4 e 6 debug_level
# coreboot config options: southbridge
#408 1 e 0 unused
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
409 2 e 7 power_on_after_fail
411 1 e 1 nmi
# coreboot config options: cpu
#424 8 r 0 unused
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
#436 548 r 0 unused
432 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
# -----------------------------------------------------------------
checksums

93
src/mainboard/asus/p5qpl-am/cmos.layout
View File

@@ -4,84 +4,59 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 5 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
# coreboot config options: cpu
#424 8 r 0 unused
# coreboot config options: northbridge
432 4 e 11 gfx_uma_size
#435 549 r 0 unused
432 4 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 1 Emergency
6 2 Alert
6 3 Critical
6 4 Error
6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
7 0 Disable
7 1 Enable
7 2 Keep
11 6 64M
11 7 128M
11 8 256M
11 9 96M
11 10 160M
11 11 224M
11 12 352M
# -----------------------------------------------------------------
checksums

98
src/mainboard/asus/p8h61-m_lx/cmos.layout
View File

@@ -4,90 +4,68 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 3 boot_option
388 4 h 0 reboot_counter
384 1 e 3 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 4 debug_level
#399 1 r 0 unused
395 4 e 4 debug_level
#400 8 r 0 reserved for century byte
#400 8 r 0 reserved for century byte
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
411 1 e 6 sata_mode
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
411 1 e 6 sata_mode
# coreboot config options: northbridge
412 3 e 7 gfx_uma_size
412 3 e 7 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
2 0 Enable
2 1 Disable
3 0 Fallback
3 1 Normal
3 0 Fallback
3 1 Normal
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
5 0 Disable
5 1 Enable
5 2 Keep
5 0 Disable
5 1 Enable
5 2 Keep
6 0 AHCI
6 1 Compatible
6 0 AHCI
6 1 Compatible
7 0 32M
7 1 64M
7 2 96M
7 3 128M
7 4 160M
7 5 192M
7 6 224M
7 0 32M
7 1 64M
7 2 96M
7 3 128M
7 4 160M
7 5 192M
7 6 224M
# -----------------------------------------------------------------
checksums

97
src/mainboard/asus/p8h61-m_pro/cmos.layout
View File

@@ -4,88 +4,61 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#390 2 r 0 unused?
384 1 e 4 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 6 debug_level
#399 1 r 0 unused
395 4 e 6 debug_level
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
#411 10 r 0 unused
421 1 e 9 sata_mode
#422 2 r 0 unused
421 1 e 9 sata_mode
# coreboot config options: cpu
#425 7 r 0 unused
# coreboot config options: northbridge
432 3 e 11 gfx_uma_size
#435 549 r 0 unused
432 3 e 11 gfx_uma_size
# coreboot config options: check sums
984 16 h 0 check_sum
984 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 IDE
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
#ID value text
1 0 Disable
1 1 Enable
4 0 Fallback
4 1 Normal
6 0 Emergency
6 1 Alert
6 2 Critical
6 3 Error
6 4 Warning
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
7 0 Disable
7 1 Enable
7 2 Keep
9 0 AHCI
9 1 IDE
11 0 32M
11 1 64M
11 2 96M
11 3 128M
11 4 160M
11 5 192M
11 6 224M
# -----------------------------------------------------------------
checksums

168
src/mainboard/asus/p8z77-m_pro/cmos.layout
View File

@@ -4,49 +4,27 @@
entries
# -----------------------------------------------------------------
# Status Register A
# -----------------------------------------------------------------
# Status Register B
# -----------------------------------------------------------------
# Status Register C
#96 4 r 0 status_c_rsvd
#100 1 r 0 uf_flag
#101 1 r 0 af_flag
#102 1 r 0 pf_flag
#103 1 r 0 irqf_flag
# -----------------------------------------------------------------
# Status Register D
#104 7 r 0 status_d_rsvd
#111 1 r 0 valid_cmos_ram
# -----------------------------------------------------------------
# Diagnostic Status Register
#112 8 r 0 diag_rsvd1
# -----------------------------------------------------------------
0 120 r 0 reserved_memory
#120 264 r 0 unused
0 120 r 0 reserved_memory
# -----------------------------------------------------------------
# RTC_BOOT_BYTE (coreboot hardcoded)
384 1 e 3 boot_option
388 4 h 0 reboot_counter
384 1 e 3 boot_option
388 4 h 0 reboot_counter
# -----------------------------------------------------------------
# coreboot config options: console
#392 3 r 0 unused
395 4 e 4 debug_level
#399 1 r 0 unused
#400 8 r 0 reserved for century byte
395 4 e 4 debug_level
#400 8 r 0 reserved for century byte
# -----------------------------------------------------------------
# coreboot config options: southbridge
# Non Maskable Interrupt(NMI) support, which is an interrupt that may
# occur on a RAM or unrecoverable error.
408 1 e 1 nmi
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
411 1 e 6 sata_mode
409 2 e 5 power_on_after_fail
411 1 e 6 sata_mode
# -----------------------------------------------------------------
# coreboot config options: northbridge
@@ -54,119 +32,119 @@ entries
# gfx_uma_size
# Quantity of shared video memory the IGP can use
#
416 5 e 7 gfx_uma_size
416 5 e 7 gfx_uma_size
# -----------------------------------------------------------------
# coreboot config options: usb3
# usb3_mode
# Controls how the motherboard's USB3 ports act at boot time
421 2 e 8 usb3_mode
421 2 e 8 usb3_mode
# usb3_drv
# Load (or not) pre-OS xHCI USB3 BIOS driver
#
423 1 e 1 usb3_drv
423 1 e 1 usb3_drv
# usb3_streams
# Streams can provide more speed (as they can use 64Kb packets),
# but they might cause incompatibilities with some devices.
#
424 1 e 1 usb3_streams
424 1 e 1 usb3_streams
# -----------------------------------------------------------------
# Sandy/Ivy Bridge MRC Scrambler Seed values
# note: MUST NOT be covered by checksum!
464 32 r 0 mrc_scrambler_seed
496 32 r 0 mrc_scrambler_seed_s3
528 16 r 0 mrc_scrambler_seed_chk
464 32 r 0 mrc_scrambler_seed
496 32 r 0 mrc_scrambler_seed_s3
528 16 r 0 mrc_scrambler_seed_chk
# -----------------------------------------------------------------
# coreboot config options: check sums
544 16 h 0 check_sum
544 16 h 0 check_sum
# -----------------------------------------------------------------
enumerations
#ID value text
#ID value text
# Generic on/off enum
1 0 Disable
1 1 Enable
1 0 Disable
1 1 Enable
# boot_option
3 0 Fallback
3 1 Normal
3 0 Fallback
3 1 Normal
# debug_level
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
4 0 Emergency
4 1 Alert
4 2 Critical
4 3 Error
4 4 Warning
4 5 Notice
4 6 Info
4 7 Debug
4 8 Spew
# power_on_after_fail
5 0 Disable
5 1 Enable
5 2 Keep
5 0 Disable
5 1 Enable
5 2 Keep
# sata_mode
6 0 AHCI
6 1 Compatible
6 0 AHCI
6 1 Compatible
# gfx_uma_size (Intel IGP Video RAM size)
7 0 32M
7 1 64M
7 2 96M
7 3 128M
7 4 160M
7 5 192M
7 6 224M
7 7 256M
7 8 288M
7 9 320M
7 10 352M
7 11 384M
7 12 416M
7 13 448M
7 14 480M
7 15 512M
7 16 544M
7 17 576M
7 18 608M
7 19 640M
7 20 672M
7 21 704M
7 22 736M
7 23 768M
7 24 800M
7 25 832M
7 26 864M
7 27 896M
7 28 928M
7 29 960M
7 30 992M
7 0 32M
7 1 64M
7 2 96M
7 3 128M
7 4 160M
7 5 192M
7 6 224M
7 7 256M
7 8 288M
7 9 320M
7 10 352M
7 11 384M
7 12 416M
7 13 448M
7 14 480M
7 15 512M
7 16 544M
7 17 576M
7 18 608M
7 19 640M
7 20 672M
7 21 704M
7 22 736M
7 23 768M
7 24 800M
7 25 832M
7 26 864M
7 27 896M
7 28 928M
7 29 960M
7 30 992M
# usb3_mode
# Disable = Use the port always as USB 2.0 for compatibility
# Enable = Use the port always as USB 3.0 for speed
# Auto = Initialize the port as USB 2.0, until the OS loads
# xHCI USB 3.0 driver
# xHCI USB 3.0 driver
# SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver
# and the computer is reset, keep the USB 3.0 mode.
# and the computer is reset, keep the USB 3.0 mode.
#
8 0 Disable
8 1 Enable
8 2 Auto
8 3 SmartAuto
8 0 Disable
8 1 Enable
8 2 Auto
8 3 SmartAuto
# -----------------------------------------------------------------
# <startBit[must be byte-aligned]> <endBit[must be byte aligned]>
# <bit where to start storing checksum[must be 16bits-aligned]>
# <bit where to start storing checksum[must be 16bits-aligned]>
checksums
checksum 392 431 544

79
src/mainboard/bap/ode_e20XX/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

79
src/mainboard/biostar/a68n_5200/cmos.layout
View File

@@ -5,50 +5,49 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
399 1 e 2 multi_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
440 4 e 9 slow_cpu
444 1 e 1 nmi
445 1 e 1 iommu
456 1 e 1 ECC_memory
728 256 h 0 user_data
984 16 h 0 check_sum
# Reserve the extended AMD configuration registers
1000 24 r 0 amd_reserved
1000 24 r 0 amd_reserved
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 5 Notice
6 6 Info
6 7 Debug
6 8 Spew
8 0 400Mhz
8 1 333Mhz
8 2 266Mhz
8 3 200Mhz
9 0 off
9 1 87.5%
9 2 75.0%
9 3 62.5%
9 4 50.0%
9 5 37.5%
9 6 25.0%
9 7 12.5%
checksums

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