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soc/intel/tigerlake: Add TGL-H power limits

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Change-Id: I6fa7c7338b3157b29ff72769238597e3c528aedb
This commit is contained in:
Jeremy Soller
2021-06-17 13:27:33 -06:00
committed by Tim Crawford
parent e5fbcd5c8e
commit d2fc13e494
2 changed files with 9 additions and 1 deletions
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4
src/soc/intel/tigerlake/chip.h
View File

@@ -27,7 +27,9 @@
#define POWER_LIMITS_U_4_CORE 1
#define POWER_LIMITS_Y_2_CORE 2
#define POWER_LIMITS_Y_4_CORE 3
#define POWER_LIMITS_MAX 4
#define POWER_LIMITS_H_6_CORE 4
#define POWER_LIMITS_H_8_CORE 5
#define POWER_LIMITS_MAX 6
/*
* Enable External V1P05 Rail in: BIT0:S0i1/S0i2,

6
src/soc/intel/tigerlake/systemagent.c
View File

@@ -90,6 +90,12 @@ void soc_systemagent_init(struct device *dev)
case PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2:
soc_config = &config->power_limits_config[POWER_LIMITS_Y_4_CORE];
break;
case PCI_DEVICE_ID_INTEL_TGL_ID_H_6_1:
soc_config = &config->power_limits_config[POWER_LIMITS_H_6_CORE];
break;
case PCI_DEVICE_ID_INTEL_TGL_ID_H_8_1:
soc_config = &config->power_limits_config[POWER_LIMITS_H_8_CORE];
break;
default:
printk(BIOS_ERR, "TGL: unknown SA ID: 0x%4x, skipping power limits "
"configuration\n", sa_pci_id);