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cpu/x86/mtrr: Error out caching limitation during NEM

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Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.

Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.

BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).

Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This commit is contained in:
Subrata Banik 2024-03-18 17:10:57 +05:30 committed by Jeremy Soller
parent 9dad323baf
commit d462108ba8
1 changed files with 3 additions and 0 deletions
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3
src/cpu/x86/mtrr/earlymtrr.c
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@ -37,6 +37,9 @@ void set_var_mtrr(
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM)
printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n",
type);
if (!IS_POWER_OF_2(size))
printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size);
if (size < 4 * KiB)