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soc/intel/common: Bring DISPLAY_MTRRS into the light

Browse Source 
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.

To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.

If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.

Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2018-11-13 19:28:07 +01:00
committed by Patrick Georgi
parent 3032d76778
commit d67edcae6e
27 changed files with 105 additions and 167 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/Intel/Board/Galileo_checklist.html
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@@ -79,8 +79,6 @@
<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>

2
Documentation/Intel/SoC/soc.html
View File

@@ -234,8 +234,6 @@ Use the following steps to locate the FSP binary:
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
</li>
<li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
specifically building
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
</li>
</ol>
</li>

5
src/Kconfig
View File

@@ -670,6 +670,11 @@ source "payloads/Kconfig"
menu "Debugging"
comment "CPU Debug Settings"
source "src/cpu/*/Kconfig.debug"
comment "General Debug Settings"
# TODO: Better help text and detailed instructions.
config GDB_STUB
bool "GDB debugging support"

6
src/arch/x86/postcar.c
View File

@@ -16,9 +16,9 @@
#include <arch/cpu.h>
#include <cbmem.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <main_decl.h>
#include <program_loading.h>
#include <soc/intel/common/util.h>
/*
* Systems without a native coreboot cache-as-ram teardown may implement
@@ -35,9 +35,7 @@ void main(void)
/* Recover cbmem so infrastruture using it is functional. */
cbmem_initialize();
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
/* Load and run ramstage. */
run_ramstage();

6
src/cpu/x86/Kconfig.debug Normal file
View File

@@ -0,0 +1,6 @@
config HAVE_DISPLAY_MTRRS
bool
config DISPLAY_MTRRS
bool "Display intermediate MTRR settings"
depends on HAVE_DISPLAY_MTRRS

6
src/cpu/x86/mtrr/Makefile.inc
View File

@@ -1,3 +1,9 @@
ramstage-y += mtrr.c
romstage-y += earlymtrr.c
bootblock-y += earlymtrr.c
bootblock-y += debug.c
romstage-y += debug.c
postcar-y += debug.c
ramstage-y += debug.c

114
src/soc/intel/common/util.c → src/cpu/x86/mtrr/debug.c
View File

@@ -16,23 +16,9 @@
#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/mtrr.h>
#include <soc/intel/common/util.h>
#include <stddef.h>
#include <stdint.h>
uint32_t soc_get_variable_mtrr_count(uint64_t *msr)
{
union {
uint64_t u64;
msr_t s;
} mtrrcap;
mtrrcap.s = rdmsr(MTRR_CAP_MSR);
if (msr != NULL)
*msr = mtrrcap.u64;
return mtrrcap.u64 & MTRR_CAP_VCNT;
}
static const char *soc_display_mtrr_type(uint32_t type)
static const char *display_mtrr_type(uint32_t type)
{
switch (type) {
default: return "reserved";
@@ -45,7 +31,7 @@ static const char *soc_display_mtrr_type(uint32_t type)
}
}
static void soc_display_mtrr_fixed_types(uint64_t msr,
static void display_mtrr_fixed_types(uint64_t msr,
uint32_t starting_address, uint32_t memory_size)
{
uint32_t base_address;
@@ -64,7 +50,7 @@ static void soc_display_mtrr_fixed_types(uint64_t msr,
if (next_type != type) {
printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n",
base_address, next_address - 1,
soc_display_mtrr_type(type));
display_mtrr_type(type));
base_address = next_address;
type = next_type;
}
@@ -72,10 +58,10 @@ static void soc_display_mtrr_fixed_types(uint64_t msr,
if (base_address != next_address)
printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n",
base_address, next_address - 1,
soc_display_mtrr_type(type));
display_mtrr_type(type));
}
static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
static void display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
const char *name)
{
union {
@@ -85,10 +71,10 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
msr.s = rdmsr(msr_reg);
printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000);
display_mtrr_fixed_types(msr.u64, starting_address, 0x1000);
}
static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
static void display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
const char *name)
{
union {
@@ -98,10 +84,10 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
msr.s = rdmsr(msr_reg);
printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000);
display_mtrr_fixed_types(msr.u64, starting_address, 0x4000);
}
static void soc_display_64k_mtrr(void)
static void display_64k_mtrr(void)
{
union {
uint64_t u64;
@@ -110,26 +96,24 @@ static void soc_display_64k_mtrr(void)
msr.s = rdmsr(MTRR_FIX_64K_00000);
printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64);
soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000);
display_mtrr_fixed_types(msr.u64, 0, 0x10000);
}
static uint32_t soc_display_mtrrcap(void)
static void display_mtrrcap(void)
{
uint64_t msr;
uint32_t variable_mtrrs;
msr_t msr;
variable_mtrrs = soc_get_variable_mtrr_count(&msr);
msr = rdmsr(MTRR_CAP_MSR);
printk(BIOS_DEBUG,
"0x%016llx: IA32_MTRRCAP: %s%s%s%d variable MTRRs\n",
msr,
(msr & MTRR_CAP_SMRR) ? "SMRR, " : "",
(msr & MTRR_CAP_WC) ? "WC, " : "",
(msr & MTRR_CAP_FIX) ? "FIX, " : "",
variable_mtrrs);
return variable_mtrrs;
"0x%08x%08x: IA32_MTRRCAP: %s%s%s%u variable MTRRs\n",
msr.hi, msr.lo,
(msr.lo & MTRR_CAP_SMRR) ? "SMRR, " : "",
(msr.lo & MTRR_CAP_WC) ? "WC, " : "",
(msr.lo & MTRR_CAP_FIX) ? "FIX, " : "",
msr.lo & MTRR_CAP_VCNT);
}
static void soc_display_mtrr_def_type(void)
static void display_mtrr_def_type(void)
{
union {
uint64_t u64;
@@ -141,13 +125,13 @@ static void soc_display_mtrr_def_type(void)
msr.u64,
(msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "",
(msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "",
soc_display_mtrr_type((uint32_t)(msr.u64 &
display_mtrr_type((uint32_t)(msr.u64 &
MTRR_DEF_TYPE_MASK)));
}
static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
uint64_t address_mask)
static void display_variable_mtrr(int index, uint64_t address_mask)
{
const uint32_t msr_reg = MTRR_PHYS_BASE(index);
uint64_t base_address;
uint64_t length;
uint64_t mask;
@@ -168,7 +152,7 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
printk(BIOS_DEBUG,
"0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n",
msr_a.u64, index, base_address,
soc_display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK));
display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK));
mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask;
length = (~mask & address_mask) + 1;
printk(BIOS_DEBUG,
@@ -181,44 +165,38 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
}
}
asmlinkage void soc_display_mtrrs(void)
static void _display_mtrrs(void)
{
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) {
uint32_t address_bits;
uint64_t address_mask;
int i;
int variable_mtrrs;
/* Display the fixed MTRRs */
variable_mtrrs = soc_display_mtrrcap();
soc_display_mtrr_def_type();
soc_display_64k_mtrr();
soc_display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000,
"IA32_MTRR_FIX16K_80000");
soc_display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000,
"IA32_MTRR_FIX16K_A0000");
soc_display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000,
"IA32_MTRR_FIX4K_C0000");
soc_display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000,
"IA32_MTRR_FIX4K_C8000");
soc_display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000,
"IA32_MTRR_FIX4K_D0000");
soc_display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000,
"IA32_MTRR_FIX4K_D8000");
soc_display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000,
"IA32_MTRR_FIX4K_E0000");
soc_display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000,
"IA32_MTRR_FIX4K_E8000");
soc_display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000,
"IA32_MTRR_FIX4K_F0000");
soc_display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000,
"IA32_MTRR_FIX4K_F8000");
display_mtrrcap();
display_mtrr_def_type();
display_64k_mtrr();
display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, "IA32_MTRR_FIX16K_80000");
display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, "IA32_MTRR_FIX16K_A0000");
display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, "IA32_MTRR_FIX4K_C0000");
display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, "IA32_MTRR_FIX4K_C8000");
display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, "IA32_MTRR_FIX4K_D0000");
display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, "IA32_MTRR_FIX4K_D8000");
display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, "IA32_MTRR_FIX4K_E0000");
display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, "IA32_MTRR_FIX4K_E8000");
display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, "IA32_MTRR_FIX4K_F0000");
display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, "IA32_MTRR_FIX4K_F8000");
address_bits = cpu_phys_address_size();
address_mask = (1ULL << address_bits) - 1;
/* Display the variable MTRRs */
variable_mtrrs = get_var_mtrr_count();
for (i = 0; i < variable_mtrrs; i++)
soc_display_variable_mtrr(MTRR_PHYS_BASE(i), i,
address_mask);
display_variable_mtrr(i, address_mask);
}
asmlinkage void display_mtrrs(void)
{
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
_display_mtrrs();
}

6
src/cpu/x86/mtrr/earlymtrr.c
View File

@@ -20,13 +20,11 @@
*/
int get_free_var_mtrr(void)
{
msr_t msr, maskm;
msr_t maskm;
int vcnt;
int i;
/* Read MTRRCap and get vcnt - variable memory type ranges. */
msr = rdmsr(MTRR_CAP_MSR);
vcnt = msr.lo & 0xff;
vcnt = get_var_mtrr_count();
/* Identify the first var mtrr which is not valid. */
for (i = 0; i < vcnt; i++) {

2
src/drivers/intel/fsp1_1/after_raminit.S
View File

@@ -66,7 +66,7 @@
1:
#endif
/* Display the MTRRs */
call soc_display_mtrrs
call display_mtrrs
/*
* The stack contents are initialized in src/soc/intel/common/stack.c

4
src/drivers/intel/fsp1_1/car.c
View File

@@ -15,10 +15,10 @@
#include <arch/early_variables.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <fsp/car.h>
#include <fsp/util.h>
#include <program_loading.h>
#include <soc/intel/common/util.h>
#include <timestamp.h>
FSP_INFO_HEADER *fih_car CAR_GLOBAL;
@@ -95,7 +95,7 @@ asmlinkage void after_cache_as_ram(void *chipset_context)
{
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);
printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n");
soc_display_mtrrs();
display_mtrrs();
after_cache_as_ram_stage();
}

1
src/drivers/intel/fsp1_1/include/fsp/ramstage.h
View File

@@ -18,7 +18,6 @@
#define _INTEL_COMMON_RAMSTAGE_H_
#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <stdint.h>
/*

1
src/drivers/intel/fsp1_1/include/fsp/romstage.h
View File

@@ -22,7 +22,6 @@
#include <memory_info.h>
#include <fsp/car.h>
#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <soc/intel/common/mma.h>
#include <soc/pei_wrapper.h>
#include <soc/pm.h> /* chip_power_state */

4
src/drivers/intel/fsp1_1/stack.c
View File

@@ -38,12 +38,12 @@ void *setup_stack_and_mtrrs(void)
uint32_t *slot;
/* Display the MTRRs */
soc_display_mtrrs();
display_mtrrs();
/* Top of stack needs to be aligned to a 8-byte boundary. */
slot = (void *)romstage_ram_stack_top();
num_mtrrs = 0;
max_mtrrs = soc_get_variable_mtrr_count(NULL);
max_mtrrs = get_var_mtrr_count();
/*
* The upper bits of the MTRR mask need to set according to the number

22
src/drivers/intel/fsp2_0/debug.c
View File

@@ -11,8 +11,8 @@
#include <console/console.h>
#include <console/streams.h>
#include <cpu/x86/mtrr.h>
#include <fsp/util.h>
#include <soc/intel/common/util.h>
asmlinkage size_t fsp_write_line(uint8_t *buffer, size_t number_of_bytes)
{
@@ -28,9 +28,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
const FSPM_UPD *fspm_old_upd,
const FSPM_UPD *fspm_new_upd)
{
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
/* Display the UPD values */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
@@ -62,9 +60,7 @@ void fsp_debug_after_memory_init(uint32_t status)
if (IS_ENABLED(CONFIG_VERIFY_HOBS))
fsp_verify_memory_init_hobs();
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
}
/*-----------
@@ -75,9 +71,7 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
const FSPS_UPD *fsps_old_upd,
const FSPS_UPD *fsps_new_upd)
{
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
/* Display the UPD values */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
@@ -99,9 +93,7 @@ void fsp_debug_after_silicon_init(uint32_t status)
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
fsp_display_hobs();
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
}
/*-----------
@@ -129,7 +121,5 @@ void fsp_debug_after_notify(uint32_t status)
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
fsp_display_hobs();
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
}

6
src/drivers/intel/fsp2_0/notify.c
View File

@@ -12,8 +12,8 @@
#include <bootstate.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <string.h>
#include <timestamp.h>
@@ -70,9 +70,7 @@ static void fsp_notify_dummy(void *arg)
{
enum fsp_notify_phase phase = (uint32_t)arg;
/* Display the MTRRs */
if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
soc_display_mtrrs();
display_mtrrs();
fsp_notify(phase);
if (phase == READY_TO_BOOT)

7
src/include/cpu/x86/mtrr.h
View File

@@ -99,10 +99,17 @@ void x86_mtrr_check(void);
* This function needs to be called after the first MTRR solution is derived. */
void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
static inline int get_var_mtrr_count(void)
{
return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT;
}
void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
unsigned int type);
int get_free_var_mtrr(void);
asmlinkage void display_mtrrs(void);
/*
* Set the MTRRs using the data on the stack from setup_stack_and_mtrrs.
* Return a new top_of_stack value which removes the setup_stack_and_mtrrs data.

5
src/soc/intel/common/Kconfig
View File

@@ -1,5 +1,6 @@
config SOC_INTEL_COMMON
bool
select HAVE_DISPLAY_MTRRS
help
common code for Intel SOCs
@@ -14,10 +15,6 @@ source "src/soc/intel/common/pch/Kconfig"
comment "Intel SoC Common coreboot stages"
source "src/soc/intel/common/basecode/Kconfig"
config DISPLAY_MTRRS
bool "MTRRs: Display the MTRR settings"
default n
config DISPLAY_SMM_MEMORY_MAP
bool "SMM: Display the SMM memory map"
default n

5
src/soc/intel/common/Makefile.inc
View File

@@ -4,23 +4,18 @@ subdirs-y += basecode/
subdirs-y += block/
subdirs-y += pch/
bootblock-y += util.c
verstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
bootblock-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
romstage-y += smbios.c
postcar-y += util.c
postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-y += hda_verb.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
ramstage-y += util.c
ramstage-$(CONFIG_MMA) += mma.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c
ramstage-y += vbt.c

26
src/soc/intel/common/util.h
View File

@@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _INTEL_COMMON_UTIL_H_
#define _INTEL_COMMON_UTIL_H_
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <stdint.h>
asmlinkage void soc_display_mtrrs(void);
uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
#endif /* _INTEL_COMMON_UTIL_H_ */

1
src/soc/intel/quark/Makefile.inc
View File

@@ -16,6 +16,7 @@
ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
subdirs-y += romstage
subdirs-y += ../../../cpu/x86/mtrr
subdirs-y += ../../../cpu/x86/tsc
bootblock-y += bootblock/esram_init.S

5
src/soc/intel/quark/bootblock/bootblock.c
View File

@@ -15,10 +15,10 @@
*/
#include <bootblock_common.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <device/pci_def.h>
#include <program_loading.h>
#include <soc/iomap.h>
#include <soc/intel/common/util.h>
#include <soc/pci_devs.h>
#include <soc/reg_access.h>
@@ -112,8 +112,7 @@ void bootblock_soc_init(void)
if (IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_SOC_INIT_ENTRY))
light_sd_led();
/* Display the MTRRs */
soc_display_mtrrs();
display_mtrrs();
}
void platform_prog_run(struct prog *prog)

1
src/soc/intel/quark/include/soc/ramstage.h
View File

@@ -17,6 +17,7 @@
#ifndef _SOC_RAMSTAGE_H_
#define _SOC_RAMSTAGE_H_
#include <arch/cpu.h>
#include <chip.h>
#include <device/device.h>
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)

1
src/soc/intel/quark/romstage/mtrr.c
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@@ -16,7 +16,6 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <soc/intel/common/util.h>
#include <soc/pci_devs.h>
#include <soc/reg_access.h>

2
src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat
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@@ -40,8 +40,6 @@ smm_region
smm_region_size
soc_after_ram_init
soc_display_memory_init_params
soc_display_mtrrs
soc_get_variable_mtrr_count
soc_memory_init_params
soc_pre_ram_init
southbridge_smi_handler

2
src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat
View File

@@ -23,8 +23,6 @@ platform_segment_loaded
save_chromeos_gpios
soc_after_ram_init
soc_display_memory_init_params
soc_display_mtrrs
soc_get_variable_mtrr_count
soc_memory_init_params
soc_pre_ram_init
southbridge_smi_handler

2
src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat
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@@ -22,8 +22,6 @@ map_oprom_vendev
platform_prog_run
platform_segment_loaded
save_chromeos_gpios
soc_display_mtrrs
soc_get_variable_mtrr_count
stage_cache_add
stage_cache_load_stage
timestamp_get

2
src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat
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@@ -9,8 +9,6 @@ mainboard_check_ec_image
mainboard_post
platform_prog_run
platform_segment_loaded
soc_display_mtrrs
soc_get_variable_mtrr_count
stage_cache_add
stage_cache_load_stage
timestamp_get