Merge remote-tracking branch 'upstream/master' into system76
This commit is contained in:
Jeremy Soller
commit
f0bd902a2a
2
.gitignore
vendored
2
.gitignore
vendored
@ -85,7 +85,6 @@ util/*/.dependencies
|
||||
util/*/.test
|
||||
util/amdfwtool/amdfwtool
|
||||
util/archive/archive
|
||||
util/bimgtool/bimgtool
|
||||
util/bincfg/bincfg
|
||||
util/board_status/board-status
|
||||
util/bucts/bucts
|
||||
@ -115,6 +114,7 @@ util/msrtool/msrtool
|
||||
util/nvramtool/.dependencies
|
||||
util/nvramtool/nvramtool
|
||||
util/optionlist/Options.wiki
|
||||
util/pmh7tool/pmh7tool
|
||||
util/romcc/build
|
||||
util/runfw/googlesnow
|
||||
util/superiotool/superiotool
|
||||
|
||||
2
3rdparty/amd_blobs
vendored
2
3rdparty/amd_blobs
vendored
@ -1 +1 @@
|
||||
Subproject commit cf227316b0fbd3995854ce21e81a63270b29bfb5
|
||||
Subproject commit 17d028869899e1ea0f6f385501088f7623121fcb
|
||||
2
3rdparty/blobs
vendored
2
3rdparty/blobs
vendored
@ -1 +1 @@
|
||||
Subproject commit 62aa0e0c54295bbb7b1a3e5e73f960bafdb59d04
|
||||
Subproject commit 034b27818450428f70aa9316c8bd0d65bacd8ee8
|
||||
2
3rdparty/fsp
vendored
2
3rdparty/fsp
vendored
@ -1 +1 @@
|
||||
Subproject commit 59964173e18950debcc6b8856c5c928935ce0b4f
|
||||
Subproject commit 0bc2b07eab29a8a75cd084963c285ee5434e6666
|
||||
2
3rdparty/opensbi
vendored
2
3rdparty/opensbi
vendored
@ -1 +1 @@
|
||||
Subproject commit e561c6303639ed510183da25d3d54555a53371c9
|
||||
Subproject commit 215421ca610a64b8ec188c96ea8588ae2de41fb7
|
||||
2
3rdparty/vboot
vendored
2
3rdparty/vboot
vendored
@ -1 +1 @@
|
||||
Subproject commit b2c8984d37e378b2faad170d4ec9b378c0c2b145
|
||||
Subproject commit 2843aa62ba7bcaab2abccf16e3f1b8bd7e058fdb
|
||||
13
Documentation/acpi/index.md
Normal file
13
Documentation/acpi/index.md
Normal file
@ -0,0 +1,13 @@
|
||||
# ACPI-specific documentation
|
||||
|
||||
This section contains documentation about coreboot on ACPI.
|
||||
|
||||
- [SSDT UID generation](uid.md)
|
||||
|
||||
## GPIO
|
||||
|
||||
- [GPIO toggling in ACPI AML](gpio.md)
|
||||
|
||||
## devicetree
|
||||
|
||||
- [Adding devices to a device tree](devicetree.md)
|
||||
14
Documentation/acpi/uid.md
Normal file
14
Documentation/acpi/uid.md
Normal file
@ -0,0 +1,14 @@
|
||||
# ACPI SSDT \_UID generation
|
||||
|
||||
According to the ACPI spec:
|
||||
|
||||
> The _UID must be unique across all devices with either a common _HID or _CID.
|
||||
|
||||
|
||||
When generating SSDTs in coreboot the independent drivers don't know
|
||||
which \_UID is already in use for a specific \_HID or \_CID. To generate
|
||||
unique \_UIDs the ACPI device's path is hashed and used as ID. As every ACPI
|
||||
device has a different path, the hash will be also different for every device.
|
||||
|
||||
Windows 10 verifies all devices with the same \_HID or \_CID and makes
|
||||
sure that no \_UID is duplicated. If it is it'll BSOD.
|
||||
@ -19,6 +19,9 @@ On entry to a stage or payload (including SELF payloads),
|
||||
* all harts are running.
|
||||
* A0 is the hart ID.
|
||||
* A1 is the pointer to the Flattened Device Tree (FDT).
|
||||
* A2 contains the additional program calling argument:
|
||||
- cbmem_top for ramstage
|
||||
- the address of the payload for opensbi
|
||||
|
||||
## Additional payload handoff requirements
|
||||
The location of cbmem should be placed in a node in the FDT.
|
||||
|
||||
@ -25,6 +25,8 @@ release = subprocess.check_output(('git', 'describe')).decode("utf-8")
|
||||
# The short X.Y version.
|
||||
version = release.split("-")[0]
|
||||
|
||||
extensions = ['sphinxcontrib.ditaa']
|
||||
|
||||
# The language for content autogenerated by Sphinx. Refer to documentation
|
||||
# for a list of supported languages.
|
||||
#
|
||||
|
||||
@ -64,7 +64,7 @@ across architectures.
|
||||
### Mentors
|
||||
* Timothy Pearson <tpearson@raptorengineering.com>
|
||||
|
||||
## Support QEMU AArch64 or MIPS
|
||||
## Support QEMU AArch64
|
||||
Having QEMU support for the architectures coreboot can boot helps with
|
||||
some (limited) compatibility testing: While QEMU generally doesn't need
|
||||
much hardware init, any CPU state changes in the boot flow will likely
|
||||
@ -105,7 +105,7 @@ would help to ensure code quality and make the runtime code more robust.
|
||||
### Mentors
|
||||
* Werner Zeh <werner.zeh@gmx.net>
|
||||
|
||||
## Port payloads to ARM, AArch64, MIPS or RISC-V
|
||||
## Port payloads to ARM, AArch64 or RISC-V
|
||||
While we have a rather big set of payloads for x86 based platforms, all other
|
||||
architectures are rather limited. Improve the situation by porting a payload
|
||||
to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
|
||||
|
||||
@ -5,3 +5,4 @@ and plugin devices, significantly reducing integration complexity and
|
||||
they allow to easily reuse existing code accross platforms.
|
||||
|
||||
* [IPMI KCS](ipmi_kcs.md)
|
||||
* [SMMSTORE](smmstore.md)
|
||||
|
||||
123
Documentation/drivers/smmstore.md
Normal file
123
Documentation/drivers/smmstore.md
Normal file
@ -0,0 +1,123 @@
|
||||
# SMM based flash storage driver
|
||||
|
||||
This documents the API exposed by the x86 system management based
|
||||
storage driver.
|
||||
|
||||
## SMMSTORE
|
||||
|
||||
SMMSTORE is a SMM mediated driver to read from, write to and erase a
|
||||
predefined region in flash. It can be enabled by setting
|
||||
`CONFIG_SMMSTORE=y` in menuconfig.
|
||||
|
||||
This can be used by the OS or the payload to implement persistent
|
||||
storage to hold for instance configuration data, without needing
|
||||
to implement a (platform specific) storage driver in the payload
|
||||
itself.
|
||||
|
||||
The API provides append-only semantics for key/value pairs.
|
||||
|
||||
## API
|
||||
|
||||
### Storage region
|
||||
|
||||
By default SMMSTORE will operate on a separate FMAP region called
|
||||
`SMMSTORE`. The default generated FMAP will include such a region.
|
||||
On systems with a locked FMAP, e.g. in an existing VBOOT setup
|
||||
with a locked RO region, the option exists to add a cbfsfile
|
||||
called `smm_store` in the `RW_LEGACY` (if CHROMEOS) or in the
|
||||
`COREBOOT` FMAP regions. It is recommended for new builds using
|
||||
a handcrafted FMD that intend to make use of SMMSTORE to include a
|
||||
sufficiently large `SMMSTORE` FMAP region. It is recommended to
|
||||
align the `SMMSTORE` region to 64KiB for the largest flash erase
|
||||
op compatibility.
|
||||
|
||||
When a default generated FMAP is used the size of the FMAP region
|
||||
is equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least
|
||||
64KiB. Given that the current implementation lacks a way to rewrite
|
||||
key-value pairs at least a multiple of this is recommended.
|
||||
|
||||
### generating the SMI
|
||||
|
||||
SMMSTORE is called via an SMI, which is generated via a write to the
|
||||
IO port defined in the smi_cmd entry of the FADT ACPI table. `%al`
|
||||
contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO
|
||||
port. `%ah` contains the SMMSTORE command. `%ebx` contains the
|
||||
parameter buffer to the SMMSTORE command.
|
||||
|
||||
### Return values
|
||||
|
||||
If a command succeeds, SMMSTORE will return with
|
||||
`SMMSTORE_RET_SUCCESS=0` on `%eax`. On failure SMMSTORE will return
|
||||
`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands
|
||||
`SMMSTORE_REG_UNSUPPORTED=2` is returned.
|
||||
|
||||
**NOTE1**: The caller **must** check the return value and should make
|
||||
no assumption on the returned data if `%eax` does not contain
|
||||
`SMMSTORE_RET_SUCCESS`.
|
||||
|
||||
**NOTE2**: If the SMI returns without changing `%ax` assume that the
|
||||
SMMSTORE feature is not installed.
|
||||
|
||||
### Calling arguments
|
||||
|
||||
SMMSTORE supports 3 subcommands that are passed via `%ah`, the additional
|
||||
calling arguments are passed via `%ebx`.
|
||||
|
||||
**NOTE**: The size of the struct entries are in the native word size of
|
||||
smihandler. This means 32 bits in almost all cases.
|
||||
|
||||
|
||||
#### - SMMSTORE_CMD_CLEAR = 1
|
||||
|
||||
This clears the `SMMSTORE` storage region. The argument in `%ebx` is
|
||||
unused.
|
||||
|
||||
#### - SMMSTORE_CMD_READ = 2
|
||||
|
||||
The additional parameter buffer `%ebx` contains a pointer to
|
||||
the following struct:
|
||||
|
||||
```C
|
||||
struct smmstore_params_read {
|
||||
void *buf;
|
||||
ssize_t bufsize;
|
||||
};
|
||||
```
|
||||
|
||||
INPUT:
|
||||
- `buf`: is a pointer to where the data needs to be read
|
||||
- `bufsize`: is the size of the buffer
|
||||
|
||||
OUTPUT:
|
||||
- `buf`
|
||||
- `bufsize`: returns the amount of data that has actually been read.
|
||||
|
||||
#### - SMMSTORE_CMD_APPEND = 3
|
||||
|
||||
SMMSTORE takes a key-value approach to appending data. key-value pairs
|
||||
are never updated, they are always appended. It is up to the caller to
|
||||
walk through the key-value pairs after reading SMMSTORE to find the
|
||||
latest one.
|
||||
|
||||
The additional parameter buffer `%ebx` contains a pointer to
|
||||
the following struct:
|
||||
|
||||
```C
|
||||
struct smmstore_params_append {
|
||||
void *key;
|
||||
size_t keysize;
|
||||
void *val;
|
||||
size_t valsize;
|
||||
};
|
||||
```
|
||||
|
||||
INPUT:
|
||||
- `key`: pointer to the key data
|
||||
- `keysize`: size of the key data
|
||||
- `val`: pointer to the value data
|
||||
- `valsize`: size of the value data
|
||||
|
||||
## External links
|
||||
|
||||
* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
|
||||
Note, this differs significantly from coreboot's implementation.
|
||||
136
Documentation/getting_started/gpio.md
Normal file
136
Documentation/getting_started/gpio.md
Normal file
@ -0,0 +1,136 @@
|
||||
# Configuring a mainboard's GPIOs in coreboot
|
||||
|
||||
## Introduction
|
||||
|
||||
Every mainboard needs to appropriately configure its General Purpose Inputs /
|
||||
Outputs (GPIOs). There are many facets of this issue, including which boot
|
||||
stage a GPIO might need to be configured.
|
||||
|
||||
## Boot stages
|
||||
|
||||
Typically, coreboot does most of its non-memory related initialization work in
|
||||
ramstage, when DRAM is available for use. Hence, the bulk of a mainboard's GPIOs
|
||||
are configured in this stage. However, some boards might need a few GPIOs
|
||||
configured before that; think of memory strapping pins which indicate what kind
|
||||
of DRAM is installed. These pins might need to be read before initializing the
|
||||
memory, so these GPIOs are then typically configured in bootblock or romstage.
|
||||
|
||||
## Configuration
|
||||
|
||||
Most mainboards will have a ``gpio.c`` file in their mainboard directory. This
|
||||
file typically contains tables which describe the configuration of the GPIO
|
||||
registers. Since these registers could be different on a per-SoC or per
|
||||
SoC-family basis, you may need to consult the datasheet for your SoC to find out
|
||||
how to appropriately set these registers. In addition, some mainboards are
|
||||
based on a baseboard/variant model, where several variant mainboards may share a
|
||||
lot of their circuitry and ICs and the commonality between the boards is
|
||||
collected into a virtual ``baseboard.`` In that case, the GPIOs which are shared
|
||||
between multiple boards are placed in the baseboard's ``gpio.c` file, while the
|
||||
ones that are board-specific go into each variant's ``gpio.c`` file.
|
||||
|
||||
## Intel SoCs
|
||||
|
||||
Many newer Intel SoCs share a common IP block for GPIOs, and that commonality
|
||||
has been taken advantage of in coreboot, which has a large set of macros that
|
||||
can be used to describe the configuration of each GPIO pad. This file lives in
|
||||
``src/soc/intel/common/block/include/intelblocks/gpio_defs.h``.
|
||||
|
||||
### Older Intel SoCs
|
||||
|
||||
Baytrail and Braswell, for example, simply expect the mainboard to supply a
|
||||
callback, `mainboard_get_gpios` which returns an array of `struct soc_gpio`
|
||||
objects, defining the configuration of each pin.
|
||||
|
||||
### AMD SoCs
|
||||
|
||||
Some AMD SoCs use a list of `struct soc_amd_gpio` objects to define the
|
||||
register values configuring each pin, similar to Intel.
|
||||
|
||||
### Register details
|
||||
|
||||
GPIO configuration registers typically control properties such as:
|
||||
1. Input / Output
|
||||
2. Pullups / Pulldowns
|
||||
3. Termination
|
||||
4. Tx / Rx Disable
|
||||
5. Which reset signal to use
|
||||
6. Native Function / IO
|
||||
7. Interrupts
|
||||
* IRQ routing (e.g. on x86, APIC, SCI, SMI)
|
||||
* Edge or Level Triggered
|
||||
* Active High or Active Low
|
||||
8. Debouncing
|
||||
|
||||
## Configuring GPIOs for pre-ramstage
|
||||
|
||||
coreboot provides for several SoC-specific and mainboard-specific callbacks at
|
||||
specific points in time, such as bootblock-early, bootblock, romstage entry,
|
||||
pre-silicon init, pre-RAM init, or post-RAM init. The GPIOs that are
|
||||
configured in either bootblock or romstage, depending on when they are needed,
|
||||
are denoted the "early" GPIOs. Some mainboard will use
|
||||
``bootblock_mainboard_init()`` to configure their early GPIOs, and this is
|
||||
probably a good place to start. Many mainboards will declare their GPIO
|
||||
configuration as structs, i.e. (Intel),
|
||||
|
||||
```C
|
||||
struct pad_config {
|
||||
/* offset of pad within community */
|
||||
int pad;
|
||||
/* Pad config data corresponding to DW0, DW1,.... */
|
||||
uint32_t pad_config[GPIO_NUM_PAD_CFG_REGS];
|
||||
};
|
||||
```
|
||||
|
||||
and will usually place these in an array, one for each pad to be configured.
|
||||
Mainboards using Intel SoCs can use a library which combines common
|
||||
configurations together into a set of macros, e.g.,
|
||||
|
||||
```C
|
||||
/* Native function configuration */
|
||||
#define PAD_CFG_NF(pad, pull, rst, func)
|
||||
/*
|
||||
* Set native function with RX Level/Edge configuration and disable
|
||||
* input/output buffer if necessary
|
||||
*/
|
||||
#define PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig)
|
||||
/* General purpose output, no pullup/down. */
|
||||
#define PAD_CFG_GPO(pad, val, rst)
|
||||
/* General purpose output, with termination specified */
|
||||
#define PAD_CFG_TERM_GPO(pad, val, pull, rst)
|
||||
/* General purpose output, no pullup/down. */
|
||||
#define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull)
|
||||
/* General purpose input */
|
||||
#define PAD_CFG_GPI(pad, pull, rst)
|
||||
```
|
||||
etc.
|
||||
|
||||
## Configuring GPIOs for ramstage and beyond...
|
||||
|
||||
In ramstage, most mainboards will configure the rest of their GPIOs for the
|
||||
function they will be performing while the device is active. The goal is the
|
||||
same as above in bootblock; another ``static const`` array is created, and the
|
||||
rest of the GPIO registers are programmed.
|
||||
|
||||
In the baseboard/variant model described above, the baseboard will provide the
|
||||
configuration for the GPIOs which are configured identically between variants,
|
||||
and will provide a mechanism for a variant to override the baseboard's
|
||||
configuration. This is usually done via two tables: the baseboard table and the
|
||||
variant's override table.
|
||||
|
||||
This configuration is often hooked into the mainboard's `enable_dev` callback,
|
||||
defined in its `struct chip_operations`.
|
||||
|
||||
## Potential issues (gotchas!)
|
||||
|
||||
There are a couple of configurations that you need to especially careful about,
|
||||
as they can have a large impact on your mainboard.
|
||||
|
||||
The first is configuring a pin as an output, when it was designed to be an
|
||||
input. There is a real risk in this case of short-circuiting a component which
|
||||
could cause catastrophic failures, up to and including your mainboard!
|
||||
|
||||
The other configuration option to watch out for deals with unconnected GPIOs.
|
||||
If no pullup or pulldown is declared with these, they may end up "floating",
|
||||
i.e., not at logical high or logical low. This can cause problems such as
|
||||
unwanted power consumption or not reading the pin correctly, if it was intended
|
||||
to be strapped.
|
||||
@ -7,3 +7,4 @@
|
||||
* [Gerrit Guidelines](gerrit_guidelines.md)
|
||||
* [Documentation License](license.md)
|
||||
* [Writing Documentation](writing_documentation.md)
|
||||
* [Setting up GPIOs](gpio.md)
|
||||
|
||||
@ -42,8 +42,25 @@ Please follow this official [guide] to install sphinx.
|
||||
You will also need python-recommonmark for sphinx to be able to handle
|
||||
markdown documentation.
|
||||
|
||||
The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and
|
||||
recommonmark 0.4.0.
|
||||
Since some Linux distributions don't package every needed sphinx extension,
|
||||
the installation via pip in a venv is recommended. You'll need these python3
|
||||
modules:
|
||||
|
||||
* sphinx
|
||||
* recommonmark
|
||||
* sphinx_rtd_theme
|
||||
* sphinxcontrib-ditaa
|
||||
|
||||
The following combination of versions has been tested: sphinx 2.3.1,
|
||||
recommonmark 0.6.0, sphinx_rtd_theme 0.4.3 and sphinxcontrib-ditaa 0.7.
|
||||
|
||||
Now change into the `Documentation` folder in the coreboot directory and run
|
||||
this command in there
|
||||
|
||||
make sphinx
|
||||
|
||||
If no error occurs, you can find the generated HTML documentation in
|
||||
`Documentation/_build` now.
|
||||
|
||||
### Optional
|
||||
|
||||
|
||||
@ -171,20 +171,19 @@ Contents:
|
||||
* [Payloads](payloads.md)
|
||||
* [Distributions](distributions.md)
|
||||
* [Technotes](technotes/index.md)
|
||||
* [GPIO toggling in ACPI AML](acpi/gpio.md)
|
||||
* [Adding devices to a device tree](acpi/devicetree.md)
|
||||
* [ACPI](acpi/index.md)
|
||||
* [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
|
||||
* [Display panel-specific documentation](gfx/display-panel.md)
|
||||
* [Architecture-specific documentation](arch/index.md)
|
||||
* [Platform independend drivers documentation](drivers/index.md)
|
||||
* [Northbridge-specific documentation](northbridge/index.md)
|
||||
* [System on Chip-specific documentation](soc/index.md)
|
||||
* [Mainboard-specific documentation](mainboard/index.md)
|
||||
* [Payload-specific documentation](lib/payloads/index.md)
|
||||
* [Library-specific documentation](lib/index.md)
|
||||
* [Display panel](gfx/display-panel.md)
|
||||
* [CPU Architecture](arch/index.md)
|
||||
* [Platform independent drivers](drivers/index.md)
|
||||
* [Northbridge](northbridge/index.md)
|
||||
* [System on Chip](soc/index.md)
|
||||
* [Mainboard](mainboard/index.md)
|
||||
* [Payloads](lib/payloads/index.md)
|
||||
* [Libraries](lib/index.md)
|
||||
* [Security](security/index.md)
|
||||
* [SuperIO-specific documentation](superio/index.md)
|
||||
* [Vendorcode-specific documentation](vendorcode/index.md)
|
||||
* [SuperIO](superio/index.md)
|
||||
* [Vendorcode](vendorcode/index.md)
|
||||
* [Utilities](util.md)
|
||||
* [Release notes for past releases](releases/index.md)
|
||||
* [Flashing firmware tutorial](flash_tutorial/index.md)
|
||||
|
||||
@ -58,7 +58,7 @@ Supported compression algorithms:
|
||||
The config entries contain a compatible string, that is used to find a
|
||||
matching config.
|
||||
|
||||
The following mainboard specific funtions provide the BOARDID and SKUID:
|
||||
The following mainboard specific functions provide the BOARDID and SKUID:
|
||||
|
||||
```c
|
||||
uint32_t board_id(void);
|
||||
|
||||
77
Documentation/mainboard/asus/p5q.md
Normal file
77
Documentation/mainboard/asus/p5q.md
Normal file
@ -0,0 +1,77 @@
|
||||
# ASUS P5Q
|
||||
|
||||
This page describes how to run coreboot on the [ASUS P5Q] desktop board.
|
||||
|
||||
## TODO
|
||||
|
||||
The following things are working in this coreboot port:
|
||||
|
||||
+ PCI slots
|
||||
+ PCI-e slots
|
||||
+ Onboard Ethernet
|
||||
+ USB
|
||||
+ Onboard sound card
|
||||
+ PS/2 keyboard
|
||||
+ All 4 DIMM slots
|
||||
+ S3 suspend and resume
|
||||
+ Red SATA ports
|
||||
|
||||
The following things are still missing from this coreboot port:
|
||||
|
||||
+ PS/2 mouse support
|
||||
+ PATA aka IDE (because of buggy IDE controller)
|
||||
+ Fan control (will be working on 100% power)
|
||||
+ TPM module (support not implemented)
|
||||
|
||||
The following things are untested on this coreboot port:
|
||||
|
||||
+ S/PDIF
|
||||
+ CD Audio In
|
||||
+ Floppy disk drive
|
||||
+ FireWire: PCI device shows up and driver loads, no further test
|
||||
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
```eval_rst
|
||||
+-------------------+----------------+
|
||||
| Type | Value |
|
||||
+===================+================+
|
||||
| Socketed flash | Yes |
|
||||
+-------------------+----------------+
|
||||
| Model | MX25L8005 |
|
||||
+-------------------+----------------+
|
||||
| Size | 1 MiB |
|
||||
+-------------------+----------------+
|
||||
| Package | Socketed DIP-8 |
|
||||
+-------------------+----------------+
|
||||
| Write protection | No |
|
||||
+-------------------+----------------+
|
||||
| Dual BIOS feature | No |
|
||||
+-------------------+----------------+
|
||||
| Internal flashing | Yes |
|
||||
+-------------------+----------------+
|
||||
```
|
||||
|
||||
You can flash coreboot into your motherboard using [this guide].
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
+------------------+---------------------------------------------------+
|
||||
| Northbridge | Intel P45 (called x4x in coreboot code) |
|
||||
+------------------+---------------------------------------------------+
|
||||
| Southbridge | Intel ICH10R (called i82801jx in coreboot code) |
|
||||
+------------------+---------------------------------------------------+
|
||||
| CPU (LGA775) | Model f4x, f6x, 6fx, 1067x (Pentium 4, d, Core 2) |
|
||||
+------------------+---------------------------------------------------+
|
||||
| SuperIO | Winbond W83667HG |
|
||||
+------------------+---------------------------------------------------+
|
||||
| Coprocessor | No |
|
||||
+------------------+---------------------------------------------------+
|
||||
| Clockgen (CK505) | ICS 9LPRS918JKLF |
|
||||
+------------------+---------------------------------------------------+
|
||||
```
|
||||
|
||||
[ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
|
||||
[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
|
||||
5
Documentation/mainboard/facebook/fbg1701.md
Executable file → Normal file
5
Documentation/mainboard/facebook/fbg1701.md
Executable file → Normal file
@ -14,8 +14,7 @@ Mainboard menu.
|
||||
|
||||
This board currently requires:
|
||||
fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
|
||||
Microcode Intel Braswell cpuid 1046C4 version 410
|
||||
(Used pre-built binary retrieved from Intel site)
|
||||
Microcode 3rdparty/intel-microcode/intel-ucode/06-4c-04
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
@ -73,7 +72,7 @@ Specifically, it's a Winbond W25Q64FV (3.3V), whose datasheet can be found
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel Braswell (N3710) |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Super I/O, EC | ITE8256 |
|
||||
| Super I/O, EC | ITE8528 |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Coprocessor | Intel Management Engine |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
||||
78
Documentation/mainboard/facebook/monolith.md
Normal file
78
Documentation/mainboard/facebook/monolith.md
Normal file
@ -0,0 +1,78 @@
|
||||
# Facebook Monolith
|
||||
|
||||
This page describes how to run coreboot on the Facebook Monolith.
|
||||
|
||||
Please note: the coreboot implementation for this boards is in its
|
||||
Alpha state and isn't fully tested yet.
|
||||
|
||||
## Required blobs
|
||||
|
||||
This board currently requires:
|
||||
fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd
|
||||
3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd
|
||||
|
||||
Microcode 3rdparty/intel-microcode/intel-ucode
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
### Internal programming
|
||||
|
||||
The SPI flash can be accessed using [flashrom].
|
||||
|
||||
### External programming
|
||||
|
||||
The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
|
||||
Specifically, it's a Winbond W25Q128JVSIQ (3.3V).
|
||||
|
||||
The system has an external flash chip which is a 16 MiB soldered SOIC-8 chip.
|
||||
Specifically, it's a Winbond W25Q128JVSIM (3.3V).
|
||||
|
||||
Flashing of these devices is very difficult, disassembling the system destroys the cooling
|
||||
solution. Wires need to be connected to be able to flash using an external programmer.
|
||||
|
||||
## Known issues
|
||||
|
||||
- None
|
||||
|
||||
## Untested
|
||||
|
||||
- Hardware monitor
|
||||
- SDIO
|
||||
- Full Embedded Controller support
|
||||
- eMMC
|
||||
- SATA
|
||||
|
||||
## Working
|
||||
|
||||
- USB
|
||||
- Gigabit Ethernet
|
||||
- Graphics (Using FSP GOP)
|
||||
- flashrom
|
||||
- PCIe
|
||||
- EC serial port
|
||||
- SMBus
|
||||
- Initialization with FSP
|
||||
- SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
|
||||
- TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
|
||||
|
||||
All of the above has been briefly tested by booting Linux from the TianoCore payload.
|
||||
SeaBios has been checked to the extend that it runs to the boot selection and provides display
|
||||
output.
|
||||
|
||||
## Technology
|
||||
|
||||
```eval_rst
|
||||
+------------------+--------------------------------------------------+
|
||||
| SoC | Intel Kaby Lake U |
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel i3-7100U |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Super I/O, EC | ITE8528 |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Coprocessor | Intel Management Engine |
|
||||
+------------------+--------------------------------------------------+
|
||||
```
|
||||
|
||||
[W25Q128JVSIQ]: https://www.winbond.com/resource-files/w25q128jv%20revf%2003272018%20plus.pdf
|
||||
[W25Q128JVSIM]: https://www.winbond.com/resource-files/w25q128jv%20dtr%20revb%2011042016.pdf
|
||||
[flashrom]: https://flashrom.org/Flashrom
|
||||
@ -39,27 +39,23 @@ leave the backup chip untouched.
|
||||
|
||||
The original IFD defines the BIOS region as the whole flash chip. While this is
|
||||
not an issue if flashing a complete image, it confuses flashrom and trashes the
|
||||
flash chip's contents when using the --ifd option. However, this can be easily
|
||||
fixed by reading the IFD with flashrom, editing the correct values into it with
|
||||
ifdtool and then reflashing it.
|
||||
|
||||
Create a layout.txt with the following contents:
|
||||
flash chip's contents when using the `--ifd` option. A possible workaround is
|
||||
to create a `layout.txt` file with a non-overlapping BIOS region:
|
||||
|
||||
00000000:00000fff fd
|
||||
00180000:003fffff bios
|
||||
00001000:0017ffff me
|
||||
|
||||
After that, simply run:
|
||||
After that, use flashrom with the new layout file. For example, to create a
|
||||
backup of the BIOS region and then flash a `coreboot.rom`, do:
|
||||
|
||||
```bash
|
||||
sudo flashrom -p internal --ifd -i fd -r ifd.rom
|
||||
ifdtool -n layout.txt ifd.rom
|
||||
sudo flashrom -p internal --ifd -i fd -w ifd.rom.new
|
||||
sudo flashrom -p internal -l layout.txt -i bios -r backup.rom
|
||||
sudo flashrom -p internal -l layout.txt -i bios -w coreboot.rom
|
||||
```
|
||||
|
||||
After flashing, power cycle the computer to ensure the new IFD is being used.
|
||||
If only a reboot is done, the old IFD layout is still seen by flashrom, even if
|
||||
the IFD on the flash chip is correctly defining the new region layout.
|
||||
Modifying the IFD so that the BIOS region does not overlap would work as well.
|
||||
However, this makes DualBIOS unable to recover from a bad flash for some reason.
|
||||
|
||||
## Technology
|
||||
|
||||
|
||||
@ -32,6 +32,7 @@ The boards in this section are not real mainboards, but emulators.
|
||||
## Facebook
|
||||
|
||||
- [FBG-1701](facebook/fbg1701.md)
|
||||
- [Monolith](facebook/monolith.md)
|
||||
|
||||
## Foxconn
|
||||
|
||||
@ -95,10 +96,6 @@ The boards in this section are not real mainboards, but emulators.
|
||||
|
||||
- [T440p](lenovo/t440p.md)
|
||||
|
||||
## Portwell
|
||||
|
||||
- [PQ7-M107](portwell/pq7-m107.md)
|
||||
|
||||
## MSI
|
||||
|
||||
- [MS-7707](msi/ms7707/ms7707.md)
|
||||
@ -129,6 +126,7 @@ The boards in this section are not real mainboards, but emulators.
|
||||
|
||||
- [X10SLM+-F](supermicro/x10slm-f.md)
|
||||
- [X11 LGA1151 series](supermicro/x11-lga1151-series/x11-lga1151-series.md)
|
||||
- [Flashing using the BMC](supermicro/flashing_on_vendorbmc.md)
|
||||
|
||||
## UP
|
||||
|
||||
|
||||
@ -14,8 +14,7 @@ menu.
|
||||
|
||||
This board currently requires:
|
||||
fsp blob 3rdparty/fsp/BraswellFspBinPkg/FspBin/BSWFSP.fd
|
||||
Microcode Intel Braswell cpuid 1046C4 version 410
|
||||
(Used pre-built binary retrieved from Intel site)
|
||||
Microcode 3rdparty/intel-microcode/intel-ucode/06-4c-04
|
||||
|
||||
## Flashing coreboot
|
||||
|
||||
@ -68,7 +67,7 @@ serial/video/pcie ports might be available.
|
||||
+------------------+--------------------------------------------------+
|
||||
| CPU | Intel Braswell (N3710) |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Super I/O, EC | ITE8256 |
|
||||
| Super I/O, EC | ITE8528 |
|
||||
+------------------+--------------------------------------------------+
|
||||
| Coprocessor | Intel Management Engine |
|
||||
+------------------+--------------------------------------------------+
|
||||
|
||||
32
Documentation/mainboard/supermicro/flashing_on_vendorbmc.md
Normal file
32
Documentation/mainboard/supermicro/flashing_on_vendorbmc.md
Normal file
@ -0,0 +1,32 @@
|
||||
# Flashing coreboot using SMC IPMI (BMC) firmware
|
||||
|
||||
## Metadata
|
||||
In order to flash anything to the "BIOS" IC, it needs to contain a valid
|
||||
BIOSINFO struct.
|
||||
|
||||
The BIOSINFO struct contains a `$FID` marker at the beginning and is
|
||||
128 bytes in total. Besides the *BoardID* it contains the *firmware version*
|
||||
and *build date*. The BMC verifies that the BoardID is correct and refuses to
|
||||
flash if it's not.
|
||||
|
||||
The struct has no checksum or cryptographic protection.
|
||||
|
||||
## The smcinfobios tool
|
||||
|
||||
The smcbiosinfo tool can be found in `util/supermicro/smcbiosinfo`.
|
||||
|
||||
It parses the `build/build.h` header to get the current coreboot version and
|
||||
build timestamp.
|
||||
The *board ID* is passed as command line argument.
|
||||
|
||||
It will place a file in CBFS called `smcbiosinfo.bin`, which is then found
|
||||
by the vendor tools. The file contains the struct described above.
|
||||
|
||||
## Flashing using SMCIPMItool
|
||||
|
||||
You can use the *SMCIPMITool* to remotely flash the BIOS:
|
||||
|
||||
`SMCIPMITool <remote BMC IP> <user> <password> bios update build/coreboot.rom`
|
||||
|
||||
Make sure that the ME isn't in recovery mode, otherwise you get an error
|
||||
message on updating the BIOS.
|
||||
@ -68,7 +68,7 @@ region is not readable even by the host.
|
||||
The main firmware flash chip is an SOIC-8 package located near the CMOS
|
||||
battery and SATA ports. It should come with a sticker attached that
|
||||
states the firmware revision (e.g. "X10SLH 4.424"). The chip model is
|
||||
an N25Q128A, and the datasheet can be found [here][N25Q128A].
|
||||
an N25Q128A ([datasheet][N25Q128A]).
|
||||
|
||||
As with [internal programming](#internal-programming), [flashrom] works
|
||||
reliably:
|
||||
@ -87,8 +87,7 @@ way without issue.
|
||||
|
||||
This board has an ASPEED [AST2400], which has BMC functionality. The
|
||||
BMC firmware resides in a 32 MiB SOIC-16 chip just above the [AST2400].
|
||||
This chip is an MX25L25635F, whose datasheet can be found
|
||||
[here][MX25L25635F].
|
||||
This chip is an MX25L25635F ([datasheet][MX25L25635F]).
|
||||
|
||||
### Removing the BMC functionality
|
||||
|
||||
|
||||
@ -31,7 +31,7 @@ Look at the [flashing tutorial] and the board-specific section.
|
||||
These issues apply to all boards. Have a look at the board-specific issues, too.
|
||||
|
||||
- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
|
||||
- MRC caching does not work with cold boot
|
||||
- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])
|
||||
|
||||
## ToDo
|
||||
|
||||
|
||||
@ -49,29 +49,34 @@ be more frequent than was needed, so we scaled it back to twice a year.
|
||||
## Checklist
|
||||
### ~2 weeks prior to release
|
||||
- [ ] Announce upcoming release to mailing list, ask people to test and
|
||||
to update release notes
|
||||
to update release notes.
|
||||
|
||||
### ~1 week prior to release
|
||||
- [ ] Send reminder email to mailing list, ask for people to test,
|
||||
and to update the release notes
|
||||
- [ ] Update the topic in the irc channel with the date of the upcoming
|
||||
release
|
||||
and to update the release notes.
|
||||
- [ ] Update the topic in the IRC channel with the date of the upcoming
|
||||
release.
|
||||
- [ ] If there are any deprecations announced for the following release,
|
||||
make sure that a list of currently affected boards and chipsets is
|
||||
part of the release notes.
|
||||
- [ ] Finalize release notes (as much as possible), without specifying
|
||||
release commit ids.
|
||||
|
||||
### Day of release
|
||||
- [ ] Update release notes, without specifying release commit ids
|
||||
- [ ] Select a commit ID to base the release upon, announce to IRC,
|
||||
ask for testing.
|
||||
- [ ] Test the commit selected for release
|
||||
- [ ] Run release script
|
||||
- [ ] Test the release from the actual release tarballs
|
||||
- [ ] Push signed Tag to repo
|
||||
- [ ] Announce that the release tag is done on IRC
|
||||
- [ ] Update release notes with actual commit id, push to repo
|
||||
- [ ] Test the commit selected for release.
|
||||
- [ ] Update release notes with actual commit id, push to repo.
|
||||
- [ ] Run release script.
|
||||
- [ ] Test the release from the actual release tarballs.
|
||||
- [ ] Push signed Tag to repo.
|
||||
- [ ] Announce that the release tag is done on IRC.
|
||||
- [ ] Upload release files to web server
|
||||
- [ ] Upload crossgcc sources to web server
|
||||
- [ ] Update download page to point to files, push to repo
|
||||
- [ ] Upload crossgcc sources to web server.
|
||||
- [ ] Update download page to point to files, push to repo.
|
||||
- [ ] Write and publish blog post with release notes.
|
||||
- [ ] Update the topic in the irc channel that the release is done.
|
||||
- [ ] Update the topic in the IRC channel that the release is done.
|
||||
- [ ] Announce the release to the mailing list.
|
||||
|
||||
## Pre-Release tasks
|
||||
Announce the upcoming release to the mailing list release 2 weeks ahead
|
||||
@ -82,9 +87,7 @@ release notes that are in the making and ask people to test the hardware
|
||||
they have to make sure it's working with the current master branch,
|
||||
from which the release will ultimately be derived from.
|
||||
|
||||
People should also be encouraged to provide additions to the
|
||||
release notes, for example by putting them on some [collaborative
|
||||
editor](https://www.piratenpad.de).
|
||||
People should be encouraged to provide additions to the release notes.
|
||||
|
||||
The final release notes will reside in coreboot's Documentation/releases
|
||||
directory, so asking for additions to that through the regular Gerrit
|
||||
@ -99,7 +102,7 @@ to have in the release. The release was based on the final of those
|
||||
patches to be pulled in.
|
||||
|
||||
When a release candidate has been selected, announce the commit ID to
|
||||
the #coreboot irc channel, and request that it get some testing, just
|
||||
the #coreboot IRC channel, and request that it get some testing, just
|
||||
to make sure that everything is sane.
|
||||
|
||||
## Generate the release
|
||||
|
||||
@ -1,35 +1,133 @@
|
||||
Upcoming release - coreboot 4.11
|
||||
================================
|
||||
coreboot 4.11
|
||||
=============
|
||||
|
||||
The 4.11 release is planned for October 2019
|
||||
coreboot 4.11 was released on November 19th.
|
||||
|
||||
Update this document with changes that should be in the release
|
||||
notes.
|
||||
* Please use Markdown.
|
||||
* See the [4.9](coreboot-4.9-relnotes.md) and [4.10](coreboot-4.10-relnotes.md)
|
||||
release notes for the general format.
|
||||
* The chip and board additions and removals will be updated right
|
||||
before the release, so those do not need to be added.
|
||||
This release cycle was a bit shorter to get closer to our regular
|
||||
schedule of releasing in spring and autumn.
|
||||
|
||||
Since 4.10 there were 1630 new commits by over 130 developers.
|
||||
Of these, about 30 contributed to coreboot for the first time.
|
||||
|
||||
Thank you to all contributors who made 4.11 what it is and welcome
|
||||
to the project to all new contributors!
|
||||
|
||||
Clean Up
|
||||
--------
|
||||
|
||||
The past few months saw lots of cleanup across the source tree:
|
||||
|
||||
The included headers in source files were stripped down to avoid reading
|
||||
unused headers, and unused code fragments, duplicate preprocessor symbols
|
||||
and configuration options were eliminated. Even ACPI got its share
|
||||
of attention, making our tables and bytecode more standards compliant
|
||||
than ever.
|
||||
|
||||
The code across Intel's chipsets was unified some more into drivers for
|
||||
common function blocks, an effort we're more confident will succeed now
|
||||
that Intel itself is driving it.
|
||||
|
||||
Chipset work
|
||||
------------
|
||||
|
||||
Most activity in the last couple months was on Intel support,
|
||||
specifically the Kaby Lake and Cannon Lake drivers were extended
|
||||
for the generations following them.
|
||||
|
||||
On ARM, the Mediatek 8173 chipset support saw significant work while
|
||||
the AMD side worked on getting Picasso support in.
|
||||
|
||||
But everything else also saw some action, the relatively old
|
||||
(e.g. Intel GM45, Via VX900), the tiny (RISC-V) and the obscure
|
||||
(Quark).
|
||||
|
||||
Verified Boot
|
||||
-------------
|
||||
|
||||
The vboot feature that Chromebooks brought into coreboot was extended
|
||||
to work on devices that weren't specially adapted for it: In addition
|
||||
to its original device family it's now supported on various Lenovo
|
||||
laptops, Open Compute Project systems and Siemens industrial machines.
|
||||
|
||||
Eltan's support for measured boot continues to be integrated with
|
||||
vboot, sharing data structures and generally working together where
|
||||
possible.
|
||||
|
||||
New devices
|
||||
-----------
|
||||
|
||||
With 4.11 there's the beginning of support for Intel Tiger Lake and
|
||||
Qualcomm's SC7180 SoCs, while we removed the unmaintained support
|
||||
for Allwinner's A10 SoC.
|
||||
|
||||
There are also 25 new mainboards in our tree:
|
||||
|
||||
* AMD PADMELON
|
||||
* ASUS P5QL-EM
|
||||
* EMULATION QEMU-AARCH64
|
||||
* GOOGLE AKEMI
|
||||
* GOOGLE ARCADA CML
|
||||
* GOOGLE DAMU
|
||||
* GOOGLE DOOD
|
||||
* GOOGLE DRALLION
|
||||
* GOOGLE DRATINI
|
||||
* GOOGLE JACUZZI
|
||||
* GOOGLE JUNIPER
|
||||
* GOOGLE KAKADU
|
||||
* GOOGLE KAPPA
|
||||
* GOOGLE PUFF
|
||||
* GOOGLE SARIEN CML
|
||||
* GOOGLE TREEYA
|
||||
* GOOGLE TROGDOR
|
||||
* LENOVO R60
|
||||
* LENOVO T410
|
||||
* LENOVO THINKPAD T440P
|
||||
* LENOVO X301
|
||||
* RAZER BLADE-STEALTH KBL
|
||||
* SIEMENS MC-APL6
|
||||
* SUPERMICRO X11SSH-TF
|
||||
* SUPERMICRO X11SSM-F
|
||||
|
||||
In addition to the Cubieboard (which uses the A10 SoC), we also
|
||||
removed Google Hatch WHL.
|
||||
|
||||
Deprecations
|
||||
------------
|
||||
|
||||
Because there was only a single developer board (AMD Torpedo)
|
||||
using AGESA family 12h, and because there were multiple,
|
||||
unique Coverity issues with it, the associated vendorcode will
|
||||
be removed shortly after this release.
|
||||
|
||||
Support for the MIPS architecture will also be removed shortly after
|
||||
this release as the only board in the tree was a discontinued development
|
||||
board and no other work has picked up MIPS support, so it's very likely
|
||||
broken already.
|
||||
|
||||
After more than a year of planning and following the announcement in
|
||||
coreboot 4.10, platforms not using relocatable ramstage, a C bootblock
|
||||
and, on systems using Cache as RAM, a postcar stage, won't be supported
|
||||
going forward.
|
||||
|
||||
Significant changes
|
||||
-------------------
|
||||
|
||||
### Add significant changes here
|
||||
|
||||
### `__PRE_RAM__` is deprecated
|
||||
|
||||
Preprocessor use of `defined(__PRE_RAM_)` have been mostly replaced with
|
||||
Preprocessor use of `defined(__PRE_RAM__)` have been mostly replaced with
|
||||
`if (ENV_ROMSTAGE_OR_BEFORE)` or the inverse `if (ENV_RAMSTAGE)`.
|
||||
|
||||
The remaining cases and `-D__PRE_RAM__` are to be removed soon after release.
|
||||
|
||||
### `__BOOTBLOCK__` et.al. are converted
|
||||
|
||||
This applies to all `ENV_xxx` definitions found in `<rules.h>`.
|
||||
|
||||
Write code without preprocessor directives whenever possible, replacing
|
||||
`#ifdef __BOOTBLOCK__` with `if (ENV_BOOTBLOCK)`
|
||||
|
||||
In cases where preprocessor is needed use `#if ENV_BOOTBLOCK` instead.
|
||||
|
||||
### `CAR_GLOBAL` is removed where possible
|
||||
|
||||
For all platform code with `NO_CAR_GLOBAL_MIGRATION=y`, any `CAR_GLOBAL`
|
||||
@ -40,3 +138,76 @@ removed soon after release.
|
||||
|
||||
Significant refactoring has bee done to achieve some consistency across platforms
|
||||
and to reduce code duplication.
|
||||
|
||||
### Build system amenities ###
|
||||
|
||||
The build system now has an `all` class of source files to remove the need to
|
||||
list source files for each and every source class (romstage, ramstage, ...)
|
||||
|
||||
The site-local/ mechanism became more robust.
|
||||
|
||||
### Stricter coding standards to improve security ###
|
||||
|
||||
The build now fails on variable length arrays (that make it way too easy to
|
||||
smash a stack) and case statements falling through without a note that it is
|
||||
intentional.
|
||||
|
||||
### Shorter file headers ###
|
||||
|
||||
This project is still under way, but we started moving author information
|
||||
from individual files into the global AUTHORS file (and there's the git
|
||||
history for more details).
|
||||
|
||||
In the future, we also want to replace the license headers (lots of lines)
|
||||
in each file with spdx identifiers (one line) and so we added a LICENSES/
|
||||
directory that contains the full text of all the licenses that are used
|
||||
throughout our tree.
|
||||
|
||||
### Variant creation scripts ###
|
||||
|
||||
To ease the creation of variant boards, `util/mainboard/` now contains
|
||||
scripts to generate a new variant to a given board. These are still
|
||||
specific to google/hatch at this time, but they're written with the idea
|
||||
of becoming more generally useful.
|
||||
|
||||
### Payloads ###
|
||||
|
||||
Payload integration has been updated, coreinfo learned to cope with
|
||||
UPPER CASE commands and libpayload knows how to deal with USB3 hubs.
|
||||
|
||||
### Added VBOOT support to the following platforms:
|
||||
|
||||
* intel/gm45
|
||||
* intel/nehalem
|
||||
|
||||
### Moved the following platforms to C_ENVIRONMENT_BOOTBLOCK:
|
||||
|
||||
* intel/i945
|
||||
* intel/x4x
|
||||
* intel/gm45
|
||||
* intel/nehalem
|
||||
* intel/sandybridge
|
||||
* intel/braswell
|
||||
|
||||
### libgfxinit ###
|
||||
|
||||
Most notable, dynamic CDClk configuration was added to libgfxinit,
|
||||
to support higher resolution displays without changes in the static
|
||||
configuration. It also received some fixes for better DP and eDP
|
||||
compatibility, better error recovery for Intel's fickle GMBus and
|
||||
updated platform support:
|
||||
* Correct HDMI clock limit for G45.
|
||||
* DP support for Ibex Peak (Ironlake graphics).
|
||||
* Fixed scaling on eDP for Broadwell.
|
||||
* Support for ULX variants of Haswell and later.
|
||||
* Support for Kaby, Amber, Coffee and Whiskey Lake.
|
||||
|
||||
### Other
|
||||
* Did cleanups around TSC timer
|
||||
* Improved automatic VR configuration on SKL/KBL
|
||||
* Filled additional fields in SMBIOS type 4
|
||||
* Removed magic value replay from Intel Nehalem/ibexpeak code base
|
||||
* Added OpenSBI on RISCV platforms
|
||||
* Did more preparations for Intel TXT support
|
||||
* Did more preparations for x86_64 stage support
|
||||
* Added SSDT generator for arbitrary SuperIO chips based on devicetree.cb
|
||||
|
||||
20
Documentation/releases/coreboot-4.12-relnotes.md
Normal file
20
Documentation/releases/coreboot-4.12-relnotes.md
Normal file
@ -0,0 +1,20 @@
|
||||
Upcoming release - coreboot 4.12
|
||||
================================
|
||||
|
||||
The 4.12 release is planned for April 2020
|
||||
|
||||
Update this document with changes that should be in the release
|
||||
notes.
|
||||
* Please use Markdown.
|
||||
* See the past few release notes for the general format.
|
||||
* The chip and board additions and removals will be updated right
|
||||
before the release, so those do not need to be added.
|
||||
|
||||
Significant changes
|
||||
-------------------
|
||||
|
||||
### SMMSTORE is now production ready
|
||||
|
||||
See [smmstore](../drivers/smmstore.md) for the documentation on the API.
|
||||
|
||||
### Add significant changes here
|
||||
@ -11,6 +11,7 @@ Release notes for previous releases
|
||||
* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
|
||||
* [4.9 - December 2018](coreboot-4.9-relnotes.md)
|
||||
* [4.10 - July 2019](coreboot-4.10-relnotes.md)
|
||||
* [4.11 - November 2019](coreboot-4.11-relnotes.md)
|
||||
|
||||
The checklist contains instructions to ensure that a release covers all
|
||||
important things and provides a reliable format for tarballs, branch
|
||||
@ -22,4 +23,4 @@ Upcoming release
|
||||
----------------
|
||||
|
||||
Please add to the release notes as changes are added:
|
||||
* [4.11 - October 2019](coreboot-4.11-relnotes.md)
|
||||
* [4.12 - April 2020](coreboot-4.12-relnotes.md)
|
||||
|
||||
@ -186,6 +186,26 @@ In addition to adding the coreboot files into the read-only region,
|
||||
enabling vboot causes the build script to add the read/write files into
|
||||
coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
|
||||
|
||||
**RO_REGION_ONLY**
|
||||
|
||||
The files added to this list will only be placed in the read-only region and
|
||||
not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
|
||||
|
||||
**VBOOT_ENABLE_CBFS_FALLBACK**
|
||||
|
||||
Normally coreboot will use the active read/write coreboot file system for all
|
||||
of it's file access when VBOOT is active and is not in recovery mode.
|
||||
|
||||
When the `VBOOT_ENABLE_CBFS_FALLBACK` option is enabled the cbfs file system will
|
||||
first try to locate a file in the active read/write file system. If the file
|
||||
doesn't exist here the file system will try to locate the file in the read-only
|
||||
file system.
|
||||
|
||||
This option can be used to prevent duplication of static data. Files can be
|
||||
removed from the read/write partitions by adding them to the `RO_REGION_ONLY`
|
||||
config. If a file needs to be changed in a later stage simply remove it from
|
||||
this list.
|
||||
|
||||
***
|
||||
|
||||
## Signing the coreboot Image
|
||||
|
||||
@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well.
|
||||
* Workaround: none
|
||||
* Issue on public tracker: [Issue 22]
|
||||
|
||||
* MRC forces memory re-training on cold boot on boards with Intel SPS
|
||||
* Releases 3.7.1, 3.7.6
|
||||
* Workaround: Flash Intel ME instead of SPS
|
||||
* Issue on public tracker: [Issue 41]
|
||||
|
||||
### BraswellFsp
|
||||
* Internal UART can't be disabled using PcdEnableHsuart*
|
||||
* Release MR2
|
||||
@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well.
|
||||
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
|
||||
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
|
||||
[Issue 35]: https://github.com/IntelFsp/FSP/issues/35
|
||||
[Issue 41]: https://github.com/IntelFsp/FSP/issues/41
|
||||
|
||||
|
||||
114
Documentation/superio/common/pnp.md
Normal file
114
Documentation/superio/common/pnp.md
Normal file
@ -0,0 +1,114 @@
|
||||
# PNP devices
|
||||
|
||||
Typical PNP devices are Super I/Os, LPC-connected TPMs and board
|
||||
management controllers.
|
||||
|
||||
PNP devices are usually connected to the LPC or eSPI bus of a system
|
||||
and shouldn't be confused with PCI(e) devices that use a completely
|
||||
different plug and play mechanism. PNP originates in the ISA plug and
|
||||
play specification. Since the original ISA bus is more or less extinct,
|
||||
the auto-detection part of ISA PNP is mostly irrelevant nowadays. For
|
||||
the register offsets for different functionality, appendix A of that
|
||||
specification is still the main reference though.
|
||||
|
||||
## Configuration access and config mode
|
||||
|
||||
Super I/O chips connected via LPC to the southbridge usually have their
|
||||
I/O-mapped configuration interface with a size of two bytes at the base
|
||||
address 0x2e or 0x4e. Other PNP devices have their configuration
|
||||
interface at other addresses.
|
||||
|
||||
The two byte registers allow access to an indirect 256 bytes big
|
||||
register space that contains the configuration. By writing the index
|
||||
to the lower byte (e.g. 0x2e), you can access the register contents at
|
||||
that index by reading/writing the higher byte (e.g. 0x2f).
|
||||
|
||||
To prevent accidental changes of the Super I/O (SIO) configuration,
|
||||
the SIOs need a configuration mode unlock sequence. After changing the
|
||||
configuration, the configuration mode should be left again, by sending
|
||||
the configuration mode lock sequence.
|
||||
|
||||
## Logical device numbers (LDN)
|
||||
|
||||
Each PNP device can contain multiple logical devices. The bytes from
|
||||
0x00 to 0x2f in the indirect configuration register space are common
|
||||
for all LDNs, but some SIO chips require a certain LDN to be selected
|
||||
in order to write certain registers in there. An LDN gets selected by
|
||||
writing the LDN number to the LDN select register 0x07. Registers 0x30
|
||||
to 0xFF are specific to each LDN number.
|
||||
|
||||
coreboot encodes the physical LDN number in the lower byte of the LDN
|
||||
number.
|
||||
|
||||
### Virtual logical device numbers
|
||||
|
||||
Register 0x30 is the LDN enable register and since it is an 8 bit
|
||||
register, it can contain up to 8 enable bits for different parts of
|
||||
the functionality of that logical device. To set a certain enable bit
|
||||
in one physical LDN, the concept of virtual LDNs was introduced.
|
||||
Virtual LDNs share the registers of their base LDN, but allow to
|
||||
specify which part of a LDN should be enabled.
|
||||
|
||||
coreboot encodes the enable bit number and by that the virtual LDN
|
||||
part in the lower 3 bits of the higher byte of the LDN number.
|
||||
|
||||
## I/O resources
|
||||
|
||||
Starting at register address 0x60, each LDN has 2 byte wide I/O base
|
||||
address registers. The size of an I/O resource is always a power of
|
||||
two.
|
||||
|
||||
### I/O resource masks
|
||||
|
||||
The I/O resource masks encode both the size and the maximum base
|
||||
address of the corresponding IO resource. The number of zeros counted
|
||||
from the least significant bit encode the resource size. If N is the
|
||||
number of LSBs being zero, which can also be zero if the LSB is a one,
|
||||
the resource has N address bits and a size of 2\*\*N bytes. The mask
|
||||
address is also the highest possible address to map the I/O region.
|
||||
|
||||
A typical example for an I/O resource mask is 0x07f8 which is
|
||||
0b0000011111111000 in binary notation. The three LSBs are zeros here,
|
||||
so it's an eight byte I/O resource with three address offset bits
|
||||
inside the resource. The highest base address it can be mapped to is
|
||||
0x07f8, so the region will end at 0x07ff.
|
||||
|
||||
The Super I/O datasheets typically contain the information about the
|
||||
I/O resource masks. On most Super I/O chips the mask can also be found
|
||||
out by writing 0xffff to the corresponding I/O base address register
|
||||
and reading back the value; since the lowest and highest bits are
|
||||
hard-wired to zero according to the I/O resource size and maximal
|
||||
possible I/O address, this gives the mask.
|
||||
|
||||
## IRQ resources
|
||||
|
||||
Each physical LDN has up to two configurable interrupt request
|
||||
register pairs 0x70, 0x71 and 0x72, 0x73. Each pair can be configured
|
||||
to use a certain IRQ number. Writing 1 to 15 into the first register
|
||||
selects the IRQ number generated by the corresponding IRQ source and
|
||||
enables IRQ generation; writing 0 to it disables the generation of
|
||||
IRQs for the source. The second register selects the IRQ type (level
|
||||
or edge) and IRQ level (high or low). For LPC SIOs the IRQ type is
|
||||
hard-wired to edge.
|
||||
|
||||
On the LPC bus a shared SERIRQ line is used to signal IRQs to the
|
||||
host; the IRQ number gets encoded by the number of LPC clock cycles
|
||||
after the start frame before the device pulls the open drain
|
||||
connection low.
|
||||
|
||||
SERIRQ can be used in two different modes: In the continuous SERIRQ
|
||||
mode the host continuously sends IRQ frame starts and the devices
|
||||
signal their IRQ request by pulling low the SERIRQ line at the right
|
||||
time. In quiet SERIRQ mode the host doesn't send IRQ frame starts, so
|
||||
the devices have to send both the IRQ frame start and the encoded IRQ
|
||||
number. The quiet mode is often broken.
|
||||
|
||||
## DRQ resources
|
||||
|
||||
Each physical LDN has two legacy ISA-style DMA request channel
|
||||
registers at 0x74 and 0x75. Those are only used for legacy devices
|
||||
like parallel printer ports or floppy disk controllers.
|
||||
|
||||
Each device using LPC legacy DMA needs its own LDMA line to the host.
|
||||
Some newer chipsets have dropped the LDMA line and with that the
|
||||
legacy DMA capability on LPC.
|
||||
@ -45,12 +45,33 @@ chip superio/common
|
||||
end
|
||||
```
|
||||
|
||||
## Automatically generated methods
|
||||
|
||||
The following methods are generated for each SuperIO:
|
||||
## AMTX()
|
||||
Acquire the global mutex and enter config mode.
|
||||
It's called this at the begining of an atomic operation to make sure
|
||||
no other ACPI code messes with the config space while working on it.
|
||||
|
||||
## RMTX()
|
||||
Exit config mode and release the global mutex.
|
||||
It's called at the end of an atomic operation.
|
||||
|
||||
## SLDN(Arg0)
|
||||
Selects the (virtual) LDN given as Arg0.
|
||||
This method isn't guarded with the global mutex.
|
||||
|
||||
## DLDN(Arg0)
|
||||
Disables the (virtual) LDN given as Arg0.
|
||||
This method aquires the global mutex.
|
||||
|
||||
## QLDN(Arg0)
|
||||
Queries the state of the (virtual) LDN given as Arg0.
|
||||
This method quires the global mutex.
|
||||
|
||||
## TODO
|
||||
|
||||
1) Add ACPI HIDs to every SuperIO driver
|
||||
2) Don't guess ACPI HID of LDNs if it's known
|
||||
3) Add "enter config" and "exit config" bytes
|
||||
4) Generate support methods that allow
|
||||
2) Generate support methods that allow
|
||||
* Setting resource settings at runtime
|
||||
* Getting resource settings at runtime
|
||||
* Disabling LDNs at runtime
|
||||
|
||||
@ -7,4 +7,5 @@ This section contains documentation about coreboot on specific SuperIOs.
|
||||
- [NPCD378](nuvoton/npcd378.md)
|
||||
|
||||
## Common
|
||||
- [PNP devices](common/pnp.md)
|
||||
- [SSDT generator for generic SuperIOs](common/ssdt.md)
|
||||
|
||||
@ -15,7 +15,7 @@ Download, configure, and build coreboot
|
||||
$ cd coreboot
|
||||
|
||||
### Step 3 - Build the coreboot toolchain
|
||||
Please note that this can take a significant amount of time
|
||||
Please note that this can take a significant amount of time.
|
||||
|
||||
$ make crossgcc-i386 CPUS=$(nproc)
|
||||
|
||||
@ -53,7 +53,7 @@ These should be the default selections, so if anything else was set, run
|
||||
select < Exit >
|
||||
select < Yes >
|
||||
|
||||
##### check your configuration (optional step):
|
||||
##### Check your configuration (optional step):
|
||||
|
||||
$ make savedefconfig
|
||||
$ cat defconfig
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
# Tutorial, part 2: Submitting a patch to coreboot.org
|
||||
|
||||
## Part 1: Setting up an account at coreboot.org
|
||||
## Step 1: Set up an account at coreboot.org
|
||||
|
||||
If you already have an account, skip to Part 2.
|
||||
If you already have an account, skip to Step 2.
|
||||
|
||||
Otherwise, go to <https://review.coreboot.org> in your preferred web browser.
|
||||
Select **Sign in** in the upper right corner.
|
||||
@ -12,13 +12,13 @@ select **Google OAuth2** (gerrit-oauth-provider plugin). **Note:** Your
|
||||
username for the account will be the username of the account you used to
|
||||
sign-in with. (ex. your Google username).
|
||||
|
||||
## Part 2a: Set up RSA Private/Public Key
|
||||
## Step 2a: Set up RSA Private/Public Key
|
||||
|
||||
If you prefer to use an HTTP password instead, skip to Part 2b.
|
||||
If you prefer to use an HTTP password instead, skip to Step 2b.
|
||||
|
||||
For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
|
||||
<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh>
|
||||
and follow the instructions there. Then, skip to Part 3.
|
||||
and follow the instructions there. Then, skip to Step 3.
|
||||
|
||||
Additionally, that section of the Web site provides explanation on starting
|
||||
an ssh-agent, which may be particularly helpful for those who anticipate
|
||||
@ -44,7 +44,7 @@ forego the password altogether as you will be using it very often.
|
||||
Open `id_rsa.pub`, copy all contents and paste into the textbox under
|
||||
"Add SSH Public Key" in the https://review.coreboot.org webpage.
|
||||
|
||||
## Part 2b: Setting up an HTTP Password
|
||||
## Step 2b: Set up an HTTP Password
|
||||
|
||||
Alternatively, instead of using SSH keys, you can use an HTTP password. To do so,
|
||||
after you select your name and click on **Settings** on the left-hand side, rather
|
||||
@ -58,7 +58,21 @@ the password, and add the following to your `$HOME/.netrc` file:
|
||||
where YourUserNameHere is your username, and YourPasswordHere is the password you
|
||||
just generated.
|
||||
|
||||
## Part 3: Clone coreboot and configure it for submitting patches
|
||||
If your system is behind a snooping HTTPS proxy, you might also have to
|
||||
make its SSL certificate known to curl, a system specific operation.
|
||||
If that's not possible for some reason, you can also disable SSL
|
||||
certificate verification in git:
|
||||
|
||||
git config [--global] http.sslVerify [true|false]
|
||||
|
||||
The `--global` argument sets it for all git transfers of your local
|
||||
user, `false` means not to validate the certificate.
|
||||
|
||||
If that still doesn't allow you to pull or push changes to the server, the
|
||||
proxy is likely tampering with the data stream, in which case there's nothing
|
||||
we can do.
|
||||
|
||||
## Step 3: Clone coreboot and configure it for submitting patches
|
||||
|
||||
On Gerrit, click on the **Browse** tab in the upper left corner and select
|
||||
**Repositories**. From the listing, select the "coreboot" repo. You may have
|
||||
@ -87,7 +101,7 @@ and other configurations.
|
||||
cd coreboot
|
||||
make gitconfig
|
||||
|
||||
## Part 4: Submit a commit
|
||||
## Step 4: Submit a commit
|
||||
|
||||
An easy first commit to make is fixing existing checkpatch errors and warnings
|
||||
in the source files. To see errors that are already present, build the files in
|
||||
@ -105,9 +119,9 @@ and can be submitted for review.
|
||||
Once you finish making your desired changes, use the command line to stage
|
||||
and submit your changes. An alternative and potentially easier way to stage
|
||||
and submit commits is to use git cola, a graphical user interface for git. For
|
||||
instructions on how to do so, skip to Part 4b.
|
||||
instructions on how to do so, skip to Step 4b.
|
||||
|
||||
## Part 4a: Using the command line to stage and submit a commit
|
||||
## Step 4a: Use the command line to stage and submit a commit
|
||||
|
||||
To use the command line to stage a commit, run
|
||||
|
||||
@ -157,17 +171,17 @@ commit, you wish to make changes to it, running `git commit --amend` allows
|
||||
you to take back your commit and amend it.
|
||||
|
||||
When you are done with your commit, run `git push` to push your commit to
|
||||
coreboot.org. **Note:** To submit as a draft, use
|
||||
`git push origin HEAD:refs/drafts/master`. Submitting as a draft means that
|
||||
your commit will be on coreboot.org, but is only visible to those you add
|
||||
as reviewers.
|
||||
coreboot.org. **Note:** To submit as a private patch, use
|
||||
`git push origin HEAD:refs/for/master%private`. Submitting as a private patch
|
||||
means that your commit will be on review.coreboot.org, but is only visible to
|
||||
yourself and those you add as reviewers.
|
||||
|
||||
This has been a quick primer on how to submit a change to Gerrit for review
|
||||
using git. You may wish to review the [Gerrit code review workflow
|
||||
documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review),
|
||||
especially if you plan to work on multiple changes at the same time.
|
||||
|
||||
## Part 4b: Using git cola to stage and submit a commit
|
||||
## Step 4b: Use git cola to stage and submit a commit
|
||||
|
||||
If git cola is not installed on your machine, see
|
||||
<https://git-cola.github.io/downloads.html> for download instructions.
|
||||
@ -227,11 +241,8 @@ explained in the extended description.
|
||||
|
||||
When ready, select 'Commit' again. Once all errors have been satisfied
|
||||
and the commit succeeds, move to the command line and run `git push`.
|
||||
**Note:** To submit as a draft, use `git push origin HEAD:refs/drafts/master`.
|
||||
Submitting as a draft means that your commit will be on coreboot.org, but is
|
||||
only visible to those you add as reviewers.
|
||||
|
||||
## Part 5: Getting your commit reviewed
|
||||
## Step 5: Let others review your commit
|
||||
|
||||
Your commits can now be seen on review.coreboot.org if you select "Your"
|
||||
and click on "Changes" and can be reviewed by others. Your code will
|
||||
@ -241,7 +252,7 @@ users may also give your commit +1. For a commit to be merged, it needs
|
||||
to receive a +2. **Note:** A +1 and a +1 does not make a +2. Only certain users
|
||||
can give a +2.
|
||||
|
||||
## Part 6 (optional): bash-git-prompt
|
||||
## Step 6 (optional): bash-git-prompt
|
||||
|
||||
To help make it easier to understand the state of the git repository
|
||||
without running `git status` or `git log`, there is a way to make the
|
||||
|
||||
@ -14,9 +14,6 @@ settings. `Perl`
|
||||
platform. `C`
|
||||
* __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
|
||||
platforms `Go`
|
||||
* __bimgtool__ - A simple tool which generates and verifies boot images
|
||||
in the BIMG format, used in systems designed by Imagination
|
||||
Technologies, for example the Pistachio SoC. `C`
|
||||
* __bincfg__ - Compiler/Decompiler for data blobs with specs `Lex`
|
||||
`Yacc`
|
||||
* __board_status__ - Tools to collect logs and upload them to the board
|
||||
|
||||
111
MAINTAINERS
111
MAINTAINERS
@ -163,6 +163,11 @@ M: Patrick Rudolph <siro@das-labor.org>
|
||||
S: Maintained
|
||||
F: src/mainboard/lenovo/
|
||||
|
||||
LENOVO G505S MAINBOARD
|
||||
M: Mike Banon <mikebdp2@gmail.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/lenovo/g505s/
|
||||
|
||||
APPLE MAINBOARDS
|
||||
M: Evgeny Zinoviev <me@ch1p.io>
|
||||
S: Maintained
|
||||
@ -217,18 +222,10 @@ F: src/mainboard/google/parrot/
|
||||
F: src/mainboard/google/slippy/
|
||||
F: src/mainboard/google/stout/
|
||||
|
||||
OCP MAINBOARDS
|
||||
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
||||
M: Patrick Rudolph <patrick.rudolph@9elements.com>
|
||||
S: Supported
|
||||
F: src/mainboard/ocp/wedge100s/
|
||||
F: src/mainboard/ocp/monolake/
|
||||
|
||||
OPENCELLULAR MAINBOARDS
|
||||
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
||||
M: Patrick Rudolph <patrick.rudolph@9elements.com>
|
||||
S: Supported
|
||||
F: src/mainboard/opencellular/rotundu/
|
||||
F: src/mainboard/opencellular/elgon/
|
||||
|
||||
PURISM MAINBOARDS
|
||||
@ -242,30 +239,6 @@ S: Maintained
|
||||
F: src/mainboard/samsung/lumpy/
|
||||
F: src/mainboard/samsung/stumpy/
|
||||
|
||||
INTEL MINNOWBOARD MAX MAINBOARD
|
||||
M: Huang Jin <huang.jin@intel.com>
|
||||
M: York Yang <york.yang@intel.com>
|
||||
S: Supported
|
||||
F: src/mainboard/intel/minnowmax/
|
||||
|
||||
INTEL FSP BAYTRAIL CHIP & CRBs
|
||||
M: Huang Jin <huang.jin@intel.com>
|
||||
M: York Yang <york.yang@intel.com>
|
||||
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
||||
S: Supported
|
||||
F: src/soc/intel/fsp_baytrail/
|
||||
F: src/vendorcode/intel/fsp1_0/baytrail/
|
||||
F: src/mainboard/intel/bakersport_fsp/
|
||||
F: src/mainboard/intel/bayleybay_fsp/
|
||||
|
||||
INTEL FSP BROADWELL-DE SOC & CRB
|
||||
M: York Yang <york.yang@intel.com>
|
||||
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
||||
S: Supported
|
||||
F: src/soc/intel/fsp_broadwell_de/
|
||||
F: src/vendorcode/intel/fsp1_0/broadwell_de/
|
||||
F: src/mainboard/intel/camelbackmountain_fsp/
|
||||
|
||||
INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB
|
||||
M: Vanessa Eusebio <vanessa.f.eusebio@intel.com>
|
||||
M: David Guckian <david.guckian@intel.com>
|
||||
@ -274,24 +247,6 @@ F: src/mainboard/intel/harcuvar/
|
||||
F: src/soc/intel/denverton_ns/
|
||||
F: src/vendorcode/intel/fsp/fsp2_0/denverton_ns/
|
||||
|
||||
FSP 1.0 RANGELEY & CRB
|
||||
M: David Guckian <david.guckian@intel.com>
|
||||
M: Fei Wang <fei.z.wang@intel.com>
|
||||
S: Supported
|
||||
F: src/cpu/intel/fsp_model_406dx/
|
||||
F: src/northbridge/intel/fsp_rangeley/
|
||||
F: src/southbridge/intel/fsp_rangeley/
|
||||
F: src/vendorcode/intel/fsp1_0/rangeley/
|
||||
F: src/mainboard/intel/mohonpeak/
|
||||
|
||||
INTEL FSP 1.0
|
||||
M: Huang Jin <huang.jin@intel.com>
|
||||
M: York Yang <york.yang@intel.com>
|
||||
M: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
|
||||
S: Supported
|
||||
F: src/drivers/intel/fsp1_0/
|
||||
F: src/vendorcode/intel/fsp1_0/broadwell_de/
|
||||
|
||||
INTEL FSP 1.1
|
||||
M: Lee Leahy <leroy.p.leahy@intel.com>
|
||||
M: Huang Jin <huang.jin@intel.com>
|
||||
@ -332,21 +287,10 @@ M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
S: Maintained
|
||||
F: src/mainboard/asrock/h81m-hds/
|
||||
|
||||
ASUS KFSN4-DRE & KFSN4-DRE_K8 MAINBOARDS
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
F: src/mainboard/asus/kfsn4-dre/
|
||||
F: src/mainboard/asus/kfsn4-dre_k8/
|
||||
|
||||
ASUS KCMA-D8 MAINBOARD
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
F: src/mainboard/asus/kcma-d8/
|
||||
|
||||
ASUS KGPE-D16 MAINBOARD
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
F: src/mainboard/asus/kgpe-d16/
|
||||
ASUS AM1I-A MAINBOARD
|
||||
M: Mike Banon <mikebdp2@gmail.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/asus/am1i-a/
|
||||
|
||||
ASUS MAXIMUS IV GENE-Z MAINBOARD
|
||||
M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
@ -383,8 +327,6 @@ SIEMENS MC_xxxx MAINBOARDS
|
||||
M: Werner Zeh <werner.zeh@siemens.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/siemens/mc_apl1/
|
||||
F: src/mainboard/siemens/mc_bdx1/
|
||||
F: src/mainboard/siemens/mc_tcu3/
|
||||
|
||||
SUPERMICRO X10SLM+-F MAINBOARD
|
||||
M: Tristan Corrick <tristan@corrick.kiwi>
|
||||
@ -402,30 +344,18 @@ M: Wim Vervoorn <wvervoorn@eltan.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/facebook/fbg1701/
|
||||
|
||||
FACEBOOK MONOLITH MAINBOARD
|
||||
M: Frans Hendriks <fhendriks@eltan.com>
|
||||
M: Wim Vervoorn <wvervoorn@eltan.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/facebook/monolith/
|
||||
|
||||
PORTWELL PQ-M107 MAINBOARD
|
||||
M: Frans Hendriks <fhendriks@eltan.com>
|
||||
M: Wim Vervoorn <wvervoorn@eltan.com>
|
||||
S: Maintained
|
||||
F: src/mainboard/portwell/m107/
|
||||
|
||||
AMD FAMILY10H & FAMILY15H (NON-AGESA) CPUS & NORTHBRIDGE
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
F: src/cpu/amd/family_10h-family_15h/
|
||||
F: src/northbridge/amd/amdfam10/
|
||||
F: src/northbridge/amd/amdmct/
|
||||
F: src/northbridge/amd/amdht/
|
||||
|
||||
AMD SB700 (NON-CIMX) SOUTHBRIDGE
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
F: src/southbridge/amd/sb700/
|
||||
|
||||
AMD SR5650 SOUTHBRIDGE
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
F: src/southbridge/amd/sr5650/
|
||||
|
||||
ASPEED AST2050 DRIVER & COMMON CODE
|
||||
M: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
||||
S: Supported
|
||||
@ -477,12 +407,6 @@ F: util/arm_boot_tools/
|
||||
F: util/exynos/
|
||||
F: util/ipqheader/
|
||||
|
||||
MIPS ARCHITECTURE
|
||||
F: src/arch/mips/
|
||||
F: src/cpu/mips/
|
||||
F: src/soc/imgtec/
|
||||
F: util/bimgtool/
|
||||
|
||||
X86 ARCHITECTURE
|
||||
F: src/arch/x86/
|
||||
F: src/cpu/x86/
|
||||
@ -508,11 +432,6 @@ F: src/northbridge/amd/
|
||||
F: src/southbridge/amd/
|
||||
F: src/include/cpu/amd/
|
||||
|
||||
VIA SUPPORT
|
||||
F: src/cpu/via/
|
||||
F: src/northbridge/via/
|
||||
F: src/southbridge/via/
|
||||
|
||||
LINT SCRIPTS
|
||||
M: Patrick Georgi <patrick@georgi-clan.de>
|
||||
M: Martin Roth <gaumless@gmail.com>
|
||||
|
||||
2
Makefile
2
Makefile
@ -119,7 +119,7 @@ help_coreboot help::
|
||||
|
||||
# This include must come _before_ the pattern rules below!
|
||||
# Order _does_ matter for pattern rules.
|
||||
include $(srck)/Makefile
|
||||
include $(srck)/Makefile.inc
|
||||
|
||||
# Three cases where we don't need fully populated $(obj) lists:
|
||||
# 1. when no .config exists
|
||||
|
||||
37
Makefile.inc
37
Makefile.inc
@ -94,7 +94,7 @@ subdirs-y += src/superio
|
||||
subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
|
||||
subdirs-y += src/cpu src/vendorcode
|
||||
subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen
|
||||
subdirs-y += util/futility util/marvell util/bincfg
|
||||
subdirs-y += util/futility util/marvell util/bincfg util/supermicro
|
||||
subdirs-y += $(wildcard src/arch/*)
|
||||
subdirs-y += src/mainboard/$(MAINBOARDDIR)
|
||||
subdirs-y += src/security
|
||||
@ -182,9 +182,9 @@ ramstage-postprocess=$$(eval DEPENDENCIES+=$$(addsuffix .d,$$(basename $(1)))) \
|
||||
$(eval $(d)ramstage.a: $(call files-in-dir,$(d),$(filter-out %.ld,$(1))); rm -f $$@ && $(AR_ramstage) rcsT $$@ $$^ ) \
|
||||
$(eval ramstage-objs:=$(d)ramstage.a $(filter-out $(filter-out %.ld, $(call files-in-dir,$(d),$(1))),$(ramstage-objs))))
|
||||
|
||||
decompressor-generic-ccopts += -D__PRE_RAM__ -D__DECOMPRESSOR__
|
||||
bootblock-generic-ccopts += -D__PRE_RAM__ -D__BOOTBLOCK__
|
||||
romstage-generic-ccopts += -D__PRE_RAM__ -D__ROMSTAGE__
|
||||
decompressor-generic-ccopts += -D__DECOMPRESSOR__
|
||||
bootblock-generic-ccopts += -D__BOOTBLOCK__
|
||||
romstage-generic-ccopts += -D__ROMSTAGE__
|
||||
ramstage-generic-ccopts += -D__RAMSTAGE__
|
||||
ifeq ($(CONFIG_TRACE),y)
|
||||
ramstage-c-ccopts += -finstrument-functions
|
||||
@ -226,7 +226,7 @@ $(foreach type,ads adb, \
|
||||
# Add handler to copy linker scripts
|
||||
define generic-objs_ld_template_gen
|
||||
de$(EMPTY)fine $(1)-objs_ld_template
|
||||
$$(call src-to-obj,$1,$$(1).ld): $$(1).ld $(obj)/config.h
|
||||
$$(call src-to-obj,$1,$$(1).ld): $$(1).ld $(obj)/config.h $(obj)/fmap_config.h
|
||||
@printf " CP $$$$(subst $$$$(obj)/,,$$$$(@))\n"
|
||||
$$(CC_$(1)) -MMD $$(CPPFLAGS_$(1)) $$($(1)-ld-ccopts) $(PREPROCESS_ONLY) -include $(obj)/config.h -MT $$$$@ -o $$$$@ $$$$<
|
||||
en$(EMPTY)def
|
||||
@ -258,7 +258,10 @@ endef
|
||||
# ResourceTemplate is the correct code.
|
||||
# As it's valid ASL, disable the warning.
|
||||
EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
|
||||
IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING)
|
||||
# Redundant offset remarks are not useful in any way and are masking useful
|
||||
# ones that might indicate an issue so it is better to hide them.
|
||||
REDUNDANT_OFFSET_REMARK = 2158
|
||||
IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK)
|
||||
|
||||
define asl_template
|
||||
$(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml
|
||||
@ -416,6 +419,7 @@ CFLAGS_common += -fno-delete-null-pointer-checks
|
||||
ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
|
||||
CFLAGS_common += -Wno-packed-not-aligned
|
||||
CFLAGS_common += -fconserve-stack
|
||||
CFLAGS_common += -Wnull-dereference -Wreturn-type
|
||||
# cf. commit f69a99db (coreboot: x86: enable gc-sections)
|
||||
CFLAGS_common += -Wno-unused-but-set-variable
|
||||
endif
|
||||
@ -482,9 +486,9 @@ ifeq ($(CONFIG_DEBUG_ADA_CODE),y)
|
||||
ADAFLAGS_common += -gnata
|
||||
endif
|
||||
|
||||
additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \
|
||||
additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \
|
||||
$(objutil)/options $(objutil)/amdfwtool \
|
||||
$(objutil)/cbootimage $(objutil)/bimgtool
|
||||
$(objutil)/cbootimage
|
||||
|
||||
export $(COREBOOT_EXPORTS)
|
||||
|
||||
@ -548,16 +552,6 @@ ifeq ($(_WINCHECK),Cygwin)
|
||||
STACK=-Wl,--stack,16384000
|
||||
endif
|
||||
|
||||
# this allows ccache to prepend itself
|
||||
# (ccache handling happens first)
|
||||
ROMCC_BIN= $(objutil)/romcc/romcc
|
||||
ROMCC?=$(ROMCC_BIN)
|
||||
$(ROMCC_BIN): $(top)/util/romcc/romcc.c
|
||||
@printf " HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n"
|
||||
@# Note: Adding -O2 here might cause problems. For details see:
|
||||
@# https://www.coreboot.org/pipermail/coreboot/2010-February/055825.html
|
||||
$(HOSTCC) -g $(STACK) -Wall -o $@ $<
|
||||
|
||||
BINCFG:=$(objutil)/bincfg/bincfg
|
||||
|
||||
IFDTOOL:=$(objutil)/ifdtool/ifdtool
|
||||
@ -577,11 +571,6 @@ FUTILITY?=$(objutil)/futility/futility
|
||||
|
||||
subdirs-y += util/nvidia
|
||||
|
||||
BIMGTOOL:=$(objutil)/bimgtool/bimgtool
|
||||
$(BIMGTOOL): $(top)/util/bimgtool/bimgtool.c
|
||||
@printf " HOSTCC $(subst $(obj)/,,$(@))\n"
|
||||
$(HOSTCC) $(HOSTCFLAGS) -o $@ $<
|
||||
|
||||
$(obj)/config.h: $(objutil)/kconfig/conf
|
||||
|
||||
#######################################################################
|
||||
@ -652,7 +641,7 @@ install-git-commit-clangfmt:
|
||||
include util/crossgcc/Makefile.inc
|
||||
|
||||
.PHONY: tools
|
||||
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL)
|
||||
tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo
|
||||
|
||||
###########################################################################
|
||||
# Common recipes for all stages
|
||||
|
||||
@ -34,7 +34,6 @@ coreboot supports a wide range of chipsets, devices, and mainboards.
|
||||
For details please consult:
|
||||
|
||||
* <https://www.coreboot.org/Supported_Motherboards>
|
||||
* <https://www.coreboot.org/Supported_Chipsets_and_Devices>
|
||||
|
||||
|
||||
Build Requirements
|
||||
|
||||
@ -4,7 +4,6 @@ CONFIG_FATAL_ASSERTS=y
|
||||
CONFIG_DEBUG_CBFS=y
|
||||
CONFIG_DEBUG_PIRQ=y
|
||||
CONFIG_DEBUG_MALLOC=y
|
||||
CONFIG_DEBUG_ACPI=y
|
||||
CONFIG_TRACE=y
|
||||
CONFIG_DEBUG_BOOT_STATE=y
|
||||
CONFIG_DEBUG_ADA_CODE=y
|
||||
|
||||
12
configs/config.facebook_fbg1701
Normal file
12
configs/config.facebook_fbg1701
Normal file
@ -0,0 +1,12 @@
|
||||
CONFIG_VENDOR_FACEBOOK=y
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000
|
||||
CONFIG_ONBOARD_SAMSUNG_MEM=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
|
||||
CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
|
||||
CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-4c-04"
|
||||
CONFIG_VENDORCODE_ELTAN_MBOOT=y
|
||||
CONFIG_VENDORCODE_ELTAN_VBOOT=y
|
||||
CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_FILE="3rdparty/vboot/tests/devkeys-acc/key_hadoken.vbpubk2"
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
CONFIG_DISPLAY_HOBS=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
|
||||
5
configs/config.google_kevin_secdata_mock
Normal file
5
configs/config.google_kevin_secdata_mock
Normal file
@ -0,0 +1,5 @@
|
||||
CONFIG_VENDOR_GOOGLE=y
|
||||
CONFIG_BOARD_GOOGLE_KEVIN=y
|
||||
CONFIG_CHROMEOS=y
|
||||
CONFIG_VBOOT_MOCK_SECDATA=y
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
40
configs/config.google_meep_cros
Normal file
40
configs/config.google_meep_cros
Normal file
@ -0,0 +1,40 @@
|
||||
CONFIG_VENDOR_GOOGLE=y
|
||||
CONFIG_BOARD_GOOGLE_MEEP=y
|
||||
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SPI_FLASH_SMM=y
|
||||
CONFIG_USE_BLOBS=y
|
||||
CONFIG_ANY_TOOLCHAIN=y
|
||||
|
||||
# Chrome OS
|
||||
CONFIG_CHROMEOS=y
|
||||
CONFIG_HAS_RECOVERY_MRC_CACHE=y
|
||||
CONFIG_MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN=y
|
||||
|
||||
# Event Logging
|
||||
CONFIG_CMOS_POST=y
|
||||
CONFIG_CMOS_POST_EXTRA=y
|
||||
CONFIG_CMOS_POST_OFFSET=0x70
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
CONFIG_ELOG=y
|
||||
CONFIG_ELOG_GSMI=y
|
||||
CONFIG_ELOG_BOOT_COUNT=y
|
||||
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
|
||||
|
||||
# Firmware Support Package
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
|
||||
# Management Engine
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
|
||||
# CONFIG_CONSOLE_SERIAL is not set
|
||||
|
||||
CONFIG_FATAL_ASSERTS=y
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
# GLK specific setting to auto select all the correct settings.
|
||||
CONFIG_UART_DEBUG=y
|
||||
CONFIG_NO_BOOTBLOCK_CONSOLE=y
|
||||
@ -3,7 +3,6 @@ CONFIG_VENDOR_GOOGLE=y
|
||||
CONFIG_BOARD_GOOGLE_REEF=y
|
||||
CONFIG_CHROMEOS=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
|
||||
CONFIG_ELOG_GSMI=y
|
||||
CONFIG_ELOG_BOOT_COUNT=y
|
||||
CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
|
||||
|
||||
9
configs/config.intel.cfl_rvp11_fsp_car
Normal file
9
configs/config.intel.cfl_rvp11_fsp_car
Normal file
@ -0,0 +1,9 @@
|
||||
CONFIG_USE_BLOBS=y
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
CONFIG_INTEL_GMA_VBT_FILE="3rdparty/fsp/CoffeeLakeFspBinPkg/SampleCode/Vbt/Vbt.bin"
|
||||
CONFIG_BOARD_INTEL_COFFEELAKE_RVP11=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_USE_CANNONLAKE_FSP_CAR=y
|
||||
CONFIG_RUN_FSP_GOP=y
|
||||
CONFIG_FSP_USE_REPO=y
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
@ -8,7 +8,6 @@ CONFIG_DEBUG_RAM_SETUP=y
|
||||
CONFIG_DEBUG_SMBUS=y
|
||||
CONFIG_DEBUG_SMI=y
|
||||
CONFIG_DEBUG_MALLOC=y
|
||||
CONFIG_DEBUG_ACPI=y
|
||||
CONFIG_DEBUG_BOOT_STATE=y
|
||||
CONFIG_DEBUG_ADA_CODE=y
|
||||
CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
|
||||
|
||||
@ -7,7 +7,6 @@ CONFIG_DEBUG_CBFS=y
|
||||
CONFIG_DEBUG_SMBUS=y
|
||||
CONFIG_DEBUG_SMI=y
|
||||
CONFIG_DEBUG_MALLOC=y
|
||||
CONFIG_DEBUG_ACPI=y
|
||||
CONFIG_DEBUG_SPI_FLASH=y
|
||||
CONFIG_DEBUG_BOOT_STATE=y
|
||||
CONFIG_DEBUG_ADA_CODE=y
|
||||
|
||||
@ -1,2 +0,0 @@
|
||||
CONFIG_VENDOR_UP=y
|
||||
CONFIG_VBOOT=y
|
||||
3
configs/config.up_squared.vboot_spi_flash_console
Normal file
3
configs/config.up_squared.vboot_spi_flash_console
Normal file
@ -0,0 +1,3 @@
|
||||
CONFIG_VENDOR_UP=y
|
||||
CONFIG_VBOOT=y
|
||||
CONFIG_CONSOLE_SPI_FLASH=y
|
||||
@ -40,21 +40,12 @@ config PAYLOAD_FIT
|
||||
You will be able to specify the location and file name of the
|
||||
payload image later.
|
||||
|
||||
config PAYLOAD_BAYOU
|
||||
bool "Bayou"
|
||||
depends on ARCH_X86
|
||||
help
|
||||
Select this option if you want to set bayou as your primary
|
||||
payload.
|
||||
|
||||
source "payloads/external/*/Kconfig.name"
|
||||
|
||||
endchoice
|
||||
|
||||
source "payloads/external/*/Kconfig"
|
||||
|
||||
source "payloads/bayou/Kconfig"
|
||||
|
||||
config PAYLOAD_FILE
|
||||
string "Payload path and filename"
|
||||
depends on PAYLOAD_ELF || PAYLOAD_FIT
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,67 +0,0 @@
|
||||
##
|
||||
## This file is part of the bayou project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License version 2 as
|
||||
## published by the Free Software Foundation.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
|
||||
CONFIG_LZMA=y
|
||||
CONFIG_NRV2B=y
|
||||
CONFIG_BUILTIN_LAR=y
|
||||
|
||||
PBUILDER_CONFIG=bayou.xml
|
||||
BUILTIN_LAR=builtin.lar
|
||||
|
||||
export src := $(CURDIR)
|
||||
export obj := $(src)/build
|
||||
|
||||
LIBPAYLOAD_DIR := $(obj)/libpayload
|
||||
|
||||
CC?=gcc
|
||||
STRIP?=strip
|
||||
OBJCOPY?=objcopy
|
||||
|
||||
FFLAGS-y=
|
||||
FFLAGS-$(CONFIG_BUILTIN_LAR) += -DCONFIG_BUILTIN_LAR
|
||||
FFLAGS-$(CONFIG_LZMA) += -DCONFIG_LZMA
|
||||
FFLAGS-$(CONFIG_NRV2B) += -DCONFIG_NRV2B
|
||||
|
||||
OBJECTS-y=main.o payload.o config.o menu.o self.o
|
||||
OBJECTS-$(CONFIG_LZMA) += lzma.o
|
||||
OBJECTS-$(CONFIG_NRV2B) += nrv2b.o
|
||||
OBJECTS-$(CONFIG_BUILTIN_LAR) += builtin-lar.o
|
||||
|
||||
CFLAGS= -Wall -Werror -Os $(FFLAGS-y)
|
||||
LDFLAGS=-Wl,-T,bayou.ldscript -static
|
||||
LIBGCC=$(shell $(CC) -m32 -print-libgcc-file-name)
|
||||
|
||||
LPCC=$(LIBPAYLOAD_DIR)/bin/lpgcc
|
||||
|
||||
bayou.elf: $(OBJECTS-y)
|
||||
$(LPCC) $(LDFLAGS) -m32 -o $@ $(OBJECTS-y)
|
||||
@$(STRIP) $@
|
||||
|
||||
builtin-lar.o: $(BUILTIN_LAR)
|
||||
@$(OBJCOPY) -I binary -B i386 -O elf32-i386 $(BUILTIN_LAR) $@
|
||||
|
||||
builtin.lar: util/pbuilder/pbuilder
|
||||
@rm -f $@
|
||||
util/pbuilder/pbuilder -c $(PBUILDER_CONFIG) create $@
|
||||
|
||||
util/pbuilder/pbuilder:
|
||||
$(MAKE) -C util/pbuilder
|
||||
|
||||
%.o: %.c
|
||||
$(LPCC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
clean:
|
||||
rm -f *.o bayou.elf builtin.lar
|
||||
$(MAKE) -C util/pbuilder clean
|
||||
@ -1,83 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef BAYOU_H_
|
||||
#define BAYOU_H_
|
||||
|
||||
#include <libpayload.h>
|
||||
|
||||
#define BAYOU_MAX_ENTRIES 10
|
||||
|
||||
struct bpt_config {
|
||||
u32 id;
|
||||
u8 timeout;
|
||||
u8 entries;
|
||||
u8 padding[10];
|
||||
};
|
||||
|
||||
struct bpt_pentry {
|
||||
u8 index;
|
||||
u8 parent;
|
||||
u8 type;
|
||||
u8 flags;
|
||||
u8 title[64];
|
||||
u8 nlen;
|
||||
};
|
||||
|
||||
#define BPT_ID 0x30545042
|
||||
#define BPT_TYPE_CHOOSER 0x01
|
||||
#define BPT_TYPE_CHAIN 0x02
|
||||
#define BPT_TYPE_SUBCHAIN 0x03
|
||||
|
||||
#define BPT_FLAG_DEFAULT 0x01
|
||||
#define BPT_FLAG_NOSHOW 0x02
|
||||
|
||||
enum bayou_params {
|
||||
BAYOU_PARAM_NAME = 0,
|
||||
BAYOU_PARAM_LIST,
|
||||
BAYOU_PARAM_DESC,
|
||||
BAYOU_PARAMS_COUNT
|
||||
};
|
||||
|
||||
struct payload {
|
||||
struct bpt_pentry pentry;
|
||||
struct larstat stat;
|
||||
u8 *fptr;
|
||||
char *params[BAYOU_PARAMS_COUNT];
|
||||
};
|
||||
|
||||
struct bayoucfg {
|
||||
u8 timeout;
|
||||
int n_entries;
|
||||
struct payload entries[BAYOU_MAX_ENTRIES];
|
||||
};
|
||||
|
||||
extern struct bayoucfg bayoucfg;
|
||||
|
||||
int verify_self(u8 *ptr);
|
||||
int self_get_params(u8 *fptr, u8 **params);
|
||||
int self_load_and_run(struct payload *p, int *ret);
|
||||
|
||||
void menu(void);
|
||||
|
||||
void run_payload(struct payload *p);
|
||||
char *payload_get_name(struct payload *p);
|
||||
struct payload *payload_get_default(void);
|
||||
void run_payload_timeout(struct payload *p, int timeout);
|
||||
void payload_parse_params(struct payload *pload, u8 *params, int len);
|
||||
|
||||
int get_configuration(struct LAR *lar);
|
||||
|
||||
#endif
|
||||
@ -1,87 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
BASE_ADDRESS = 0x19000;
|
||||
|
||||
OUTPUT_FORMAT(elf32-i386)
|
||||
OUTPUT_ARCH(i386)
|
||||
|
||||
ENTRY(_entry)
|
||||
|
||||
HEAP_SIZE = 16384;
|
||||
STACK_SIZE = 16384;
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = BASE_ADDRESS;
|
||||
|
||||
. = ALIGN(16);
|
||||
_start = .;
|
||||
|
||||
.text : {
|
||||
*(.text._entry)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
}
|
||||
|
||||
.rodata : {
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
}
|
||||
|
||||
.data : {
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
}
|
||||
|
||||
_edata = .;
|
||||
|
||||
.bss : {
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
/* Stack and heap */
|
||||
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
. += HEAP_SIZE;
|
||||
. = ALIGN(16);
|
||||
_eheap = .;
|
||||
|
||||
_estack = .;
|
||||
. += STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
_stack = .;
|
||||
}
|
||||
|
||||
_end = .;
|
||||
|
||||
/DISCARD/ : { *(.comment) *(.note) *(.note.*) }
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
<!--
|
||||
## This file is part of the bayou project.
|
||||
##
|
||||
## Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License version 2 as
|
||||
## published by the Free Software Foundation.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
-->
|
||||
|
||||
<!-- Sample Bayou config file. Adapt as needed, then rename to bayou.xml. -->
|
||||
|
||||
<BayouConfig>
|
||||
<global>
|
||||
<timeout>10</timeout>
|
||||
</global>
|
||||
<payloads>
|
||||
<payload type="chain" flags="default">
|
||||
<title>Default Chain</title>
|
||||
<chain>
|
||||
<file>payloads/passwd.elf</file>
|
||||
<lar>passwd</lar>
|
||||
</chain>
|
||||
<chain>
|
||||
<file>payloads/coreinfo.elf</file>
|
||||
</chain>
|
||||
</payload>
|
||||
<payload type="chooser">
|
||||
<file>payloads/coreinfo.elf</file>
|
||||
</payload>
|
||||
</payloads>
|
||||
</BayouConfig>
|
||||
@ -1,161 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "bayou.h"
|
||||
|
||||
struct bayoucfg bayoucfg;
|
||||
|
||||
static int add_payload(struct LAR *lar, struct larent *larent)
|
||||
{
|
||||
struct payload *payload;
|
||||
int plen;
|
||||
u8 *params = NULL;
|
||||
u8 *fptr;
|
||||
|
||||
if (bayoucfg.n_entries == BAYOU_MAX_ENTRIES)
|
||||
return -1;
|
||||
|
||||
payload = &bayoucfg.entries[bayoucfg.n_entries];
|
||||
|
||||
if (strncmp((char *)larent->name, "payload/", 8))
|
||||
return -1;
|
||||
|
||||
if (larstat(lar, (const char *)larent->name, &payload->stat))
|
||||
return -1;
|
||||
|
||||
/* Make sure the LAR entry is valid. */
|
||||
if (!lfverify(lar, (const char *)larent->name))
|
||||
return -1;
|
||||
|
||||
/* Get a pointer to the start of the file. */
|
||||
fptr = larfptr(lar, (const char *)larent->name);
|
||||
|
||||
if (fptr == NULL)
|
||||
return -1;
|
||||
|
||||
if (!verify_self(fptr))
|
||||
return -1;
|
||||
|
||||
payload->pentry.index = bayoucfg.n_entries;
|
||||
payload->pentry.parent = 0;
|
||||
payload->pentry.type = BPT_TYPE_CHOOSER;
|
||||
payload->pentry.flags = 0;
|
||||
|
||||
plen = self_get_params(fptr, ¶ms);
|
||||
payload_parse_params(payload, params, plen);
|
||||
|
||||
payload->fptr = fptr;
|
||||
|
||||
bayoucfg.n_entries++;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lar_walk_files(struct LAR *lar,
|
||||
int (*cb) (struct LAR *, struct larent *))
|
||||
{
|
||||
struct larent *larent;
|
||||
int ret = 0;
|
||||
|
||||
rewindlar(lar);
|
||||
|
||||
while ((larent = readlar(lar)) != NULL) {
|
||||
if ((ret = cb(lar, larent)))
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* If reading the bayou_payload_table fails for some reason, then construct
|
||||
* a dummy table. All valid payloads in the lar are added as chooser items.
|
||||
*/
|
||||
static void build_dummy_table(struct LAR *lar)
|
||||
{
|
||||
bayoucfg.timeout = 0xFF;
|
||||
bayoucfg.n_entries = 0;
|
||||
|
||||
lar_walk_files(lar, add_payload);
|
||||
}
|
||||
|
||||
int get_configuration(struct LAR *lar)
|
||||
{
|
||||
struct larstat stat;
|
||||
struct bpt_config *bptcfg;
|
||||
u8 *fptr, *ptr;
|
||||
int i;
|
||||
|
||||
/*
|
||||
* If bayou_payload_table doesn't exist, then dummy up
|
||||
* a table from the LAR contents.
|
||||
*/
|
||||
if (larstat(lar, "bayou_payload_table", &stat) ||
|
||||
!lfverify(lar, "bayou_payload_table"))
|
||||
build_dummy_table(lar);
|
||||
|
||||
/* Open up the BPT and get the creamy goodness within. */
|
||||
|
||||
fptr = larfptr(lar, "bayou_payload_table");
|
||||
|
||||
if (fptr == NULL)
|
||||
build_dummy_table(lar);
|
||||
|
||||
bptcfg = (struct bpt_config *)fptr;
|
||||
bayoucfg.timeout = bptcfg->timeout;
|
||||
|
||||
bayoucfg.n_entries = bptcfg->entries;
|
||||
|
||||
if (bayoucfg.n_entries > BAYOU_MAX_ENTRIES) {
|
||||
printf("W: Limiting the number of entries to %d\n",
|
||||
BAYOU_MAX_ENTRIES);
|
||||
bayoucfg.n_entries = BAYOU_MAX_ENTRIES;
|
||||
}
|
||||
|
||||
ptr = fptr + sizeof(struct bpt_config);
|
||||
|
||||
for (i = 0; i < bayoucfg.n_entries; i++) {
|
||||
struct bpt_pentry *entry = (struct bpt_pentry *)ptr;
|
||||
struct payload *p = &(bayoucfg.entries[i]);
|
||||
int plen;
|
||||
u8 *params = NULL;
|
||||
|
||||
memcpy(&p->pentry, entry, sizeof(struct bpt_pentry));
|
||||
|
||||
if (entry->type != BPT_TYPE_CHAIN) {
|
||||
char *lname = (char *)ptr + sizeof(struct bpt_pentry);
|
||||
|
||||
if (larstat(lar, (const char *)lname, &p->stat))
|
||||
build_dummy_table(lar);
|
||||
|
||||
if (!lfverify(lar, (const char *)lname))
|
||||
build_dummy_table(lar);
|
||||
|
||||
fptr = larfptr(lar, (const char *)lname);
|
||||
|
||||
if (verify_self(fptr))
|
||||
p->fptr = fptr;
|
||||
else
|
||||
build_dummy_table(lar);
|
||||
|
||||
plen = self_get_params(fptr, ¶ms);
|
||||
payload_parse_params(p, params, plen);
|
||||
}
|
||||
|
||||
ptr += sizeof(struct bpt_pentry) + entry->nlen;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,43 +0,0 @@
|
||||
/*
|
||||
|
||||
coreboot interface to memory-saving variant of LZMA decoder
|
||||
|
||||
(C)opyright 2006 Carl-Daniel Hailfinger
|
||||
Released under the GNU GPL v2 or later
|
||||
|
||||
Parts of this file are based on C/7zip/Compress/LZMA_C/LzmaTest.c from the LZMA
|
||||
SDK 4.42, which is written and distributed to public domain by Igor Pavlov.
|
||||
|
||||
*/
|
||||
|
||||
#include <libpayload.h>
|
||||
#include "lzmadecode.c"
|
||||
|
||||
unsigned long ulzma(u8 *src, u8 *dst)
|
||||
{
|
||||
unsigned char properties[LZMA_PROPERTIES_SIZE];
|
||||
UInt32 outSize;
|
||||
SizeT inProcessed;
|
||||
SizeT outProcessed;
|
||||
int res;
|
||||
CLzmaDecoderState state;
|
||||
SizeT mallocneeds;
|
||||
unsigned char scratchpad[15980];
|
||||
|
||||
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
|
||||
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
|
||||
if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
|
||||
printf("Incorrect stream properties\n");
|
||||
}
|
||||
mallocneeds = (LzmaGetNumProbs(&state.Properties) * sizeof(CProb));
|
||||
if (mallocneeds > 15980) {
|
||||
printf("Decoder scratchpad too small!\n");
|
||||
}
|
||||
state.Probs = (CProb *)scratchpad;
|
||||
res = LzmaDecode(&state, src + LZMA_PROPERTIES_SIZE + 8, (SizeT)0xffffffff, &inProcessed,
|
||||
dst, outSize, &outProcessed);
|
||||
if (res != 0) {
|
||||
printf("Decoding error = %d\n", res);
|
||||
}
|
||||
return outSize;
|
||||
}
|
||||
@ -1,398 +0,0 @@
|
||||
/*
|
||||
LzmaDecode.c
|
||||
LZMA Decoder (optimized for Speed version)
|
||||
|
||||
LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
|
||||
http://www.7-zip.org/
|
||||
|
||||
LZMA SDK is licensed under two licenses:
|
||||
1) GNU Lesser General Public License (GNU LGPL)
|
||||
2) Common Public License (CPL)
|
||||
It means that you can select one of these two licenses and
|
||||
follow rules of that license.
|
||||
|
||||
SPECIAL EXCEPTION:
|
||||
Igor Pavlov, as the author of this Code, expressly permits you to
|
||||
statically or dynamically link your Code (or bind by name) to the
|
||||
interfaces of this file without subjecting your linked Code to the
|
||||
terms of the CPL or GNU LGPL. Any modifications or additions
|
||||
to this file, however, are subject to the LGPL or CPL terms.
|
||||
*/
|
||||
|
||||
#include "lzmadecode.h"
|
||||
|
||||
#define kNumTopBits 24
|
||||
#define kTopValue ((UInt32)1 << kNumTopBits)
|
||||
|
||||
#define kNumBitModelTotalBits 11
|
||||
#define kBitModelTotal (1 << kNumBitModelTotalBits)
|
||||
#define kNumMoveBits 5
|
||||
|
||||
#define RC_READ_BYTE (*Buffer++)
|
||||
|
||||
#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \
|
||||
{ int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }}
|
||||
|
||||
|
||||
#define RC_TEST { if (Buffer == BufferLim) return LZMA_RESULT_DATA_ERROR; }
|
||||
|
||||
#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2
|
||||
|
||||
|
||||
#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; }
|
||||
|
||||
#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound)
|
||||
#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits;
|
||||
#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits;
|
||||
|
||||
#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \
|
||||
{ UpdateBit0(p); mi <<= 1; A0; } else \
|
||||
{ UpdateBit1(p); mi = (mi + mi) + 1; A1; }
|
||||
|
||||
#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;)
|
||||
|
||||
#define RangeDecoderBitTreeDecode(probs, numLevels, res) \
|
||||
{ int i = numLevels; res = 1; \
|
||||
do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \
|
||||
res -= (1 << numLevels); }
|
||||
|
||||
|
||||
#define kNumPosBitsMax 4
|
||||
#define kNumPosStatesMax (1 << kNumPosBitsMax)
|
||||
|
||||
#define kLenNumLowBits 3
|
||||
#define kLenNumLowSymbols (1 << kLenNumLowBits)
|
||||
#define kLenNumMidBits 3
|
||||
#define kLenNumMidSymbols (1 << kLenNumMidBits)
|
||||
#define kLenNumHighBits 8
|
||||
#define kLenNumHighSymbols (1 << kLenNumHighBits)
|
||||
|
||||
#define LenChoice 0
|
||||
#define LenChoice2 (LenChoice + 1)
|
||||
#define LenLow (LenChoice2 + 1)
|
||||
#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits))
|
||||
#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits))
|
||||
#define kNumLenProbs (LenHigh + kLenNumHighSymbols)
|
||||
|
||||
|
||||
#define kNumStates 12
|
||||
#define kNumLitStates 7
|
||||
|
||||
#define kStartPosModelIndex 4
|
||||
#define kEndPosModelIndex 14
|
||||
#define kNumFullDistances (1 << (kEndPosModelIndex >> 1))
|
||||
|
||||
#define kNumPosSlotBits 6
|
||||
#define kNumLenToPosStates 4
|
||||
|
||||
#define kNumAlignBits 4
|
||||
#define kAlignTableSize (1 << kNumAlignBits)
|
||||
|
||||
#define kMatchMinLen 2
|
||||
|
||||
#define IsMatch 0
|
||||
#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax))
|
||||
#define IsRepG0 (IsRep + kNumStates)
|
||||
#define IsRepG1 (IsRepG0 + kNumStates)
|
||||
#define IsRepG2 (IsRepG1 + kNumStates)
|
||||
#define IsRep0Long (IsRepG2 + kNumStates)
|
||||
#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax))
|
||||
#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits))
|
||||
#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex)
|
||||
#define LenCoder (Align + kAlignTableSize)
|
||||
#define RepLenCoder (LenCoder + kNumLenProbs)
|
||||
#define Literal (RepLenCoder + kNumLenProbs)
|
||||
|
||||
#if Literal != LZMA_BASE_SIZE
|
||||
StopCompilingDueBUG
|
||||
#endif
|
||||
|
||||
int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size)
|
||||
{
|
||||
unsigned char prop0;
|
||||
if (size < LZMA_PROPERTIES_SIZE)
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
prop0 = propsData[0];
|
||||
if (prop0 >= (9 * 5 * 5))
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
{
|
||||
for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5));
|
||||
for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9);
|
||||
propsRes->lc = prop0;
|
||||
/*
|
||||
unsigned char remainder = (unsigned char)(prop0 / 9);
|
||||
propsRes->lc = prop0 % 9;
|
||||
propsRes->pb = remainder / 5;
|
||||
propsRes->lp = remainder % 5;
|
||||
*/
|
||||
}
|
||||
|
||||
return LZMA_RESULT_OK;
|
||||
}
|
||||
|
||||
#define kLzmaStreamWasFinishedId (-1)
|
||||
|
||||
int LzmaDecode(CLzmaDecoderState *vs,
|
||||
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
|
||||
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed)
|
||||
{
|
||||
CProb *p = vs->Probs;
|
||||
SizeT nowPos = 0;
|
||||
Byte previousByte = 0;
|
||||
UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1;
|
||||
UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1;
|
||||
int lc = vs->Properties.lc;
|
||||
|
||||
|
||||
int state = 0;
|
||||
UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1;
|
||||
int len = 0;
|
||||
const Byte *Buffer;
|
||||
const Byte *BufferLim;
|
||||
UInt32 Range;
|
||||
UInt32 Code;
|
||||
|
||||
*inSizeProcessed = 0;
|
||||
*outSizeProcessed = 0;
|
||||
|
||||
{
|
||||
UInt32 i;
|
||||
UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp));
|
||||
for (i = 0; i < numProbs; i++)
|
||||
p[i] = kBitModelTotal >> 1;
|
||||
}
|
||||
|
||||
RC_INIT(inStream, inSize);
|
||||
|
||||
|
||||
while(nowPos < outSize)
|
||||
{
|
||||
CProb *prob;
|
||||
UInt32 bound;
|
||||
int posState = (int)(
|
||||
(nowPos
|
||||
)
|
||||
& posStateMask);
|
||||
|
||||
prob = p + IsMatch + (state << kNumPosBitsMax) + posState;
|
||||
IfBit0(prob)
|
||||
{
|
||||
int symbol = 1;
|
||||
UpdateBit0(prob)
|
||||
prob = p + Literal + (LZMA_LIT_SIZE *
|
||||
(((
|
||||
(nowPos
|
||||
)
|
||||
& literalPosMask) << lc) + (previousByte >> (8 - lc))));
|
||||
|
||||
if (state >= kNumLitStates)
|
||||
{
|
||||
int matchByte;
|
||||
matchByte = outStream[nowPos - rep0];
|
||||
do
|
||||
{
|
||||
int bit;
|
||||
CProb *probLit;
|
||||
matchByte <<= 1;
|
||||
bit = (matchByte & 0x100);
|
||||
probLit = prob + 0x100 + bit + symbol;
|
||||
RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break)
|
||||
}
|
||||
while (symbol < 0x100);
|
||||
}
|
||||
while (symbol < 0x100)
|
||||
{
|
||||
CProb *probLit = prob + symbol;
|
||||
RC_GET_BIT(probLit, symbol)
|
||||
}
|
||||
previousByte = (Byte)symbol;
|
||||
|
||||
outStream[nowPos++] = previousByte;
|
||||
if (state < 4) state = 0;
|
||||
else if (state < 10) state -= 3;
|
||||
else state -= 6;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(prob);
|
||||
prob = p + IsRep + state;
|
||||
IfBit0(prob)
|
||||
{
|
||||
UpdateBit0(prob);
|
||||
rep3 = rep2;
|
||||
rep2 = rep1;
|
||||
rep1 = rep0;
|
||||
state = state < kNumLitStates ? 0 : 3;
|
||||
prob = p + LenCoder;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(prob);
|
||||
prob = p + IsRepG0 + state;
|
||||
IfBit0(prob)
|
||||
{
|
||||
UpdateBit0(prob);
|
||||
prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState;
|
||||
IfBit0(prob)
|
||||
{
|
||||
UpdateBit0(prob);
|
||||
|
||||
if (nowPos == 0)
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
|
||||
state = state < kNumLitStates ? 9 : 11;
|
||||
previousByte = outStream[nowPos - rep0];
|
||||
outStream[nowPos++] = previousByte;
|
||||
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(prob);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
UInt32 distance;
|
||||
UpdateBit1(prob);
|
||||
prob = p + IsRepG1 + state;
|
||||
IfBit0(prob)
|
||||
{
|
||||
UpdateBit0(prob);
|
||||
distance = rep1;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(prob);
|
||||
prob = p + IsRepG2 + state;
|
||||
IfBit0(prob)
|
||||
{
|
||||
UpdateBit0(prob);
|
||||
distance = rep2;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(prob);
|
||||
distance = rep3;
|
||||
rep3 = rep2;
|
||||
}
|
||||
rep2 = rep1;
|
||||
}
|
||||
rep1 = rep0;
|
||||
rep0 = distance;
|
||||
}
|
||||
state = state < kNumLitStates ? 8 : 11;
|
||||
prob = p + RepLenCoder;
|
||||
}
|
||||
{
|
||||
int numBits, offset;
|
||||
CProb *probLen = prob + LenChoice;
|
||||
IfBit0(probLen)
|
||||
{
|
||||
UpdateBit0(probLen);
|
||||
probLen = prob + LenLow + (posState << kLenNumLowBits);
|
||||
offset = 0;
|
||||
numBits = kLenNumLowBits;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(probLen);
|
||||
probLen = prob + LenChoice2;
|
||||
IfBit0(probLen)
|
||||
{
|
||||
UpdateBit0(probLen);
|
||||
probLen = prob + LenMid + (posState << kLenNumMidBits);
|
||||
offset = kLenNumLowSymbols;
|
||||
numBits = kLenNumMidBits;
|
||||
}
|
||||
else
|
||||
{
|
||||
UpdateBit1(probLen);
|
||||
probLen = prob + LenHigh;
|
||||
offset = kLenNumLowSymbols + kLenNumMidSymbols;
|
||||
numBits = kLenNumHighBits;
|
||||
}
|
||||
}
|
||||
RangeDecoderBitTreeDecode(probLen, numBits, len);
|
||||
len += offset;
|
||||
}
|
||||
|
||||
if (state < 4)
|
||||
{
|
||||
int posSlot;
|
||||
state += kNumLitStates;
|
||||
prob = p + PosSlot +
|
||||
((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) <<
|
||||
kNumPosSlotBits);
|
||||
RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot);
|
||||
if (posSlot >= kStartPosModelIndex)
|
||||
{
|
||||
int numDirectBits = ((posSlot >> 1) - 1);
|
||||
rep0 = (2 | ((UInt32)posSlot & 1));
|
||||
if (posSlot < kEndPosModelIndex)
|
||||
{
|
||||
rep0 <<= numDirectBits;
|
||||
prob = p + SpecPos + rep0 - posSlot - 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
numDirectBits -= kNumAlignBits;
|
||||
do
|
||||
{
|
||||
RC_NORMALIZE
|
||||
Range >>= 1;
|
||||
rep0 <<= 1;
|
||||
if (Code >= Range)
|
||||
{
|
||||
Code -= Range;
|
||||
rep0 |= 1;
|
||||
}
|
||||
}
|
||||
while (--numDirectBits != 0);
|
||||
prob = p + Align;
|
||||
rep0 <<= kNumAlignBits;
|
||||
numDirectBits = kNumAlignBits;
|
||||
}
|
||||
{
|
||||
int i = 1;
|
||||
int mi = 1;
|
||||
do
|
||||
{
|
||||
CProb *prob3 = prob + mi;
|
||||
RC_GET_BIT2(prob3, mi, ; , rep0 |= i);
|
||||
i <<= 1;
|
||||
}
|
||||
while(--numDirectBits != 0);
|
||||
}
|
||||
}
|
||||
else
|
||||
rep0 = posSlot;
|
||||
if (++rep0 == (UInt32)(0))
|
||||
{
|
||||
/* it's for stream version */
|
||||
len = kLzmaStreamWasFinishedId;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
len += kMatchMinLen;
|
||||
if (rep0 > nowPos)
|
||||
return LZMA_RESULT_DATA_ERROR;
|
||||
|
||||
|
||||
do
|
||||
{
|
||||
previousByte = outStream[nowPos - rep0];
|
||||
len--;
|
||||
outStream[nowPos++] = previousByte;
|
||||
}
|
||||
while(len != 0 && nowPos < outSize);
|
||||
}
|
||||
}
|
||||
RC_NORMALIZE;
|
||||
|
||||
|
||||
*inSizeProcessed = (SizeT)(Buffer - inStream);
|
||||
*outSizeProcessed = nowPos;
|
||||
return LZMA_RESULT_OK;
|
||||
}
|
||||
@ -1,67 +0,0 @@
|
||||
/*
|
||||
LzmaDecode.h
|
||||
LZMA Decoder interface
|
||||
|
||||
LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01)
|
||||
http://www.7-zip.org/
|
||||
|
||||
LZMA SDK is licensed under two licenses:
|
||||
1) GNU Lesser General Public License (GNU LGPL)
|
||||
2) Common Public License (CPL)
|
||||
It means that you can select one of these two licenses and
|
||||
follow rules of that license.
|
||||
|
||||
SPECIAL EXCEPTION:
|
||||
Igor Pavlov, as the author of this code, expressly permits you to
|
||||
statically or dynamically link your code (or bind by name) to the
|
||||
interfaces of this file without subjecting your linked code to the
|
||||
terms of the CPL or GNU LGPL. Any modifications or additions
|
||||
to this file, however, are subject to the LGPL or CPL terms.
|
||||
*/
|
||||
|
||||
#ifndef LZMADECODE_H
|
||||
#define LZMADECODE_H
|
||||
|
||||
typedef unsigned char Byte;
|
||||
typedef unsigned short UInt16;
|
||||
typedef unsigned int UInt32;
|
||||
typedef UInt32 SizeT;
|
||||
|
||||
#define CProb UInt16
|
||||
|
||||
#define LZMA_RESULT_OK 0
|
||||
#define LZMA_RESULT_DATA_ERROR 1
|
||||
|
||||
|
||||
#define LZMA_BASE_SIZE 1846
|
||||
#define LZMA_LIT_SIZE 768
|
||||
|
||||
#define LZMA_PROPERTIES_SIZE 5
|
||||
|
||||
typedef struct _CLzmaProperties
|
||||
{
|
||||
int lc;
|
||||
int lp;
|
||||
int pb;
|
||||
}CLzmaProperties;
|
||||
|
||||
int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size);
|
||||
|
||||
#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp)))
|
||||
|
||||
#define kLzmaNeedInitId (-2)
|
||||
|
||||
typedef struct _CLzmaDecoderState
|
||||
{
|
||||
CLzmaProperties Properties;
|
||||
CProb *Probs;
|
||||
|
||||
|
||||
} CLzmaDecoderState;
|
||||
|
||||
|
||||
int LzmaDecode(CLzmaDecoderState *vs,
|
||||
const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed,
|
||||
unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed);
|
||||
|
||||
#endif /* LZMADECODE_H */
|
||||
@ -1,66 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "bayou.h"
|
||||
|
||||
static void print_banner(void)
|
||||
{
|
||||
printf("\e[H\e[JBayou Payload Chooser v0.3\n");
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
extern unsigned long _binary_builtin_lar_start;
|
||||
struct LAR *lar;
|
||||
|
||||
print_banner();
|
||||
|
||||
lar = openlar((void *)&_binary_builtin_lar_start);
|
||||
|
||||
if (lar == NULL) {
|
||||
printf("[CHOOSER]: Unable to scan the attached LAR file\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
get_configuration(lar);
|
||||
|
||||
if (bayoucfg.n_entries == 0) {
|
||||
printf("[CHOOSER]: No payloads were found in the LAR\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* If timeout == 0xFF, then show the menu immediately.
|
||||
* If timeout is zero, then find and run the default item immediately.
|
||||
* If there is no default item, then show the menu.
|
||||
* If timeout is anything else, then show a message and wait for a
|
||||
* keystroke. If there is no keystroke in time then run the default.
|
||||
* If there is no default then show the menu.
|
||||
*/
|
||||
if (bayoucfg.timeout != 0xFF) {
|
||||
struct payload *d = payload_get_default();
|
||||
|
||||
if (d != NULL) {
|
||||
if (bayoucfg.timeout == 0)
|
||||
run_payload(d);
|
||||
else
|
||||
run_payload_timeout(d, bayoucfg.timeout);
|
||||
}
|
||||
}
|
||||
|
||||
menu();
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,152 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <libpayload.h>
|
||||
#include <curses.h>
|
||||
#include "bayou.h"
|
||||
|
||||
#define SCREEN_X 80
|
||||
#define SCREEN_Y 25
|
||||
|
||||
static int menu_width = 0;
|
||||
static struct payload *mpayloads[BAYOU_MAX_ENTRIES];
|
||||
static int m_entries = 0;
|
||||
static unsigned int selected = 0;
|
||||
static WINDOW *menuwin, *status;
|
||||
|
||||
void create_menu(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < bayoucfg.n_entries; i++) {
|
||||
struct payload *p = &(bayoucfg.entries[i]);
|
||||
char *name;
|
||||
|
||||
if ((p->pentry.parent != 0) ||
|
||||
(p->pentry.flags & BPT_FLAG_NOSHOW))
|
||||
continue;
|
||||
|
||||
mpayloads[m_entries++] = p;
|
||||
|
||||
name = payload_get_name(p);
|
||||
|
||||
if (strlen(name) > menu_width)
|
||||
menu_width = strlen(name);
|
||||
}
|
||||
|
||||
menu_width += 4;
|
||||
|
||||
if (menu_width < 30)
|
||||
menu_width = 30;
|
||||
|
||||
menuwin = newwin(m_entries + 3, menu_width,
|
||||
(SCREEN_Y - (m_entries + 3)) / 2,
|
||||
(SCREEN_X - menu_width) / 2);
|
||||
}
|
||||
|
||||
void draw_menu(void)
|
||||
{
|
||||
struct payload *s;
|
||||
int i;
|
||||
|
||||
wattrset(menuwin, COLOR_PAIR(3));
|
||||
wclear(menuwin);
|
||||
wborder(menuwin, ACS_VLINE, ACS_VLINE, ACS_HLINE, ACS_HLINE,
|
||||
ACS_ULCORNER, ACS_URCORNER, ACS_LLCORNER, ACS_LRCORNER);
|
||||
|
||||
wattrset(menuwin, COLOR_PAIR(4) | A_BOLD);
|
||||
mvwprintw(menuwin, 0, (menu_width - 17) / 2, " Payload Chooser ");
|
||||
|
||||
wattrset(menuwin, COLOR_PAIR(3));
|
||||
|
||||
for (i = 0; i < m_entries; i++) {
|
||||
char *name = payload_get_name(mpayloads[i]);
|
||||
int col = (menu_width - (2 + strlen(name))) / 2;
|
||||
|
||||
if (i == selected)
|
||||
wattrset(menuwin, COLOR_PAIR(5) | A_BOLD);
|
||||
else
|
||||
wattrset(menuwin, COLOR_PAIR(3));
|
||||
|
||||
mvwprintw(menuwin, 2 + i, col, name);
|
||||
}
|
||||
|
||||
s = mpayloads[selected];
|
||||
|
||||
wclear(status);
|
||||
|
||||
if (s->params[BAYOU_PARAM_DESC] != NULL) {
|
||||
char buf[66];
|
||||
int len = strnlen(s->params[BAYOU_PARAM_DESC], 65);
|
||||
|
||||
snprintf(buf, 65, s->params[BAYOU_PARAM_DESC]);
|
||||
buf[65] = 0;
|
||||
|
||||
mvwprintw(status, 0, (80 - len) / 2, buf);
|
||||
}
|
||||
|
||||
wrefresh(menuwin);
|
||||
wrefresh(status);
|
||||
}
|
||||
|
||||
void loop(void)
|
||||
{
|
||||
int key;
|
||||
|
||||
while (1) {
|
||||
key = getch();
|
||||
|
||||
if (key == ERR)
|
||||
continue;
|
||||
|
||||
if (key == KEY_DOWN)
|
||||
selected = (selected + 1) % m_entries;
|
||||
else if (key == KEY_UP)
|
||||
selected = (selected - 1) % m_entries;
|
||||
else if (key == KEY_ENTER) {
|
||||
run_payload(mpayloads[selected]);
|
||||
clear();
|
||||
refresh();
|
||||
} else
|
||||
continue;
|
||||
|
||||
draw_menu();
|
||||
}
|
||||
}
|
||||
|
||||
void menu(void)
|
||||
{
|
||||
initscr();
|
||||
|
||||
init_pair(1, COLOR_WHITE, COLOR_RED);
|
||||
init_pair(2, COLOR_BLACK, COLOR_WHITE);
|
||||
init_pair(3, COLOR_BLACK, COLOR_WHITE);
|
||||
init_pair(4, COLOR_CYAN, COLOR_WHITE);
|
||||
init_pair(5, COLOR_WHITE, COLOR_RED);
|
||||
|
||||
wattrset(stdscr, COLOR_PAIR(1));
|
||||
wclear(stdscr);
|
||||
|
||||
status = newwin(1, 80, 24, 0);
|
||||
wattrset(status, COLOR_PAIR(2));
|
||||
wclear(status);
|
||||
|
||||
refresh();
|
||||
|
||||
create_menu();
|
||||
draw_menu();
|
||||
|
||||
loop();
|
||||
}
|
||||
@ -1,86 +0,0 @@
|
||||
#include <libpayload.h>
|
||||
|
||||
// This GETBIT is supposed to work on little endian
|
||||
// 32bit systems. The algorithm will definitely need
|
||||
// some fixing on other systems, but it might not be
|
||||
// a problem since the nrv2b binary behaves the same..
|
||||
|
||||
#ifndef ENDIAN
|
||||
#define ENDIAN 0
|
||||
#endif
|
||||
#ifndef BITSIZE
|
||||
#define BITSIZE 32
|
||||
#endif
|
||||
|
||||
#define GETBIT_8(bb, src, ilen) \
|
||||
(((bb = bb & 0x7f ? bb*2 : ((unsigned)src[ilen++]*2+1)) >> 8) & 1)
|
||||
|
||||
#define GETBIT_LE16(bb, src, ilen) \
|
||||
(bb*=2,bb&0xffff ? (bb>>16)&1 : (ilen+=2,((bb=(src[ilen-2]+src[ilen-1]*256u)*2+1)>>16)&1))
|
||||
#define GETBIT_LE32(bb, src, ilen) \
|
||||
(bc > 0 ? ((bb>>--bc)&1) : (bc=31,\
|
||||
bb=*(const u32 *)((src)+ilen),ilen+=4,(bb>>31)&1))
|
||||
|
||||
#if ENDIAN == 0 && BITSIZE == 8
|
||||
#define GETBIT(bb, src, ilen) GETBIT_8(bb, src, ilen)
|
||||
#endif
|
||||
#if ENDIAN == 0 && BITSIZE == 16
|
||||
#define GETBIT(bb, src, ilen) GETBIT_LE16(bb, src, ilen)
|
||||
#endif
|
||||
#if ENDIAN == 0 && BITSIZE == 32
|
||||
#define GETBIT(bb, src, ilen) GETBIT_LE32(bb, src, ilen)
|
||||
#endif
|
||||
|
||||
unsigned long unrv2b(u8 *src, u8 *dst, unsigned long *ilen_p)
|
||||
{
|
||||
unsigned long ilen = 0, olen = 0, last_m_off = 1;
|
||||
u32 bb = 0;
|
||||
unsigned bc = 0;
|
||||
const u8 *m_pos;
|
||||
|
||||
// skip length
|
||||
src += 4;
|
||||
/* FIXME: check olen with the length stored in first 4 bytes */
|
||||
|
||||
for (;;) {
|
||||
unsigned int m_off, m_len;
|
||||
while (GETBIT(bb, src, ilen)) {
|
||||
dst[olen++] = src[ilen++];
|
||||
}
|
||||
|
||||
m_off = 1;
|
||||
do {
|
||||
m_off = m_off * 2 + GETBIT(bb, src, ilen);
|
||||
} while (!GETBIT(bb, src, ilen));
|
||||
if (m_off == 2) {
|
||||
m_off = last_m_off;
|
||||
} else {
|
||||
m_off = (m_off - 3) * 256 + src[ilen++];
|
||||
if (m_off == 0xffffffffU)
|
||||
break;
|
||||
last_m_off = ++m_off;
|
||||
}
|
||||
|
||||
m_len = GETBIT(bb, src, ilen);
|
||||
m_len = m_len * 2 + GETBIT(bb, src, ilen);
|
||||
if (m_len == 0) {
|
||||
m_len++;
|
||||
do {
|
||||
m_len = m_len * 2 + GETBIT(bb, src, ilen);
|
||||
} while (!GETBIT(bb, src, ilen));
|
||||
m_len += 2;
|
||||
}
|
||||
m_len += (m_off > 0xd00);
|
||||
|
||||
m_pos = dst + olen - m_off;
|
||||
dst[olen++] = *m_pos++;
|
||||
do {
|
||||
dst[olen++] = *m_pos++;
|
||||
} while (--m_len > 0);
|
||||
}
|
||||
|
||||
*ilen_p = ilen;
|
||||
|
||||
return olen;
|
||||
|
||||
}
|
||||
@ -1,107 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "bayou.h"
|
||||
|
||||
#define TIMEOUT_MESSAGE "Press ESC for the menu (%2d)...\r"
|
||||
#define TIMEOUT_KEY '\033'
|
||||
|
||||
void run_payload(struct payload *p)
|
||||
{
|
||||
int ret, i;
|
||||
|
||||
/* For chooser entries, just run the payload. */
|
||||
if (p->pentry.type == BPT_TYPE_CHOOSER) {
|
||||
self_load_and_run(p, &ret);
|
||||
return;
|
||||
}
|
||||
|
||||
/* For chained entries, run all the sub-chain items. */
|
||||
for (i = 0; i < bayoucfg.n_entries; i++) {
|
||||
struct payload *s = &(bayoucfg.entries[i]);
|
||||
|
||||
if (s->pentry.parent == p->pentry.index)
|
||||
self_load_and_run(s, &ret);
|
||||
}
|
||||
}
|
||||
|
||||
char *payload_get_name(struct payload *p)
|
||||
{
|
||||
if (p->pentry.type == BPT_TYPE_CHAIN)
|
||||
return (char *)p->pentry.title;
|
||||
else if (p->pentry.type == BPT_TYPE_CHOOSER) {
|
||||
if (p->pentry.title[0] != 0)
|
||||
return (char *)p->pentry.title;
|
||||
return p->params[BAYOU_PARAM_DESC];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct payload *payload_get_default(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < bayoucfg.n_entries; i++) {
|
||||
struct payload *s = &(bayoucfg.entries[i]);
|
||||
|
||||
if (s->pentry.parent == 0 && s->pentry.flags & BPT_FLAG_DEFAULT)
|
||||
return s;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void run_payload_timeout(struct payload *p, int timeout)
|
||||
{
|
||||
int t, ch, tval;
|
||||
|
||||
for (t = timeout; t >= 0; t--) {
|
||||
printf(TIMEOUT_MESSAGE, t);
|
||||
|
||||
tval = 1000;
|
||||
ch = getchar_timeout(&tval);
|
||||
|
||||
if (ch == TIMEOUT_KEY)
|
||||
return;
|
||||
}
|
||||
|
||||
run_payload(p);
|
||||
}
|
||||
|
||||
void payload_parse_params(struct payload *pload, u8 *params, int len)
|
||||
{
|
||||
char *ptr = (char *)params;
|
||||
int i = 0;
|
||||
|
||||
if (ptr == NULL)
|
||||
return;
|
||||
|
||||
while (ptr < ((char *)params + len)) {
|
||||
|
||||
if (!strncmp(ptr, "name=", 5)) {
|
||||
pload->params[BAYOU_PARAM_NAME] = ptr + 5;
|
||||
} else if (!strncmp(ptr, "desc=", 5)) {
|
||||
pload->params[BAYOU_PARAM_DESC] = ptr + 5;
|
||||
} else if (!strncmp(ptr, "listname=", 9)) {
|
||||
pload->params[BAYOU_PARAM_LIST] = ptr + 9;
|
||||
}
|
||||
|
||||
ptr += strnlen(ptr, len - i);
|
||||
|
||||
if (ptr < ((char *)params + len) && *ptr == 0)
|
||||
ptr++;
|
||||
}
|
||||
}
|
||||
@ -1,143 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include "bayou.h"
|
||||
#include "self.h"
|
||||
|
||||
static int nop_decompress(void *dst, void *src, int len)
|
||||
{
|
||||
memcpy(dst, src, len);
|
||||
return len;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LZMA
|
||||
extern int ulzma(u8 *, u8 *);
|
||||
|
||||
static int lzma_decompress(void *dst, void *src, int len)
|
||||
{
|
||||
return ulzma((u8 *) src, (u8 *) dst);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NRV2B
|
||||
extern int unrv2b(u8 *, u8 *, unsigned long *);
|
||||
|
||||
static int nrv2b_decompress(void *dst, void *src, int len)
|
||||
{
|
||||
unsigned long l = (u32) len;
|
||||
return unrv2b(src, dst, &l);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int zeros_decompress(void *dst, void *src, int len)
|
||||
{
|
||||
memset(dst, 0, len);
|
||||
return len;
|
||||
}
|
||||
|
||||
int self_get_params(u8 *fptr, u8 **params)
|
||||
{
|
||||
struct self_segment *seg = (struct self_segment *)fptr;
|
||||
|
||||
while (seg->type != SELF_TYPE_ENTRY) {
|
||||
if (seg->type == 0)
|
||||
return -1;
|
||||
|
||||
if (seg->type == SELF_TYPE_PARAMS) {
|
||||
*params = (u8 *) (fptr + seg->offset);
|
||||
return seg->len;
|
||||
}
|
||||
|
||||
seg++;
|
||||
}
|
||||
|
||||
*params = NULL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int verify_self(u8 *ptr)
|
||||
{
|
||||
struct self_segment *seg = (struct self_segment *)ptr;
|
||||
|
||||
switch (seg->type) {
|
||||
case SELF_TYPE_CODE:
|
||||
case SELF_TYPE_DATA:
|
||||
case SELF_TYPE_BSS:
|
||||
case SELF_TYPE_PARAMS:
|
||||
case SELF_TYPE_ENTRY:
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int self_load_and_run(struct payload *p, int *ret)
|
||||
{
|
||||
struct self_segment *seg = (struct self_segment *)p->fptr;
|
||||
int (*dcmp) (void *, void *, int);
|
||||
int dlen;
|
||||
|
||||
switch (p->stat.compression) {
|
||||
#ifdef CONFIG_LZMA
|
||||
case ALGO_LZMA:
|
||||
dcmp = lzma_decompress;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_NRV2B
|
||||
case ALGO_NRV2B:
|
||||
dcmp = nrv2b_decompress;
|
||||
break;
|
||||
#endif
|
||||
case ALGO_ZEROES:
|
||||
dcmp = zeros_decompress;
|
||||
break;
|
||||
case ALGO_NONE:
|
||||
dcmp = nop_decompress;
|
||||
default:
|
||||
printf("E: Unsupported decompression type\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
while (1) {
|
||||
u32 laddr = (u32) (seg->load_addr & 0xFFFFFFFF);
|
||||
|
||||
switch (seg->type) {
|
||||
case SELF_TYPE_CODE:
|
||||
case SELF_TYPE_DATA:
|
||||
dlen = dcmp((void *)laddr,
|
||||
(void *)p->fptr + seg->offset, seg->len);
|
||||
|
||||
if (dlen < seg->mem_len) {
|
||||
memset((void *)(laddr + dlen), 0,
|
||||
seg->mem_len - dlen);
|
||||
}
|
||||
break;
|
||||
|
||||
case SELF_TYPE_BSS:
|
||||
memset((void *)laddr, 0, seg->len);
|
||||
break;
|
||||
case SELF_TYPE_ENTRY:
|
||||
*ret = exec(laddr, 0, NULL);
|
||||
return 0;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
seg++;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
||||
@ -1,40 +0,0 @@
|
||||
/*
|
||||
* This file is part of the bayou project.
|
||||
*
|
||||
* Copyright (C) 2008 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SELF_H_
|
||||
#define SELF_H_
|
||||
|
||||
#include <libpayload.h>
|
||||
|
||||
struct self_segment {
|
||||
u32 type;
|
||||
u32 offset;
|
||||
u64 load_addr;
|
||||
u32 len;
|
||||
u32 mem_len;
|
||||
};
|
||||
|
||||
struct self {
|
||||
struct larstat stat;
|
||||
void *fptr;
|
||||
};
|
||||
|
||||
#define SELF_TYPE_CODE 0x45444F43
|
||||
#define SELF_TYPE_DATA 0x41544144
|
||||
#define SELF_TYPE_BSS 0x20535342
|
||||
#define SELF_TYPE_PARAMS 0x41524150
|
||||
#define SELF_TYPE_ENTRY 0x52544E45
|
||||
|
||||
#endif
|
||||
3
payloads/external/GRUB2/Makefile
vendored
3
payloads/external/GRUB2/Makefile
vendored
@ -17,7 +17,8 @@ checkout:
|
||||
echo " GIT GRUB2 $(NAME-y)"
|
||||
test -d $(project_dir) || git clone $(project_git_repo) $(project_dir)
|
||||
git -C $(project_dir) fetch
|
||||
ifeq ("$(shell git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain)",)
|
||||
ifeq ("$(shell test -d $(project_dir) && \
|
||||
(git -C $(project_dir) status --ignored=no --untracked-files=no --porcelain))",)
|
||||
git -C $(project_dir) checkout -f $(TAG-y)
|
||||
else
|
||||
echo "WARNING: index/tree not clean, skipping update / force checkout."
|
||||
|
||||
1
payloads/external/LinuxBoot/Kconfig
vendored
1
payloads/external/LinuxBoot/Kconfig
vendored
@ -117,7 +117,6 @@ config LINUXBOOT_KERNEL_ARCH_DEFAULT_CONFIG
|
||||
|
||||
config LINUXBOOT_KERNEL_CUSTOM_CONFIG
|
||||
bool "Custom (def)config file"
|
||||
help
|
||||
|
||||
endchoice
|
||||
|
||||
|
||||
6
payloads/external/Makefile.inc
vendored
6
payloads/external/Makefile.inc
vendored
@ -29,10 +29,10 @@ endif
|
||||
ifeq ($(CONFIG_PAYLOAD_DEPTHCHARGE),y)
|
||||
PAYLOAD_CONFIG=payloads/external/depthcharge/depthcharge/.config
|
||||
$(PAYLOAD_CONFIG): payloads/external/depthcharge/depthcharge/build/depthcharge.elf
|
||||
ifneq ($(CONFIG_MAINBOARD_DEPTHCHARGE),)
|
||||
BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE)
|
||||
else
|
||||
ifeq ($(call strip_quotes,$(CONFIG_MAINBOARD_DEPTHCHARGE))),)
|
||||
BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER))))
|
||||
else
|
||||
BOARD=$(CONFIG_MAINBOARD_DEPTHCHARGE)
|
||||
endif
|
||||
#TODO: Figure out version
|
||||
endif
|
||||
|
||||
2
payloads/external/SeaBIOS/Kconfig
vendored
2
payloads/external/SeaBIOS/Kconfig
vendored
@ -5,7 +5,7 @@ choice
|
||||
default SEABIOS_STABLE
|
||||
|
||||
config SEABIOS_STABLE
|
||||
bool "1.12.1"
|
||||
bool "1.13.0"
|
||||
help
|
||||
Stable SeaBIOS version
|
||||
config SEABIOS_MASTER
|
||||
|
||||
2
payloads/external/SeaBIOS/Makefile
vendored
2
payloads/external/SeaBIOS/Makefile
vendored
@ -1,5 +1,5 @@
|
||||
TAG-$(CONFIG_SEABIOS_MASTER)=origin/master
|
||||
TAG-$(CONFIG_SEABIOS_STABLE)=a5cab58e9a3fb6e168aba919c5669bea406573b4
|
||||
TAG-$(CONFIG_SEABIOS_STABLE)=f21b5a4aeb020f2a5e2c6503f906a9349dd2f069
|
||||
TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID)
|
||||
|
||||
project_git_repo=https://review.coreboot.org/seabios.git
|
||||
|
||||
@ -114,11 +114,6 @@ config ARCH_ARM64
|
||||
help
|
||||
Support the ARM64 architecture
|
||||
|
||||
config ARCH_MIPS
|
||||
bool "MIPS"
|
||||
help
|
||||
Support the MIPS architecture
|
||||
|
||||
endchoice
|
||||
|
||||
config MULTIBOOT
|
||||
@ -147,12 +142,11 @@ config BASE_ADDRESS
|
||||
hex "Base address"
|
||||
default 0x04000000 if ARCH_ARM
|
||||
default 0x80100000 if ARCH_ARM64
|
||||
default 0x00000000 if ARCH_MIPS
|
||||
default 0x00100000 if ARCH_X86
|
||||
help
|
||||
This is the base address for the payload.
|
||||
|
||||
If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS,
|
||||
If unsure, set to 0x00100000 on x86,
|
||||
0x04000000 on ARM or 0x80100000 on ARM64.
|
||||
|
||||
endmenu
|
||||
@ -349,8 +343,8 @@ config PC_KEYBOARD
|
||||
default y if ARCH_X86 # uses IO
|
||||
default n
|
||||
|
||||
config PC_KEYBOARD_IGNORE_INIT_FAILURE
|
||||
bool "Ignore keyboard failures during init and always add input device"
|
||||
config PC_KEYBOARD_AT_TRANSLATED
|
||||
bool "AT Translation keyboard device"
|
||||
default n
|
||||
|
||||
config PC_KEYBOARD_LAYOUT_US
|
||||
@ -452,5 +446,4 @@ config IO_ADDRESS_SPACE
|
||||
|
||||
source "arch/arm/Kconfig"
|
||||
source "arch/arm64/Kconfig"
|
||||
source "arch/mips/Kconfig"
|
||||
source "arch/x86/Kconfig"
|
||||
|
||||
@ -95,7 +95,6 @@ include $(HAVE_DOTCONFIG)
|
||||
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
|
||||
|
||||
ARCH-y := $(ARCHDIR-y)
|
||||
@ -105,7 +104,6 @@ ARCH-y := $(ARCHDIR-y)
|
||||
ARCH-$(CONFIG_LP_ARCH_ARM) := arm
|
||||
ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
|
||||
ARCH-$(CONFIG_LP_ARCH_X86) := x86_32
|
||||
ARCH-$(CONFIG_LP_ARCH_MIPS) := mips
|
||||
|
||||
# Three cases where we don't need fully populated $(obj) lists:
|
||||
# 1. when no .config exists
|
||||
@ -165,7 +163,6 @@ CCACHE:=CCACHE_COMPILERCHECK=content CCACHE_BASEDIR=$(top) $(CCACHE)
|
||||
CC := $(CCACHE) $(CC)
|
||||
HOSTCC := $(CCACHE) $(HOSTCC)
|
||||
HOSTCXX := $(CCACHE) $(HOSTCXX)
|
||||
ROMCC := $(CCACHE) $(ROMCC)
|
||||
endif
|
||||
|
||||
strip_quotes = $(subst ",,$(subst \",,$(1)))
|
||||
|
||||
@ -33,7 +33,6 @@ export KERNELVERSION := 0.2.0
|
||||
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips
|
||||
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
|
||||
DESTDIR ?= install
|
||||
|
||||
|
||||
@ -92,7 +92,7 @@ static void lpae_map_init(void)
|
||||
/* get work block address */
|
||||
work_block = ALIGN_UP((uintptr_t)_end, 2*MiB);
|
||||
assert(work_block);
|
||||
printf("Work block for LPAE mapping is @ 0x%p\n", (void *)work_block);
|
||||
printf("Work block for LPAE mapping is @ %p\n", (void *)work_block);
|
||||
|
||||
/* get the address of the 1st pmd from pgd[0] */
|
||||
pgd = (pgd_t *)((uintptr_t)read_ttbr0() & PGD_MASK);
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
#include <libpayload.h>
|
||||
#include <stdint.h>
|
||||
|
||||
u64 exception_stack[0x200] __attribute__((aligned(16)));
|
||||
u64 exception_stack[2*KiB] __attribute__((aligned(16)));
|
||||
u64 *exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
|
||||
extern unsigned int test_exc;
|
||||
|
||||
|
||||
@ -273,7 +273,7 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges)
|
||||
max_tables = (TTB_DEFAULT_SIZE >> GRANULE_SIZE_SHIFT);
|
||||
free_idx = 1;
|
||||
|
||||
printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n",
|
||||
printf("Libpayload ARM64: TTB_BUFFER: %p Max Tables: %d\n",
|
||||
(void*)xlat_addr, max_tables);
|
||||
|
||||
/*
|
||||
|
||||
@ -1,24 +0,0 @@
|
||||
#
|
||||
# This file is part of the libpayload project.
|
||||
#
|
||||
# Copyright (C) 2014 Imagination Technologies
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; version 2 of
|
||||
# the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
|
||||
if ARCH_MIPS
|
||||
|
||||
config ARCH_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select LITTLE_ENDIAN
|
||||
|
||||
endif
|
||||
@ -1,33 +0,0 @@
|
||||
#
|
||||
# This file is part of the libpayload project.
|
||||
#
|
||||
# Copyright (C) 2014 Imagination Technologies
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; version 2 of
|
||||
# the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
|
||||
###############################################################################
|
||||
CFLAGS += -march=mips32r2 -mxgot
|
||||
|
||||
head.o-y += head.S
|
||||
|
||||
libc-y += cache.c
|
||||
libc-y += coreboot.c
|
||||
libc-y += dummy_media.c
|
||||
libc-y += exception_asm.S
|
||||
libc-y += exception.c
|
||||
libc-y += gdb.c
|
||||
libc-y += main.c
|
||||
libc-y += selfboot.c
|
||||
libc-y += sysinfo.c
|
||||
libc-y += string.c
|
||||
libc-y += timer.c
|
||||
libc-y += util.S
|
||||
@ -1,72 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/cache.h>
|
||||
|
||||
|
||||
void dcache_clean_all(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void dcache_invalidate_all(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
void dcache_clean_invalidate_all(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void tlb_invalidate_all(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
unsigned int dcache_line_bytes(void)
|
||||
{
|
||||
/* TO DO */
|
||||
return 0;
|
||||
}
|
||||
|
||||
void dcache_mmu_disable(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void dcache_mmu_enable(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void cache_sync_instructions(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void mmu_init(void)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
void mmu_disable_range(unsigned long start_mb, unsigned long size_mb)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
|
||||
enum dcache_policy policy)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
@ -1,51 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <libpayload-config.h>
|
||||
#include <libpayload.h>
|
||||
#include <coreboot_tables.h>
|
||||
|
||||
/* This pointer gets set in head.S and is passed in from coreboot. */
|
||||
void *cb_header_ptr;
|
||||
|
||||
static void cb_parse_dma(void *ptr)
|
||||
{
|
||||
struct lb_range *dma = (struct lb_range *)ptr;
|
||||
init_dma_memory(bus_to_virt(dma->range_start), dma->range_size);
|
||||
}
|
||||
|
||||
/* Architecture specific */
|
||||
int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
|
||||
{
|
||||
switch (rec->tag) {
|
||||
case CB_TAG_DMA:
|
||||
cb_parse_dma(rec);
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
int get_coreboot_info(struct sysinfo_t *info)
|
||||
{
|
||||
return cb_parse_header(cb_header_ptr, 1, info);
|
||||
}
|
||||
|
||||
void *get_cb_header_ptr(void)
|
||||
{
|
||||
return cb_header_ptr;
|
||||
}
|
||||
@ -1,42 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Google, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
#define LIBPAYLOAD
|
||||
|
||||
#include <cbfs.h>
|
||||
|
||||
/* The generic cbfs code relies on the libpayload_init_default_cbfs_media
|
||||
* symbol. Therefore, provide an implementation that just throws an error. */
|
||||
|
||||
int libpayload_init_default_cbfs_media(struct cbfs_media *media);
|
||||
|
||||
__attribute__((weak)) int libpayload_init_default_cbfs_media(
|
||||
struct cbfs_media *media)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
@ -1,103 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/exception.h>
|
||||
#include <exception.h>
|
||||
#include <libpayload.h>
|
||||
#include <stdint.h>
|
||||
|
||||
u32 exception_stack[0x400] __attribute__((aligned(8)));
|
||||
struct exception_state_t exception_state;
|
||||
|
||||
static const char *names[EXC_COUNT] = {
|
||||
[EXC_CACHE_ERROR] = "Cache error exception",
|
||||
[EXC_TLB_REFILL_AND_ALL] = "TLB refill or general exception",
|
||||
[EXC_INTERRUPT] = "Interrupt",
|
||||
[EXC_EJTAG_DEBUG] = "EJTAG debug exception"
|
||||
};
|
||||
|
||||
static void dump_exception_state(void)
|
||||
{
|
||||
printf("%s exception!\n", names[exception_state_ptr->vector]);
|
||||
printf("\nRegisters:\n");
|
||||
printf("ZERO:\t0x%08x\n", exception_state_ptr->regs.zero);
|
||||
printf("AT:\t0x%08x\n", exception_state_ptr->regs.at);
|
||||
printf("V0:\t0x%08x\n", exception_state_ptr->regs.v0);
|
||||
printf("V1:\t0x%08x\n", exception_state_ptr->regs.v1);
|
||||
printf("A0:\t0x%08x\n", exception_state_ptr->regs.a0);
|
||||
printf("A1:\t0x%08x\n", exception_state_ptr->regs.a1);
|
||||
printf("A2:\t0x%08x\n", exception_state_ptr->regs.a2);
|
||||
printf("A3:\t0x%08x\n", exception_state_ptr->regs.a3);
|
||||
printf("T0:\t0x%08x\n", exception_state_ptr->regs.t0);
|
||||
printf("T1:\t0x%08x\n", exception_state_ptr->regs.t1);
|
||||
printf("T2:\t0x%08x\n", exception_state_ptr->regs.t2);
|
||||
printf("T3:\t0x%08x\n", exception_state_ptr->regs.t3);
|
||||
printf("T4:\t0x%08x\n", exception_state_ptr->regs.t4);
|
||||
printf("T5:\t0x%08x\n", exception_state_ptr->regs.t5);
|
||||
printf("T6:\t0x%08x\n", exception_state_ptr->regs.t6);
|
||||
printf("T7:\t0x%08x\n", exception_state_ptr->regs.t7);
|
||||
printf("S0:\t0x%08x\n", exception_state_ptr->regs.s0);
|
||||
printf("S1:\t0x%08x\n", exception_state_ptr->regs.s1);
|
||||
printf("S2:\t0x%08x\n", exception_state_ptr->regs.s2);
|
||||
printf("S3:\t0x%08x\n", exception_state_ptr->regs.s3);
|
||||
printf("S4:\t0x%08x\n", exception_state_ptr->regs.s4);
|
||||
printf("S5:\t0x%08x\n", exception_state_ptr->regs.s5);
|
||||
printf("S6:\t0x%08x\n", exception_state_ptr->regs.s6);
|
||||
printf("S7:\t0x%08x\n", exception_state_ptr->regs.s7);
|
||||
printf("T8:\t0x%08x\n", exception_state_ptr->regs.t8);
|
||||
printf("T9:\t0x%08x\n", exception_state_ptr->regs.t9);
|
||||
printf("K0:\t0x%08x\n", exception_state_ptr->regs.k0);
|
||||
printf("K1:\t0x%08x\n", exception_state_ptr->regs.k1);
|
||||
printf("GP:\t0x%08x\n", exception_state_ptr->regs.gp);
|
||||
printf("SP:\t0x%08x\n", exception_state_ptr->regs.sp);
|
||||
printf("FP:\t0x%08x\n", exception_state_ptr->regs.fp);
|
||||
printf("RA:\t0x%08x\n", exception_state_ptr->regs.ra);
|
||||
}
|
||||
|
||||
static void dump_stack(uintptr_t addr, size_t bytes)
|
||||
{
|
||||
int i, j;
|
||||
const int words_per_line = 8;
|
||||
int words_to_print;
|
||||
uint32_t *ptr = (uint32_t *)
|
||||
(addr & ~(words_per_line * sizeof(*ptr) - 1));
|
||||
|
||||
printf("Dumping stack:\n");
|
||||
words_to_print = bytes/sizeof(*ptr);
|
||||
for (i = words_to_print; i >= 0; i -= words_per_line) {
|
||||
printf("%p: ", ptr + i);
|
||||
for (j = i; j < i + words_per_line; j++)
|
||||
printf("%08x ", *(ptr + j));
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void exception_dispatch(void)
|
||||
{
|
||||
u32 vec = exception_state_ptr->vector;
|
||||
die_if(vec >= EXC_COUNT || !names[vec], "Bad exception vector %u", vec);
|
||||
|
||||
dump_exception_state();
|
||||
dump_stack(exception_state_ptr->regs.sp, 512);
|
||||
halt();
|
||||
}
|
||||
|
||||
void exception_init(void)
|
||||
{
|
||||
exception_stack_end = exception_stack + ARRAY_SIZE(exception_stack);
|
||||
exception_state_ptr = &exception_state;
|
||||
exception_init_asm();
|
||||
}
|
||||
@ -1,200 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#define STATUS_REGISTER $12,0
|
||||
#define BOOT_EXC_VECTOR_MASK (1 << 22)
|
||||
#define EBASE_REGISTER $15,1
|
||||
#define EXCEPTION_BASE_MASK (0xFFFFF000)
|
||||
|
||||
/* Don't reorder instructions */
|
||||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.align 4
|
||||
.global exception_stack_end
|
||||
exception_stack_end:
|
||||
.word 0
|
||||
|
||||
.global exception_state_ptr
|
||||
exception_state_ptr:
|
||||
.word 0
|
||||
|
||||
/* Temporary variables. */
|
||||
ret_addr:
|
||||
.word 0
|
||||
exception_sp:
|
||||
.word 0
|
||||
vector:
|
||||
.word 0
|
||||
|
||||
/* Cache error */
|
||||
.org 0x100
|
||||
li $v0, 0x0
|
||||
la $at, vector
|
||||
sw $v0, 0x00($at)
|
||||
b exception_common
|
||||
nop
|
||||
|
||||
/* TLB refill and all others */
|
||||
.org 0x180
|
||||
li $v0, 0x1
|
||||
la $at, vector
|
||||
sw $v0, 0x00($at)
|
||||
b exception_common
|
||||
nop
|
||||
|
||||
/* Interrupt */
|
||||
.org 0x200
|
||||
li $v0, 0x2
|
||||
la $at, vector
|
||||
sw $v0, 0x00($at)
|
||||
b exception_common
|
||||
nop
|
||||
|
||||
/* EJTAG debug exception */
|
||||
.org 0x480
|
||||
li $v0, 0x3
|
||||
la $at, vector
|
||||
sw $v0, 0x00($at)
|
||||
b exception_common
|
||||
nop
|
||||
|
||||
exception_common:
|
||||
/* Obtain return address of exception */
|
||||
la $v0, ret_addr
|
||||
sw $ra, 0x00($v0)
|
||||
|
||||
/* Initialize $gp */
|
||||
bal 1f
|
||||
nop
|
||||
.word _gp
|
||||
1:
|
||||
lw $gp, 0($ra)
|
||||
|
||||
la $at, exception_sp
|
||||
sw $sp, 0x00($at)
|
||||
lw $sp, exception_state_ptr
|
||||
|
||||
/* Save all registers */
|
||||
sw $zero, 0x00($sp)
|
||||
sw $at, 0x04($sp)
|
||||
sw $v0, 0x08($sp)
|
||||
sw $v1, 0x0C($sp)
|
||||
sw $a0, 0x10($sp)
|
||||
sw $a1, 0x14($sp)
|
||||
sw $a2, 0x18($sp)
|
||||
sw $a3, 0x1C($sp)
|
||||
sw $t0, 0x20($sp)
|
||||
sw $t1, 0x34($sp)
|
||||
sw $t2, 0x28($sp)
|
||||
sw $t3, 0x2C($sp)
|
||||
sw $t4, 0x30($sp)
|
||||
sw $t5, 0x34($sp)
|
||||
sw $t6, 0x38($sp)
|
||||
sw $t7, 0x3C($sp)
|
||||
sw $s0, 0x40($sp)
|
||||
sw $s1, 0x44($sp)
|
||||
sw $s2, 0x48($sp)
|
||||
sw $s3, 0x4C($sp)
|
||||
sw $s4, 0x50($sp)
|
||||
sw $s5, 0x54($sp)
|
||||
sw $s6, 0x58($sp)
|
||||
sw $s7, 0x5C($sp)
|
||||
sw $t8, 0x60($sp)
|
||||
sw $t9, 0x64($sp)
|
||||
sw $k0, 0x68($sp)
|
||||
sw $k1, 0x6C($sp)
|
||||
sw $gp, 0x70($sp)
|
||||
lw $v0, exception_sp
|
||||
sw $v0, 0x74($sp)
|
||||
sw $fp, 0x78($sp)
|
||||
lw $v0, ret_addr
|
||||
sw $v0, 0x7C($sp)
|
||||
lw $v0, vector
|
||||
sw $v0, 0x80($sp)
|
||||
|
||||
/* Point SP to the stack for C code */
|
||||
lw $sp, exception_stack_end
|
||||
/* Give control to exception dispatch */
|
||||
la $a2, exception_dispatch
|
||||
jalr $a2
|
||||
nop
|
||||
lw $sp, exception_state_ptr
|
||||
/* Restore registers */
|
||||
lw $zero, 0x00($sp)
|
||||
lw $at, 0x04($sp)
|
||||
lw $v0, 0x08($sp)
|
||||
lw $v1, 0x0C($sp)
|
||||
lw $a0, 0x10($sp)
|
||||
lw $a1, 0x14($sp)
|
||||
lw $a2, 0x18($sp)
|
||||
lw $a3, 0x1C($sp)
|
||||
lw $t0, 0x20($sp)
|
||||
lw $t1, 0x24($sp)
|
||||
lw $t2, 0x28($sp)
|
||||
lw $t3, 0x2C($sp)
|
||||
lw $t4, 0x30($sp)
|
||||
lw $t5, 0x34($sp)
|
||||
lw $t6, 0x38($sp)
|
||||
lw $t7, 0x3C($sp)
|
||||
lw $s0, 0x40($sp)
|
||||
lw $s1, 0x44($sp)
|
||||
lw $s2, 0x48($sp)
|
||||
lw $s3, 0x4C($sp)
|
||||
lw $s4, 0x50($sp)
|
||||
lw $s5, 0x54($sp)
|
||||
lw $s6, 0x58($sp)
|
||||
lw $s7, 0x5C($sp)
|
||||
lw $t8, 0x60($sp)
|
||||
lw $t9, 0x64($sp)
|
||||
lw $k0, 0x68($sp)
|
||||
sw $k1, 0x6C($sp)
|
||||
sw $gp, 0x70($sp)
|
||||
sw $fp, 0x78($sp)
|
||||
sw $ra, 0x7C($sp)
|
||||
/* Return */
|
||||
eret
|
||||
|
||||
.global exception_init_asm
|
||||
exception_init_asm:
|
||||
.set push
|
||||
/* Make sure boot exception vector is 1 before writing EBASE */
|
||||
mfc0 $t0, STATUS_REGISTER
|
||||
li $t1, BOOT_EXC_VECTOR_MASK
|
||||
or $t0, $t0, $t1
|
||||
mtc0 $t0, STATUS_REGISTER
|
||||
|
||||
/*Prepare base address */
|
||||
la $t1, exception_stack_end
|
||||
li $t2, EXCEPTION_BASE_MASK
|
||||
and $t1, $t1, $t2
|
||||
|
||||
/* Prepare EBASE register value */
|
||||
mfc0 $t0, EBASE_REGISTER
|
||||
li $t2, ~(EXCEPTION_BASE_MASK)
|
||||
and $t0, $t0, $t2
|
||||
/* Filling base address */
|
||||
or $t0, $t0, $t1
|
||||
mtc0 $t0, EBASE_REGISTER
|
||||
|
||||
/* Clear boot exception vector bit for EBASE value to take effect */
|
||||
mfc0 $t0, STATUS_REGISTER
|
||||
li $t1, ~BOOT_EXC_VECTOR_MASK
|
||||
and $t0, $t0, $t1
|
||||
mtc0 $t0, STATUS_REGISTER
|
||||
|
||||
.set pop
|
||||
/* Return */
|
||||
jr $ra
|
||||
@ -1,27 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
|
||||
#include <gdb.h>
|
||||
#include <libpayload.h>
|
||||
|
||||
|
||||
void gdb_arch_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
void gdb_arch_enter(void)
|
||||
{
|
||||
}
|
||||
@ -1,96 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/cpu.h>
|
||||
|
||||
/* Disable interrupts and mark the kernel mode */
|
||||
.macro setup_c0_status clr
|
||||
.set push
|
||||
mfc0 $t0, $CP0_STATUS
|
||||
or $t0, ST0_CU0 | 0x1f | \clr
|
||||
xor $t0, 0x1f | \clr
|
||||
mtc0 $t0, $CP0_STATUS
|
||||
.set noreorder
|
||||
sll $zero, 3
|
||||
.set pop
|
||||
.endm
|
||||
|
||||
/* Don't reorder instructions */
|
||||
.set noreorder
|
||||
|
||||
.align 4
|
||||
|
||||
.global cb_header_ptr
|
||||
cb_header_ptr:
|
||||
.word 0
|
||||
|
||||
.global old_sp
|
||||
old_sp:
|
||||
.word 0
|
||||
|
||||
|
||||
.global _entry, _leave
|
||||
.text
|
||||
|
||||
/* Our entry point */
|
||||
_entry:
|
||||
|
||||
/*
|
||||
* This function saves off the previous stack and switches us to our
|
||||
* own execution environment.
|
||||
*/
|
||||
|
||||
/* Clear watch and cause registers */
|
||||
mtc0 $zero, $CP0_WATCHLO
|
||||
mtc0 $zero, $CP0_WATCHHI
|
||||
mtc0 $zero, $CP0_CAUSE
|
||||
|
||||
/* Disable interrupts */
|
||||
setup_c0_status 0
|
||||
|
||||
/* Don't use at in synthetic instr. */
|
||||
.set noat
|
||||
|
||||
/* Init timer */
|
||||
mtc0 $zero, $CP0_COUNT
|
||||
mtc0 $zero, $CP0_COMPARE
|
||||
|
||||
/* Initialize $gp */
|
||||
bal 1f
|
||||
nop
|
||||
.word _gp
|
||||
1:
|
||||
lw $gp, 0($ra)
|
||||
|
||||
/* Save off the location of the coreboot tables */
|
||||
la $at, cb_header_ptr
|
||||
sw $a0, 0x00($at)
|
||||
|
||||
/* Save old stack pointer */
|
||||
la $at, old_sp
|
||||
sw $sp, 0x00($at)
|
||||
|
||||
/* Setup new stack */
|
||||
la $sp, _stack
|
||||
|
||||
/* Let's rock */
|
||||
la $a2, start_main
|
||||
jalr $a2
|
||||
nop
|
||||
_leave:
|
||||
/* Restore old stack. */
|
||||
lw $sp, old_sp
|
||||
/* Return to the original context. */
|
||||
eret
|
||||
@ -1,86 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* Based on src/arch/arm/ramstage.ld:
|
||||
* Written by Johan Rydberg, based on work by Daniel Kahlin.
|
||||
* Rewritten by Eric Biederman
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(mips)
|
||||
|
||||
ENTRY(_entry)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
. = CONFIG_LP_BASE_ADDRESS;
|
||||
|
||||
. = ALIGN(16);
|
||||
_start = .;
|
||||
|
||||
.text : {
|
||||
*(.text._entry)
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
}
|
||||
|
||||
.rodata : {
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
}
|
||||
|
||||
.data : {
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
}
|
||||
|
||||
_edata = .;
|
||||
|
||||
.sdata : {
|
||||
*(.srodata)
|
||||
*(.sdata)
|
||||
}
|
||||
|
||||
_bss = .;
|
||||
.bss : {
|
||||
*(.sbss)
|
||||
*(.sbss.*)
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
*(COMMON)
|
||||
|
||||
/* Stack and heap */
|
||||
|
||||
. = ALIGN(16);
|
||||
_heap = .;
|
||||
. += CONFIG_LP_HEAP_SIZE;
|
||||
. = ALIGN(16);
|
||||
_eheap = .;
|
||||
|
||||
_estack = .;
|
||||
. += CONFIG_LP_STACK_SIZE;
|
||||
. = ALIGN(16);
|
||||
_stack = .;
|
||||
}
|
||||
_ebss = .;
|
||||
|
||||
_end = .;
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.comment)
|
||||
*(.note*)
|
||||
*(.reginfo)
|
||||
|
||||
}
|
||||
}
|
||||
@ -1,58 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <exception.h>
|
||||
#include <libpayload.h>
|
||||
|
||||
/* The argc value to pass to main() */
|
||||
int main_argc;
|
||||
/* The argv value to pass to main() */
|
||||
char *main_argv[MAX_ARGC_COUNT];
|
||||
|
||||
/*
|
||||
* This is our C entry function - set up the system
|
||||
* and jump into the payload entry point.
|
||||
*/
|
||||
void start_main(void);
|
||||
void start_main(void)
|
||||
{
|
||||
extern int main(int argc, char **argv);
|
||||
|
||||
/* Gather system information. */
|
||||
lib_get_sysinfo();
|
||||
|
||||
/* Optionally set up the consoles. */
|
||||
#if !CONFIG(LP_SKIP_CONSOLE_INIT)
|
||||
console_init();
|
||||
#endif
|
||||
|
||||
exception_init();
|
||||
/*
|
||||
* Any other system init that has to happen before the
|
||||
* user gets control goes here
|
||||
*/
|
||||
|
||||
/*
|
||||
* Go to the entry point.
|
||||
* In the future we may care about the return value.
|
||||
*/
|
||||
|
||||
(void) main(main_argc, (main_argc != 0) ? main_argv : NULL);
|
||||
|
||||
/*
|
||||
* Returning here will go to the _leave function to return
|
||||
* us to the original context.
|
||||
*/
|
||||
}
|
||||
@ -1,36 +0,0 @@
|
||||
/*
|
||||
* Copyright 2014 Google Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. The name of the author may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <libpayload.h>
|
||||
|
||||
extern void *cb_header_ptr;
|
||||
|
||||
void selfboot(void *entry)
|
||||
{
|
||||
void (*entry_func)(void *) = entry;
|
||||
entry_func(cb_header_ptr);
|
||||
}
|
||||
@ -1,77 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "string.h"
|
||||
|
||||
/*
|
||||
* Alternative string functions to the default ones are added
|
||||
* because there is no guarantee that the provided source and
|
||||
* destination addresses are properly aligned;
|
||||
* The default string functions work with multiple of 4 bytes
|
||||
* (sizeof(unsinged long)); MIPS will use LW/SW instructions
|
||||
* for these operations and if the source and destination
|
||||
* addresses are not aligned it will trigger an exception.
|
||||
*/
|
||||
|
||||
void *memcpy(void *dest, const void *src, size_t n)
|
||||
{
|
||||
u8 *ptr_d = dest;
|
||||
const u8 *ptr_s = src;
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
*ptr_d++ = *ptr_s++;
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
void *memmove(void *dest, const void *src, size_t n)
|
||||
{
|
||||
if ((src < dest) && (dest - src < n)) {
|
||||
u8 *ptr_d = dest;
|
||||
const u8 *ptr_s = src;
|
||||
|
||||
/* copy backwards */
|
||||
while (n--)
|
||||
ptr_d[n] = ptr_s[n];
|
||||
|
||||
return dest;
|
||||
}
|
||||
|
||||
/* copy forwards */
|
||||
return memcpy(dest, src, n);
|
||||
}
|
||||
|
||||
void *memset(void *s, int c, size_t n)
|
||||
{
|
||||
u8 *ptr = s;
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
*ptr++ = c;
|
||||
|
||||
return s;
|
||||
}
|
||||
|
||||
int memcmp(const void *s1, const void *s2, size_t n)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
if (((u8 *)s1)[i] != ((u8 *)s2)[i])
|
||||
return ((u8 *)s1)[i] - ((u8 *)s2)[i];
|
||||
return 0;
|
||||
}
|
||||
@ -1,49 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <libpayload-config.h>
|
||||
#include <libpayload.h>
|
||||
#include <coreboot_tables.h>
|
||||
#include <multiboot_tables.h>
|
||||
|
||||
/*
|
||||
* This is a global structure that is used through the library - we set it
|
||||
* up initially with some dummy values - hopefully they will be overridden.
|
||||
*/
|
||||
struct sysinfo_t lib_sysinfo = {
|
||||
.cpu_khz = 200,
|
||||
};
|
||||
|
||||
int lib_get_sysinfo(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Get the CPU speed (for delays). */
|
||||
lib_sysinfo.cpu_khz = get_cpu_speed();
|
||||
|
||||
/* Get information from the coreboot tables,
|
||||
* if they exist */
|
||||
ret = get_coreboot_info(&lib_sysinfo);
|
||||
|
||||
/* If we can't get a good memory range, use the default. */
|
||||
if (!lib_sysinfo.n_memranges) {
|
||||
lib_sysinfo.n_memranges = 1;
|
||||
lib_sysinfo.memrange[0].base = 0;
|
||||
lib_sysinfo.memrange[0].size = 1024 * 1024;
|
||||
lib_sysinfo.memrange[0].type = CB_MEM_RAM;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -1,52 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <libpayload.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/io.h>
|
||||
|
||||
#define PISTACHIO_CLOCK_SWITCH 0xB8144200
|
||||
#define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002
|
||||
|
||||
/**
|
||||
* @ingroup arch
|
||||
* Global variable containing the speed of the processor in KHz.
|
||||
*/
|
||||
u32 cpu_khz;
|
||||
|
||||
/**
|
||||
* Calculate the speed of the processor for use in delays.
|
||||
*
|
||||
* @return The CPU speed in kHz.
|
||||
*/
|
||||
unsigned int get_cpu_speed(void)
|
||||
{
|
||||
if (IMG_PLATFORM_ID() != IMG_PLATFORM_ID_SILICON)
|
||||
cpu_khz = 50000; /* FPGA board */
|
||||
else {
|
||||
/* If MIPS PLL external bypass bit is set, it means
|
||||
* that the MIPS PLL is already set up to work at a
|
||||
* frequency of 550 MHz; otherwise, the crystal is
|
||||
* used with a frequency of 52 MHz
|
||||
*/
|
||||
if (read32(PISTACHIO_CLOCK_SWITCH) &
|
||||
MIPS_EXTERN_PLL_BYPASS_MASK)
|
||||
cpu_khz = 550000;
|
||||
else
|
||||
cpu_khz = 52000;
|
||||
}
|
||||
|
||||
return cpu_khz;
|
||||
}
|
||||
@ -1,22 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libpayload project.
|
||||
*
|
||||
* Copyright (C) 2014 Imagination Technologies
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
.global halt
|
||||
.text
|
||||
.align 4
|
||||
.type halt, function
|
||||
halt:
|
||||
j halt
|
||||
nop
|
||||
@ -80,12 +80,6 @@ if [ "$CONFIG_LP_ARCH_ARM64" = "y" ]; then
|
||||
_ARCHEXTRA=""
|
||||
_ARCH=arm64
|
||||
fi
|
||||
if [ "$CONFIG_LP_ARCH_MIPS" = "y" ]; then
|
||||
_ARCHINCDIR=$_INCDIR/mips
|
||||
_ARCHLIBDIR=$_LIBDIR/mips
|
||||
_ARCHEXTRA=""
|
||||
_ARCH=mips
|
||||
fi
|
||||
if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
|
||||
_ARCHINCDIR=$_INCDIR/x86
|
||||
_ARCHLIBDIR=$_LIBDIR/x86
|
||||
@ -170,9 +164,7 @@ if [ $DOLINK -eq 0 ]; then
|
||||
|
||||
$DEFAULT_CC $CMDLINE $_CFLAGS
|
||||
else
|
||||
if [ -z "${CONFIG_LP_ARCH_MIPS}" ]; then
|
||||
_LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
|
||||
fi
|
||||
_LIBGCC=`$DEFAULT_CC $_ARCHEXTRA -print-libgcc-file-name`
|
||||
if [ -f $_ARCHLIBDIR/head.o ]; then
|
||||
HEAD_O=$_ARCHLIBDIR/head.o
|
||||
elif [ -f $BASE/../build/head.o ]; then
|
||||
|
||||
6
payloads/libpayload/configs/config.trogdor
Normal file
6
payloads/libpayload/configs/config.trogdor
Normal file
@ -0,0 +1,6 @@
|
||||
CONFIG_LP_CHROMEOS=y
|
||||
CONFIG_LP_ARCH_ARM64=y
|
||||
CONFIG_LP_TIMER_ARM64_ARCH=y
|
||||
CONFIG_LP_USB=y
|
||||
CONFIG_LP_USB_EHCI=y
|
||||
CONFIG_LP_USB_XHCI=y
|
||||
@ -1,6 +0,0 @@
|
||||
CONFIG_LP_ARCH_MIPS=y
|
||||
CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y
|
||||
CONFIG_LP_PC_KEYBOARD=y
|
||||
CONFIG_LP_TIMER_IMG_PISTACHIO=y
|
||||
# CONFIG_LP_USB_EHCI is not set
|
||||
# CONFIG_LP_USB_XHCI is not set
|
||||
@ -54,7 +54,6 @@ ifneq ($(CONFIG_LP_TIMER_GENERIC_HZ),0)
|
||||
libc-y += timer/generic.c
|
||||
endif
|
||||
libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c
|
||||
libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c
|
||||
libc-$(CONFIG_LP_TIMER_ARM64_ARCH) += timer/arm64_arch_timer.c
|
||||
|
||||
# Video console drivers
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
x
Reference in New Issue
Block a user