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Remove old clock gate patch

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This commit is contained in:
Jeremy Soller
2019-07-15 14:26:18 -06:00
parent 95778bf7ea
commit f7b117bba7
2 changed files with 0 additions and 7 deletions
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3
src/mainboard/system76/whl-u/devicetree.cb
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@@ -156,9 +156,6 @@ chip soc/intel/cannonlake
# Address 0x90: Disabled # Address 0x90: Disabled
register "gen4_dec" = "0x00000000" register "gen4_dec" = "0x00000000"
# 8254
register "clock_gate_8254" = "0"
# PMC (soc/intel/cannonlake/pmc.c) # PMC (soc/intel/cannonlake/pmc.c)
# Enable deep Sx states # Enable deep Sx states
register "deep_s3_enable_ac" = "0" register "deep_s3_enable_ac" = "0"

4
src/soc/intel/cannonlake/fsp_params.c
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@@ -241,10 +241,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* S0ix */ /* S0ix */
params->PchPmSlpS0Enable = config->s0ix_enable; params->PchPmSlpS0Enable = config->s0ix_enable;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = config->clock_gate_8254;
params->Enable8254ClockGatingOnS3 = config->clock_gate_8254;
/* disable Legacy PME */ /* disable Legacy PME */
memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));