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soc/intel/adl: Update DCACHE_BSP_STACK_SIZE

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During the stages which use Cache-as-RAM (CAR), coreboot needs more than
1 KiB as configured in DCACHE_BSP_STACK_SIZE. After studying the UPDs
for various SoCs(ADL-P, ADL-N, RPL), coreboot stack requirement is
estimated to be 32 KiB. Update DCACHE_BSP_STACK_SIZE accordingly.

BUG=None
TEST=Build Brox BIOS image and boot to OS.

Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83680
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Karthikeyan Ramasubramanian
2024-07-29 13:37:36 -06:00
committed by Jon Murphy
parent 8200a9ac38
commit fa66d33336
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/alderlake/Kconfig
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@@ -191,12 +191,12 @@ config DCACHE_RAM_SIZE
config DCACHE_BSP_STACK_SIZE config DCACHE_BSP_STACK_SIZE
hex hex
default 0x80400 default 0x88000
help help
The amount of anticipated stack usage in CAR by bootblock and The amount of anticipated stack usage in CAR by bootblock and
other stages. In the case of FSP_USES_CB_STACK default value will be other stages. In the case of FSP_USES_CB_STACK default value will be
sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement
(~1KiB). (~32KiB).
config FSP_TEMP_RAM_SIZE config FSP_TEMP_RAM_SIZE
hex hex