sb/amd/sr5650: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which platforms using this code lack. Change-Id: I63551b9ad861fecb689036c9f26c3b0950a8b8e9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36969 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
committed by
Kyösti Mälkki
Kyösti Mälkki
parent
57803ba3f5
commit
fc20682f07
@ -1,26 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Advanced Micro Devices, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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config SOUTHBRIDGE_AMD_SR5650
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bool
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if SOUTHBRIDGE_AMD_SR5650
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config EXT_CONF_SUPPORT
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bool "Enable PCI-E MMCONFIG support"
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default y
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help
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Select to enable PCI-E MMCONFIG support on the SR5650.
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endif
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@ -1,9 +0,0 @@
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ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SR5650),y)
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ramstage-y += sr5650.c
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ramstage-y += pcie.c
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ramstage-y += ht.c
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romstage-y += early_setup.c
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endif
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@ -1,384 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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* Copyright (C) 2009 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope(\) {
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Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
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Name(HPBA, 0xFED00000) /* Base address of HPET table */
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/* PIC IRQ mapping registers, C00h-C01h */
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OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002)
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Field(PRQM, ByteAcc, NoLock, Preserve) {
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PRQI, 0x00000008,
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PRQD, 0x00000008, /* Offset: 1h */
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}
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IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PINA, 0x00000008, /* Index 0 */
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PINB, 0x00000008, /* Index 1 */
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PINC, 0x00000008, /* Index 2 */
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PIND, 0x00000008, /* Index 3 */
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AINT, 0x00000008, /* Index 4 */
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SINT, 0x00000008, /* Index 5 */
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, 0x00000008, /* Index 6 */
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AAUD, 0x00000008, /* Index 7 */
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AMOD, 0x00000008, /* Index 8 */
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PINE, 0x00000008, /* Index 9 */
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PINF, 0x00000008, /* Index A */
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PING, 0x00000008, /* Index B */
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PINH, 0x00000008, /* Index C */
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}
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/* PCI Error control register */
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OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001)
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Field(PERC, ByteAcc, NoLock, Preserve) {
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SENS, 0x00000001,
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PENS, 0x00000001,
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SENE, 0x00000001,
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PENE, 0x00000001,
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}
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Scope(\_SB) {
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/* PCIe Configuration Space for 16 busses */
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OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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*/
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Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
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STB5, 32,
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Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
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PT0D, 1,
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PT1D, 1,
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PT2D, 1,
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PT3D, 1,
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PT4D, 1,
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PT5D, 1,
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PT6D, 1,
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PT7D, 1,
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PT8D, 1,
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PT9D, 1,
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Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
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SBIE, 1,
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SBME, 1,
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Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
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SBRI, 8,
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Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
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SBB1, 32,
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Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
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,14,
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P92E, 1, /* Port92 decode enable */
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}
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OperationRegion(SB5, SystemMemory, STB5, 0x1000)
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Field(SB5, AnyAcc, NoLock, Preserve){
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/* Port 0 */
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Offset(0x120), /* Port 0 Task file status */
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P0ER, 1,
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, 2,
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P0DQ, 1,
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, 3,
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P0BY, 1,
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Offset(0x128), /* Port 0 Serial ATA status */
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P0DD, 4,
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, 4,
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P0IS, 4,
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Offset(0x12C), /* Port 0 Serial ATA control */
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P0DI, 4,
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Offset(0x130), /* Port 0 Serial ATA error */
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, 16,
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P0PR, 1,
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/* Port 1 */
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offset(0x1A0), /* Port 1 Task file status */
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P1ER, 1,
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, 2,
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P1DQ, 1,
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, 3,
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P1BY, 1,
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Offset(0x1A8), /* Port 1 Serial ATA status */
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P1DD, 4,
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, 4,
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P1IS, 4,
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Offset(0x1AC), /* Port 1 Serial ATA control */
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P1DI, 4,
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Offset(0x1B0), /* Port 1 Serial ATA error */
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, 16,
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P1PR, 1,
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/* Port 2 */
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Offset(0x220), /* Port 2 Task file status */
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P2ER, 1,
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, 2,
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P2DQ, 1,
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, 3,
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P2BY, 1,
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Offset(0x228), /* Port 2 Serial ATA status */
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P2DD, 4,
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, 4,
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P2IS, 4,
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Offset(0x22C), /* Port 2 Serial ATA control */
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P2DI, 4,
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Offset(0x230), /* Port 2 Serial ATA error */
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, 16,
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P2PR, 1,
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/* Port 3 */
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Offset(0x2A0), /* Port 3 Task file status */
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P3ER, 1,
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, 2,
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P3DQ, 1,
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, 3,
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P3BY, 1,
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Offset(0x2A8), /* Port 3 Serial ATA status */
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P3DD, 4,
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, 4,
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P3IS, 4,
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Offset(0x2AC), /* Port 3 Serial ATA control */
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P3DI, 4,
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Offset(0x2B0), /* Port 3 Serial ATA error */
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, 16,
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P3PR, 1,
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}
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Method(CIRQ, 0x00, NotSerialized){
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Store(0, PINA)
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Store(0, PINB)
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Store(0, PINC)
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Store(0, PIND)
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Store(0, PINE)
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Store(0, PINF)
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Store(0, PING)
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Store(0, PINH)
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}
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/* set "A", 8259 interrupts */
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Name (PRSA, ResourceTemplate () {
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IRQ(Level, ActiveLow, Exclusive) {4, 7, 10, 11, 12, 14, 15}
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})
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Method (CRSA, 1, Serialized) {
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Name (LRTL, ResourceTemplate() {
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IRQ(Level, ActiveLow, Shared) {15}
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})
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CreateWordField(LRTL, 1, LIRQ)
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ShiftLeft(1, Arg0, LIRQ)
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Return (LRTL)
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}
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Method (SRSA, 1, Serialized) {
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CreateWordField(Arg0, 1, LIRQ)
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FindSetRightBit(LIRQ, Local0)
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if (Local0) {
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Decrement(Local0)
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}
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Return (Local0)
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}
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Device(LNKA) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 1)
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Method(_STA, 0) {
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if (PINA) {
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Return(0x0B) /* LNKA is invisible */
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} else {
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Return(0x09) /* LNKA is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINA)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINA))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINA)
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}
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}
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Device(LNKB) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 2)
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Method(_STA, 0) {
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if (PINB) {
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Return(0x0B) /* LNKB is invisible */
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} else {
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Return(0x09) /* LNKB is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINB)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINB))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINB)
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}
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}
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Device(LNKC) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 3)
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Method(_STA, 0) {
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if (PINC) {
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Return(0x0B) /* LNKC is invisible */
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} else {
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Return(0x09) /* LNKC is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINC)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINC))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINC)
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}
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}
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Device(LNKD) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 4)
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Method(_STA, 0) {
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if (PIND) {
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Return(0x0B) /* LNKD is invisible */
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} else {
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Return(0x09) /* LNKD is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PIND)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PIND))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PIND)
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}
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}
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Device(LNKE) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 5)
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Method(_STA, 0) {
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if (PINE) {
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Return(0x0B) /* LNKE is invisible */
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} else {
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Return(0x09) /* LNKE is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINE)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINE))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINE)
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}
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}
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Device(LNKF) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 6)
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Method(_STA, 0) {
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if (PINF) {
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Return(0x0B) /* LNKF is invisible */
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} else {
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Return(0x09) /* LNKF is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINF)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINF))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PINF)
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}
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}
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Device(LNKG) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 7)
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Method(_STA, 0) {
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if (PING) {
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Return(0x0B) /* LNKG is invisible */
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} else {
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Return(0x09) /* LNKG is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PING)
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PING))
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}
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Method (_SRS, 1, Serialized) {
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Store (SRSA(Arg0), PING)
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}
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}
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Device(LNKH) {
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Name(_HID, EISAID("PNP0C0F"))
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Name(_UID, 8)
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Method(_STA, 0) {
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if (PINH) {
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Return(0x0B) /* LNKH is invisible */
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} else {
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Return(0x09) /* LNKH is disabled */
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}
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}
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Method(_DIS, 0) {
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Store(0, PINH)
|
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}
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Method(_PRS, 0) {
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Return (PRSA)
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}
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Method (_CRS, 0, Serialized) {
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Return (CRSA(PINH))
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}
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Method (_SRS, 1, Serialized) {
|
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Store (SRSA(Arg0), PINH)
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}
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}
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} /* End Scope(_SB) */
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} /* End Scope(/) */
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@ -1,34 +0,0 @@
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/*
|
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* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef SR5650_CHIP_H
|
||||
#define SR5650_CHIP_H
|
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|
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#include <stdint.h>
|
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|
||||
/* Member variables are defined in Config.lb. */
|
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struct southbridge_amd_sr5650_config
|
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{
|
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u8 gpp1_configuration; /* The configuration of General Purpose Port. */
|
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u8 gpp2_configuration; /* The configuration of General Purpose Port. */
|
||||
u8 gpp3a_configuration; /* The configuration of General Purpose Port. */
|
||||
u16 port_enable; /* Which port is enabled? GPP(2,3,4,5,6,7,9,10,11,12,13) */
|
||||
uint32_t pcie_settling_time; /* How long to wait after link training for PCI-e devices to
|
||||
* initialize before probing PCI-e busses (in microseconds).
|
||||
*/
|
||||
};
|
||||
|
||||
#endif /* SR5650_CHIP_H */
|
||||
@ -1,219 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SR5650_CMN_H__
|
||||
#define __SR5650_CMN_H__
|
||||
|
||||
#include <device/pci_ops.h>
|
||||
|
||||
#define NBMISC_INDEX 0x60
|
||||
#define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */
|
||||
#define NBMC_INDEX 0xE8
|
||||
#define NBPCIE_INDEX 0xE0
|
||||
#define L2CFG_INDEX 0xF0
|
||||
#define L1CFG_INDEX 0xF8
|
||||
#define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS
|
||||
#define TEMP_MMIO_BASE_ADDRESS 0xC0000000
|
||||
|
||||
#define axindxc_reg(reg, mask, val) \
|
||||
alink_ax_indx(0, (reg), (mask), (val))
|
||||
|
||||
#define AB_INDX 0xCD8
|
||||
#define AB_DATA (AB_INDX+4)
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline u32 nb_read_index(pci_devfn_t dev, u32 index_reg, u32 index)
|
||||
#else
|
||||
static inline u32 nb_read_index(struct device *dev, u32 index_reg, u32 index)
|
||||
#endif
|
||||
{
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
return pci_read_config32(dev, index_reg + 0x4);
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void nb_write_index(pci_devfn_t dev, u32 index_reg, u32 index,
|
||||
u32 data)
|
||||
#else
|
||||
static inline void nb_write_index(struct device *dev, u32 index_reg, u32 index,
|
||||
u32 data)
|
||||
#endif
|
||||
{
|
||||
pci_write_config32(dev, index_reg, index);
|
||||
pci_write_config32(dev, index_reg + 0x4, data);
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline u32 nbmisc_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
#else
|
||||
static inline u32 nbmisc_read_index(struct device *nb_dev, u32 index)
|
||||
#endif
|
||||
{
|
||||
return nb_read_index((nb_dev), NBMISC_INDEX, (index));
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void nbmisc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
#else
|
||||
static inline void nbmisc_write_index(struct device *nb_dev, u32 index,
|
||||
u32 data)
|
||||
#endif
|
||||
{
|
||||
nb_write_index((nb_dev), NBMISC_INDEX, ((index) | 0x80), (data));
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void set_nbmisc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#else
|
||||
static inline void set_nbmisc_enable_bits(struct device *nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#endif
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = nbmisc_read_index(nb_dev, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
nbmisc_write_index(nb_dev, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline u32 htiu_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
#else
|
||||
static inline u32 htiu_read_index(struct device *nb_dev, u32 index)
|
||||
#endif
|
||||
{
|
||||
return nb_read_index((nb_dev), NBHTIU_INDEX, (index));
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void htiu_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
#else
|
||||
static inline void htiu_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
#endif
|
||||
{
|
||||
nb_write_index((nb_dev), NBHTIU_INDEX, ((index) | 0x100), (data));
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline u32 nbmc_read_index(pci_devfn_t nb_dev, u32 index)
|
||||
#else
|
||||
static inline u32 nbmc_read_index(struct device *nb_dev, u32 index)
|
||||
#endif
|
||||
{
|
||||
return nb_read_index((nb_dev), NBMC_INDEX, (index));
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void nbmc_write_index(pci_devfn_t nb_dev, u32 index, u32 data)
|
||||
#else
|
||||
static inline void nbmc_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
#endif
|
||||
{
|
||||
nb_write_index((nb_dev), NBMC_INDEX, ((index) | 1 << 9), (data));
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void set_htiu_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#else
|
||||
static inline void set_htiu_enable_bits(struct device *nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#endif
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = htiu_read_index(nb_dev, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
htiu_write_index(nb_dev, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void set_nbcfg_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#else
|
||||
static inline void set_nbcfg_enable_bits(struct device *nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#endif
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = pci_read_config32(nb_dev, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
pci_write_config32(nb_dev, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void set_nbcfg_enable_bits_8(pci_devfn_t nb_dev, u32 reg_pos,
|
||||
u8 mask, u8 val)
|
||||
#else
|
||||
static inline void set_nbcfg_enable_bits_8(struct device *nb_dev, u32 reg_pos,
|
||||
u8 mask, u8 val)
|
||||
#endif
|
||||
{
|
||||
u8 reg_old, reg;
|
||||
reg = reg_old = pci_read_config8(nb_dev, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
pci_write_config8(nb_dev, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void set_nbmc_enable_bits(pci_devfn_t nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#else
|
||||
static inline void set_nbmc_enable_bits(struct device *nb_dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#endif
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = nbmc_read_index(nb_dev, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
nbmc_write_index(nb_dev, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
#if ENV_PCI_SIMPLE_DEVICE
|
||||
static inline void set_pcie_enable_bits(pci_devfn_t dev, u32 reg_pos, u32 mask,
|
||||
u32 val)
|
||||
#else
|
||||
static inline void set_pcie_enable_bits(struct device *dev, u32 reg_pos,
|
||||
u32 mask, u32 val)
|
||||
#endif
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
reg = reg_old = nb_read_index(dev, NBPCIE_INDEX, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
nb_write_index(dev, NBPCIE_INDEX, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
void set_pcie_reset(void);
|
||||
void set_pcie_dereset(void);
|
||||
|
||||
#endif /* __SR5650_CMN_H__ */
|
||||
@ -1,586 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch/cpu.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <option.h>
|
||||
#include <southbridge/amd/common/reset.h>
|
||||
#include "sr5650.h"
|
||||
#include "cmn.h"
|
||||
|
||||
/* space = 0: AX_INDXC, AX_DATAC
|
||||
* space = 1: AX_INDXP, AX_DATAP
|
||||
*/
|
||||
static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
/* read axindc to tmp */
|
||||
outl(space << 30 | space << 3 | 0x30, AB_INDX);
|
||||
outl(axindc, AB_DATA);
|
||||
outl(space << 30 | space << 3 | 0x34, AB_INDX);
|
||||
tmp = inl(AB_DATA);
|
||||
|
||||
tmp &= ~mask;
|
||||
tmp |= val;
|
||||
|
||||
/* write tmp */
|
||||
outl(space << 30 | space << 3 | 0x30, AB_INDX);
|
||||
outl(axindc, AB_DATA);
|
||||
outl(space << 30 | space << 3 | 0x34, AB_INDX);
|
||||
outl(tmp, AB_DATA);
|
||||
}
|
||||
|
||||
|
||||
static void set_fam10_ext_cfg_enable_bits(pci_devfn_t fam10_dev,
|
||||
u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
||||
/* family 10 only, for reg > 0xFF */
|
||||
if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
|
||||
return;
|
||||
|
||||
reg = reg_old = pci_read_config32(fam10_dev, reg_pos);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
pci_write_config32(fam10_dev, reg_pos, reg);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Compliant with CIM_33's ATINB_PrepareInit
|
||||
*/
|
||||
static void get_cpu_rev(void)
|
||||
{
|
||||
u32 eax;
|
||||
|
||||
eax = cpuid_eax(1);
|
||||
printk(BIOS_INFO, "get_cpu_rev EAX=0x%x.\n", eax);
|
||||
if (eax <= 0xfff)
|
||||
printk(BIOS_INFO, "CPU Rev is K8_Cx.\n");
|
||||
else if (eax <= 0x10fff)
|
||||
printk(BIOS_INFO, "CPU Rev is K8_Dx.\n");
|
||||
else if (eax <= 0x20fff)
|
||||
printk(BIOS_INFO, "CPU Rev is K8_Ex.\n");
|
||||
else if (eax <= 0x40fff)
|
||||
printk(BIOS_INFO, "CPU Rev is K8_Fx.\n");
|
||||
else if (eax == 0x60fb1 || eax == 0x60f81) /*These two IDS are exception, they are G1. */
|
||||
printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
|
||||
else if (eax <= 0X60FF0)
|
||||
printk(BIOS_INFO, "CPU Rev is K8_G0.\n");
|
||||
else if (eax <= 0x100000)
|
||||
printk(BIOS_INFO, "CPU Rev is K8_G1.\n");
|
||||
else if (eax <= 0x100fa0)
|
||||
printk(BIOS_INFO, "CPU Rev is Fam 10.\n");
|
||||
else if (eax <= 0x600f20)
|
||||
printk(BIOS_INFO, "CPU Rev is Fam 15.\n");
|
||||
else
|
||||
printk(BIOS_INFO, "CPU Rev is not recognized.\n");
|
||||
}
|
||||
|
||||
/*
|
||||
CIM NB_GetRevisionInfo()
|
||||
*/
|
||||
static u8 get_nb_rev(pci_devfn_t nb_dev)
|
||||
{
|
||||
u8 reg;
|
||||
reg = pci_read_config8(nb_dev, 0x8); /* copy from CIM, can't find in doc */
|
||||
switch (reg & 3)
|
||||
{
|
||||
case 0x00:
|
||||
reg = REV_SR5650_A11;
|
||||
break;
|
||||
case 0x02:
|
||||
default:
|
||||
reg = REV_SR5650_A12;
|
||||
break;
|
||||
}
|
||||
return reg;
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Compliant with SR5650_CIMX_4_5_0 NBHT_InitHT().
|
||||
* Init HT link speed/width for sr5650 -- k8 link
|
||||
1: Check CPU Family, Family10?
|
||||
2: Get CPU's HT speed and width
|
||||
3: Decide HT mode 1 or 3 by HT Speed. >1GHz: HT3, else HT1
|
||||
4:
|
||||
*****************************************/
|
||||
static const u8 sr5650_ibias[] = {
|
||||
/* 1, 3 are reserved. */
|
||||
[0x0] = 0x44, /* 200MHz HyperTransport 1 only */
|
||||
[0x2] = 0x44, /* 400MHz HyperTransport 1 only */
|
||||
[0x4] = 0xB6, /* 600MHz HyperTransport 1 only */
|
||||
[0x5] = 0x44, /* 800MHz HyperTransport 1 only */
|
||||
[0x6] = 0x96, /* 1GHz HyperTransport 1 only */
|
||||
/* HT3 for Family 10 */
|
||||
[0x7] = 0xB6, /* 1.2GHz HyperTransport 3 only */
|
||||
[0x8] = 0x23, /* 1.4GHz HyperTransport 3 only */
|
||||
[0x9] = 0x44, /* 1.6GHz HyperTransport 3 only */
|
||||
[0xa] = 0x64, /* 1.8GHz HyperTransport 3 only */
|
||||
[0xb] = 0x96, /* 2.0GHz HyperTransport 3 only */
|
||||
[0xc] = 0xA6, /* 2.2GHz HyperTransport 3 only */
|
||||
[0xd] = 0xB6, /* 2.4GHz HyperTransport 3 only */
|
||||
[0xe] = 0xC6, /* 2.6GHz HyperTransport 3 only */
|
||||
};
|
||||
|
||||
void sr5650_htinit(void)
|
||||
{
|
||||
/*
|
||||
* About HT, it has been done in enumerate_ht_chain().
|
||||
*/
|
||||
pci_devfn_t cpu_f0, sr5650_f0, clk_f1;
|
||||
u32 reg;
|
||||
u8 cpu_ht_freq, cpu_htfreq_max, ibias;
|
||||
u8 sbnode;
|
||||
u8 sblink;
|
||||
u16 linkfreq_reg;
|
||||
u16 linkfreqext_reg;
|
||||
|
||||
/************************
|
||||
* get cpu's ht freq, in cpu's function 0, offset 0x88
|
||||
* bit11-8, specifics the maximum operation frequency of the link's transmitter clock.
|
||||
* The link frequency field (Frq) is cleared by cold reset. SW can write a nonzero
|
||||
* value to this reg, and that value takes effect on the next warm reset or
|
||||
* LDTSTOP_L disconnect sequence.
|
||||
* please see the table sr5650_ibias about the value and its corresponding frequency.
|
||||
************************/
|
||||
/* Link0, Link1 are for connection between P0 and P1.
|
||||
* TODO: Check the topology of the MP and NB. Or we just read the nbconfig? */
|
||||
/* NOTE: In most cases, we only have one CPU. In that case, we should read 0x88. */
|
||||
|
||||
/* Find out the node ID and the Link ID that
|
||||
* connects to the Southbridge (system IO hub).
|
||||
*/
|
||||
sbnode = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 8) & 7;
|
||||
sblink = (pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64) >> 8) & 3; /* bit[10] sublink, bit[9,8] link. */
|
||||
cpu_f0 = PCI_DEV(0, (0x18 + sbnode), 0);
|
||||
|
||||
/*
|
||||
* link freq reg of Link0, 1, 2, 3 is 0x88, 0xA8, 0xC8, 0xE8 respectively
|
||||
* link freq ext reg of Link0, 1, 2, 3 is 0x9C, 0xBC, 0xDC, 0xFC respectively
|
||||
*/
|
||||
linkfreq_reg = 0x88 + (sblink << 5);
|
||||
linkfreqext_reg = 0x9C + (sblink << 5);
|
||||
reg = pci_read_config32(cpu_f0, linkfreq_reg);
|
||||
|
||||
cpu_ht_freq = (reg & 0xf00) >> 8;
|
||||
|
||||
/* Freq[4] is only valid for revision D and later processors */
|
||||
if (cpuid_eax(1) >= 0x100F80) {
|
||||
cpu_htfreq_max = 0x14;
|
||||
cpu_ht_freq |= ((pci_read_config32(cpu_f0, linkfreqext_reg) & 0x01) << 4);
|
||||
} else {
|
||||
cpu_htfreq_max = 0x0F;
|
||||
}
|
||||
|
||||
printk(BIOS_INFO, "sr5650_htinit: Node %x Link %x, HT freq=%x.\n",
|
||||
sbnode, sblink, cpu_ht_freq);
|
||||
sr5650_f0 = PCI_DEV(0, 0, 0);
|
||||
|
||||
clk_f1 = PCI_DEV(0, 0, 1); /* We need to make sure the F1 is accessible. */
|
||||
|
||||
ibias = sr5650_ibias[cpu_ht_freq];
|
||||
|
||||
/* If HT freq>1GHz, we assume the CPU is fam10, else it is K8.
|
||||
* Is it appropriate?
|
||||
* Frequency is 1GHz, i.e. cpu_ht_freq is 6, in most cases.
|
||||
* So we check 6 only, it would be faster. */
|
||||
if ((cpu_ht_freq == 0x6) || (cpu_ht_freq == 0x5) || (cpu_ht_freq == 0x4) ||
|
||||
(cpu_ht_freq == 0x2) || (cpu_ht_freq == 0x0)) {
|
||||
printk(BIOS_INFO, "sr5650_htinit: HT1 mode\n");
|
||||
|
||||
/* HT1 mode, RPR 5.4.2 */
|
||||
/* set IBIAS code */
|
||||
set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
|
||||
/* Optimizes chipset HT transmitter drive strength */
|
||||
set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x3);
|
||||
} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < cpu_htfreq_max)) {
|
||||
printk(BIOS_INFO, "sr5650_htinit: HT3 mode\n");
|
||||
|
||||
/* Enable Protocol checker */
|
||||
set_htiu_enable_bits(sr5650_f0, 0x1E, 0xFFFFFFFF, 0x7FFFFFFC);
|
||||
|
||||
#if CONFIG(NORTHBRIDGE_AMD_AMDFAM10)
|
||||
/* HT3 mode, RPR 5.4.3 */
|
||||
set_nbcfg_enable_bits(sr5650_f0, 0x9c, 0x3 << 16, 0);
|
||||
|
||||
/* set IBIAS code */
|
||||
set_nbcfg_enable_bits(clk_f1, 0xD8, 0x3FF, ibias);
|
||||
/* Optimizes chipset HT transmitter drive strength */
|
||||
set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3, 0x1);
|
||||
/* Enables error-retry mode */
|
||||
set_nbcfg_enable_bits(sr5650_f0, 0x44, 0x1, 0x1);
|
||||
/* Enables scrambling and Disables command throttling */
|
||||
set_nbcfg_enable_bits(sr5650_f0, 0xac, (1 << 3) | (1 << 14), (1 << 3) | (1 << 14));
|
||||
/* Enables transmitter de-emphasis */
|
||||
set_nbcfg_enable_bits(sr5650_f0, 0xa4, 1 << 31, 1 << 31);
|
||||
/* Enables transmitter de-emphasis level */
|
||||
/* Sets training 0 time */
|
||||
set_nbcfg_enable_bits(sr5650_f0, 0xa0, 0x3F, 0x14);
|
||||
|
||||
/* Enables strict TM4 detection */
|
||||
set_htiu_enable_bits(sr5650_f0, 0x15, 0x1 << 22, 0x1 << 22);
|
||||
|
||||
/* Optimizes chipset HT transmitter drive strength */
|
||||
set_htiu_enable_bits(sr5650_f0, 0x2A, 0x3 << 0, 0x1 << 0);
|
||||
|
||||
/* HyperTransport 3 Processor register settings to be done in northbridge */
|
||||
|
||||
/* Enables error-retry mode */
|
||||
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x130 + (sblink << 2), 1 << 0, 1 << 0);
|
||||
|
||||
/* Enables scrambling */
|
||||
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x170 + (sblink << 2), 1 << 3, 1 << 3);
|
||||
|
||||
/* Enables transmitter de-emphasis
|
||||
* This depends on the PCB design and the trace
|
||||
*/
|
||||
/* Disables command throttling */
|
||||
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x168, 1 << 10, 1 << 10);
|
||||
|
||||
/* Sets Training 0 Time. See T0Time table for encodings */
|
||||
/* AGESA have set it to recommended value already
|
||||
* The recommended values are 14h(2us) if F0x[18C:170][LS2En]=0
|
||||
* and 26h(12us) if F0x[18C:170][LS2En]=1
|
||||
*/
|
||||
//set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x26);
|
||||
|
||||
/* HT Buffer Allocation for Ganged Links!!! */
|
||||
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
/* Must be run immediately after HT setup is complete and first warm reset has occurred (if applicable)
|
||||
* Attempting to switch the NB into isochronous mode before the CPUs have engaged isochronous mode
|
||||
* will cause a system hard lockup...
|
||||
*/
|
||||
void sr5650_htinit_dect_and_enable_isochronous_link(void)
|
||||
{
|
||||
pci_devfn_t sr5650_f0;
|
||||
unsigned char iommu;
|
||||
|
||||
sr5650_f0 = PCI_DEV(0, 0, 0);
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
if (iommu) {
|
||||
/* Enable isochronous mode */
|
||||
set_nbcfg_enable_bits(sr5650_f0, 0xc8, 1 << 12, 1 << 12);
|
||||
|
||||
/* Apply pending changes */
|
||||
if (!((pci_read_config32(sr5650_f0, 0xc8) >> 12) & 0x1)) {
|
||||
printk(BIOS_INFO, "...WARM RESET...\n\n\n");
|
||||
soft_reset();
|
||||
die("After soft_reset - shouldn't see this message!!!\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fam10_optimization(void)
|
||||
{
|
||||
pci_devfn_t cpu_f0, cpu_f2, cpu_f3;
|
||||
pci_devfn_t cpu1_f0, cpu1_f2, cpu1_f3;
|
||||
msr_t msr;
|
||||
u32 val;
|
||||
|
||||
if (!CONFIG(NORTHBRIDGE_AMD_AMDFAM10))
|
||||
return;
|
||||
|
||||
printk(BIOS_INFO, "fam10_optimization()\n");
|
||||
msr = rdmsr(NB_CFG_MSR);
|
||||
msr.hi |= 1 << 14; /* bit 46: EnableCf8ExtCfg */
|
||||
wrmsr(NB_CFG_MSR, msr);
|
||||
|
||||
cpu_f0 = PCI_DEV(0, 0x18, 0);
|
||||
cpu_f2 = PCI_DEV(0, 0x18, 2);
|
||||
cpu_f3 = PCI_DEV(0, 0x18, 3);
|
||||
cpu1_f0 = PCI_DEV(0, 0x19, 0);
|
||||
cpu1_f2 = PCI_DEV(0, 0x19, 2);
|
||||
cpu1_f3 = PCI_DEV(0, 0x19, 3);
|
||||
|
||||
val = pci_read_config32(cpu1_f3, 0x8C);
|
||||
val |= 1 << 14;
|
||||
pci_write_config32(cpu1_f3, 0x8C, val);
|
||||
|
||||
/* TODO: HT Buffer Allocation for (un)Ganged Links */
|
||||
/* rpr Table 5-11, 5-12 */
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's ATINB_PCICFG_POR_TABLE
|
||||
*****************************************/
|
||||
static void sr5650_por_pcicfg_init(pci_devfn_t nb_dev)
|
||||
{
|
||||
/* enable PCI Memory Access */
|
||||
set_nbcfg_enable_bits_8(nb_dev, 0x04, (u8)(~0xFD), 0x02);
|
||||
|
||||
set_nbcfg_enable_bits(nb_dev, 0x14, ~0, 0x0);
|
||||
set_nbcfg_enable_bits(nb_dev, 0x18, ~0, 0x0);
|
||||
set_nbcfg_enable_bits(nb_dev, 0x20, ~0, 0x0);
|
||||
set_nbcfg_enable_bits(nb_dev, 0x84, ~0, 0x03000010);
|
||||
|
||||
/* Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
|
||||
* Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
|
||||
* BMMsgEn */
|
||||
set_nbcfg_enable_bits(nb_dev, 0x4C, (u8)(~0x00), 0x52042);
|
||||
|
||||
set_nbcfg_enable_bits(nb_dev, 0x7C, (u8)(~0), 0x0);
|
||||
|
||||
/* Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR,
|
||||
* force this BAR as mem type in sr5650_gfx.c */
|
||||
//set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03);
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's ATINB_MISCIND_POR_TABLE
|
||||
* Compliant with CIM_33's MISC_INIT_TBL
|
||||
*****************************************/
|
||||
static void sr5650_por_misc_index_init(pci_devfn_t nb_dev)
|
||||
{
|
||||
unsigned char iommu;
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
if (iommu) {
|
||||
/* enable IOMMU */
|
||||
printk(BIOS_DEBUG, "Enabling IOMMU\n");
|
||||
set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x1);
|
||||
} else {
|
||||
/* disable IOMMU */
|
||||
printk(BIOS_DEBUG, "Disabling IOMMU\n");
|
||||
set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x0);
|
||||
}
|
||||
|
||||
/* NBMISCIND:0x75[29]= 1 Device ID for hotplug and PME message */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 29, 1 << 29);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 9, 1 << 9); /* no doc reference, comply with BTS */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x46, 1 << 7, 1 << 7); /* bit7 BTS fail*/
|
||||
/*P2P*/
|
||||
set_nbmisc_enable_bits(nb_dev, 0x48, 1 << 8, 0);
|
||||
|
||||
set_nbmisc_enable_bits(nb_dev, 0x2A, 1 << 15 | 1 << 17, 1 << 17);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x2B, 1 << 15 | 1 << 27, 1 << 15 | 1 << 27);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x2C, 1 << 0 | 1 << 1 | 1 << 5 | 1 << 4 | 1 << 10, 1 << 0 | 1 << 1 | 1 << 5);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x32, 0x3F << 20, 0x2A << 20);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x34, 1 << 7 | 1 << 15 | 1 << 23, 0);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3F << 26, 0x2A << 26);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x37, 0xfff << 20, 0xddd << 20);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x37, 7 << 11, 0);
|
||||
/* PCIE CDR setting */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x38, 0xFFFFFFFF, 0xC0C0C0);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x22, 0xFFFFFFFF, (1 << 27) | (0x8 << 12) | (0x8 << 16) | (0x8 << 20));
|
||||
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7, 1 << 1 | 1 << 2 | 1 << 6 | 1 << 7);
|
||||
|
||||
set_nbmisc_enable_bits(nb_dev, 0x07, 0xF << 4 | 1 << 24, 0xF << 4 | 1 << 24);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x67, 1 << 10 | 1 << 11 | 1 << 26, 1 << 11);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x67, 3 << 21, 3 << 21);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x68, 1 << 8 | 1 << 9 | 1 << 19, 1 << 9 | 1 << 19);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x6B, 3 << 3 | 1 << 15 | 0x1F << 27, 3 << 3 | 1 << 15 | 0x1F << 27);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x6C, 0xFFFFFFFF, 0x41183000);
|
||||
|
||||
/* NB_MISC_IND_WR_EN + IOC_PCIE_CNTL
|
||||
* Block non-snoop DMA request if PMArbDis is set.
|
||||
* Set BMSetDis */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0B, 0xFFFFFFFF, 0x00400180);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310);
|
||||
|
||||
/* NBCFG (NBMISCIND 0x0): NB_CNTL -
|
||||
* HIDE_NB_AGP_CAP ([0], default=1)HIDE
|
||||
* HIDE_P2P_AGP_CAP ([1], default=1)HIDE
|
||||
* HIDE_NB_GART_BAR ([2], default=1)HIDE
|
||||
* HIDE_MMCFG_BAR ([3], default=1)SHOW
|
||||
* AGPMODE30 ([4], default=0)DISABLE
|
||||
* AGP30ENCHANCED ([5], default=0)DISABLE
|
||||
* HIDE_CLKCFG_HEADER ([8], default=0)SHOW */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8);
|
||||
|
||||
/* IOC_LAT_PERF_CNTR_CNTL */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00);
|
||||
//set_nbmisc_enable_bits(nb_dev, 0x31, 0xFF, 0x00);
|
||||
|
||||
/* IOC_LAT_PERF_CNTR_OUT */
|
||||
/* IOC_JTAG_CNTL */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x47, 0xFFFFFFFF, 0x0000000B);
|
||||
|
||||
set_nbmisc_enable_bits(nb_dev, 0x12, 0xFFFFFFFF, 0x00FB5555);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0C, 0xFFFFFFFF, 0x001F37FC);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x15, 0xFFFFFFFF, 0x0);
|
||||
|
||||
/* NB_PROG_DEVICE_REMAP */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x20, 0xFFFFFFFF, 0x0);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x21, 0xFFFFFFFF, 0x0);
|
||||
|
||||
/* Compliant with CIM_33's MISC_INIT_TBL, except Hide NB_BAR3_PCIE
|
||||
* Enable access to DEV8
|
||||
* Enable setPower message for all ports
|
||||
*/
|
||||
set_nbmisc_enable_bits(nb_dev, 0x51, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x53, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x55, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x57, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x59, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x5B, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x5D, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x5F, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x61, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x63, 1 << 20 | 1 << 8, 1 << 20 | 1 << 8);
|
||||
|
||||
/* Disable bus-master trigger event from SB and Enable set_slot_power message to SB */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0B, 0xffffffff, 0x400180);
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Some setting is from rpr. Some is from CIMx.
|
||||
*****************************************/
|
||||
static void sr5650_por_htiu_index_init(pci_devfn_t nb_dev)
|
||||
{
|
||||
pci_devfn_t cpu_f0;
|
||||
|
||||
cpu_f0 = PCI_DEV(0, 0x18, 0);
|
||||
|
||||
set_htiu_enable_bits(nb_dev, 0x1C, 0x1<<17, 0x1<<17);
|
||||
set_htiu_enable_bits(nb_dev, 0x05, 0x1<<8, 0x1<<8);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<0, 0x0<<0);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<1, 0x1<<1);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<9, 0x1<<9);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<13, 0x1<<13);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<17, 0x1<<17);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x3<<15, 0x3<<15);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<25, 0x1<<25);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<30, 0x1<<30);
|
||||
|
||||
set_htiu_enable_bits(nb_dev, 0x07, 0x1 << 0 | 0x1 << 1 | 0x1 << 2, 0x1 << 0);
|
||||
|
||||
set_htiu_enable_bits(nb_dev, 0x16, 0x1<<11, 0x1<<11);
|
||||
|
||||
set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<2, 0x1<<2);
|
||||
set_htiu_enable_bits(nb_dev, 0x1D, 0x1<<4, 0x1<<4);
|
||||
|
||||
axindxc_reg(0x10, 1 << 9, 1 << 9);
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | 5 << 16, 1 << 9, 1 << 9);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0x1<<26, 0x1<<26);
|
||||
set_htiu_enable_bits(nb_dev, 0x16, 0x1<<10, 0x1<<10);
|
||||
|
||||
/* Enable BIAS circuit for all lanes. */
|
||||
//set_htiu_enable_bits(nb_dev, 0x2B, 0xF<<28, 0xF<<28);
|
||||
set_htiu_enable_bits(nb_dev, 0x2B, 0xF << 28, 0);
|
||||
set_htiu_enable_bits(nb_dev, 0x05, 0xFFFFFF, 0xFF558);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 0xFFFFFFFE, 0x04203A202);
|
||||
set_htiu_enable_bits(nb_dev, 0x0C, 0xFFFF, 0x101);
|
||||
|
||||
/* A21 only */
|
||||
//if (REV_SR5650_A21 == get_nb_rev(nb_dev)) {
|
||||
if (get_nb_rev(nb_dev) > REV_SR5650_A11) {
|
||||
set_htiu_enable_bits(nb_dev, 0x05, 0x3<<3| 1<<6 | 1<<10 | 0xFF<<12, 0x3<<3 | 1<<6 | 1<<10 | 0xFF<<12);
|
||||
set_htiu_enable_bits(nb_dev, 0x1D, 1 << 2 | 1 << 4, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's ATINB_POR_INIT_JMPDI
|
||||
* Configure SR5650 registers to power-on default RPR.
|
||||
* POR: Power On Reset
|
||||
* RPR: Register Programming Requirements
|
||||
*****************************************/
|
||||
static void sr5650_por_init(pci_devfn_t nb_dev)
|
||||
{
|
||||
printk(BIOS_INFO, "sr5650_por_init\n");
|
||||
/* ATINB_PCICFG_POR_TABLE, initialize the values for sr5650 PCI Config registers */
|
||||
sr5650_por_pcicfg_init(nb_dev);
|
||||
|
||||
/* ATINB_MISCIND_POR_TABLE */
|
||||
sr5650_por_misc_index_init(nb_dev);
|
||||
|
||||
/* ATINB_HTIUNBIND_POR_TABLE */
|
||||
sr5650_por_htiu_index_init(nb_dev);
|
||||
|
||||
/* ATINB_CLKCFG_PORT_TABLE */
|
||||
/* sr5650 A11 SB Link full swing? */
|
||||
}
|
||||
|
||||
/* enable CFG access to Dev8, which is the SB P2P Bridge */
|
||||
void enable_sr5650_dev8(void)
|
||||
{
|
||||
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
|
||||
}
|
||||
|
||||
/*
|
||||
* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
|
||||
*/
|
||||
void sr5650_before_pci_init(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* The calling sequence is same as CIM.
|
||||
*/
|
||||
void sr5650_early_setup(void)
|
||||
{
|
||||
pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
|
||||
printk(BIOS_INFO, "sr5650_early_setup()\n");
|
||||
|
||||
/*ATINB_PrepareInit */
|
||||
get_cpu_rev();
|
||||
|
||||
uint8_t revno = get_nb_rev(nb_dev);
|
||||
switch (revno) { /* PCIEMiscInit */
|
||||
case REV_SR5650_A11:
|
||||
printk(BIOS_INFO, "NB Revision is A11.\n");
|
||||
break;
|
||||
case REV_SR5650_A12:
|
||||
printk(BIOS_INFO, "NB Revision is A12.\n");
|
||||
break;
|
||||
case REV_SR5650_A21:
|
||||
printk(BIOS_INFO, "NB Revision is A21.\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_INFO, "NB Revision is %02x (Unrecognized).\n", revno);
|
||||
break;
|
||||
}
|
||||
|
||||
fam10_optimization();
|
||||
sr5650_por_init(nb_dev);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief disable GPP1 Port0,1, GPP2, GPP3a Port0,1,2,3,4,5, GPP3b
|
||||
*
|
||||
*/
|
||||
void sr5650_disable_pcie_bridge(void)
|
||||
{
|
||||
u32 mask;
|
||||
u32 reg;
|
||||
pci_devfn_t nb_dev = PCI_DEV(0, 0, 0);
|
||||
|
||||
mask = (1 << 2) | (1 << 3); /*GPP1*/
|
||||
mask |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
|
||||
mask |= (1 << 18) | (1 << 19); /*GPP2*/
|
||||
mask |= (1 << 20); /*GPP3b*/
|
||||
reg = mask;
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0c, mask, reg);
|
||||
}
|
||||
@ -1,290 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include "sr5650.h"
|
||||
#include "cmn.h"
|
||||
|
||||
/* Table 6-6 Recommended Interrupt Routing Configuration */
|
||||
typedef struct _apic_device_info {
|
||||
u8 group;
|
||||
u8 swizzle;
|
||||
u8 pin;
|
||||
} apic_device_info;
|
||||
|
||||
#define ABCD 0
|
||||
#define BCDA 1
|
||||
#define CDAB 2
|
||||
#define DABC 3
|
||||
|
||||
static const apic_device_info default_apic_device_info_t [] = {
|
||||
/* Group Swizzling Port Int Pin */
|
||||
[0] = {0, 0, 31}, /* HT */
|
||||
[1] = {0, 0, 31}, /* IOMMU */
|
||||
[2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */
|
||||
[3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */
|
||||
[4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */
|
||||
[5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */
|
||||
[6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */
|
||||
[7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */
|
||||
[8] = {0, 0, 0 }, /* Reserved */
|
||||
[9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */
|
||||
[10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */
|
||||
[11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */
|
||||
[12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */
|
||||
[13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */
|
||||
};
|
||||
|
||||
/* These define names are common, so undefine them to avoid potential issues in other code */
|
||||
#undef ABCD
|
||||
#undef BCDA
|
||||
#undef CDAB
|
||||
#undef DABC
|
||||
|
||||
/* Init APIC of sr5690 */
|
||||
static void sr5690_apic_init(struct device *dev)
|
||||
{
|
||||
u32 dword;
|
||||
const apic_device_info *entry = default_apic_device_info_t;
|
||||
|
||||
/* rpr6.2.(2). Write to the IOAPIC Features Enable register */
|
||||
pci_write_config32(dev, 0xF8, 0x0);
|
||||
pci_write_config32(dev, 0xFC, 0x1F);
|
||||
/* rpr6.2.(3). Write to the remaining interrupt routing registers */
|
||||
|
||||
/* IOAPICCMISCIND:0x3, group & swizzle of Dev 2,3,4,5 */
|
||||
dword = (entry[2].group | entry[2].swizzle << 4) << 0 |
|
||||
(entry[3].group | entry[3].swizzle << 4) << 8 |
|
||||
(entry[4].group | entry[4].swizzle << 4) << 16 |
|
||||
(entry[5].group | entry[5].swizzle << 4) << 24;
|
||||
pci_write_config32(dev, 0xF8, 0x3);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
/* IOAPICCMISCIND:0x4, group & swizzle of Dev 6,7,9,10 */
|
||||
dword = (entry[6].group | entry[6].swizzle << 4) << 0 |
|
||||
(entry[7].group | entry[7].swizzle << 4) << 8 |
|
||||
(entry[9].group | entry[9].swizzle << 4) << 16 |
|
||||
(entry[10].group | entry[10].swizzle << 4) << 24;
|
||||
pci_write_config32(dev, 0xF8, 0x4);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
/* IOAPICCMISCIND:0x5, group & swizzle of Dev 11,12,13 */
|
||||
dword = (entry[11].group | entry[11].swizzle << 4) << 0 |
|
||||
(entry[12].group | entry[12].swizzle << 4) << 8 |
|
||||
(entry[13].group | entry[13].swizzle << 4) << 16;
|
||||
pci_write_config32(dev, 0xF8, 0x5);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
/* IOAPICCMISCIND:0x6, pin map of dev 2,3,4,5 */
|
||||
dword = entry[2].pin |
|
||||
entry[3].pin << 8 |
|
||||
entry[4].pin << 16|
|
||||
entry[5].pin << 24;
|
||||
pci_write_config32(dev, 0xF8, 0x6);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
/* IOAPICCMISCIND:0x7, pin map of dev 6,7,8,9 */
|
||||
dword = entry[6].pin |
|
||||
entry[7].pin << 8 |
|
||||
entry[8].pin << 16|
|
||||
entry[9].pin << 24;
|
||||
pci_write_config32(dev, 0xF8, 0x7);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
/* IOAPICCMISCIND:0x8, pin map of dev 10,11,12,13 */
|
||||
dword = entry[10].pin |
|
||||
entry[11].pin << 8 |
|
||||
entry[12].pin << 16|
|
||||
entry[13].pin << 24;
|
||||
pci_write_config32(dev, 0xF8, 0x8);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
/* IOAPICCMISCIND:0x9, pin map of ht, iommu */
|
||||
dword = entry[0].pin | entry[1].pin << 8;
|
||||
pci_write_config32(dev, 0xF8, 0x9);
|
||||
pci_write_config32(dev, 0xFC, dword);
|
||||
|
||||
pci_write_config32(dev, 0xF8, 0x1);
|
||||
dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
|
||||
/* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the
|
||||
* 2nd one. We need to check if it also is on your board. */
|
||||
setup_ioapic((void *)dword, 1);
|
||||
}
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
/* Enable pci error detecting */
|
||||
u32 dword;
|
||||
|
||||
printk(BIOS_INFO, "pcie_init in sr5650_ht.c\n");
|
||||
|
||||
/* System error enable */
|
||||
dword = pci_read_config32(dev, 0x04);
|
||||
dword |= (1 << 8); /* System error enable */
|
||||
dword |= (1 << 30); /* Clear possible errors */
|
||||
pci_write_config32(dev, 0x04, dword);
|
||||
|
||||
/*
|
||||
* 1 is APIC enable
|
||||
* 18 is enable nb to accept A4 interrupt request from SB.
|
||||
*/
|
||||
dword = pci_read_config32(dev, 0x4C);
|
||||
dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
|
||||
pci_write_config32(dev, 0x4C, dword);
|
||||
|
||||
sr5690_apic_init(dev);
|
||||
}
|
||||
|
||||
static void sr5690_read_resource(struct device *dev)
|
||||
{
|
||||
if (CONFIG(EXT_CONF_SUPPORT)) {
|
||||
printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev));
|
||||
set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */
|
||||
}
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
/* rpr6.2.(1). Write the Base Address Register (BAR) */
|
||||
pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
|
||||
pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */
|
||||
|
||||
compact_resources(dev);
|
||||
}
|
||||
|
||||
/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
|
||||
static void sr5690_set_resources(struct device *dev)
|
||||
{
|
||||
pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
|
||||
|
||||
if (CONFIG(EXT_CONF_SUPPORT)) {
|
||||
uint32_t reg;
|
||||
struct device *amd_ht_cfg_dev;
|
||||
struct device *amd_addr_map_dev;
|
||||
resource_t res_base;
|
||||
resource_t res_end;
|
||||
uint32_t base;
|
||||
uint32_t limit;
|
||||
struct resource *res;
|
||||
|
||||
printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
|
||||
|
||||
/* Find requisite AMD CPU devices */
|
||||
amd_ht_cfg_dev = pcidev_on_root(0x18, 0);
|
||||
amd_addr_map_dev = pcidev_on_root(0x18, 1);
|
||||
|
||||
if (!amd_ht_cfg_dev || !amd_addr_map_dev) {
|
||||
printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev));
|
||||
} else {
|
||||
res = sr5650_retrieve_cpu_mmio_resource();
|
||||
if (res) {
|
||||
/* Set up MMCONFIG bus range */
|
||||
set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */
|
||||
set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */
|
||||
set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */
|
||||
pci_write_config32(dev, 0x1c, res->base);
|
||||
|
||||
/* Enable MMCONFIG decoding. */
|
||||
set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
|
||||
set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */
|
||||
set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */
|
||||
|
||||
/* Set up nonposted resource in MMIO space */
|
||||
res_base = res->base; /* Get the base address */
|
||||
res_end = resource_end(res); /* Get the limit (rounded up) */
|
||||
printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end);
|
||||
|
||||
/* Locate an unused MMIO resource */
|
||||
for (reg = 0xb8; reg >= 0x80; reg -= 8) {
|
||||
base = pci_read_config32(amd_addr_map_dev, reg);
|
||||
limit = pci_read_config32(amd_addr_map_dev, reg + 4);
|
||||
if (!(base & 0x3))
|
||||
break; /* Unused resource found */
|
||||
}
|
||||
|
||||
/* If an unused MMIO resource was available, set up the mapping */
|
||||
if (!(base & 0x3)) {
|
||||
uint32_t sblk;
|
||||
|
||||
/* Remember this resource has been stored. */
|
||||
res->flags |= IORESOURCE_STORED;
|
||||
report_resource_stored(dev, res, " <mmconfig>");
|
||||
|
||||
/* Get SBLink value (HyperTransport I/O Hub Link ID). */
|
||||
sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3;
|
||||
|
||||
/* Calculate the MMIO mapping base */
|
||||
base &= 0x000000f0;
|
||||
base |= ((res_base >> 8) & 0xffffff00);
|
||||
base |= 3;
|
||||
|
||||
/* Calculate the MMIO mapping limit */
|
||||
limit &= 0x00000048;
|
||||
limit |= ((res_end >> 8) & 0xffffff00);
|
||||
limit |= (sblk << 4);
|
||||
limit |= (1 << 7);
|
||||
|
||||
/* Configure and enable MMIO mapping */
|
||||
printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit);
|
||||
pci_write_config32(amd_addr_map_dev, reg + 4, limit);
|
||||
pci_write_config32(amd_addr_map_dev, reg, base);
|
||||
}
|
||||
else {
|
||||
printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev));
|
||||
}
|
||||
} else {
|
||||
printk(BIOS_WARNING, "%s: %s Unable to locate CPU MMCONF resource\n", __func__, dev_path(dev));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
static struct pci_operations lops_pci = {
|
||||
.set_subsystem = pci_dev_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations ht_ops = {
|
||||
.read_resources = sr5690_read_resource,
|
||||
.set_resources = sr5690_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &lops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5690 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5690_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5670 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5670_HT,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5650 __pci_driver = {
|
||||
.ops = &ht_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5650_HT,
|
||||
};
|
||||
@ -1,940 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <delay.h>
|
||||
#include "sr5650.h"
|
||||
#include "cmn.h"
|
||||
|
||||
/*------------------------------------------------
|
||||
* Global variable
|
||||
------------------------------------------------*/
|
||||
PCIE_CFG AtiPcieCfg = {
|
||||
PCIE_ENABLE_STATIC_DEV_REMAP, /* Config */
|
||||
0, /* ResetReleaseDelay */
|
||||
0, /* Gfx0Width */
|
||||
0, /* Gfx1Width */
|
||||
0, /* GfxPayload */
|
||||
0, /* GppPayload */
|
||||
0, /* PortDetect, filled by GppSbInit */
|
||||
0, /* PortHp */
|
||||
0, /* DbgConfig */
|
||||
0, /* DbgConfig2 */
|
||||
0, /* GfxLx */
|
||||
0, /* GppLx */
|
||||
0, /* NBSBLx */
|
||||
0, /* PortSlotInit */
|
||||
0, /* Gfx0Pwr */
|
||||
0, /* Gfx1Pwr */
|
||||
0 /* GppPwr */
|
||||
};
|
||||
|
||||
static void ValidatePortEn(struct device *nb_dev);
|
||||
|
||||
static void ValidatePortEn(struct device *nb_dev)
|
||||
{
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* Compliant with CIM_33's PCIEPowerOffGppPorts
|
||||
* Power off unused GPP lines
|
||||
*****************************************************************/
|
||||
static void PciePowerOffGppPorts(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
printk(BIOS_DEBUG, "PciePowerOffGppPorts() port %d\n", port);
|
||||
u32 reg;
|
||||
u32 state_save;
|
||||
uint8_t i;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
u32 state = cfg->port_enable;
|
||||
|
||||
if (!(AtiPcieCfg.Config & PCIE_DISABLE_HIDE_UNUSED_PORTS))
|
||||
state &= AtiPcieCfg.PortDetect;
|
||||
state = ~state;
|
||||
state &= (1 << 4) + (1 << 5) + (1 << 6) + (1 << 7);
|
||||
state_save = state << 17;
|
||||
/* Disable ports any that failed training */
|
||||
for (i = 9; i <= 13; i++) {
|
||||
if (!(AtiPcieCfg.PortDetect & 1 << i)) {
|
||||
if ((port >= 9) && (port <= 13)) {
|
||||
state |= (1 << (port + 7));
|
||||
}
|
||||
if (port == 9)
|
||||
state_save |= 1 << 25;
|
||||
if (port == 10)
|
||||
state_save |= 1 << 26;
|
||||
if (port == 11)
|
||||
state_save |= 1 << 6;
|
||||
if (port == 12)
|
||||
state_save |= 1 << 7;
|
||||
|
||||
if (port == 13) {
|
||||
reg = nbmisc_read_index(nb_dev, 0x2a);
|
||||
reg |= 1 << 4;
|
||||
nbmisc_write_index(nb_dev, 0x2a, reg);
|
||||
}
|
||||
}
|
||||
}
|
||||
state &= !(AtiPcieCfg.PortHp);
|
||||
reg = nbmisc_read_index(nb_dev, 0x0c);
|
||||
reg |= state;
|
||||
nbmisc_write_index(nb_dev, 0x0c, reg);
|
||||
|
||||
reg = nbmisc_read_index(nb_dev, 0x08);
|
||||
reg |= state_save;
|
||||
nbmisc_write_index(nb_dev, 0x08, reg);
|
||||
|
||||
if ((AtiPcieCfg.Config & PCIE_OFF_UNUSED_GPP_LANES)
|
||||
&& !(AtiPcieCfg.
|
||||
Config & (PCIE_DISABLE_HIDE_UNUSED_PORTS +
|
||||
PCIE_GFX_COMPLIANCE))) {
|
||||
}
|
||||
/* step 3 Power Down Control for Southbridge */
|
||||
reg = nbpcie_p_read_index(dev, 0xa2);
|
||||
|
||||
switch ((reg >> 4) & 0x7) { /* get bit 4-6, LC_LINK_WIDTH_RD */
|
||||
case 1:
|
||||
nbpcie_ind_write_index(nb_dev, 0x65, 0x0e0e);
|
||||
break;
|
||||
case 2:
|
||||
nbpcie_ind_write_index(nb_dev, 0x65, 0x0c0c);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
**********************************************************************/
|
||||
static void switching_gpp1_configurations(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
/* 4.3.3.1.1.1.step1. Asserts PCIE-GPP1 global reset */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg |= 1 << 15;
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
/* 4.3.3.1.1.1.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP1 core */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg |= 1 << 28;
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
|
||||
/* 4.3.3.1.1.1.step3. Programs PCIE-GPP1 to be desired port configuration 8:8 or 16:0. */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg &= ~(1 << 8); /* clean */
|
||||
reg |= cfg->gpp1_configuration << 8;
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
/* 4.3.3.1.1.1.step4. Wait for 2ms */
|
||||
mdelay(1);
|
||||
|
||||
/* 4.3.3.1.1.1.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP1 core */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg &= ~(1 << 28);
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
|
||||
/* 4.3.3.1.1.1.step6. De-asserts PCIE-GPP1 global reset */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg &= ~(1 << 15);
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
/* Follow the procedure for PCIE-GPP1 common initialization and
|
||||
* link training sequence. */
|
||||
}
|
||||
|
||||
/**********************************************************************
|
||||
**********************************************************************/
|
||||
static void switching_gpp2_configurations(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
/* 4.3.3.1.1.2.step1. Asserts PCIE-GPP2 global reset */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg |= 1 << 13;
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
/* 4.3.3.1.1.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP2 core */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg |= 1 << 29;
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
|
||||
/* 4.3.3.1.1.2.step3. Programs PCIE-GPP2 to be desired port configuration 8:8 or 16:0. */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg &= ~(1 << 9); /* clean */
|
||||
reg |= (cfg->gpp2_configuration & 1) << 9;
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
/* 4.3.3.1.1.2.step4. Wait for 2ms */
|
||||
mdelay(2);
|
||||
|
||||
/* 4.3.3.1.1.2.step5. Asserts STRAP_BIF_all_valid for PCIE-GPP2 core */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg &= ~(1 << 29);
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
|
||||
/* 4.3.3.1.1.2.step6. De-asserts PCIE-GPP2 global reset */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg &= ~(1 << 13);
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
/* Follow the procedure for PCIE-GPP2 common initialization and
|
||||
* link training sequence. */
|
||||
}
|
||||
static void switching_gpp3a_configurations(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
/* 4.3.3.2.3.2.step1. Asserts PCIE-GPP3a global reset. */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg |= 1 << 31;
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
/* 4.3.3.2.3.2.step2. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg |= 1 << 30;
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
/* 4.3.3.2.3.2.step3. Programs the desired PCIE-GPP3a configuration. */
|
||||
reg = nbmisc_read_index(nb_dev, 0x67);
|
||||
reg &= ~0x1F; /* clean */
|
||||
reg |= cfg->gpp3a_configuration;
|
||||
nbmisc_write_index(nb_dev, 0x67, reg);
|
||||
/* 4.3.3.2.3.2.step4. Programs PCIE-GPP3a Line Director. */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg &= 0xF0000000; /* TODO:Lane reversed. */
|
||||
switch (cfg->gpp3a_configuration) {
|
||||
case 0xB: /* 1:1:1:1:1:1 */
|
||||
reg |= 0x2AA3554;
|
||||
break;
|
||||
case 0x1: /* 4:2:0:0:0:0 */
|
||||
reg |= 0x055B000;
|
||||
break;
|
||||
case 0x2: /* 4:1:1:0:0:0 */
|
||||
reg |= 0x215B400;
|
||||
break;
|
||||
case 0xC: /* 2:2:2:0:0:0 */
|
||||
reg |= 0xFF0BAA0;
|
||||
break;
|
||||
case 0xA: /* 2:2:1:1:0:0 */
|
||||
reg |= 0x215B400;
|
||||
break;
|
||||
case 0x4: /* 2:1:1:1:1:0 */
|
||||
reg |= 0xFF0BAA0;
|
||||
break;
|
||||
default: /* shouldn't be here. */
|
||||
printk(BIOS_DEBUG, "Warning:gpp3a_configuration is not correct. Check your devicetree.cb\n");
|
||||
break;
|
||||
}
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
/* 4.3.3.2.3.2.step5. De-asserts STRAP_BIF_all_valid for PCIE-GPP3a core */
|
||||
reg = nbmisc_read_index(nb_dev, 0x26);
|
||||
reg &= ~(1 << 30);
|
||||
nbmisc_write_index(nb_dev, 0x26, reg);
|
||||
/* 4.3.3.2.3.2.step6. De-asserts PCIE-GPP3a global reset. */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg &= ~(1 << 31);
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* The sr5650 uses NBCONFIG:0x1c (BAR3) to map the PCIE Extended Configuration
|
||||
* Space to a 256MB range within the first 4GB of addressable memory.
|
||||
*****************************************************************/
|
||||
void enable_pcie_bar3(struct device *nb_dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "%s\n", __func__);
|
||||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register. */
|
||||
set_nbcfg_enable_bits(nb_dev, 0x84, 7 << 16, 0 << 16);
|
||||
|
||||
pci_write_config32(nb_dev, 0x1C, EXT_CONF_BASE_ADDRESS); /* PCIEMiscInit */
|
||||
pci_write_config32(nb_dev, 0x20, 0x00000000);
|
||||
set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
|
||||
ProgK8TempMmioBase(1, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
|
||||
}
|
||||
|
||||
/*****************************************************************
|
||||
* We should disable bar3 when we want to exit sr5650_enable, because bar3 will be
|
||||
* remapped in set_resource later.
|
||||
*****************************************************************/
|
||||
void disable_pcie_bar3(struct device *nb_dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "%s\n", __func__);
|
||||
pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */
|
||||
set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */
|
||||
ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS);
|
||||
}
|
||||
|
||||
/*
|
||||
* GEN2 Software Compliance
|
||||
*/
|
||||
void init_gen2(struct device *nb_dev, struct device *dev, u8 port)
|
||||
{
|
||||
u32 reg, val;
|
||||
|
||||
/* for A11 (0x89 == 0) */
|
||||
reg = 0x34;
|
||||
if (port <= 3) {
|
||||
val = 1<<5;
|
||||
} else {
|
||||
val = 1<<31;
|
||||
if (port >= 9)
|
||||
reg = 0x39;
|
||||
}
|
||||
|
||||
/* TODO: check for rev > a11 */
|
||||
switch (port) {
|
||||
case 2:
|
||||
reg = 0x34;
|
||||
val = 1<<5;
|
||||
break;
|
||||
case 3:
|
||||
reg = 0x22;
|
||||
val = 1<<6;
|
||||
break;
|
||||
case 4:
|
||||
reg = 0x34;
|
||||
val = 1<<31;
|
||||
break;
|
||||
case 5:
|
||||
case 6:
|
||||
reg = 0x39;
|
||||
val = 1<<31;
|
||||
break;
|
||||
case 7:
|
||||
case 8:
|
||||
case 9:
|
||||
reg = 0x37;
|
||||
val = 1<<port;
|
||||
break;
|
||||
case 10:
|
||||
reg = 0x22;
|
||||
val = 1<<5;
|
||||
break;
|
||||
default:
|
||||
reg = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Enables GEN2 capability of the device */
|
||||
set_pcie_enable_bits(dev, 0xA4, 0x1, 0x1);
|
||||
/* Advertise the link speed to be Gen2 */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1<<2); /* LINK_CRTL2 */
|
||||
set_nbmisc_enable_bits(nb_dev, reg, val, val);
|
||||
}
|
||||
|
||||
|
||||
/* Alternative to default CPL buffer count */
|
||||
const u8 pGpp420000[] = {0x38, 0x1C};
|
||||
const u8 pGpp411000[] = {0x38, 0x0E, 0x0E};
|
||||
const u8 pGpp222000[] = {0x1C, 0x1C, 0x1C};
|
||||
const u8 pGpp221100[] = {0x1C, 0x1C, 0x0E, 0x0E};
|
||||
const u8 pGpp211110[] = {0x1C, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E};
|
||||
const u8 pGpp111111[] = {0x0E, 0x0E, 0x0E, 0x0E, 0, 0x0E, 0x0E};
|
||||
|
||||
/*
|
||||
* Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP3a Ports
|
||||
* PcieLibCplBufferAllocation
|
||||
*/
|
||||
static void gpp3a_cpl_buf_alloc(struct device *nb_dev, struct device *dev)
|
||||
{
|
||||
u8 dev_index;
|
||||
u8 value;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
dev_index = dev->path.pci.devfn >> 3;
|
||||
|
||||
if (dev_index < 4)
|
||||
return;
|
||||
|
||||
dev_index -= 4;
|
||||
|
||||
switch (cfg->gpp3a_configuration) {
|
||||
case 0x1: /* 4:2:0:0:0:0 */
|
||||
if (dev_index >= ARRAY_SIZE(pGpp420000))
|
||||
return;
|
||||
value = pGpp420000[dev_index];
|
||||
break;
|
||||
case 0x2: /* 4:1:1:0:0:0 */
|
||||
if (dev_index >= ARRAY_SIZE(pGpp411000))
|
||||
return;
|
||||
value = pGpp411000[dev_index];
|
||||
break;
|
||||
case 0xC: /* 2:2:2:0:0:0 */
|
||||
if (dev_index >= ARRAY_SIZE(pGpp222000))
|
||||
return;
|
||||
value = pGpp222000[dev_index];
|
||||
break;
|
||||
case 0xA: /* 2:2:1:1:0:0 */
|
||||
if (dev_index >= ARRAY_SIZE(pGpp221100))
|
||||
return;
|
||||
value = pGpp221100[dev_index];
|
||||
break;
|
||||
case 0x4: /* 2:1:1:1:1:0 */
|
||||
if (dev_index >= ARRAY_SIZE(pGpp211110))
|
||||
return;
|
||||
value = pGpp211110[dev_index];
|
||||
break;
|
||||
case 0xB: /* 1:1:1:1:1:1 */
|
||||
if (dev_index >= ARRAY_SIZE(pGpp111111))
|
||||
return;
|
||||
value = pGpp111111[dev_index];
|
||||
break;
|
||||
default: /* shouldn't be here. */
|
||||
printk(BIOS_WARNING, "buggy gpp3a_configuration\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (value != 0) {
|
||||
set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8);
|
||||
set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Enabling Dynamic Slave CPL Buffer Allocation Feature for PCIE-GPP1/PCIE-GPP2 Ports
|
||||
* PcieLibCplBufferAllocation
|
||||
*/
|
||||
static void gpp12_cpl_buf_alloc(struct device *nb_dev, struct device *dev)
|
||||
{
|
||||
u8 gpp_cfg;
|
||||
u8 value;
|
||||
u8 dev_index;
|
||||
|
||||
dev_index = dev->path.pci.devfn >> 3;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
if (dev_index < 4) {
|
||||
gpp_cfg = cfg->gpp1_configuration;
|
||||
} else if (dev_index > 0xa) {
|
||||
gpp_cfg = cfg->gpp2_configuration;
|
||||
} else {
|
||||
return;
|
||||
}
|
||||
|
||||
if (gpp_cfg == 0) {
|
||||
/* Configuration 16:0, leave the default value */
|
||||
} else if (gpp_cfg == 1) {
|
||||
/* Configuration 8:8 */
|
||||
value = 0x60;
|
||||
set_pcie_enable_bits(dev, 0x10, 0x3f << 8, value << 8);
|
||||
set_pcie_enable_bits(dev, 0x20, 1 << 11, 1 << 11);
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "buggy gpp configuration\n");
|
||||
}
|
||||
}
|
||||
|
||||
#if 1 /* BTS report error without this function. But some board
|
||||
* fail to boot. Leave it here for future debug. */
|
||||
|
||||
/*
|
||||
* Enable LCLK clock gating
|
||||
*/
|
||||
static void EnableLclkGating(struct device *dev)
|
||||
{
|
||||
u8 port;
|
||||
u32 reg = 0;
|
||||
u32 mask = 0;
|
||||
u32 value = 0;
|
||||
struct device *nb_dev = pcidev_on_root(0x0, 0);
|
||||
struct device *clk_f1 = pcidev_on_root(0x0, 1);
|
||||
|
||||
reg = 0xE8;
|
||||
port = dev->path.pci.devfn >> 3;
|
||||
switch (port) {
|
||||
//PCIE_CORE_INDEX_GPP1
|
||||
case 2:
|
||||
case 3:
|
||||
reg = 0x94;
|
||||
mask = 1 << 16;
|
||||
break;
|
||||
|
||||
//PCIE_CORE_INDEX_GPP2
|
||||
case 11:
|
||||
case 12:
|
||||
value = 1 << 28;
|
||||
break;
|
||||
|
||||
//PCIE_CORE_INDEX_GPP3a
|
||||
case 4 ... 7:
|
||||
case 9:
|
||||
case 10:
|
||||
value = 1 << 31;
|
||||
break;
|
||||
|
||||
//PCIE_CORE_INDEX_GPP3b;
|
||||
case 13:
|
||||
value = 1 << 25;
|
||||
break;
|
||||
|
||||
//PCIE_CORE_INDEX_SB;
|
||||
case 8:
|
||||
reg = 0x94;
|
||||
mask = 1 << 24;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
/* enable access func1 */
|
||||
set_nbcfg_enable_bits(nb_dev, 0x4C, 1 << 0, 1 << 0);
|
||||
set_nbcfg_enable_bits(clk_f1, reg, mask, value);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's PCIEGPPInit
|
||||
* nb_dev:
|
||||
* root bridge struct
|
||||
* dev:
|
||||
* p2p bridge struct
|
||||
* port:
|
||||
* p2p bridge number, 4-10
|
||||
*****************************************/
|
||||
void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
uint8_t training_ok = 1;
|
||||
|
||||
u32 gpp_sb_sel = 0;
|
||||
struct southbridge_amd_sr5650_config *cfg =
|
||||
(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: nb_dev=0x%p, dev=0x%p, port=0x%x\n", __func__, nb_dev, dev, port);
|
||||
switch (port) {
|
||||
case 2:
|
||||
case 3:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP1;
|
||||
break;
|
||||
case 4 ... 7:
|
||||
case 9:
|
||||
case 10:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP3a;
|
||||
break;
|
||||
case 8:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_SB;
|
||||
break;
|
||||
case 11:
|
||||
case 12:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP2;
|
||||
break;
|
||||
case 13:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP3b;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Init common Core registers */
|
||||
set_pcie_enable_bits(dev, 0xB1, 1 << 28 | 1 << 23 | 1 << 20 | 1 << 19,
|
||||
1 << 28 | 1 << 23 | 1 << 20 | 1 << 19);
|
||||
if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a) {
|
||||
set_pcie_enable_bits(dev, 0xB1, 1 << 22, 1 << 22);
|
||||
/* 4.3.3.2.3 Step 10: Dynamic Slave CPL Buffer Allocation */
|
||||
gpp3a_cpl_buf_alloc(nb_dev, dev);
|
||||
}
|
||||
if (gpp_sb_sel == PCIE_CORE_INDEX_GPP1 || gpp_sb_sel == PCIE_CORE_INDEX_GPP2) {
|
||||
gpp12_cpl_buf_alloc(nb_dev, dev);
|
||||
}
|
||||
set_pcie_enable_bits(dev, 0xA1, (1 << 26) | (1 << 24) | (1 << 11), 1 << 11);
|
||||
set_pcie_enable_bits(dev, 0xA0, 0x0000FFF0, 0x6830);
|
||||
// PCIE should not ignore malformed packet error or ATS request
|
||||
set_pcie_enable_bits(dev, 0x70, 1 << 12, 0);
|
||||
//Step 14.1: Advertising Hot Plug Capabilities
|
||||
set_pcie_enable_bits(dev, 0x10, 1 << 4, 1 << 4); //Enable power fault
|
||||
|
||||
set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 0, 1 << 0);
|
||||
|
||||
/* init GPP core */
|
||||
/* 4.4.2.step13.1. Sets RCB completion timeout to be 200ms */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x80, 0xF << 0, 0x6 << 0);
|
||||
/* 4.4.2.step13.2. RCB completion timeout on link down to shorten enumeration time. */
|
||||
set_pcie_enable_bits(dev, 0x70, 1 << 19, 1 << 19);
|
||||
/* 4.4.2.step13.3. Enable slave ordering rules */
|
||||
set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 8, 0 << 8);
|
||||
/* 4.4.2.step13.4. Sets DMA payload size to 64 bytes. */
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 7 << 10, 4 << 10);
|
||||
/* 4.4.2.step13.5. Set REGS_DLP_IGNORE_IN_L1_EN to ignore DLLPs
|
||||
during L1 so that Tx Clk can be turned off. */
|
||||
set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 0 | 1 << 8, 1 << 0 | 1 << 8); // add bit 8 from CIMx
|
||||
/* 4.4.2.step13.6. Set REGS_LC_ALLOW_TX_L1_CONTROL to allow TX to
|
||||
prevent LC from going to L1 when there are outstanding completions.*/
|
||||
set_pcie_enable_bits(dev, 0x02, 1 << 15, 1 << 15);
|
||||
|
||||
/* Enables the PLL power down when all lanes are inactive.
|
||||
* It should be on in GPP.
|
||||
*/
|
||||
if (gpp_sb_sel == PCIE_CORE_INDEX_GPP3a || gpp_sb_sel == PCIE_CORE_INDEX_GPP3b || gpp_sb_sel == PCIE_CORE_INDEX_SB) {
|
||||
set_pcie_enable_bits(nb_dev, 0x02 | gpp_sb_sel, 1 << 3, 1 << 3);
|
||||
}
|
||||
|
||||
/* 4.4.2.step13.7. Set REGS_LC_DONT_GO_TO_L0S_IF_L1_ARMED to prevent
|
||||
lc to go to from L0 to Rcv_L0s if L1 is armed. */
|
||||
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
|
||||
/* 4.4.2.step13.8. CMGOOD_OVERRIDE for all five PCIe cores. */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x22, 1 << 27, 1 << 27);
|
||||
/* 4.4.2.step13.9. Prevents Electrical Idle from causing a
|
||||
transition from Rcv_L0 to Rcv_L0s. */
|
||||
set_pcie_enable_bits(dev, 0xB1, 1 << 20, 1 << 20);
|
||||
/* 4.4.2.step13.10. Prevents the LTSSM from going to Rcv_L0s if
|
||||
it has already acknowledged a request to go
|
||||
to L1 but it has not transitioned there yet. */
|
||||
/* seems the same as step13.7 */
|
||||
set_pcie_enable_bits(dev, 0xA1, 1 << 11, 1 << 11);
|
||||
/* 4.4.2.step13.11. Transmits FTS before Recovery. */
|
||||
set_pcie_enable_bits(dev, 0xA3, 1 << 9, 1 << 9);
|
||||
/* 4.4.2.step13.12. Sets TX arbitration algorithm to round robin
|
||||
for PCIE-GPP1, PCIE-GPP2, PCIE-GPP3a and PCIE-GPP3b cores only. */
|
||||
//if (gpp_sb_sel != PCIE_CORE_INDEX_SB) /* RPR NOT set SB_CORE, BTS set SB_CORE, we comply with BTS */
|
||||
set_pcie_enable_bits(nb_dev, 0x1C | gpp_sb_sel, 0x7FF, 0x109);
|
||||
/* 4.4.2.step13.13. Sets number of TX Clocks to drain TX Pipe to 0x3.*/
|
||||
set_pcie_enable_bits(dev, 0xA0, 0xF << 4, 0x3 << 4);
|
||||
/* 4.4.2.step13.14. Lets PI use Electrical Idle from PHY when
|
||||
turning off PLL in L1 at Gen 2 speed instead of Inferred Electrical
|
||||
Idle.
|
||||
NOTE: LC still uses Inferred Electrical Idle. */
|
||||
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 3 << 14, 2 << 14);
|
||||
/* 4.4.2.step13.15. Turn on rx_fronten_en for all active lanes upon
|
||||
exit from Electrical Idle, rather than being tied to PLL_PDNB. */
|
||||
set_pcie_enable_bits(nb_dev, 0xC2 | gpp_sb_sel, 1 << 25, 1 << 25);
|
||||
|
||||
/* 4.4.2.step13.16. Advertises TX L0s and L1 exit latency.
|
||||
TX L0s exit latency to be 100b: 512ns to less than 1us;
|
||||
L1 exit latency to be 011b: 4us to less than 8us.
|
||||
For Hot-Plug Slots: Advertise TX L0s and L1 exit latency.
|
||||
TX L0s exit latency to be 110b: 2us to 4us.
|
||||
L1 exit latency to be 111b: more than 64us.*/
|
||||
//set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xC << 0); /* 0xF for hotplug. */
|
||||
set_pcie_enable_bits(dev, 0xC1, 0xF << 0, 0xF << 0); /* 0xF for hotplug. */
|
||||
/* 4.4.2.step13.17. Always ACK an ASPM L1 entry DLLP to
|
||||
workaround credit control issue on PM_NAK
|
||||
message of SB700 and SB800. */
|
||||
/* 4.4.4.step13.18. To allow advertising Gen 2 capabilities to Southbridge. */
|
||||
if (port == 8) {
|
||||
set_pcie_enable_bits(dev, 0xA0, 1 << 23, 1 << 23);
|
||||
set_pcie_enable_bits(nb_dev, 0xC1 | gpp_sb_sel, 1 << 1, 1 << 1);
|
||||
}
|
||||
/* 4.4.2.step13.19. CMOS Option (Gen 2 AUTO-Part 1 - Enabled by Default) */
|
||||
/* 4.4.2.step13.20. CMOS Option (RC Advertised Gen 2-Part1 - Disabled by Default)*/
|
||||
set_nbcfg_enable_bits(dev, 0x88, 0xF << 0, 0x2 << 0);
|
||||
/* Disables GEN2 capability of the device.
|
||||
* RPR typo- it says enable but the bit setting says disable.
|
||||
* Disable it here and we enable it later. */
|
||||
set_pcie_enable_bits(dev, 0xA4, 1 << 0, 1 << 0);
|
||||
|
||||
/* 4.4.2.step13.21. Legacy Hot Plug -CMOS Option */
|
||||
/* NOTE: This feature can be enabled only for Hot-Plug slots implemented on SR5690 platform. */
|
||||
|
||||
/* 4.4.2.step13.22. Native PCIe Mode -CMOS Option */
|
||||
/* Enable native PME. */
|
||||
set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 < 3);
|
||||
/* This bit when set indicates that the PCIe Link associated with this port
|
||||
is connected to a slot. */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x5a, 1 << 8, 1 << 8);
|
||||
/* This bit when set indicates that this slot is capable of supporting
|
||||
Hot-Plug operations. */
|
||||
set_nbcfg_enable_bits(dev, 0x6C, 1 << 6, 1 << 6);
|
||||
/* Enables flushing of TLPs when Data Link is down. */
|
||||
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
|
||||
|
||||
/* 4.4.2.step14. Server Class Hot Plug Feature. NOTE: This feature is not supported on SR5670 and SR5650 */
|
||||
/* 4.4.2 step14.1: Advertising Hot Plug Capabilities */
|
||||
/* 4.4.2.step14.2: Firmware Upload */
|
||||
/* 4.4.2.Step14.3: SBIOS Acknowledgment to Firmware of Successful Firmware Upload */
|
||||
/* step14.4 */
|
||||
/* step14.5 */
|
||||
/* skip */
|
||||
|
||||
/* CIMx LPC Deadlock workaround - Enable Memory Write Map*/
|
||||
if (gpp_sb_sel == PCIE_CORE_INDEX_SB) {
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | gpp_sb_sel, 1 << 9, 1 << 9);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 1 << 26, 1 << 26);
|
||||
}
|
||||
|
||||
/* This CPL setup requires more than this one register and should be done in gpp_core.
|
||||
* The additional setup is for the different revisions. */
|
||||
|
||||
/* CIMx CommonPortInit settings that are not set above. */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x88, 0xF0, 1 << 0); /* LINK_CRTL2 */
|
||||
|
||||
if (port == 8)
|
||||
set_pcie_enable_bits(dev, 0xA0, 0, 1 << 23);
|
||||
|
||||
#if 0 //SR56x0 pcie Gen2 code is not tested yet, we should enable it again when test finished.
|
||||
/* set automatic Gen2 support, needs mainboard config option as Gen2 can cause issues on some platforms. */
|
||||
init_gen2(nb_dev, dev, port);
|
||||
set_pcie_enable_bits(dev, 0xA4, 1 << 29, 1 << 29);
|
||||
set_pcie_enable_bits(dev, 0xC0, 1 << 15, 0);
|
||||
set_pcie_enable_bits(dev, 0xA2, 1 << 13, 0);
|
||||
#endif
|
||||
|
||||
/* Hotplug Support - bit5 + bit6 capable and surprise */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x60, 0x60);
|
||||
|
||||
/* Set interrupt pin info 0x3d */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x3c, 1 << 8, 1 << 8);
|
||||
|
||||
/* 5.12.9.3 Hotplug step 1 - NB_PCIE_ROOT_CTRL - enable pm irq
|
||||
The RPR is wrong - this is not a PCIEND_P register */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x74, 1 << 3, 1 << 3);
|
||||
|
||||
/* 5.12.9.3 step 2 - PCIEP_PORT_CNTL - enable hotplug messages */
|
||||
if (port != 8)
|
||||
set_pcie_enable_bits(dev, 0x10, 1 << 2, 1 << 2);
|
||||
|
||||
/* Not sure about this PME setup */
|
||||
/* Native PME */
|
||||
set_pcie_enable_bits(dev, 0x10, 1 << 3, 1 << 3); /* Not set in CIMx */
|
||||
|
||||
/* PME Enable */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x54, 1 << 8, 1 << 8); /* Not in CIMx */
|
||||
|
||||
/* 4.4.3 Training for GPP devices */
|
||||
/* init GPP */
|
||||
switch (port) {
|
||||
case 2:
|
||||
case 3:
|
||||
case 4: /* GPP_SB */
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
case 9: /*GPP*/
|
||||
case 10:
|
||||
case 11:
|
||||
case 12:
|
||||
case 13:
|
||||
/* 4.4.2.step13.5. Blocks DMA traffic during C3 state */
|
||||
set_pcie_enable_bits(dev, 0x10, 1 << 0, 0 << 0);
|
||||
/* Enables TLP flushing */
|
||||
set_pcie_enable_bits(dev, 0x20, 1 << 19, 0 << 19);
|
||||
|
||||
/* check port enable */
|
||||
if (cfg->port_enable & (1 << port)) {
|
||||
uint32_t hw_port = port;
|
||||
switch (cfg->gpp3a_configuration) {
|
||||
case 0x1: /* 4:2:0:0:0:0 */
|
||||
if (hw_port == 9)
|
||||
hw_port = 4 + 1;
|
||||
break;
|
||||
case 0x2: /* 4:1:1:0:0:0 */
|
||||
if (hw_port == 9)
|
||||
hw_port = 4 + 1;
|
||||
else if (hw_port == 10)
|
||||
hw_port = 4 + 2;
|
||||
break;
|
||||
case 0xc: /* 2:2:2:0:0:0 */
|
||||
if (hw_port == 6)
|
||||
hw_port = 4 + 1;
|
||||
else if (hw_port == 9)
|
||||
hw_port = 4 + 2;
|
||||
break;
|
||||
case 0xa: /* 2:2:1:1:0:0 */
|
||||
if (hw_port == 6)
|
||||
hw_port = 4 + 1;
|
||||
else if (hw_port == 9)
|
||||
hw_port = 4 + 2;
|
||||
else if (hw_port == 10)
|
||||
hw_port = 4 + 3;
|
||||
break;
|
||||
case 0x4: /* 2:1:1:1:1:0 */
|
||||
if (hw_port == 6)
|
||||
hw_port = 4 + 1;
|
||||
else if (hw_port == 7)
|
||||
hw_port = 4 + 2;
|
||||
else if (hw_port == 9)
|
||||
hw_port = 4 + 3;
|
||||
else if (hw_port == 10)
|
||||
hw_port = 4 + 4;
|
||||
break;
|
||||
case 0xb: /* 1:1:1:1:1:1 */
|
||||
break;
|
||||
default: /* shouldn't be here. */
|
||||
printk(BIOS_WARNING, "invalid gpp3a_configuration\n");
|
||||
return;
|
||||
}
|
||||
PcieReleasePortTraining(nb_dev, dev, hw_port);
|
||||
if (!(AtiPcieCfg.Config & PCIE_GPP_COMPLIANCE)) {
|
||||
u8 res = PcieTrainPort(nb_dev, dev, hw_port);
|
||||
printk(BIOS_DEBUG, "%s: port=0x%x hw_port=0x%x result=%d\n",
|
||||
__func__, port, hw_port, res);
|
||||
if (res) {
|
||||
AtiPcieCfg.PortDetect |= 1 << port;
|
||||
} else {
|
||||
/* Even though nothing is attached to this port
|
||||
* the port needs to be "enabled" to obtain
|
||||
* a bus number from the PCI resource allocator
|
||||
*/
|
||||
training_ok = 0;
|
||||
dev->enabled = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 8: /* SB */
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* Re-enable RC ordering logic after training (from CIMx)*/
|
||||
set_pcie_enable_bits(nb_dev, 0x20 | gpp_sb_sel, 1 << 9, 0);
|
||||
|
||||
/* Advertising Hot Plug Capabilities */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x04001B, 0x00001B);
|
||||
|
||||
/* PCIE Late Init (CIMx late init - Maybe move somewhere else? Later in the coreboot PCI device enum?) */
|
||||
/* Set Slot Number */
|
||||
pci_ext_write_config32(nb_dev, dev, 0x6c, 0x1FFF << 19, port << 19);
|
||||
|
||||
/* Set Slot present 0x5A*/
|
||||
pci_ext_write_config32(nb_dev, dev, 0x58, 1 << 24, 1 << 24);
|
||||
|
||||
//PCIE-GPP1 TXCLK Clock Gating In L1 Late Core setting - Maybe move somewhere else? */
|
||||
set_pcie_enable_bits(nb_dev, 0x11 | gpp_sb_sel, 0xF << 0, 0x0C << 0);
|
||||
/* Enable powering down PLLs in L1 or L23 Ready states.
|
||||
* Turns off PHY`s RX FRONTEND during L1 when PLL power down is enabled */
|
||||
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 0x1219, 0x1009);
|
||||
/* 4.4..7.1 TXCLK Gating in L1, Enables powering down TXCLK clock pads on the receive side. */
|
||||
set_pcie_enable_bits(nb_dev, 0x40 | gpp_sb_sel, 1 << 6, 1 << 6);
|
||||
|
||||
/* Step 20: Disables immediate RCB timeout on link down */
|
||||
if (!((pci_read_config32(dev, 0x6C) >> 6) & 0x01)) {
|
||||
set_pcie_enable_bits(dev, 0x70, 1 << 19, 0 << 19);
|
||||
}
|
||||
|
||||
/* Step 27: LCLK Gating */
|
||||
EnableLclkGating(dev);
|
||||
|
||||
/* Set Common Clock */
|
||||
/* If dev present, set PcieCapPtr+0x10, BIT6);
|
||||
* set dev 0x68,bit 6
|
||||
* retrain link, set dev, 0x68 bit 5;
|
||||
* wait dev 0x6B bit3 clear
|
||||
*/
|
||||
|
||||
if ((port == 8) || (!training_ok)) {
|
||||
PciePowerOffGppPorts(nb_dev, dev, port); /* This is run for all ports that are not hotplug and don't detect devices */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Step 21: Register Locking
|
||||
* Lock HWInit Register of each pcie core
|
||||
*/
|
||||
static void lock_hwinitreg(struct device *nb_dev)
|
||||
{
|
||||
/* Step 21: Register Locking, Lock HWInit Register */
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP1, 1 << 0, 1 << 0);
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_SB, 1 << 0, 1 << 0);
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP2, 1 << 0, 1 << 0);
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3a, 1 << 0, 1 << 0);
|
||||
set_pcie_enable_bits(nb_dev, 0x10 | PCIE_CORE_INDEX_GPP3b, 1 << 0, 1 << 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* Lock HWInit Register
|
||||
*/
|
||||
void sr56x0_lock_hwinitreg(void)
|
||||
{
|
||||
struct device *nb_dev = pcidev_on_root(0, 0);
|
||||
|
||||
/* Lock HWInit Register */
|
||||
lock_hwinitreg(nb_dev);
|
||||
|
||||
/* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
|
||||
|
||||
/* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8);
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's PCIEConfigureGPPCore
|
||||
*****************************************/
|
||||
void config_gpp_core(struct device *nb_dev, struct device *sb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = nbmisc_read_index(nb_dev, 0x20);
|
||||
if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
|
||||
reg &= 0xfffffffd; /* set bit1 = 0 */
|
||||
else
|
||||
reg |= 0x2; /* set bit1 = 1 */
|
||||
nbmisc_write_index(nb_dev, 0x20, reg);
|
||||
|
||||
/* Must perform PCIE-GPP1, GPP2, GPP3a global reset anyway */
|
||||
reg = nbmisc_read_index(nb_dev, 0x8);
|
||||
reg |= (1 << 31) | (1 << 15) | (1 << 13); //asserts
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
reg &= ~((1 << 31) | (1 << 15) | (1 << 13)); //De-asserts
|
||||
nbmisc_write_index(nb_dev, 0x8, reg);
|
||||
|
||||
switching_gpp3a_configurations(nb_dev, sb_dev);
|
||||
switching_gpp1_configurations(nb_dev, sb_dev);
|
||||
switching_gpp2_configurations(nb_dev, sb_dev);
|
||||
ValidatePortEn(nb_dev);
|
||||
}
|
||||
|
||||
/*****************************************
|
||||
* Compliant with CIM_33's PCIEMiscClkProg
|
||||
*****************************************/
|
||||
void pcie_config_misc_clk(struct device *nb_dev)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
reg = pci_read_config32(nb_dev, 0x4c);
|
||||
reg |= 1 << 0;
|
||||
pci_write_config32(nb_dev, 0x4c, reg);
|
||||
|
||||
#if 0
|
||||
/* TODO: Check the mics clock later. */
|
||||
pci_devfn_t d0f1 = PCI_DEV(0, 0, 1);
|
||||
|
||||
if (AtiPcieCfg.Config & PCIE_GFX_CLK_GATING) {
|
||||
/* TXCLK Clock Gating */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 0, 3 << 0);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
|
||||
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_GFX, (3 << 6) | (~0xf), 3 << 6);
|
||||
|
||||
/* LCLK Clock Gating */
|
||||
reg = pci_io_read_config32(d0f1, 0x94);
|
||||
reg &= ~(1 << 16);
|
||||
pci_io_write_config32(d0f1, 0x94, reg);
|
||||
}
|
||||
|
||||
if (AtiPcieCfg.Config & PCIE_GPP_CLK_GATING) {
|
||||
/* TXCLK Clock Gating */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x07, 3 << 4, 3 << 4);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x07, 1 << 22, 1 << 22);
|
||||
set_pcie_enable_bits(nb_dev, 0x11 | PCIE_CORE_INDEX_SB, (3 << 6) | (~0xf), 3 << 6);
|
||||
|
||||
/* LCLK Clock Gating */
|
||||
reg = pci_io_read_config32(d0f1, 0x94);
|
||||
reg &= ~(1 << 24);
|
||||
pci_io_write_config32(d0f1, 0x94, reg);
|
||||
}
|
||||
#endif
|
||||
|
||||
reg = pci_read_config32(nb_dev, 0x4c);
|
||||
reg &= ~(1 << 0);
|
||||
pci_write_config32(nb_dev, 0x4c, reg);
|
||||
}
|
||||
@ -1,23 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SR5650_REV_H__
|
||||
#define __SR5650_REV_H__
|
||||
|
||||
#define REV_SR5650_A11 0
|
||||
#define REV_SR5650_A12 1
|
||||
#define REV_SR5650_A21 2
|
||||
|
||||
#endif /* __SR5650_REV_H__ */
|
||||
@ -1,931 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/mmio.h>
|
||||
#include <arch/acpi_ivrs.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <cpu/x86/msr.h>
|
||||
#include <cpu/amd/msr.h>
|
||||
#include <cpu/amd/mtrr.h>
|
||||
#include <stdlib.h>
|
||||
#include <delay.h>
|
||||
#include <option.h>
|
||||
#include "sr5650.h"
|
||||
#include "cmn.h"
|
||||
|
||||
/*
|
||||
* extern function declaration
|
||||
*/
|
||||
struct resource *sr5650_retrieve_cpu_mmio_resource()
|
||||
{
|
||||
struct device *domain;
|
||||
struct resource *res;
|
||||
|
||||
for (domain = all_devices; domain; domain = domain->next) {
|
||||
if (domain->bus->dev->path.type != DEVICE_PATH_DOMAIN)
|
||||
continue;
|
||||
res = probe_resource(domain->bus->dev, MMIO_CONF_BASE);
|
||||
if (res)
|
||||
return res;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* extension registers */
|
||||
u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg)
|
||||
{
|
||||
/*get BAR3 base address for nbcfg0x1c */
|
||||
u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
|
||||
printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
|
||||
dev->path.pci.devfn);
|
||||
addr |= dev->bus->secondary << 20 | /* bus num */
|
||||
dev->path.pci.devfn << 12 | reg;
|
||||
return *((u32 *) addr);
|
||||
}
|
||||
|
||||
void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg_pos, u32 mask, u32 val)
|
||||
{
|
||||
u32 reg_old, reg;
|
||||
|
||||
/*get BAR3 base address for nbcfg0x1c */
|
||||
u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF;
|
||||
/*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary,
|
||||
dev->path.pci.devfn);*/
|
||||
addr |= dev->bus->secondary << 20 | /* bus num */
|
||||
dev->path.pci.devfn << 12 | reg_pos;
|
||||
|
||||
reg = reg_old = *((u32 *) addr);
|
||||
reg &= ~mask;
|
||||
reg |= val;
|
||||
if (reg != reg_old) {
|
||||
*((u32 *) addr) = reg;
|
||||
}
|
||||
}
|
||||
|
||||
u32 nbpcie_p_read_index(struct device *dev, u32 index)
|
||||
{
|
||||
return nb_read_index((dev), NBPCIE_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbpcie_p_write_index(struct device *dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((dev), NBPCIE_INDEX, (index), (data));
|
||||
}
|
||||
|
||||
u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index)
|
||||
{
|
||||
return nb_read_index((nb_dev), NBPCIE_INDEX, (index));
|
||||
}
|
||||
|
||||
void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data)
|
||||
{
|
||||
nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data));
|
||||
}
|
||||
|
||||
uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index)
|
||||
{
|
||||
return nb_read_index((nb_dev), L2CFG_INDEX, (index));
|
||||
}
|
||||
|
||||
void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
|
||||
{
|
||||
nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data));
|
||||
}
|
||||
|
||||
uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index)
|
||||
{
|
||||
return nb_read_index((nb_dev), L1CFG_INDEX, (index));
|
||||
}
|
||||
|
||||
void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index, uint32_t data)
|
||||
{
|
||||
nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data));
|
||||
}
|
||||
|
||||
/***********************************************************
|
||||
* To access bar3 we need to program PCI MMIO 7 in K8.
|
||||
* in_out:
|
||||
* 1: enable/enter k8 temp mmio base
|
||||
* 0: disable/restore
|
||||
***********************************************************/
|
||||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add)
|
||||
{
|
||||
/* K8 Function1 is address map */
|
||||
struct device *k8_f1 = pcidev_on_root(0x18, 1);
|
||||
struct device *k8_f0 = pcidev_on_root(0x18, 0);
|
||||
|
||||
if (in_out) {
|
||||
u32 dword, sblk;
|
||||
|
||||
/* Get SBLink value (HyperTransport I/O Hub Link ID). */
|
||||
dword = pci_read_config32(k8_f0, 0x64);
|
||||
sblk = (dword >> 8) & 0x3;
|
||||
|
||||
/* Fill MMIO limit/base pair. */
|
||||
pci_write_config32(k8_f1, 0xbc,
|
||||
(((pcie_base_add + 0x10000000 -
|
||||
1) >> 8) & 0xffffff00) | 0x80 | (sblk << 4));
|
||||
pci_write_config32(k8_f1, 0xb8, (pcie_base_add >> 8) | 0x3);
|
||||
pci_write_config32(k8_f1, 0xb4,
|
||||
(((mmio_base_add + 0x10000000 -
|
||||
1) >> 8) & 0xffffff00) | (sblk << 4));
|
||||
pci_write_config32(k8_f1, 0xb0, (mmio_base_add >> 8) | 0x3);
|
||||
} else {
|
||||
pci_write_config32(k8_f1, 0xb8, 0);
|
||||
pci_write_config32(k8_f1, 0xbc, 0);
|
||||
pci_write_config32(k8_f1, 0xb0, 0);
|
||||
pci_write_config32(k8_f1, 0xb4, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void PcieReleasePortTraining(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
switch (port) {
|
||||
case 2: /* GPP1, bit4-5 */
|
||||
case 3:
|
||||
set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
|
||||
1 << (port + 2), 0 << (port + 2));
|
||||
break;
|
||||
case 4: /* GPP3a, bit20-24 */
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
|
||||
1 << (port + 17), 0 << (port + 17));
|
||||
break;
|
||||
case 9: /* GPP3a, bit25,26 */
|
||||
case 10:
|
||||
set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
|
||||
1 << (port + 16), 0 << (port + 16));
|
||||
break;
|
||||
case 11: /* GPP2, bit6-7 */
|
||||
case 12:
|
||||
set_nbmisc_enable_bits(nb_dev, PCIE_LINK_CFG,
|
||||
1 << (port - 5), 0 << (port - 5));
|
||||
break;
|
||||
case 13: /* GPP3b, bit4 of NBMISCIND:0x2A */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x2A,
|
||||
1 << 4, 0 << 4);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/********************************************************************************************************
|
||||
* Output:
|
||||
* 0: no device is present.
|
||||
* 1: device is present and is trained.
|
||||
********************************************************************************************************/
|
||||
u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port)
|
||||
{
|
||||
u16 count = 5000;
|
||||
u32 lc_state, reg, current_link_width, lane_mask;
|
||||
u8 current, res = 0;
|
||||
u32 gpp_sb_sel = 0;
|
||||
|
||||
switch (port) {
|
||||
case 2:
|
||||
case 3:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP1;
|
||||
break;
|
||||
case 4 ... 7:
|
||||
case 9:
|
||||
case 10:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP3a;
|
||||
break;
|
||||
case 11:
|
||||
case 12:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP2;
|
||||
break;
|
||||
case 13:
|
||||
gpp_sb_sel = PCIE_CORE_INDEX_GPP3b;
|
||||
break;
|
||||
}
|
||||
|
||||
while (count--) {
|
||||
udelay(40200);
|
||||
lc_state = nbpcie_p_read_index(dev, 0xa5); /* lc_state */
|
||||
printk(BIOS_DEBUG, "PcieLinkTraining port=%x:lc current state=%x\n",
|
||||
port, lc_state);
|
||||
current = lc_state & 0x3f; /* get LC_CURRENT_STATE, bit0-5 */
|
||||
|
||||
switch (current) {
|
||||
/* 0x00-0x04 means no device is present */
|
||||
case 0x06:
|
||||
/* read back current link width [6:4]. */
|
||||
current_link_width = (nbpcie_p_read_index(dev, 0xA2) >> 4) & 0x7;
|
||||
/* 4 means 7:4 and 15:12
|
||||
* 3 means 7:2 and 15:10
|
||||
* 2 means 7:1 and 15:9
|
||||
* ignoring the reversal case
|
||||
*/
|
||||
lane_mask = (0xFF << (current_link_width - 2) * 2) & 0xFF;
|
||||
reg = nbpcie_ind_read_index(nb_dev, 0x65 | gpp_sb_sel);
|
||||
reg |= lane_mask << 8 | lane_mask;
|
||||
/* NOTE: See the comments in rs780_pcie.c
|
||||
* switching_gppsb_configurations
|
||||
* In CIMx 4.5.0 and RPR, 4c is done before 5 & 6.
|
||||
* But in this way, a x4 device in port B (dev 4) of
|
||||
* Configuration B can only be detected as x1, instead
|
||||
* of x4. When the port B is being trained, the
|
||||
* LC_CURRENT_STATE is 6 and the LC_LINK_WIDTH_RD is 1.
|
||||
* We have to set the PCIEIND:0x65 as 0xE0E0 and reset
|
||||
* the slot. Then the card seems to work in x1 mode.
|
||||
*/
|
||||
reg = 0xE0E0; /*I think that the lane_mask calc above is wrong, and this can't be hardcoded because the configuration changes.*/
|
||||
nbpcie_ind_write_index(nb_dev, 0x65 | gpp_sb_sel, reg);
|
||||
printk(BIOS_DEBUG, "link_width=%x, lane_mask=%x",
|
||||
current_link_width, lane_mask);
|
||||
set_pcie_reset();
|
||||
mdelay(1);
|
||||
set_pcie_dereset();
|
||||
break;
|
||||
case 0x07: /* device is in compliance state (training sequence is done). Move to train the next device */
|
||||
res = 1;
|
||||
count = 0;
|
||||
break;
|
||||
case 0x10:
|
||||
reg =
|
||||
pci_ext_read_config32(nb_dev, dev,
|
||||
PCIE_VC0_RESOURCE_STATUS);
|
||||
printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg);
|
||||
/* check bit1 */
|
||||
if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
|
||||
/* set bit8=1, bit0-2=bit4-6 */
|
||||
u32 tmp;
|
||||
reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
|
||||
tmp = (reg >> 4) & 0x7; /* get bit4-6 */
|
||||
reg &= 0xfff8; /* clear bit0-2 */
|
||||
reg += tmp; /* merge */
|
||||
reg |= 1 << 8;
|
||||
nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
|
||||
count++; /* CIM said "keep in loop"? */
|
||||
} else {
|
||||
res = 1;
|
||||
count = 0;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
/* CIMx Unknown Workaround - There is a device that won't train. Try to reset it. */
|
||||
/* if there are no device resets and nothing works, CIMx does a cf9 system reset (yikes!) */
|
||||
set_pcie_reset();
|
||||
mdelay(1);
|
||||
set_pcie_dereset();
|
||||
res = 0;
|
||||
count = 0; /* break loop */
|
||||
break;
|
||||
}
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
/*
|
||||
* Set Top Of Memory below and above 4G.
|
||||
*/
|
||||
void sr5650_set_tom(struct device *nb_dev)
|
||||
{
|
||||
msr_t sysmem;
|
||||
|
||||
/* The system top memory in SR56X0. */
|
||||
sysmem = rdmsr(TOP_MEM);
|
||||
printk(BIOS_DEBUG, "Sysmem TOM = %x_%x\n", sysmem.hi, sysmem.lo);
|
||||
pci_write_config32(nb_dev, 0x90, sysmem.lo);
|
||||
|
||||
sysmem = rdmsr(TOP_MEM2);
|
||||
printk(BIOS_DEBUG, "Sysmem TOM2 = %x_%x\n", sysmem.hi, sysmem.lo);
|
||||
htiu_write_index(nb_dev, 0x31, sysmem.hi);
|
||||
htiu_write_index(nb_dev, 0x30, sysmem.lo | 1);
|
||||
}
|
||||
|
||||
u32 get_vid_did(struct device *dev)
|
||||
{
|
||||
return pci_read_config32(dev, 0);
|
||||
}
|
||||
|
||||
void detect_and_enable_iommu(struct device *iommu_dev) {
|
||||
uint32_t dword;
|
||||
uint8_t l1_target;
|
||||
unsigned char iommu;
|
||||
void *mmio_base;
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
if (iommu) {
|
||||
printk(BIOS_DEBUG, "Initializing IOMMU\n");
|
||||
|
||||
struct device *nb_dev = pcidev_on_root(0, 0);
|
||||
|
||||
if (!nb_dev) {
|
||||
printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n");
|
||||
return;
|
||||
}
|
||||
|
||||
mmio_base = (void *)(pci_read_config32(iommu_dev, 0x44) &
|
||||
0xffffc000);
|
||||
|
||||
// if (get_nb_rev(nb_dev) == REV_SR5650_A11) {
|
||||
// dword = pci_read_config32(iommu_dev, 0x6c);
|
||||
// dword &= ~(0x1 << 8);
|
||||
// pci_write_config32(iommu_dev, 0x6c, dword);
|
||||
// }
|
||||
|
||||
dword = pci_read_config32(iommu_dev, 0x50);
|
||||
dword &= ~(0x1 << 22);
|
||||
pci_write_config32(iommu_dev, 0x50, dword);
|
||||
|
||||
dword = pci_read_config32(iommu_dev, 0x44);
|
||||
dword |= 0x1;
|
||||
pci_write_config32(iommu_dev, 0x44, dword);
|
||||
|
||||
write32((void *)(mmio_base + 0x8), 0x0);
|
||||
write32((void *)(mmio_base + 0xc), 0x08000000);
|
||||
write32((void *)(mmio_base + 0x10), 0x0);
|
||||
write32((void *)(mmio_base + 0x2008), 0x0);
|
||||
write32((void *)(mmio_base + 0x2010), 0x0);
|
||||
|
||||
/* IOMMU L1 initialization */
|
||||
for (l1_target = 0; l1_target < 6; l1_target++) {
|
||||
dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0xc);
|
||||
dword |= (0x7 << 28);
|
||||
l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0xc, dword);
|
||||
|
||||
dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0x7);
|
||||
dword |= (0x1 << 5);
|
||||
l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0x7, dword);
|
||||
}
|
||||
|
||||
/* IOMMU L2 initialization */
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0xc);
|
||||
dword |= (0x7 << 29);
|
||||
l2cfg_ind_write_index(nb_dev, 0xc, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x10);
|
||||
dword &= ~(0x3 << 8);
|
||||
dword |= (0x2 << 8);
|
||||
l2cfg_ind_write_index(nb_dev, 0x10, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x14);
|
||||
dword &= ~(0x3 << 8);
|
||||
dword |= (0x2 << 8);
|
||||
l2cfg_ind_write_index(nb_dev, 0x14, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x18);
|
||||
dword &= ~(0x3 << 8);
|
||||
dword |= (0x2 << 8);
|
||||
l2cfg_ind_write_index(nb_dev, 0x18, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x1c);
|
||||
dword &= ~(0x3 << 8);
|
||||
dword |= (0x2 << 8);
|
||||
l2cfg_ind_write_index(nb_dev, 0x1c, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x50);
|
||||
dword &= ~(0x3 << 8);
|
||||
dword |= (0x2 << 8);
|
||||
l2cfg_ind_write_index(nb_dev, 0x50, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x10);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x10, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x14);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x14, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x18);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x18, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x1c);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x1c, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x50);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x50, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x6);
|
||||
dword |= (0x1 << 7);
|
||||
l2cfg_ind_write_index(nb_dev, 0x6, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x44);
|
||||
dword |= (0x1 << 0);
|
||||
l2cfg_ind_write_index(nb_dev, 0x44, dword);
|
||||
|
||||
// if (get_nb_rev(nb_dev) == REV_SR5650_A21) {
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 1);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x44);
|
||||
dword |= (0x1 << 1);
|
||||
l2cfg_ind_write_index(nb_dev, 0x44, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 2);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 3);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x44);
|
||||
dword |= (0x1 << 3);
|
||||
l2cfg_ind_write_index(nb_dev, 0x44, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x6);
|
||||
dword |= (0x1 << 5);
|
||||
l2cfg_ind_write_index(nb_dev, 0x6, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x6);
|
||||
dword |= (0x1 << 6);
|
||||
l2cfg_ind_write_index(nb_dev, 0x6, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 5);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x44);
|
||||
dword |= (0x1 << 4);
|
||||
l2cfg_ind_write_index(nb_dev, 0x44, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 6);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x7);
|
||||
dword |= (0x1 << 7);
|
||||
l2cfg_ind_write_index(nb_dev, 0x7, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x6);
|
||||
dword |= (0x1 << 8);
|
||||
l2cfg_ind_write_index(nb_dev, 0x6, dword);
|
||||
// }
|
||||
|
||||
l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x80);
|
||||
dword |= (0x1 << 0);
|
||||
l2cfg_ind_write_index(nb_dev, 0x80, dword);
|
||||
|
||||
dword = l2cfg_ind_read_index(nb_dev, 0x30);
|
||||
dword |= (0x1 << 0);
|
||||
l2cfg_ind_write_index(nb_dev, 0x30, dword);
|
||||
}
|
||||
}
|
||||
|
||||
void sr5650_iommu_read_resources(struct device *dev)
|
||||
{
|
||||
unsigned char iommu;
|
||||
struct resource *res;
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
/* Get the normal pci resources of this device */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
if (iommu) {
|
||||
/* Request MMIO range allocation */
|
||||
res = new_resource(dev, 0x44); /* IOMMU */
|
||||
res->base = 0x0;
|
||||
res->size = 0x4000;
|
||||
res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */
|
||||
res->align = 14; /* 16k alignment */
|
||||
res->gran = 14;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE;
|
||||
}
|
||||
|
||||
compact_resources(dev);
|
||||
}
|
||||
|
||||
void sr5650_iommu_set_resources(struct device *dev)
|
||||
{
|
||||
unsigned char iommu;
|
||||
struct resource *res;
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
/* Get the normal pci resources of this device */
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
if (iommu) {
|
||||
/* Get the allocated range */
|
||||
res = find_resource(dev, 0x44);
|
||||
|
||||
if (res->base == 0) {
|
||||
printk(BIOS_WARNING, "Unable to allocate MMIO range to IOMMU\n");
|
||||
}
|
||||
|
||||
/* Assign the range to hardware */
|
||||
pci_write_config32(dev, 0x44, res->base & 0xffffc000);
|
||||
pci_write_config32(dev, 0x48, 0x0);
|
||||
}
|
||||
|
||||
/* Run standard resource set routine */
|
||||
pci_dev_set_resources(dev);
|
||||
}
|
||||
|
||||
void sr5650_iommu_enable_resources(struct device *dev)
|
||||
{
|
||||
detect_and_enable_iommu(dev);
|
||||
}
|
||||
|
||||
void sr5650_nb_pci_table(struct device *nb_dev)
|
||||
{ /* NBPOR_InitPOR function. */
|
||||
u8 temp8;
|
||||
u16 temp16;
|
||||
u32 temp32;
|
||||
|
||||
/* Program NB PCI table. */
|
||||
temp16 = pci_read_config16(nb_dev, 0x04);
|
||||
printk(BIOS_DEBUG, "NB_PCI_REG04 = %x.\n", temp16);
|
||||
temp32 = pci_read_config32(nb_dev, 0x84);
|
||||
printk(BIOS_DEBUG, "NB_PCI_REG84 = %x.\n", temp32);
|
||||
//Reg4Ch[1]=1 (APIC_ENABLE) force CPU request with address 0xFECx_xxxx to south-bridge
|
||||
//Reg4Ch[6]=1 (BMMsgEn) enable BM_Set message generation
|
||||
pci_write_config8(nb_dev, 0x4c, 0x42);
|
||||
temp8 = pci_read_config8(nb_dev, 0x4e);
|
||||
temp8 |= 0x05; /* BAR1_ENABLE */
|
||||
pci_write_config8(nb_dev, 0x4e, temp8);
|
||||
|
||||
temp32 = pci_read_config32(nb_dev, 0x4c);
|
||||
printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32);
|
||||
|
||||
/* disable GFX debug. */
|
||||
temp8 = pci_read_config8(nb_dev, 0x8d);
|
||||
temp8 &= ~(1<<1);
|
||||
pci_write_config8(nb_dev, 0x8d, temp8);
|
||||
|
||||
/* The system top memory in SR56X0. */
|
||||
sr5650_set_tom(nb_dev);
|
||||
|
||||
/* Program NB HTIU table. */
|
||||
//set_htiu_enable_bits(nb_dev, 0x05, 1<<10 | 1<<9, 1<<10|1<<9);
|
||||
set_htiu_enable_bits(nb_dev, 0x06, 1, 0x4203a202);
|
||||
//set_htiu_enable_bits(nb_dev, 0x07, 1<<1 | 1<<2, 0x8001);
|
||||
set_htiu_enable_bits(nb_dev, 0x15, 0, 1<<31 | 1<<30 | 1<<27);
|
||||
set_htiu_enable_bits(nb_dev, 0x1c, 0, 0xfffe0000);
|
||||
set_htiu_enable_bits(nb_dev, 0x0c, 0x3f, 1 | 1<<3);
|
||||
set_htiu_enable_bits(nb_dev, 0x19, 0xfffff+(1<<31), 0x186a0+(1<<31));
|
||||
set_htiu_enable_bits(nb_dev, 0x16, 0x3f<<10, 0x7<<10);
|
||||
set_htiu_enable_bits(nb_dev, 0x23, 0, 1<<28);
|
||||
}
|
||||
|
||||
/***********************************************
|
||||
* 0:00.0 NBCFG :
|
||||
* 0:00.1 CLK : bit 0 of nb_cfg 0x4c : 0 - disable, default
|
||||
* 0:01.0 P2P Internal:
|
||||
* 0:02.0 P2P : bit 2 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
|
||||
* 0:03.0 P2P : bit 3 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
|
||||
* 0:04.0 P2P : bit 4 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
|
||||
* 0:05.0 P2P : bit 5 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
|
||||
* 0:06.0 P2P : bit 6 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
|
||||
* 0:07.0 P2P : bit 7 of nbmiscind 0x0c : 0 - enable, default + 32 * 2
|
||||
* 0:08.0 NB2SB : bit 6 of nbmiscind 0x00 : 0 - disable, default + 32 * 1
|
||||
* case 0 will be called twice, one is by CPU in hypertransport.c line458,
|
||||
* the other is by sr5650.
|
||||
***********************************************/
|
||||
void sr5650_enable(struct device *dev)
|
||||
{
|
||||
struct device *nb_dev = NULL, *sb_dev = NULL;
|
||||
int dev_ind;
|
||||
struct southbridge_amd_sr5650_config *cfg;
|
||||
|
||||
printk(BIOS_INFO, "sr5650_enable: dev=%p, VID_DID=0x%x\n", dev, get_vid_did(dev));
|
||||
nb_dev = pcidev_on_root(0, 0);
|
||||
if (!nb_dev) {
|
||||
die("sr5650_enable: CAN NOT FIND SR5650 DEVICE, HALT!\n");
|
||||
/* NOT REACHED */
|
||||
}
|
||||
cfg = (struct southbridge_amd_sr5650_config *)nb_dev->chip_info;
|
||||
|
||||
/* sb_dev (dev 8) is a bridge that links to southbridge. */
|
||||
sb_dev = pcidev_on_root(8, 0);
|
||||
if (!sb_dev) {
|
||||
die("sr5650_enable: CAN NOT FIND SB bridge, HALT!\n");
|
||||
/* NOT REACHED */
|
||||
}
|
||||
|
||||
dev_ind = dev->path.pci.devfn >> 3;
|
||||
switch (dev_ind) {
|
||||
case 0: /* bus0, dev0, fun0; */
|
||||
switch (dev->path.pci.devfn & 0x7) {
|
||||
case 0:
|
||||
printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n");
|
||||
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
|
||||
|
||||
config_gpp_core(nb_dev, sb_dev);
|
||||
sr5650_gpp_sb_init(nb_dev, sb_dev, 8);
|
||||
|
||||
sr5650_nb_pci_table(nb_dev);
|
||||
break;
|
||||
case 1:
|
||||
printk(BIOS_INFO, "Bus-0, Dev-0, Fun-1.\n");
|
||||
break;
|
||||
case 2:
|
||||
printk(BIOS_INFO, "Bus-0, Dev-0, Fun-2.\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case 2: /* bus0, dev2,3 GPP1 */
|
||||
case 3:
|
||||
printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
|
||||
(dev->enabled ? 0 : 1) << dev_ind);
|
||||
if (dev->enabled)
|
||||
sr5650_gpp_sb_init(nb_dev, dev, dev_ind); /* Note, dev 2,3 are generic PCIe ports. */
|
||||
break;
|
||||
case 4: /* bus0, dev4-7, four GPP3a */
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
|
||||
printk(BIOS_INFO, "Bus-0, Dev-4,5,6,7, Fun-0. enable=%d\n",
|
||||
dev->enabled);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
|
||||
(dev->enabled ? 0 : 1) << dev_ind);
|
||||
if (dev->enabled)
|
||||
sr5650_gpp_sb_init(nb_dev, dev, dev_ind);
|
||||
break;
|
||||
case 8: /* bus0, dev8, SB */
|
||||
printk(BIOS_INFO, "Bus-0, Dev-8, Fun-0. enable=%d\n", dev->enabled);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 6,
|
||||
(dev->enabled ? 1 : 0) << 6);
|
||||
if (dev->enabled)
|
||||
sr5650_gpp_sb_init(nb_dev, dev, dev_ind);
|
||||
disable_pcie_bar3(nb_dev);
|
||||
break;
|
||||
case 9: /* bus 0, dev 9,10, GPP3a */
|
||||
case 10:
|
||||
printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n",
|
||||
dev->enabled);
|
||||
enable_pcie_bar3(nb_dev); /* PCIEMiscInit */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
|
||||
(dev->enabled ? 0 : 1) << (7 + dev_ind));
|
||||
if (dev->enabled)
|
||||
sr5650_gpp_sb_init(nb_dev, dev, dev_ind);
|
||||
/* Don't call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */
|
||||
break;
|
||||
case 11:
|
||||
case 12: /* bus 0, dev 11,12, GPP2 */
|
||||
printk(BIOS_INFO, "Bus-0, Dev-11,12, Fun-0. enable=%d\n", dev->enabled);
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
|
||||
(dev->enabled ? 0 : 1) << (7 + dev_ind));
|
||||
if (dev->enabled)
|
||||
sr5650_gpp_sb_init(nb_dev, dev, dev_ind);
|
||||
break;
|
||||
case 13: /* bus 0, dev 12, GPP3b */
|
||||
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind),
|
||||
(dev->enabled ? 0 : 1) << (7 + dev_ind));
|
||||
if (dev->enabled)
|
||||
sr5650_gpp_sb_init(nb_dev, dev, dev_ind);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
|
||||
}
|
||||
|
||||
/* Lock HWInit Register after the last device was done */
|
||||
if (dev_ind == 13) {
|
||||
sr56x0_lock_hwinitreg();
|
||||
udelay(cfg->pcie_settling_time);
|
||||
}
|
||||
}
|
||||
|
||||
static void add_ivrs_device_entries(struct device *parent, struct device *dev,
|
||||
int depth, int linknum, int8_t *root_level,
|
||||
unsigned long *current, uint16_t *length)
|
||||
{
|
||||
uint8_t *p = (uint8_t *) *current;
|
||||
|
||||
struct device *sibling;
|
||||
struct bus *link;
|
||||
|
||||
if ((dev->path.type == DEVICE_PATH_PCI) &&
|
||||
(dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0))
|
||||
*root_level = depth;
|
||||
|
||||
if ((dev->path.type == DEVICE_PATH_PCI) && (*root_level != -1) &&
|
||||
(depth >= *root_level) && (dev->enabled)) {
|
||||
|
||||
*p = 0;
|
||||
if (depth == *root_level) {
|
||||
if (dev->path.pci.devfn < (0x1 << 3)) {
|
||||
/* SR5690 control device */
|
||||
} else if ((dev->path.pci.devfn >= (0x1 << 3)) &&
|
||||
(dev->path.pci.devfn < (0xe << 3))) {
|
||||
/* SR5690 PCIe bridge device */
|
||||
} else if (dev->path.pci.devfn == (0x14 << 3)) {
|
||||
/* SMBUS controller */
|
||||
p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */
|
||||
p[1] = dev->path.pci.devfn; /* Device */
|
||||
p[2] = dev->bus->secondary; /* Bus */
|
||||
p[3] = IVHD_DTE_LINT_1_PASS | /* Data */
|
||||
IVHD_DTE_SYS_MGT_NO_TRANS |
|
||||
IVHD_DTE_NMI_PASS |
|
||||
IVHD_DTE_EXT_INT_PASS |
|
||||
IVHD_DTE_INIT_PASS;
|
||||
} else {
|
||||
/* Other southbridge device */
|
||||
p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */
|
||||
p[1] = dev->path.pci.devfn; /* Device */
|
||||
p[2] = dev->bus->secondary; /* Bus */
|
||||
p[3] = 0x0; /* Data */
|
||||
}
|
||||
} else if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
|
||||
/* Device behind bridge */
|
||||
if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) {
|
||||
/* Device is PCIe */
|
||||
p[0] = IVHD_DEV_4_BYTE_SELECT; /* Entry type */
|
||||
p[1] = dev->path.pci.devfn; /* Device */
|
||||
p[2] = dev->bus->secondary; /* Bus */
|
||||
p[3] = 0x0; /* Data */
|
||||
} else {
|
||||
/* Device is legacy PCI or PCI-X */
|
||||
p[0] = IVHD_DEV_8_BYTE_ALIAS_SELECT; /* Entry */
|
||||
p[1] = dev->path.pci.devfn; /* Device */
|
||||
p[2] = dev->bus->secondary; /* Bus */
|
||||
p[3] = 0x0; /* Data */
|
||||
p[4] = 0x0; /* Reserved */
|
||||
p[5] = parent->path.pci.devfn; /* Device */
|
||||
p[6] = parent->bus->secondary; /* Bus */
|
||||
p[7] = 0x0; /* Reserved */
|
||||
}
|
||||
}
|
||||
|
||||
if (*p == IVHD_DEV_4_BYTE_SELECT) {
|
||||
*length += 4;
|
||||
*current += 4;
|
||||
} else if (*p == IVHD_DEV_8_BYTE_ALIAS_SELECT) {
|
||||
*length += 8;
|
||||
*current += 8;
|
||||
}
|
||||
}
|
||||
|
||||
for (link = dev->link_list; link; link = link->next)
|
||||
for (sibling = link->children; sibling;
|
||||
sibling = sibling->sibling)
|
||||
add_ivrs_device_entries(dev, sibling, depth + 1,
|
||||
depth, root_level, current, length);
|
||||
}
|
||||
|
||||
unsigned long acpi_fill_mcfg(unsigned long current)
|
||||
{
|
||||
struct resource *res;
|
||||
resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
|
||||
|
||||
if (CONFIG(EXT_CONF_SUPPORT)) {
|
||||
res = sr5650_retrieve_cpu_mmio_resource();
|
||||
if (res)
|
||||
mmconf_base = res->base;
|
||||
|
||||
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f);
|
||||
}
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
|
||||
{
|
||||
uint8_t *p;
|
||||
|
||||
struct device *nb_dev = pcidev_on_root(0, 0);
|
||||
if (!nb_dev) {
|
||||
printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
|
||||
"device! IVRS table not generated...\n");
|
||||
return (unsigned long)ivrs;
|
||||
}
|
||||
|
||||
struct device *iommu_dev = pcidev_on_root(0, 2);
|
||||
if (!iommu_dev) {
|
||||
printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
|
||||
"IOMMU device! IVRS table not generated...\n");
|
||||
return (unsigned long)ivrs;
|
||||
}
|
||||
|
||||
ivrs->iv_info = IVINFO_VA_SIZE_64_BITS | IVINFO_PA_SIZE_52_BITS;
|
||||
|
||||
ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED;
|
||||
ivrs->ivhd.flags = IVHD_FLAG_ISOC |
|
||||
IVHD_FLAG_RES_PASS_PW |
|
||||
IVHD_FLAG_PASS_PW |
|
||||
IVHD_FLAG_IOTLB_SUP;
|
||||
|
||||
ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd);
|
||||
|
||||
/* BDF <bus>:00.2 */
|
||||
ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8);
|
||||
|
||||
/* Capability block 0x40 (type 0xf, "Secure device") */
|
||||
ivrs->ivhd.capability_offset = 0x40;
|
||||
ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) &
|
||||
0xffffc000;
|
||||
ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48);
|
||||
ivrs->ivhd.pci_segment_group = 0x0;
|
||||
ivrs->ivhd.iommu_info = 0x0;
|
||||
ivrs->ivhd.iommu_info |= (0x14 << IOMMU_INFO_UNIT_ID_SHIFT);
|
||||
ivrs->ivhd.iommu_feature_info = 0x0;
|
||||
|
||||
/* Describe HPET */
|
||||
p = (uint8_t *)current;
|
||||
p[0] = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; /* Entry type */
|
||||
p[1] = 0; /* Device */
|
||||
p[2] = 0; /* Bus */
|
||||
p[3] = IVHD_DTE_LINT_1_PASS | /* DTE */
|
||||
IVHD_DTE_LINT_0_PASS |
|
||||
IVHD_DTE_SYS_MGT_INTX_NO_TRANS |
|
||||
IVHD_DTE_NMI_PASS |
|
||||
IVHD_DTE_EXT_INT_PASS |
|
||||
IVHD_DTE_INIT_PASS;
|
||||
p[4] = 0x0; /* HPET number */
|
||||
p[5] = 0x14 << 3; /* HPET device */
|
||||
p[6] = nb_dev->bus->secondary; /* HPET bus */
|
||||
p[7] = IVHD_SPECIAL_DEV_HPET; /* Variety */
|
||||
ivrs->ivhd.length += 8;
|
||||
current += 8;
|
||||
|
||||
/* Describe PCI devices */
|
||||
int8_t root_level = -1;
|
||||
add_ivrs_device_entries(NULL, all_devices, 0, -1, &root_level, ¤t,
|
||||
&ivrs->ivhd.length);
|
||||
|
||||
/* Describe IOAPICs */
|
||||
unsigned long prev_current = current;
|
||||
current = acpi_fill_ivrs_ioapic(ivrs, current);
|
||||
ivrs->ivhd.length += (current - prev_current);
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
unsigned long southbridge_write_acpi_tables(struct device *device,
|
||||
unsigned long current,
|
||||
struct acpi_rsdp *rsdp)
|
||||
{
|
||||
unsigned char iommu;
|
||||
|
||||
iommu = 1;
|
||||
get_option(&iommu, "iommu");
|
||||
|
||||
if (iommu) {
|
||||
acpi_ivrs_t *ivrs;
|
||||
|
||||
/* IVRS */
|
||||
current = ALIGN(current, 8);
|
||||
printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
|
||||
ivrs = (acpi_ivrs_t *) current;
|
||||
acpi_create_ivrs(ivrs, acpi_fill_ivrs);
|
||||
current += ivrs->header.length;
|
||||
acpi_add_table(rsdp, ivrs);
|
||||
}
|
||||
|
||||
return current;
|
||||
}
|
||||
|
||||
static struct pci_operations iommu_ops_pci = {
|
||||
.set_subsystem = pci_dev_set_subsystem,
|
||||
};
|
||||
|
||||
static struct device_operations iommu_ops = {
|
||||
.read_resources = sr5650_iommu_read_resources,
|
||||
.set_resources = sr5650_iommu_set_resources,
|
||||
.enable_resources = sr5650_iommu_enable_resources,
|
||||
.write_acpi_tables = southbridge_write_acpi_tables,
|
||||
.init = 0,
|
||||
.scan_bus = 0,
|
||||
.ops_pci = &iommu_ops_pci,
|
||||
};
|
||||
|
||||
static const struct pci_driver ht_driver_sr5690 __pci_driver = {
|
||||
.ops = &iommu_ops,
|
||||
.vendor = PCI_VENDOR_ID_ATI,
|
||||
.device = PCI_DEVICE_ID_AMD_SR5650_IOMMU,
|
||||
};
|
||||
|
||||
struct chip_operations southbridge_amd_sr5650_ops = {
|
||||
CHIP_NAME("ATI SR5650")
|
||||
.enable_dev = sr5650_enable,
|
||||
};
|
||||
@ -1,139 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2010 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef __SR5650_H__
|
||||
#define __SR5650_H__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch/acpi.h>
|
||||
#include "chip.h"
|
||||
#include "rev.h"
|
||||
|
||||
typedef struct __PCIE_CFG__ {
|
||||
u16 Config;
|
||||
u8 ResetReleaseDelay;
|
||||
u8 Gfx0Width;
|
||||
u8 Gfx1Width;
|
||||
u8 GfxPayload;
|
||||
u8 GppPayload;
|
||||
u16 PortDetect;
|
||||
u8 PortHp; /* hot plug */
|
||||
u16 DbgConfig;
|
||||
u32 DbgConfig2;
|
||||
u8 GfxLx;
|
||||
u8 GppLx;
|
||||
u8 NBSBLx;
|
||||
u8 PortSlotInit;
|
||||
u8 Gfx0Pwr;
|
||||
u8 Gfx1Pwr;
|
||||
u8 GppPwr;
|
||||
} PCIE_CFG;
|
||||
|
||||
/* PCIE config flags */
|
||||
#define PCIE_DUALSLOT_CONFIG (1 << 0)
|
||||
#define PCIE_OVERCLOCK_ENABLE (1 << 1)
|
||||
#define PCIE_GPP_CLK_GATING (1 << 2)
|
||||
#define PCIE_ENABLE_STATIC_DEV_REMAP (1 << 3)
|
||||
#define PCIE_OFF_UNUSED_GFX_LANES (1 << 4)
|
||||
#define PCIE_OFF_UNUSED_GPP_LANES (1 << 5)
|
||||
#define PCIE_DISABLE_HIDE_UNUSED_PORTS (1 << 7)
|
||||
#define PCIE_GFX_CLK_GATING (1 << 11)
|
||||
#define PCIE_GFX_COMPLIANCE (1 << 14)
|
||||
#define PCIE_GPP_COMPLIANCE (1 << 15)
|
||||
|
||||
/* -------------------- ----------------------
|
||||
* NBMISCIND
|
||||
------------------- -----------------------*/
|
||||
#define PCIE_LINK_CFG 0x8
|
||||
#define PCIE_NBCFG_REG7 0x37
|
||||
#define STRAPS_OUTPUT_MUX_7 0x67
|
||||
#define STRAPS_OUTPUT_MUX_A 0x6a
|
||||
|
||||
/* -------------------- ----------------------
|
||||
* PCIEIND
|
||||
------------------- -----------------------*/
|
||||
#define PCIE_CI_CNTL 0x20
|
||||
#define PCIE_LC_LINK_WIDTH 0xa2
|
||||
#define PCIE_LC_STATE0 0xa5
|
||||
#define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */
|
||||
|
||||
#define PCIE_CORE_INDEX_SB (0x05 << 16) /* see rpr 4.3.2.2, bdg 2.1 */
|
||||
#define PCIE_CORE_INDEX_GPP1 (0x04 << 16)
|
||||
#define PCIE_CORE_INDEX_GPP2 (0x06 << 16)
|
||||
#define PCIE_CORE_INDEX_GPP1_GPP2 (0x00 << 16)
|
||||
#define PCIE_CORE_INDEX_GPP3a (0x07 << 16)
|
||||
#define PCIE_CORE_INDEX_GPP3b (0x03 << 16)
|
||||
|
||||
/* contents of PCIE_VC0_RESOURCE_STATUS */
|
||||
#define VC_NEGOTIATION_PENDING (1 << 1)
|
||||
|
||||
#define LC_STATE_RECONFIG_GPPSB 0x10
|
||||
|
||||
/* ------------------------------------------------
|
||||
* Global variable
|
||||
* ------------------------------------------------- */
|
||||
extern PCIE_CFG AtiPcieCfg;
|
||||
|
||||
/* ----------------- export functions ----------------- */
|
||||
u32 nbpcie_p_read_index(struct device *dev, u32 index);
|
||||
void nbpcie_p_write_index(struct device *dev, u32 index, u32 data);
|
||||
u32 nbpcie_ind_read_index(struct device *nb_dev, u32 index);
|
||||
void nbpcie_ind_write_index(struct device *nb_dev, u32 index, u32 data);
|
||||
uint32_t l2cfg_ind_read_index(struct device *nb_dev, uint32_t index);
|
||||
void l2cfg_ind_write_index(struct device *nb_dev, uint32_t index,
|
||||
uint32_t data);
|
||||
uint32_t l1cfg_ind_read_index(struct device *nb_dev, uint32_t index);
|
||||
void l1cfg_ind_write_index(struct device *nb_dev, uint32_t index,
|
||||
uint32_t data);
|
||||
u32 pci_ext_read_config32(struct device *nb_dev, struct device *dev, u32 reg);
|
||||
void pci_ext_write_config32(struct device *nb_dev, struct device *dev, u32 reg,
|
||||
u32 mask, u32 val);
|
||||
void sr5650_set_tom(struct device *nb_dev);
|
||||
|
||||
unsigned long southbridge_write_acpi_tables(struct device *device,
|
||||
unsigned long current,
|
||||
struct acpi_rsdp *rsdp);
|
||||
|
||||
void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add);
|
||||
void enable_pcie_bar3(struct device *nb_dev);
|
||||
void disable_pcie_bar3(struct device *nb_dev);
|
||||
|
||||
void enable_sr5650_dev8(void);
|
||||
void sr5650_htinit(void);
|
||||
void sr5650_htinit_dect_and_enable_isochronous_link(void);
|
||||
void sr5650_early_setup(void);
|
||||
void sr5650_before_pci_init(void);
|
||||
void sr5650_enable(struct device *dev);
|
||||
void sr5650_gpp_sb_init(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void sr5650_gfx_init(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void avoid_lpc_dma_deadlock(struct device *nb_dev, struct device *sb_dev);
|
||||
void config_gpp_core(struct device *nb_dev, struct device *sb_dev);
|
||||
void PcieReleasePortTraining(struct device *nb_dev, struct device *dev,
|
||||
u32 port);
|
||||
u8 PcieTrainPort(struct device *nb_dev, struct device *dev, u32 port);
|
||||
void pcie_config_misc_clk(struct device *nb_dev);
|
||||
void fam10_optimization(void);
|
||||
void sr5650_disable_pcie_bridge(void);
|
||||
u32 get_vid_did(struct device *dev);
|
||||
void detect_and_enable_iommu(struct device *iommu_dev);
|
||||
void sr5650_iommu_read_resources(struct device *dev);
|
||||
void sr5650_iommu_set_resources(struct device *dev);
|
||||
void sr5650_iommu_enable_resources(struct device *dev);
|
||||
void sr5650_nb_pci_table(struct device *nb_dev);
|
||||
void init_gen2(struct device *nb_dev, struct device *dev, u8 port);
|
||||
void sr56x0_lock_hwinitreg(void);
|
||||
struct resource * sr5650_retrieve_cpu_mmio_resource(void);
|
||||
#endif /* __SR5650_H__ */
|
||||
Reference in New Issue
Block a user