Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities of the SPI interface. The
reference code for both Picasso and Cezanne also only sets the
SPI_USE_SPI100 bit and doesn't zero out the other bits.
TEST=Verified that Mandolin still boots. It didn't show any signs of
possibly related instabilities before though, so this test doesn't say
much.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I71c2ec1729d5cb4cdff6444b637af29caaa6f1c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
commit 90ac882a32 (soc/amd/common/block/
spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST) introduced a Kconfig
option to enable/disable the 4DW burst support in the SPI flash data
prefetcher, but missed to update the documentation above the
fch_spi_early_init prototype, so update the outdated documentation now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I07c4b0b02251da63d34a172e2636894e99845d6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Current log2_ceil(x) is defined as log2(x * 2 - 1). When x is larger
than (1 << 31), (x * 2 - 1) won't fit in u32, leading to incorrect
result. Therefore, correct it as (log2(x - 1) + 1). Also add unit tests
for inline functions in lib.h.
BUG=none
TEST=make tests/lib/lib-test
BRANCH=none
Change-Id: If868f793b909a6ad7fc48a7affac15e2c714fa2e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
These functions can't be weak, because they actually need to configure
the GPIOs for eSPI and the TPM. With this change zork boots again.
I also noticed that zork doesn't use the early table in bootblock. This
means that zork will only boot if psp_verstage is enabled.
BUG=b:209465425
TEST=boot zork to ramstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Add a list of gpios to lock for brya. This currently includes
GPIOs connected to the FPMCU.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.
Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change supplies a list of ADL gpios that are connected to non-host
(x86) controllers and should be locked after initial configuration.
Set SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS to enable GPIO locking.
BUG=b:210430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.
Change-Id: I457bab39f945ab31a89542c6498a73af70cbf9ee
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
For added security, there are some gpios that an SoC will want to lock
once initially configured, such as gpios attached to non-host (x86)
controllers, so that they can't be recofigured at a later point in
time by rogue code.
Likewise, a mainboard may have some gpios connected to secure busses
and/or devices that they want to protect from being changed post
initial configuration.
This change adds a generic gpio locking mechanism that allows the SoC
to export a list of GPIOs to be locked down and allows the mainboard
to export a list of GPIOs that it wants locked down once
initialization is complete.
Use the SOC_INTEL_COMMON_BLOCK_SMM_LOCK_GPIO_PADS Kconfig option to
enable this feature.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify
brya0 boots successfully to kernel.
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Change-Id: I42979fb89567d8bcd9392da4fb8c4113ef427b14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We only have ADL-P 6+8+2 (45W) VR configuration now. Based on the
power map, fill in correct ADL-P 6+8+2 (28W) VR configuration.
BUG=b:202486131
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ie8dbd95b2d8e49b5898b2a97aff72e0e64868c8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Disable LEGACY_SMP_INIT to enable PARALLEL_MP.
Also remove a large amount of APIC code that is now unnecessary.
TEST=Boot on PC Engines apu3
Boot time reduced from 1.707 seconds to 1.620 seconds average across
5 coldboots.
Inspired by CB:59693
Change-Id: Ib49e7d3f5956ac7831664d50db5f233b70aa54db
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With CPU_INFO_V2 enabled %gs holds the pointer to the cpu_info struct,
so don't clobber it. Backup and restore %gs where possible.
Fixes a crash in MPinit seen after calling FSP-S.
Change-Id: If9fc999b34530de5d8b6ad27b9af25fc552e9420
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The patch defines below APIs :
cpu_is_hybrid_supported() : Check whether CPU is hybrid CPU or not.
cpu_get_bus_frequency() : Get CPU's bus frequency in MHz
cpu_get_max_non_turbo_ratio() : Get CPU's max non-turbo ratio
cpu_get_cpu_type() : Get CPU type. The function must be called if
executing CPU is hybrid.
TEST=Verified the APIs on the Brya board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I680f43952ab4abce6e342206688ad32814970a91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This enum is useful to have around for more than just the one file, so
move it to a common header file, and while we're there, also add an
option for UNKNOWN.
TEST=boot test on brya0
Change-Id: I9ccf0ed9504dbf6c60e521a45ea4b916d3dcbeda
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Some acpigen code may use mutexes, and it is a common idiom to pass
a value for the Timeout field of 0xffff, which is interpreted by OSPM
to mean "no timeout". Therefore add a macro for this value.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I16bc9f3f04dd1e3dc0f3eca3e56377e6f48132b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both
backwards, and was causing the system to fail to enter sleep states
because the event was always asserted.
BUG=b:208937710
TEST=only release switch can wake system.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fixes commit 29c7622 ("cpu/x86/mp_init.c: Fix building with no
smihandler") broke SMM init because is_smm_enable() was called before
smm_enable.
Rework the code a little to make it clear what codepaths are used with
CONFIG_HAVE_SMI_HANDLER.
TESTED: now prodrive/hermes boots again.
Change-Id: If4ce0dca2f29754d131dacf2da63e946be9a7b6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59912
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the following support to coreboot
1. Kconfig to add IOM/NPHY in the COREBOOT/FW_MAIN_A/FW_MAIN_B
partition of BIOS
2. Helper functions to support update.
Pre-requisites to enable IOM/NPHY FW Update:
1. NPHY and IOM blobs have to be added to added COREBOOT, FW_MAIN_A and
FW_MAIN_B through board configuration files.
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE: IOM blob Path
SOC_INTEL_CSE_NPHY_CBFS_FILE: NPHY blob path
2. Enable CONFIG_CSE_SUB_PARTITION_UPDATE to enable CSE sub-partition
NPHY/IOM update.
coreboot follows below procedure to update NPHY and IOM:
NPHY Update:
1. coreboot will navigate through the CSE region,
identify the CSE’s NPHY FW version and BIOS NPHY version.
2. Compare both versions, if there is a difference, CSE will trigger an
NPHY FW update. Otherwise, skips the NPHY FW update.
IOM Update:
1. coreboot will navigate through the CSE region, identify CSE's IOM
FW version and BIOS IOM version.
2. Compares both versions, if there is a difference, coreboot will
trigger an IOM FW update.Otherwise, skip IOM FW update.
Before coreboot triggers update of NPHY/IOM, BIOS sends SET BOOT
PARTITION INFO(RO) to CSE and issues GLOBAL RESET commands if CSE
boots from RW. coreboot updates CSE's NPHY and IOM sub-partition only
if CSE boots from CSE RO Boot partition.
Once CSE boots from RO, BIOS sends HMRFPO command to CSE, then
triggers update of NPHY and IOM FW in the CSE Region(RO and RW).
coreboot triggers NPHY/IOM update procedure in all ChromeOS boot
modes(Normal and Recovery).
BUG=b:202143532
BRANCH=None
TEST=Build and verify CSE sub-partitions IOM and NPHY are getting
updated with CBFS IOM and NPHY blobs.
Verified TBT, type-C display, NVMe, SD card, WWAN, Wifi working after
the update.
Change-Id: I7c0cda51314c4f722f5432486a43e19b46f4b240
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds a check to determine if the CSE's current operation mode
is ME_HFS1_COM_SECOVER_MEI_MSG or not before sending HMRFPO_ENABLE
command to CSE. If CSE is already in the ME_HFS1_COM_SECOVER_MEI_MSG,
coreboot skips sending HMRFPO_ENABLE command to CSE to unlock the CSE RW
partition.
TEST=Verify sending HMRFPO_ENABLE command on Brya system.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I387ac7c7296ab06b9bb440d5d40c3286bf879d3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch renames the compare_cse_version() function to the
cse_compare_sub_part_version(). It makes the function generic so that
it can be used to compare version of any CSE sub-partition like IOM,
NPHY etc.
TEST=Verified build for Brya
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I88a44a3c0ba2ad8a589602a35ea644dab535b287
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59689
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce the `SOC_INTEL_ALDERLAKE_PCH_N` Kconfig option and use it to
specify the correct amount of PCIe I/O.
Document number 645550 indicates that Alder Lake-N has 12 PCH root ports
and no CPU root ports.
Document number 645548 indicates ADL-N has 5 clock sources and 5 clock
request signals.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7ebbcdcdb1ccc34b80ec71ac3e591fe4ad6b1904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch moves the CBFS file measurement when CONFIG_TPM_MEASURED_BOOT
is enabled from the lookup step into the code where a file is actually
loaded or mapped from flash. This has the advantage that CBFS routines
which just look up a file to inspect its metadata (e.g. cbfs_get_size())
do not cause the file to be measured twice. It also removes the existing
inefficiency that files are loaded twice when measurement is enabled
(once to measure and then again when they are used). When CBFS
verification is enabled and uses the same hash algorithm as the TPM, we
are even able to only hash the file a single time and use the result for
both purposes.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I70d7066c6768195077f083c7ffdfa30d9182b2b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Change HID name from INT3499 to PRP0001 along with size and
address width. Size decreased from 10K to 2K, address width
decreased from 14 to 8.
BUG=b:203014972
Test= Boot board and issue commands:
`cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom >
./brya_imx208_eeprom.bin`
`hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log`
You should see the result in brya_imx208_eeprom_dump.log to be
same as module nvm file by vendor provided or meet the Intel nvm
calibration format.
(e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00)
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The Hermes mainboard is used in different system configurations. The
current VBT for Poseidon systems is unsuitable for Avalanche systems
because display ports are connected differently.
Add a new field in the BMC config EEPROM layout and use it to choose
the correct VBT for every system configuration.
Change-Id: I2647f2ae3f496b9ad75980ba86beb7800fdb0668
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The original RCOMP resistor and target values only apply to ULT CPUs and
do not make sense for the CFL-S CPUs Hermes uses. Fix the RCOMP settings
and the associated comments.
Tested, still boots.
Change-Id: I015797c58c914c6581d472e6d70d2dd7bad2b14f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Define a new field in the board config EEPROM layout for port B Vref.
Write port B Vref settings to unused non-volatile NID 0x12 instead of
NID 0x18, the actual port B NID. Because per-port Vref settings don't
persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
to restore port B Vref after resetting the codec.
Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use lowercase for hex numbers, sort includes alphabetically and avoid
relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead
of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one
definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up
the indentation of some includes.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There's no need to use a variant structure here. Only one variant is
used, and revision-specific differences are handled at run-time, and
it's unlikely that another variant will ever exist.
Reorganize the mainboard code to get rid of the variant structure.
Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
