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Author SHA1 Message Date
Jeremy Soller
29f9270d39 darp7 SD card does not support RTD3 
Change-Id: Ie393e9cd42f58d2b3b7172c99b9cd5a1b3a41d87
 2020-12-28 09:30:35 -07:00
Jeremy Soller
b625b0db73 Disable invalid PLD group 
Change-Id: I2c8f8aa405a34e56ba1bd8f38b35447bed999a5e
 2020-12-22 14:45:08 -07:00
Jeremy Soller
d0dbaebd28 Fixes for S0ix 
Change-Id: I293b4219332f6ea58f81a231a613b03b74f5e1c4
 2020-12-22 14:28:06 -07:00
Jeremy Soller
7e69c5aae8 Fix PLD groups 
Change-Id: I6b0aaab65350a6588cee7956f9a2d2d773bf458a
 2020-12-22 14:27:20 -07:00
Jeremy Soller
7bb6096cb5 Enable darp7 color keyboard 
Change-Id: I839e32dfea4a3c26f49da8b0aeb92bff711c7a9a
 2020-12-22 13:26:01 -07:00
Jeremy Soller
5cf1e853cc Add darp7 
Change-Id: I8c47a18095ad19f907c9018952dec551865e27fe
 2020-12-22 11:32:42 -07:00
Jeremy Soller
6690cc7c7a Ensure that GPU SSID is restored 
Change-Id: Iada67ff9b7d882167ca2047a1618230e73d4300d
 2020-12-15 10:09:48 -07:00
Jeremy Soller
ebf03eb621 Fix galp5 integrated graphics mode 
Change-Id: I3f46b0fd1e5c66ace2f0c45fa9e4bc580d907547
 2020-12-14 14:59:13 -07:00
Jeremy Soller
776cb6366b Do not ping GPU_EVENT 
Change-Id: I07f0852d57a1cc52f8595c06960db6e7dc78ce76
 2020-12-08 09:07:39 -07:00
Jeremy Soller
36f3b1af84 Enable galp5 NVIDIA GPU 
Change-Id: I9dd1a7b0150672925bf454202947ccace8b0edb7
 2020-12-08 09:05:34 -07:00
Jeremy Soller
3b186d8baf Add debugging and _PR3 linkage for RTD3 driver 
Change-Id: I243e0d8a65f682b1a68af68fa911c8fb8e000cb0
 2020-12-08 09:03:52 -07:00
Jeremy Soller
5fbdab4ddb Remove invalid writes to set TCSS D3 2020-12-03 21:32:32 -07:00
Jeremy Soller
fd716f3457 Casually disable TBT RTD3 
Change-Id: Ia20aded6de9769d9e69a374e67b7ceb569169bc5
 2020-12-03 20:39:14 -07:00
Jeremy Soller
8d4dd30363 Use 9KB VBT 
Change-Id: I19017f4af04bde2b681255a32a9ffc073deb4f62
 2020-12-03 13:17:49 -07:00
Jeremy Soller
c6f49ca48a Revert removal of MMCONFIG 
Change-Id: I22be03d5714b58bd19fdf0cd126487b1e72d7473
 2020-12-03 11:03:30 -07:00
Jeremy Soller
a20126a4b3 Use SCI to wake from suspend whe on TGL models 
Change-Id: I153a9627b846516404b8fd2dceb86872307eecd2
 2020-12-03 09:08:25 -07:00
Jeremy Soller
869eebbbb5 Hide MMCONFIG on TGL and set VBT to 8KB 
Change-Id: I46d9535266e2ca1946213d899ddecc1b426d2294
 2020-12-03 08:45:48 -07:00
Jeremy Soller
bbfea8bd39 Merge remote-tracking branch 'upstream/master' into HEAD 
Change-Id: Id25620ddd031ef761b2f7962acb6682223c9753b
 2020-12-02 20:42:22 -07:00
Jeremy Soller
d95db48cd7 Re-enable lpit 2020-12-02 15:59:24 -07:00
Felix Held
ab0d85c987 soc/amd/stoneyridge: align AOAC code with Picasso 
In commit 09d50671e6 the AOAC code was
reworked for Picasso and this patch ports this back to Stoneyridge to
facilitate factoring out the functionality into common code.

Change-Id: I836b91dc647987d064170fff7c8ca6ef2ee49211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2020-12-01 20:59:32 +00:00
Felix Held
0d57f42e83 soc/amd/picasso/aoac: make aoac_devs array unsigned 
The numbers in the array are unsigned, so use an unsigned type there.

Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2020-12-01 20:59:19 +00:00
Felix Held
9bc16ed856 soc/amd/picasso/aoac: fix typo in comment 
The power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit,
so the comment should be that it powers off the devices.

Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2020-12-01 18:07:33 +00:00
Patrick Rudolph
ee38ccecf8 soc/intel/common/block/smm/smihandler: Fix compilation under x86_64 
Change-Id: Ie44ded11a6a9ddd2a1163d2f57dad6935e1ea167
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:02:19 +00:00
Patrick Rudolph
ed5835a04d soc/intel/common/block/cpu/car/exit_car: Fix compilation on x86_64 
Change-Id: Ieac4a4924ff4684b2a419471cd54e3d3b1f5bbe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48171
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 16:01:58 +00:00
Patrick Rudolph
2b77112e66 soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support 
Doesn't affect x86_32.
Tested on Intel Skylake. Boots into bootblock and console is working.

Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 16:01:44 +00:00
Patrick Rudolph
0e3884cfff drivers/aspeed/common/ast: Fix compilation under x86_64 
Change-Id: I5fb6594ff83904df02083bcbea14b2d0b89cd9dd
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:01:31 +00:00
Patrick Rudolph
90fda02f60 drivers/intel/fsp2_0/notify: Fix compilation under x86_64 
Change-Id: Id63b9b372bf23e80e25b7dbef09d1b8bfa9be069
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:01:19 +00:00
Patrick Rudolph
3805354ff9 soc/intel/common/block/systemagent: Fix compilation on x86_64 
Change-Id: Ibc8dc1cf33f594284edb82d4730967e077739c3c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:01:10 +00:00
Patrick Rudolph
2dbbb83ae4 lib/reg_script: Add cast to fix compilation on x86_64 
Change-Id: Ia713e7dbe8c75b764f7a4ef1a029e64fb2d321fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:00:57 +00:00
Patrick Rudolph
429c77a5e3 cpu/x86/early_reset: Mark assemblycode as 32bit 
Allows to compile the file under x86_64 without errors.

The caller has to make sure to call the functions while in protected
mode, which is usually the case in early bootblock.

Change-Id: Ic6601e2af57e0acc6474fc3a4297e3d2281decd6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:00:40 +00:00
Patrick Rudolph
983ea18f17 cpu/intel/microcode: Mark assemblycode as 32bit 
Allows to compile the file under x86_64 without errors.

The caller has to make sure to call the functions while in protected
mode, which is usually the case in early bootblock.

Change-Id: Ic6d98febb357226183c293c11ba7961f27fac40c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 16:00:34 +00:00
V Sowmya
a99f61fec4 mb/intel/jslrvp: Modify the flash layout for fsp debug build 
Current flash layout doesn't support the fsp debug builds since
the FW_MAIN_A/B doesn't have enough space to hold the fsp debug
binaries along with ME RW binaries.
This patch reduces the SI_ALL size to 3.5MiB and increase the
SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries.

BRANCH=dedede
TEST=Build and Boot jslrvp with fsp debug enabled coreboot.

Cq-Depend: chrome-internal:3425366
Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
 2020-12-01 15:27:01 +00:00
Martin Roth
e2ce56928c mb/google/zork: Mark RW_MRC_CACHE as "Preserve" 
AGESA checks to make sure that the firmware version reading the MRC
cache is the same version that wrote it, so it doesn't need to be
erased during a firmware update.

BUG=b:173724014
TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was
not erased
BRANCH=Zork

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47776
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
 2020-12-01 15:24:13 +00:00
Patrick Rudolph
a169550479 cpu/x86/sipi: Add x86_64 support 
Enter long mode on secondary APs.

Tested on Lenovo T410 with additional x86_64 patches.
Tested on HP Z220 with additional x86_64 patches.

Still boots on x86_32.

Change-Id: I53eae082123d1a12cfa97ead1d87d84db4a334c0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
 2020-12-01 14:53:44 +00:00
Felix Singer
45dc92a8c2 mb/kontron/mal10: Use the system library for headers 
Use the system library for header files instead of relative filesystem
paths.

Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2020-12-01 13:47:39 +00:00
Felix Singer
fee6974452 mb/kontron/mal10/Kconfig: Reorder selects alphabetically 
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
 2020-12-01 13:47:20 +00:00
Felix Singer
3c02ed9cb6 MAINTAINERS: Add missing trailing slashes 
Add missing trailing slashes so that Gerrit recognizes maintainers
correctly.

Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I35fcaf41617247e2b86cd6ddd7ee1b319a695797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48137
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 13:46:54 +00:00
Tim Chu
39ea223249 mb/ocp/deltalake: Update SMBIOS type 8 information 
Update port connector information for Delta Lake.

Tested=Execute "dmidecode -t 8" to check all the information of
SMBIOS type 8 is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-12-01 08:04:30 +00:00
Subrata Banik
f5c3e29bdf ec/google/chromeec/acpi: Make OperationRegion brace align 
Inject TAB to make OperationRegion closing brace align with
opening brace.

Change-Id: Idb9f23cf6a2c249fb1fd02f4a2ac314d4f7e180b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-12-01 08:00:23 +00:00
Subrata Banik
52fabb1247 mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVP 
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ
hence remove the unused GPIO.

Wrong GPIO configuration is causing platform reboot issue on
ADLRVP with Chrome SKU.

Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
 2020-12-01 08:00:09 +00:00
Varshit Pandya
5e1d4dd947 mb/intel/adlrvp: Add ASL support for WFC annd UFC 
1. Add 2 ports and 2 endpoints
2. Add support for OVTI5675

WFC Cam is on I2C5 and UFC is on I2C1
BUG=None
BRANCH=None
TEST=Build and Boot adlrvp board and able to capture image
using camera.

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 07:59:52 +00:00
Varshit Pandya
e9695f0d70 mb/intel/adlrvp: Configure Camera related GPIO as per schematics 
Configure RST and PWR_EN signals for both WFC and UFC

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47496
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 07:59:23 +00:00
Varshit Pandya
1ce5f5827d mb/intel/adlrvp: Update GPIO configuration as per schematics 
Configure I2C related GPIO as per ADL-P schematics.
This is based on Revision 0.974 of schematics.

Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
 2020-12-01 07:58:57 +00:00
Subrata Banik
840679d2c1 mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot 
List of changes:
1. Enable Root Port 8 aka 0:0x1c:7
2. Assign free running clock for RP8
3. Apply W/A to get card detected on x1 slot
- Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low

TEST=Able to detect PCIe SD card over x1 slot
localhost ~ # dmesg | grep mmc
[ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA
[ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8
[ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB
[ 3.849158] mmcblk0: p1

Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 07:52:26 +00:00
Subrata Banik
0f044a5007 mainboard/intel/adlrvp/spd: Update SPD for LP4x SKU 
List of changes in SPD:
1. SPD Revision (of JEDEC spec)
2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB)
3. MSB -> CAS Latencies Supported, First Byte
4. CAS Latencies Supported, Second Byte
5. CAS Latencies Supported, Third Byte
6. LSB -> CAS Latencies Supported, Fourth Byte
7. Minimum CAS Latency Time (tAAmin)
8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax)
9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin)
10.Cyclical Redundancy Code (0- 125 byte)

TEST=Able to build and boot with updated SPD.

Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
 2020-12-01 07:49:58 +00:00
Sridhar Siricilla
ae81d59eca mb/intel/adlrvp: Add support for LPDDR5 
This patch adds LPDDR5 memory configuration parameters to FSP.

TEST=Able to pass FSP-M MRC training on LPDDR5 RVP.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
 2020-12-01 07:49:47 +00:00
Subrata Banik
4cb8776c31 mb/intel/adlrvp: Refactor lpddr4_mem_config structure 
List of changes:
1. Initialize dq_map array in a single line
2. Make dqs_map array also in a single line

TEST=Able to build and boot ADLRVP LP4 SKU.

Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 07:49:32 +00:00
Yu-Ping Wu
3c729487bf Makefile.inc: Alloc .bss* sections for "struct" file type 
When the global variable of a "struct" CBFS file is zero (for example,
CB:47696), the binary will appear in the .bss* section in the ELF file
(instead of .data). This results in an empty binary file added to CBFS,
so that file size check will fail when reading it at runtime.

BUG=b:173751635
TEST=emerge-asurada coreboot
TEST=Check sdram-lpddr4x-KMDP6001DA-B425-4GB is non-empty in CBFS
BRANCH=none

Change-Id: Idfd17d10101a948de0eb0522a672afd5c2f83b04
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47903
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-12-01 07:31:22 +00:00
Paul Fagerburg
679b236bed util/mb/google/puff: remove HECI from overridetree 
The template for overridetree.cb includes HeciEnabled, which has
been removed from the CNL config struct, so remove it from the
overridetree.

BUG=b:174360951
TEST=`new_variant_fulltest.sh puff` succeeds

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I87f67c53cc75d9ddd40b4960739180a95de6ecd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
 2020-12-01 01:25:17 +00:00
Felix Singer
617150e0ff mb/siemens/chili: Configure GPIOs in gpio.c 
Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead
of passing data around.

Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-11-30 23:08:50 +00:00