Commit Graph

35813 Commits

Author SHA1 Message Date
Tim Crawford
25e164c5e2 mb/system76/gaze15: Annotate GPIOs
This was done using the schematics for the 15" GTX 1660 Ti variant.

Change-Id: I2f7628d68bd5491438b6d71556b5cb73873b9b89
2020-08-14 11:34:44 -06:00
Jeremy Soller
df0ecca51d select TPM_RDRESP_NEED_DELAY for system76 laptops
Change-Id: I7909b05e9203ce9ad07c8e87a847bc46cf281b34
2020-08-13 13:12:15 -06:00
Jeremy Soller
e4bfd5b28a Merge pull request #23 from system76/bonw14
bonw14
2020-08-13 12:20:24 -06:00
Jeremy Soller
fe9ea17423 bonw14
Change-Id: I533acb5e835de97c1ac52a201bca95671f53d932
2020-08-13 12:18:59 -06:00
Tim Crawford
efe04c82e0 mb/system76: Fix left USB3 port on gaze14/gaze15
The USB table in the manuals incorrectly list the USB3 port as 5.
The labeled pins show it correctly as port 2.

Change-Id: I9a6a96af847ca66ad667738d83cfca7c3166956a
2020-08-13 08:01:00 -06:00
Jeremy Soller
011439cb91 Sync addw2 devicetree with oryp6
Change-Id: Id32845c96479ce124a6bb55c2434e78e6f96b519
2020-08-06 08:24:46 -06:00
Jeremy Soller
599ca05c8c Update devicetree.cb 2020-08-04 10:42:15 -06:00
Jeremy Soller
d563135d4b Sync changes from upstream PRs
Change-Id: If65cd6262ab625047edb8d242d00f520e4ff8d14
2020-07-21 09:09:38 -06:00
Jeremy Soller
bccef94545 Quote MAINBOARD_DIR
Change-Id: Ida3ca099fd8ab6d7b1112e5f203b791e6c46dd0d
2020-07-20 12:09:30 -06:00
Jeremy Soller
dca083da74 Absolute path for qc_blobs in gitmodules
Change-Id: I5bab7ace1503f54fafff9073b35f9b3e0952c0b7
2020-07-20 11:55:13 -06:00
Jeremy Soller
94612338ef Merge remote-tracking branch 'upstream/master' into system76
Change-Id: Idceb013b3495324b8d84a388ea5ee5b5ea4b69db
2020-07-20 11:54:36 -06:00
Jeremy Soller
9e729e44a8 Refactor DGPU support code into drivers/system76/dgpu
Change-Id: Id29d6ade82b7212a3a68f6f3c27769e17d3fdcdc
2020-07-20 11:52:44 -06:00
Pandya, Varshit B
65e5b100e2 mb/google/dedede: Update link frequency and end point structure for OV9734
1. Update Link frequency to 180 Mhz
2. Set data-lanes to 1 and
3. Update the clock-lane used by sensor

BUG=b:155285666
BRANCH=None
TEST=Build and able to capture image using user facing camera.

Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com>
Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-20 15:18:23 +00:00
Raul E Rangel
500eb450b5 mb/amd/mandolin: Delete sleep.asl
These methods are empty and the kernel treats these as optional.

BUG=b:153001807, b:154756391
TEST=none

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 14:01:24 +00:00
Raul E Rangel
030bace562 mb/google/zork: Delete sleep.asl
These methods are empty and the kernel treats these as optional.

BUG=b:153001807, b:154756391
TEST=Suspend and resume trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 14:01:09 +00:00
Furquan Shaikh
dce0ce954f mb/google/zork: Drop unnecessary PULL_UPs for dalboz reference
This change drops internal pulls for dalboz reference configured on pads
which already have external pull-ups in hardware.

GPIO_0(PWR_BTN_L): Pulled up to PP3300_A
GPIO_2(WAKE_L): Pulled up to PP3300_A
GPIO_10: Unused. Changed to PAD_NC.
GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A
GPIO_12(USI_INT_ODL): Pulled up to PP3300_A
GPIO_16(USB_OC0_L): Pulled up to PP3300_A
GPIO_17(USB_OC1_L): Pulled up to PP3300_A
GPIO_21(EMMC_CMD): Pulled up to PP1800_S0
GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A
GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A
GPIO_32: Unused. Changed to PAD_NC.
GPIO_113(I2C2_SCL): Pulled up to PP3300_S0
GPIO_114(I2C2_SDA): Pulled up to PP3300_S0
GPIO_129(KBRST_L): Pulled up to PP1800_S0
GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0
GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0
GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0

BUG=b:154351731

Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20 13:54:31 +00:00
Furquan Shaikh
7571110d78 mb/google/zork: Drop unnecessary PULL_UPs for trembyle reference
This change drops internal pulls for trembyle reference configured on pads
which already have external pull-ups in hardware.

GPIO_0(PWR_BTN_L): Pulled up to PP3300_A
GPIO_2(WAKE_L): Pulled up to PP3300_A
GPIO_10: Unused. Changed to PAD_NC.
GPIO_12(USI_INT_ODL): Pulled up to PP3300_A
GPIO_16(USB_OC0_L): Pulled up to PP3300_A
GPIO_17(USB_OC1_L): Pulled up to PP3300_A
GPIO_21(EMMC_CMD): Pulled up to PP3300_A
GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A
GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A
GPIO_90: Unused. Changed to PAD_NC.
GPIO_113(I2C2_SCL): Pulled up to PP3300_S0
GPIO_114(I2C2_SDA): Pulled up to PP3300_S0
GPIO_129(KBRST_L): Pulled up to PP1800_S0
GPIO_130(EC_IN_RW_OD): Pulled up to PP3300_S0
GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0
GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0
GPIO_132(CLK_REQ4_L): Pulled up to PP3300_S0

BUG=b:154351731

Change-Id: Id84b801e019eede7ef543c24aac968f3ef99b3fd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:54:09 +00:00
Angel Pons
12a4d05b9e src: Report word-sized access for PM1a_EVT
According to the ACPI specification, version 6.3:

    Accesses to the PM1 status registers are done through byte or word
    accesses.

The same is said about the PM1 Enable registers. Therefore, reporting
dword-sized access is wrong and means nothing anyway. Since some other
platforms use word-sized access, use word everywhere for consistency.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: I6f85c9a4126f37ab2a193c3ab50a6c8e62cf6515
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43432
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:33:32 +00:00
Angel Pons
94b0c791a0 sb/intel/i82801dx/fadt.c: Use ACPI_ADDRESS_SPACE_IO
Tested with BUILD_TIMELESS=1, AOpen DXPL Plus-U remains identical.

Change-Id: I80ec4d0d6a8ec0dc02b377cfa3f3b5f0362dbb6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-20 13:33:23 +00:00
Angel Pons
89cdb36279 sb/intel/bd82x6x/fadt.c: Use definitions instead of numbers
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: I2212a6dd4b02ac8fdcf1eafbab0226ad9faa825e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-20 13:33:15 +00:00
Angel Pons
38eec5bc73 sb/intel/ibexpeak/fadt.c: Use definitions instead of numbers
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: If0ee1b65a1be67ee9f5f832f076c365017a14e6a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-20 13:33:08 +00:00
Angel Pons
79572e4f32 src: Make HAVE_CF9_RESET set the FADT reset register
All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.

To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-20 13:23:13 +00:00
Angel Pons
3eb8dbaee2 src: Drop useless cache flush settings in FADT
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-20 13:22:44 +00:00
Angel Pons
b74975e403 soc/amd/stoneyridge: Select HAVE_CF9_RESET
Looks like some preparation is needed before reset. However, Picasso
also needs some special handling and still selects this option without
selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now.

Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:22:13 +00:00
Angel Pons
a208c6ce73 src: Never overwrite fadt->flags
Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:22:03 +00:00
Angel Pons
4b1b0efeda soc/intel/xeon_sp/skx: Clean up FADT
Both `acpi_fill_fadt` and `soc_fill_fadt` set many FADT fields. Since
the latter runs later, the values programmed in it overwrite any other
values. Drop unused assignments and consolidate everything in a single
function. Use `acpi_fill_fadt` as it is mandatory (no weak definition).

Change-Id: Ia8248f20dae2b93426f309605bb2076592b08df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43386
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:19:31 +00:00
Angel Pons
e8e2e3e00d sb/intel/i82371eb: Declare reset register in FADT
According to Intel Order Number 290562 (PIIX4 datasheet), 0xcf9 is the
reset register, and setting bits 1 and 2 will result in a hard reset.

Change-Id: Id5ada6a10b2269d51908c6a5fd7745ef6c33a29a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20 13:19:05 +00:00
Angel Pons
2e5e99c48c sb/intel/i82801dx: Declare reset register in FADT
According to Intel Document 290744 (ICH4 datasheet), 0xcf9 is the reset
register, and setting bits 1 and 2 will result in a hard reset.

Change-Id: Id1a532857d9643d222d61c3902faadd471ae2a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20 13:18:56 +00:00
Angel Pons
7db5ce15a3 sb/intel/i82801dx: Drop unneeded PM2 settings from FADT
The PM2_CNT register block is not present on this southbridge, as per
Intel Document 290744 (ICH4 datasheet). Also, the ACPI specification,
version 6.3, section 4.8.1.3 (PM2 Control Register), says:

 This register block is optional, if not supported its block pointer and
 length contain a value of zero.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.

Also delete a comment about `pm2_cnt_len`, which said that the right
value differs from zero. Looks like that comment was wrong instead.

Change-Id: Icbb32f5db7b368c764b3477c40f8ae9c788df5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:18:14 +00:00
Angel Pons
4787f2953c sb/intel/i82371eb: Drop unneeded PM2 settings from FADT
The PM2_CNT register block is not present on this southbridge, according
to comments on the code. As per the ACPI specification, version 6.3,
section 4.8.1.3 (PM2 Control Register):

 This register block is optional, if not supported its block pointer and
 length contain a value of zero.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.

Change-Id: Ib3ff0fd9e0725f61c38e60ba56b95e6e77b0b1ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43382
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:17:28 +00:00
Angel Pons
192b57cc8b amd/{hudson,stoney,picasso}: Drop PM2 settings from FADT
The PM2_CNT register block is no longer needed, as explained in some
comments. While they may have been copy-pasted around a lot, they are at
least true for Hudson, and it makes sense to assume that they are true
for newer chipsets as well. As per the ACPI specification, version 6.3,
section 4.8.1.3 (PM2 Control Register):

 This register block is optional, if not supported its block pointer and
 length contain a value of zero.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.

Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:16:46 +00:00
Angel Pons
1b5a7dec43 src: Drop useless PM1b settings from FADT
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):

 If the PM1b_EVT_BLK is not supported, its pointer contains a value of
 zero in the FADT.

 If the PM1b_CNT_BLK is not supported, its pointer contains a value of
 zero in the FADT.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:16:05 +00:00
Angel Pons
77653e3bce src: Drop useless GPE1 settings from FADT
None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:

 If a generic register block is not supported then its respective
 block pointer and block length values in the FADT table contain zeros.

Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 13:15:45 +00:00
Tim Chen
24a61841e3 mb/google/puff: update USB3 gen2 parameters
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2.

BRANCH=none
BUG=b:150515720
TEST=build and check the USB3 gen2 register on DUT is correct.

Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-20 12:37:19 +00:00
Jamie Chen
3658c62908 soc/intel/cannonlake: Add configs for USB 3.1 Gen2 EV settings
Add configs for USB 3.1 Gen2 EV settings so that people can set the
EV settings per board in device tree.

BUG=b:150515720
BRANCH=none
TEST=build coreboot and fsp with enabled fw_debug.
     Flashed to puff and checked the log.
     All usb configs were set correctly.

Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: Id4860665619095139c329565d433d9eb495cac02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39448
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 12:36:59 +00:00
Angel Pons
73e35f6af9 mb/asrock/b85m_pro4: Enable VGA port
Now that libgfxinit has been fixed, trying to enable the Analog port no
longer hangs the system, nor fills the monitor with unreadable garbage.

Tested with linear framebuffer, displays correctly on a 1920x1080 VGA
monitor. Scaling also works when a smaller HDMI monitor is connected as
well. Legacy VGA text mode is also functional on either monitor, too.

Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 12:09:58 +00:00
Angel Pons
9b09093878 3rdparty/libgfxinit: Update submodule pointer
This brings in 4 new commits:
* c0db994 common/Makefile.inc: Factor out generation TLAs
* 3f86b0b Move `PSR_Off` out of `Power_And_Clocks_Haswell`
* 450c24c haswell: Make VGA on FDI work
* 3318bf2 Drop generation suffix from `Power_And_Clocks`

Change-Id: I023b0c2bb403b3a9c9fe575a78cd2cf2f20b112a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20 12:09:47 +00:00
Angel Pons
a92878152f 3rdparty/libhwbase: Update submodule pointer
This brings in 5 new commits:
* 69e9086 mutime: Make Sinfo an imported constant
* 9f87a10 time: Add T_First constant
* 4e22910 Makefile: Adapt $(space) definition
* d822df5 Makefile: Delay expansion of `$(ADAFLAGS)`
* a3edc6e Makefile: Add `-gnatw_R` to suppress spurious warning

Change-Id: I907e66fcf85da256a112a7069a3c551a6d8caaf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43558
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 12:09:30 +00:00
Srinidhi N Kaushik
9ea45ffb39 vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3274
Update FSP headers for Tiger Lake platform generated based FSP
version 3274.

Compared to the current version 3197, v3274 adds most of the legacy UPDs
in both FSPM and FSPS.

BUG=b:159151231
BRANCH=none
TEST=build and boot volteer proto2

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Id3f957aa9d9ad9710a3c930717c22f485699315e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43473
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20 03:59:46 +00:00
Angel Pons
45d5f8f163 sio/nuvoton/common/early_serial.c: Guard serial enable
If CONSOLE_SERIAL is not set, do not reconfigure the UART LDN.
Otherwise, SerialICE stops working when the UART LDN is disabled.

Change-Id: Ie3113e6b7b830dfdddc4d7709f00719f29e094bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-19 18:18:12 +00:00
Maxim Polyakov
75db8c8ea8 soc/intel/common/gpio_defs: Fix coding style
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.

Change-Id: Ib4b4c28153398b6275728b28bda90e527d97e823
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41035
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19 16:25:05 +00:00
Nico Huber
666c8f8fc5 mb/qemu-i440fx/memmap: Add warning when falling back to CMOS infos
Change-Id: Iefac6fd45791cf6a051450b41046f7e7ebc1dc41
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19 11:20:15 +00:00
Nico Huber
d2245d890b mb/qemu/fw_cfg: Fix return code check for fw_cfg_e820_select()
Change-Id: I22b9eb6ead37dbba6807d145468843bd01c94c84
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19 11:20:10 +00:00
Nico Huber
ef59c93f77 mb/qemu/fw_cfg: Add info messages about (not) found files
Print some more information at BIOS_INFO, like our CBFS code does.

Change-Id: I1431d569c57634277ea5cf7feb352419db432b44
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43444
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19 11:20:05 +00:00
Jeremy Soller
65600cdec6 Move most mainboard/system76 ACPI code to ec/system76 (#21)
* Move most mainboard/system76 ACPI code to ec/system76

* Move drivers/system76_ec to ec/system76

* Include system76_ec.c when CONSOLE_SYSTEM76 is set

* Fix inclusion of system76 EC code

* Default CONSOLE_SYSTEM76_EC to n

* addw2: fix SSD2 clkreq
2020-07-18 13:49:05 -06:00
Tim Wawrzynczak
0115ba8835 Documentation: Add documentation for drivers/intel/dptf chip driver
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8915ead08a89dcf95fd92983eca5f85b82916dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-18 16:05:43 +00:00
Tim Wawrzynczak
f524188f48 ec/google/chromeec: Fix oversights in ec_dptf_helpers
GTSH was 2 instead of 20 (so it's 2 degrees K hysteresis), and TSRD was
accidentally defined to take 0 arguments, instead of 1.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14d28bacf44ac65043060b8579b3fbcec758c56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18 16:05:33 +00:00
Tim Wawrzynczak
bec6731c76 ec/google/chromeec: Fix \_SB.DPTF._OSC
The DPTF._OSC method incorrectly assumed that all available UUIDs would
be present in the IDSP package, but this is not always the case. Instead
of matching an incoming UUID against an index into IDSP, search the IDSP
package for the matching UUID.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I718b6abe09152647b14f7c1405b2d0d20035726b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-18 16:05:22 +00:00
Tim Wawrzynczak
752c471348 mb/google/dedede: Convert static DPTF ASL into devicetree entries
Since there is now a mechanism to generate DPTF ACPI tables and methods
at runtime, dedede should switch to using that instead of raw ASL files.
This patch converts the existing .asl files into devicetree entries.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18 16:05:07 +00:00
Tim Wawrzynczak
c6a593bc3e drivers/intel/dptf: Add missing scope operator around TSR options
The previous DPTF patch train missed the proper scope operator around
all of the TSR options. Without this, the optional GTSH and/or _STR
Methods end up in the wrong scope.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9298c442c047c5f7f606574d900057a7c004b47f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43458
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18 16:04:51 +00:00