8bf197653f
nb/intel/sandybridge: Deduplicate PCIEXBAR decoding
...
We can use `decode_pcie_bar` instead, as other northbridges do.
Change-Id: I35bede573ef2635c54123f9e553003577ecd0ea7
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-06 10:57:39 +00:00
20905cfe26
nb/intel/sandybridge: Refactor get_pcie_bar
...
Turn it into `decode_pcie_bar`, taken from gm45.
Change-Id: Id1c2cfbcac1a798d046beced790930511dc97972
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44121
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-06 07:25:25 +00:00
96b32f194b
drivers/intel/fsp2_0: Do AP re-init after FSP-S if USE_INTEL_FSP_MP_INIT enable
...
This patch ensures that coreboot is able to take control of APs back
by doing a full AP re-initialization after FSP-S is done.
TEST=Able to see all cores available after booting to OS using below command
when coreboot is built with USE_INTEL_FSP_MP_INIT enable.
> cat /proc/cpuinfo
Without this CL :
shows only 1 core (only BSP)
With this CL :
shows all possible cores available (BSP + APs)
Change-Id: I247d8d1166c77bd01922323b6a0f14ec6640a666
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-08-06 04:24:24 +00:00
a3c33c6e21
soc/intel/common/block/cpu: Refactor init_cpus function
...
This patch makes init_cpus function external so that it can be used
in below scenarios:
1. When coreboot is doing MP initialization as part of
BS_DEV_INIT_CHIPS (exclude this call if user has selected
USE_INTEL_FSP_MP_INIT)
2. coreboot would like to take APs control back after FSP-S has done
with MP initialization based on user select USE_INTEL_FSP_MP_INIT
Also make sure post_cpus_init function is getting executed
unconditionally to update MTRR snapshot on all cores.
Change-Id: Idc03090360f34df074b33ba0fced2d192edf068a
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-08-06 04:24:16 +00:00
4bcb63bdd8
soc/mediatek/mt8183: Set MMU default map length to 8GB befor mem init
...
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I072745933fe141cac26afd044836a564e345d036
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43795
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-06 03:03:53 +00:00
d4eb14aa3c
mb/google/kukui: Add ddr geometry to support 6GB, 8GB DDR bootup
...
Set correct DDR geometry for all existing memory modules.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I9b53ab2bf43e0dfb7448eb37a18faf686267eaed
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
2020-08-06 03:03:25 +00:00
0e6cb83abb
soc/mediatek/mt8183: Add ddr geometry to support 6GB, 8GB DDR bootup
...
Currently the DRAM initialization code can only work on 4GB size and
want to support larger memory sizes in future, so add geometry
information to the DRAM calibration parameters.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I1fdf50b75c6a552c0a889f21e1a81ab4b9a305fa
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-08-06 03:03:00 +00:00
92fb91935b
soc/mediatek/mt8183: Adjust tRFCab and tRFCpb by the density value
...
Different density should correspond to different tRFCab and tRFCpb
timing.
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I2599fcd620cdefe2e12480932ffd75e0416b9545
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2020-08-06 03:02:40 +00:00
cac990f186
soc/mediatek/mt8183: Add missing register settings for channels
...
Some DRAM control settings need to apply to all channels,
so add those missing settings.
Also fix a typo (0x1 < 0) to (0x1 << 0).
BUG=none
BRANCH=kukui
TEST=Boots correctly on Kukui
Change-Id: I35e25c922ed45216d5f04835abcd10809a8d559a
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Reviewed-by: Hung-Te Lin <hungte@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-08-06 03:02:17 +00:00
8aca8da2ea
mb/google/kukui: Add a new config 'Fennel'
...
A new board introduced to Kukui family.
BUG=b:162478693
TEST=make # select Fennel
BRANCH=kukui
Signed-off-by: xiatao5 <xiatao5@huaqin.corp-partner.google.com >
Change-Id: I1f742a36793f38c37fbd4e1b4cbddbd542e785ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44061
Reviewed-by: Zhuohao Lee <zhuohao@google.com >
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org >
Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-06 03:01:52 +00:00
1e8ef3c458
vendorcode/amd/fsp/picasso Fix type 17 smbios misalignment
...
Add __packed to TYPE17_DMI_INFO structure to remove padding. Remove
reserved fields that are no longer required. Corresponding change will
also be made within fsp to pack the structure.
BUG=b:154046847
TEST=Boot a trembyle with and without the reserved fields and confirm
type 17 table is unchanged.
Cq-Depend: chrome-internal:3194239
Change-Id: I9ba7e2a4fb82c7b0b77ee7c6c075e6211d4f6adf
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Rob Barnes <robbarnes@google.com >
2020-08-05 20:10:53 +00:00
01707406a1
mb/intel/jasperlake_rvp: Replace static camera ACPI by driver
...
This change updates devicetree to enable SSDT generation for world
facing and user facing cameras of jasperlake_rvp. Also removes DSDT
changes related to the world facing camera.
Change-Id: Ib439572bc1d15ef02c86c7bfa88af6b16eb06f97
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2020-08-05 16:30:50 +00:00
3ea036f9ce
drivers/intel/mipi_camera: Fix SSDT generation for IPU devices
...
Includes changes in mipi_camera driver to fix following issues related
to SSDT generation for IPU devices.
1. acpigen_write_device was not getting called for IPU devices
2. acpigen_pop_len was called for a generic devices without calling
acpigen_write_device
Change-Id: I309edd065719cb8250f1241898bb5854004d2a9f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44025
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 16:30:10 +00:00
94e0a10f00
sb/intel/i82801{gx,ix,jx}/acpi/lpc.asl: Drop dead code
...
This code is not even being build-tested. Drop it before it grows moss.
Also drop a now-unnecessary #undef directive from one mainboard.
Change-Id: I613e77723d108641f16ec732358849c3bc0e49e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43220
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 15:46:27 +00:00
5567bb5c25
{sb,soc}/intel/*/acpi/lpc.asl: Drop commented-out code
...
This code has been commented out for a long time. Drop it.
Change-Id: Iddc635dc5bbc7a8b42e97f4e2f6d579a839d874b
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43264
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 15:46:17 +00:00
b7db12bf7e
{nb,soc}/intel: Use get_current_microcode_rev() for ucode version
...
This patch removes all redundant read microcode version implementation
from SoC directory and refer from cpu/intel/microcode/microcode.c file.
TEST=Able to get correct microcode version.
Change-Id: Icb905b18d85f1c5b68fac6905f3c65e95bffa2da
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44175
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 15:36:38 +00:00
053b972a2a
mb/google/volteer/var/voxel: Add Raydium touchscreen support
...
Update gpio GPP_E7 and enable the Raydium TS support
BUG=b:157402209,b:162632701,b:162636271
BRANCH=master
TEST= 1. emerge-volteer coreboot chromeos-bootimage
2. boot up on voxel DUT and make sure the raydium TS can work.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: YH Lin <yueherngl@google.com >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Caveh Jalali <caveh@chromium.org >
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com >
2020-08-05 15:32:59 +00:00
92887375c5
mb/google/vilboz: update telemetry settings for vilboz
...
update telemetry value for SDLE test result.
BUG=b:160698427
BRANCH=None
TEST=emerge-zork coreboot
Change-Id: Icce57f9be2732ff79f336daa6c447a30247366cf
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-08-05 15:19:54 +00:00
026e940f03
drivers/genesyslogic/gl9763e: Add driver for Genesys Logic GL9763E
...
The device is a PCIe to eMMC bridge controller to be used in the
Chromebook as the boot disk. The datasheet name is GL9763E and
the revision is 02.
The patch sets single request AXI, disables ASPM L0s and enables SSC.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com >
Change-Id: I158c79f5ac6e559f335b6b50092469c7b1646c56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-08-05 15:16:16 +00:00
e2497d0181
mb/google/zork: keep the c-state IO base address alignment
...
Align the C-state MSR value of BSP with AGESA.
BUG=b:162705221
BRANCH=none
TEST=Check the MSR value is correct and BSP can enter CC6 with AVT tool
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Change-Id: Ib98d34af518439d338326446c20601867ad31690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-08-05 14:45:37 +00:00
b7184e28ba
mb/google/zork/ezkinil: Fix ELAN touchscreen ACPI node
...
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Add Delay after stop_gpio Low - 300ms
BUG=b:162263398
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com >
Change-Id: I3d4dcb6e5cae5d9515abfd415315ec4114ca80b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44107
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 13:42:08 +00:00
5ba154a597
src: Use space after 'if', 'for'
...
Change-Id: I5d3a5ede47aefc7cc2ee330f8a0bcded16138764
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44173
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 11:37:00 +00:00
6aa9d66873
src: Use space after switch, while
...
Change-Id: I150591aa3624895c4c321101a251547dd23d1db5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44172
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 11:36:52 +00:00
239272e43d
src/soc/intel/common: Make top_of_ram till TOLUD region mmio_resource
...
Ideally don't need to mark the entire top_of_ram till TOLUD range (used
for stolen memory like GFX and ME, PTT, DPR, PRMRR, TSEG etc) as
cacheable for OS usage as coreboot already done with mpinit w/ smm
relocation early.
TEST=Able to build and boot ICL, TGL RVP.
Without this CL :
PCI: 00:00.0 resource base 77000000 size 4800000 align 0 gran 0 limit 0 flags f0004200 index 9
PCI: 00:00.0 resource base 7b800000 size 4400000 align 0 gran 0 limit 0 flags f0000200 index a
With this CL :
PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index 9
No changes observed with MTRRs snapshot.
Change-Id: I64c14b14caf0a53219fdc02ec6bbd375955a0c8e
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-08-05 07:27:38 +00:00
e58c6f5dfa
baytrail mainboards: Clean up mainboard.c
...
This cleans up some unneeded no-ops in the mainboard.c files
of baytrail boards.
Change-Id: I7662f6e860d672a99b211488122bec073cc78acf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Máté Kukri <kukri.mate@gmail.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-08-05 07:05:33 +00:00
6d097b831b
include/device/azalia_device.h: Include <stdint.h>
...
This file only needs <stdint.h>. So replace <types.h> with <stdint.h>.
Change-Id: Ib58532837941d5324b28bc2c607d70555ce9caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44134
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-05 07:04:22 +00:00
fc726b9888
mb/google/zork: update DRAM SPD table for dirinboz
...
DRAM support list
0x00 HYNIX HMA851S6CJR6N-VK
0x01 HYNIX H5ANAG6NCMR-VKC
0x02 Samsung K4A8G165WC-BCTD
0x03 Samsung K4AAG165WB-MCTD
0x04 Samsung K4A8G165WC-BCWE
0x05 HYNIX H5AN8G6NDJR-XNC
0x06 HYNIX H5ANAG6NCMR-XNC
0x07 Micron MT40A512M16TB-062E:J
0x08 Micron MT40A1G16KD-062E:E
0x09 Samsung K4AAG165WA-BCTD
0x0A Samsung K4AAG165WA-BCWE
BUG=b:161579679
BRANCH=master
TEST=build
Change-Id: Ib9fa5ae98568d659326d431a4006174a343fa299
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-08-05 06:19:50 +00:00
f672f7ff7d
soc/intel/common: Include Alder Lake device IDs
...
Add Alder Lake specific CPU, System Agent, PCH (Alder Point aka ADP),
IGD device IDs.
Document Number: 619501, 619362
Change-Id: I17ce56a220e4dce2db2e0e69561b3d6dac9e65a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2020-08-05 05:38:14 +00:00
d1c590a666
nb/intel/x4x: Define and use HOST_BRIDGE macro
...
Other Intel northbridges do this.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change
Change-Id: I50785b7bf3e3cc0eade7fda4b4b2e2bb71a54c31
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 22:44:06 +00:00
4bc8dfb820
Revert "device/pci_device.c: Do not complain about disabled devices"
...
This reverts commit ad247ac5d8nico.huber@secunet.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2020-08-04 22:07:21 +00:00
96a80133e1
soc/intel/skylake: Add RMRRs after all DRHDs
...
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:
BIOS implementations must report these remapping structure types in
numerical order. i.e., All remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
So, update the corresponding code to adhere to the specification.
Change-Id: I2446d536603559f637f3f8b1b44e9d712aa35492
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-08-04 21:43:45 +00:00
37799b3439
soc/intel/broadwell: Add RMRRs after all DRHDs
...
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:
BIOS implementations must report these remapping structure types in
numerical order. i.e., All remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
So, update the corresponding code to adhere to the specification.
Change-Id: Ib5ef5e006e590d72bec52e057e9b72150e0e636f
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-08-04 21:43:35 +00:00
c05a3f86ab
soc/intel/apollolake/acpi.c: Add RMRRs after all DRHDs
...
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:
BIOS implementations must report these remapping structure types in
numerical order. i.e., All remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
So, update the corresponding code to adhere to the specification.
Change-Id: I4ee3ae6c45e2a2c921fbccbb62b853e4a141a58d
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-08-04 21:42:29 +00:00
9dfd6150bd
nb/intel/sandybridge/acpi.c: Add RMRRs after all DRHDs
...
The VT-d architecture specification (Doc. D51397-011, Rev. 3.1) says:
BIOS implementations must report these remapping structure types in
numerical order. i.e., All remapping structures of type 0 (DRHD)
enumerated before remapping structures of type 1 (RMRR), and so forth.
So, update the corresponding code to adhere to the specification.
Change-Id: I1f84cae41c6281e0d545669f1e7de5cab0d9f9c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2020-08-04 21:42:13 +00:00
579ccdf9c9
nb/intel/x4x: Remove dead assignments
...
The call to `decode_pcie_bar` always initializes these values.
Change-Id: Iffdb2fc846a6fc1a1abc504370b6283e292b61c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:41:23 +00:00
9e757a0ab0
soc/amd/picasso/acpi: clean up global NVS
...
Some fields in GNVS seem to be copied over from Apollolake to
Stoneyridge to Picasso. This patch removes the unused fields.
BUG=b:161165393
TEST=Mandolin still boots and dmesg shows no new ACPI errors.
Change-Id: I8c6b580543089bf0180a7caeb9e6a47dc4ed4a1d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2020-08-04 21:37:44 +00:00
8f917b1d4b
nb/intel/x4x: Refactor decode_pcie_bar
...
Constify and eliminate local variables where possible to ease reading.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.
Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:36:32 +00:00
ce3e6380b9
nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding
...
Other northbridges have a `decode_pcie_bar` function. Since it's not
needed anywhere else, keep it as a static function for now.
Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:36:00 +00:00
4a2f08c846
nb/intel/i945: Deduplicate PCIEXBAR decoding
...
We can use `decode_pcie_bar` instead, if we make it non-static.
Change-Id: Ic39f3df0293b4d44f031515b1f868e0bb9f750c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:35:26 +00:00
cff4d1649f
nb/intel/i945: Refactor get_pcie_bar
...
Turn it into `decode_pcie_bar`, taken from gm45.
Change-Id: I81a398535f18ced10b5521bddcf21f3568e1d854
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:35:08 +00:00
1850396dc4
nb/intel/haswell: Use ASL 2.0 syntax
...
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I9c69028ff13efa6999b6110fbcd9233a09def991
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2020-08-04 21:33:58 +00:00
d19332ca3a
sb/intel/i82801gx: Use PCI bitwise ops
...
While we are at it, also reflow a few lines that fit in 96 characters.
Tested with BUILD_TIMELESS=1, Getac P470 does not change.
Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:33:35 +00:00
302a1437cd
nb/intel/ironlake/acpi/hostbridge.asl: Use ASL 2.0 syntax
...
This brings Ironlake closer to Sandy Bridge.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Idde75e7295f642f8add34168bffe5851ea02fbc6
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43687
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2020-08-04 21:31:08 +00:00
5cd8c7c3e6
nb/intel/sandybridge: Update to ASL 2.0 syntax
...
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: Ie3570cd0a75c6b34581b35165c1c6393214ad0bb
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2020-08-04 21:30:43 +00:00
ecec9474d8
nb/intel/x4x: Change signature of decode_pciebar
...
Rename it and make it return an int, like other northbridges do.
Change-Id: I8bbf28350976547c83e039731d316e0911197d54
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:28:52 +00:00
f4fa1e1d06
nb/intel/haswell: Deduplicate PCIEXBAR decoding
...
Add `decode_pcie_bar` for consistency with other Intel northbridges.
Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:28:05 +00:00
90de10c17a
nb/intel/pineview: Refactor decode_pcie_bar
...
Constify and eliminate local variables where possible to ease reading.
Tested with BUILD_TIMELESS, Foxconn D41S remains identical.
Change-Id: Iaad759886a8f5ac07aabdea8ab1c6d1aa7020dfc
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:27:31 +00:00
653d8717ba
nb/intel/pineview: Change signature of decode_pciebar
...
Rename it and make it return an int, like other northbridges do.
Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:27:16 +00:00
69356489fe
nb/intel/pineview: Use MiB definition
...
Also constify a local variable while we're at it.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2020-08-04 21:26:49 +00:00
92e4ca6a38
mb/google/zork/var/vilboz: Enable support for garaged stylus
...
This change adds support for pen insert/eject operations in S0 and
wake on pen eject from S3 for vilboz.
BUG=b:157628650
Change-Id: I7ba0881b67dfb67c032667d591f7d1806a50af22
Signed-off-by: Furquan Shaikh <furquan@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2020-08-04 20:35:59 +00:00
