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30238 Commits

Author SHA1 Message Date
Julius Werner
aa4c1d2b5b google/trogdor: Remove GPIO_AP_SUSPEND_L 
This pin has been removed from recent revisions (or at least moved to a
pin that's not controlled like a normal GPIO). It has also never been
used on older ones (I think?). The same GPIO is now used as a SKU ID
pin, so make sure we're not incorrectly configuring it as an output
(although sku_id() overrides that later anyway, but it's still
incorrect).

BUG=b:160754995

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-16 00:58:24 +00:00
Rob Barnes
9754f38e82 mb/google/zork: Remove redundant PCI info from overridetrees 
This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb

domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.

BUG=b:157580724
TEST=Boot zork, usb functional

Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-16 00:16:40 +00:00
Karthikeyan Ramasubramanian
e0407a8e44 mb/google/dedede: Enable SIS touchscreen for Waddledee 
Add SiS9813 USI touchscreen support.

BUG=b:160129126
TEST="emerge-dedede coreboot chromeos-bootimage", build successful.

Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:42:25 +00:00
Jett Rink
3f5de1c8f4 security/vboot: ensure that NVMEM is saved on every kernel space write 
If the AP actually needs to write to the TPM, then it is important and
the TPM should commit those changes to NVMEM immediately in case there
is an unexpected power loss (e.g. from a USB-C port partner reset upon
cold reboot request).

BRANCH=none
BUG=b:160913048
TEST=Verify that puff will no longer reboot loop when coreboot writes a
new Hmir (Hash mirror) in the TPM

Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:42:11 +00:00
Shaunak Saha
60e6f6e1e5 mb/google/volteer: Enable SATA Port Dito Config 
Enable SataPortsEnableDitoConfig for port 1.

BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42415
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:40:37 +00:00
Shaunak Saha
1a8949c0c4 soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs 
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.

* PxDEVSLP.DM ->     SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
 Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
 (DITO), Default is 625ms.

BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.

Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:40:25 +00:00
Raul E Rangel
742abd3daf soc/amd/picasso/acpi: Delete unused and invalid OperationRegions 
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.

BUG=b:153001807, b:154756391
TEST=Build Trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-07-15 08:38:43 +00:00
Raul E Rangel
1aa5cff709 soc/amd/picasso/acpi: Remove old AOAC register definitions 
We no longer need this code. It's been added differently in CB:42473.

BUG=b:153001807, b:154756391
TEST=Build Trembyle

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6fe1e465f137ba6afbf9f0dbce501b5fc845e210
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-07-15 08:38:34 +00:00
Raul E Rangel
e62a17b118 soc/amd/picasso/acpi: Remove invalid and unnecessary devices 
These devices are not referenced by anything else.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ea3c326247dce095b5ac1706dbc37f8b215a21e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-07-15 08:38:19 +00:00
Raul E Rangel
b3d7ced512 mb/google/zork/.../sleep.asl: Remove unnecessary variable 
There is no reason to create a named variable. We can just return the
package.

BUG=b:153001807, b:154756391
TEST=None

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
 2020-07-15 08:37:42 +00:00
Tim Wawrzynczak
0c0bcd4072 PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device 
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:34:29 +00:00
Angel Pons
380789a6ee mainboard: Drop optional and empty ACPI \_BFS methods 
The ACPI specification, version 2.0 says:

    _BFS is an optional control method.

So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.

Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:33:43 +00:00
Felix Held
f06d7d7003 amd/picasso: rework DXIO and DDI UPD handling 
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.

BUG=b:158695393
TEST=Mandolin still boots.

Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:32:47 +00:00
Felix Held
692dde599f vc/amd/fsp/picasso: replace #pragma pack(1) with __packed attribute 
Forgetting to add the #pragma pack() at the end of the header file can
lead to hard to debug breakage, so get rid of the #pragma pack usage and
add a __packed to the structs that need to be packed which has less
possibly unwanted side effects.

Since commit d44221f9c8 coreboot always
includes commonlib/compiler.h which provides __packed.

TEST=Timeless build results in identical binary.

Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-07-15 08:32:18 +00:00
Angel Pons
de3fe84ca9 mb/lippert/frontrunner-af: Drop commented-out Kconfig symbol 
Drop it before it grows moss.

Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 08:31:21 +00:00
Rob Barnes
13ec6a03ab mb/google/zork: Change SPI fast speed to 66mhz 
Morphius cannot support 100Mhz fast SPI causing it to not boot.
Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe.

BUG=b:161233767
TEST=Boot morphius

Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-15 03:41:18 +00:00
wuxy
288646744f mb/google/oak: Add new DRAM modules for oak 
Add DRAM support for oak:
Samsung  K4E6E304ED-4GB        # 1001
Nanya    NT6CL512T32AM-H0-4GB  # 1010

BUG=b:157702981
BRANCH=oak
TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge,
update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours.

Signed-off-by: Xingyu Wu <wuxy@bitland.corp-partner.google.com>
Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
 2020-07-15 01:55:03 +00:00
Edward O'Callaghan
0f72ddfd20 mb/hatch: Fix Puff baseboard missing mainboard symbols 
Fix a missing CONFIG_ prefix in Makefile.

BUG=b:161154280
BRANCH=puff
TEST=builds

Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11
Spotted-by: Ryan Lin.
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 22:45:36 +00:00
Angel Pons
c3c7ef3ec2 soc/intel/skylake: Move acpi_fill_fadt to fadt.c 
Intel southbridges do this.

Change-Id: I8ecf3c0b0c822185ca66bae1bd65b0cf24512a49
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:34:03 +00:00
Angel Pons
6ee77517c0 soc/intel/braswell: Move acpi_fill_fadt to fadt.c 
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.

Change-Id: I2fd2ec5a3029dc1bd1fa65dc3d1af5505f1f1dad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:56 +00:00
Angel Pons
91ca2ddde1 soc/intel/baytrail: Move acpi_fill_fadt to fadt.c 
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.

Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:50 +00:00
Angel Pons
34e417316a soc/intel/broadwell: Move acpi_fill_fadt to fadt.c 
Intel southbridges do this.

Change-Id: Id120e4a6b42168de58c396439593900a00d7e757
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:13 +00:00
Angel Pons
2bd25bfb7f sb/intel/lynxpoint: Move acpi_fill_fadt to fadt.c 
Other Intel southbridges do this.

Change-Id: I9b0c8be34e01b617352da4ff8ff37f4b44a4b334
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:33:06 +00:00
Angel Pons
530cde8a9e sb/intel/bd82x6x: Move acpi_fill_fadt to fadt.c 
Other Intel southbridges do this.

Change-Id: I6ae78696b0fa2d91dd2c6de0a3ef28e08d85e93b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:32:59 +00:00
Angel Pons
cee5ff0629 sb/intel/ibexpeak: Move acpi_fill_fadt to fadt.c 
Other Intel southbridges do this.

Change-Id: I8306295fb87776aab5ed0e56e1a9c480c65fe3c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
 2020-07-14 22:32:50 +00:00
Elyes HAOUAS
e3ee36498e soc/amd/common/block/include/amdblocks/acpi.h: Add missing <types.h> 
BIT(x) needs <types.h>

Change-Id: I5dc0d45567ae9879a7e12f2ccc48929d2abc9456
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-07-14 16:15:55 +00:00
Elyes HAOUAS
a0545e6e15 arch/x86/postcar_loader: Remove unused 'include <cpu/cpu.h>' 
Change-Id: I5a36f5729a1a5ad5819ebb3c46b775ba52237d65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42080
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:15:28 +00:00
Elyes HAOUAS
3992698388 cpu/intel/model_1067x: Drop <cpu/x86/mp.h> include 
Found using:
diff <(git grep -l 'include <cpu/x86/mp.h>' -- src) <(git grep -l 'CACHELINE_SIZE\|cpu_info\|mfence\|mfence\|mp_ops\|mp_init_with_smm\|MP_RUN_ON_ALL_CPUS\|mp_run_on_aps\|mp_run_on_all_cpus\|mp_park_aps\|smm_initiate_relocation_parallel\|smm_initiate_relocation' -- src/) |grep '<'

Change-Id: Ib721e667144d6803261f3761a077570e0e27391d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
 2020-07-14 16:15:09 +00:00
Elyes HAOUAS
06a5e854e1 src: Drop unused <cpu/x86/tsc.h> include 
Found using:
diff <(git grep -l '#include <cpu/x86/tsc.h>' -- src/) <(git grep -l 'TSC_SYNC\|tsc_struct\|rdtsc\|tsc_t\|multiply_to_tsc\|rdtscll\|tsc_to_uint64\|tsc_freq_mhz\|tsc_constant_rate' -- src/)|grep '<'

Change-Id: Id090e232a96323adb8d9a24b81f7ae5669248f57
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42393
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:14:33 +00:00
Elyes HAOUAS
14aff23b92 src: Remove unused 'include <cpu/x86/msr.h>' 
Found using:
diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<'

Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:14:09 +00:00
Elyes HAOUAS
d970e39eae src/drivers/usb/gadget.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I1ca111a30153526c3915bf393208fb2b4c569c01
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43347
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:53 +00:00
Elyes HAOUAS
eb7e166ea1 soc/intel/baytrail/northcluster.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I85745c331c81a419cef4547fc1c67bde1e202e8f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43346
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:39 +00:00
Elyes HAOUAS
bd42b06495 soc/intel/baytrail/romstage/pmc.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: If8384f4fea66e26d7377311e7bd8379c7848a26f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43345
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:25 +00:00
Elyes HAOUAS
8ebad6d78d soc/intel/baytrail/romstage/raminit.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I659a067e3b737dc7efe5bdadfd88207cd4d7175d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43344
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:12:12 +00:00
Elyes HAOUAS
3ea5b2d2e6 soc/intel/braswell/romstage/romstage.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: I43b8ba5849de30e2ee253382ef85b17f2d0ae589
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43343
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:11:59 +00:00
Elyes HAOUAS
0badea85a7 soc/rockchip/rk3399/display.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>.

Change-Id: Ibdde8fb5ec5bf7d25facd78064a7837d24fa2c8a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43342
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:11:42 +00:00
Elyes HAOUAS
ad619a2473 src/drivers/usb/ehci_debug.c: Add missing include 
Replace unused <stddef.h> with missing <stdint.h>. This is needed for 'u64'.

Change-Id: Ie99c27bd6a7d982bba9a93342f3e3b83a1c09e8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2020-07-14 16:11:27 +00:00
Elyes HAOUAS
854782330c src: Remove unused 'include <stdint.h> 
Found using:
diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:11:10 +00:00
Elyes HAOUAS
5320f5387e src/acpi/soundwire.c: Add missing <stddef.h> 
size_t needs <stddef.h>. Replace unused <stdint.h> with <stddef.h>.

Change-Id: Ib9ab5555adeeddd9eea7a93dbb166d8479eca42e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43340
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:10:43 +00:00
Elyes HAOUAS
225be5f7ee src: Remove unused 'include <types.h>' 
Files found using:
diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<'

Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:10:17 +00:00
Elyes HAOUAS
5a8e072020 src: Remove unused 'include <string.h>' 
Found using:
diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<'

Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41913
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:09:44 +00:00
Rob Barnes
f0d1c9a423 mb/google/zork: Add USB to baseboard devicetree 
Add USB ports, USB user-facing camera and USB bluetooth to devicetree.
USB ports 4 and 5 are duplicated for picasso and dali.

BUG=b:158096224
TEST=Boot Trembyle and Dalboz, Dump acpi tables

Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-07-14 16:09:01 +00:00
Rob Barnes
ddeba9f196 mb/google/zork: Split devicetree between baseboards 
Split zork baseboard devicetree between dalboz and trembyle.
The devicetree is simply duplicated, no other changes in this commit.

BUG=b:158096224
TEST=Build coreboot for zork

Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2020-07-14 16:08:43 +00:00
Wisley Chen
51c6d4429c mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratini 
Screen flickered on VT2 on some devices  after idle a period of time.

Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.

Because CB:38212 (commit eae254e) caused this issue.

BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered

Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:08:06 +00:00
Shreesh Chhabbi
370868766b mainboard/volteer: Enable SaGv for volteer2, delbin & voxel 
SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.

BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.

Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2020-07-14 16:07:25 +00:00
xuxinxiong
8cf43f6c98 mb/google/kukui: Add new configs 'Cerise' and 'Stern' 
New boards introduced to Kukui family.

BUG=b:160854400
TEST=make # select Cerise and Stern
BRANCH=kukui

Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320
Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-14 16:05:49 +00:00
Angel Pons
30392ae396 sb/intel/lynxpoint: Define SerialIO devfns 
This reduces differences with Broadwell.

Tested with BUILD_TIMELESS=1, Google Panther remains identical.

Change-Id: I81c34fd03a176d0575f2fbd254052d90f2b38487
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
 2020-07-14 16:04:56 +00:00
Nick Vaccaro
20cf396c96 mb/google/volteer: config QS silicon devices for CSE LITE 
Configure volteer2 and delbin, the two variants currently using
preQS or QS silicon, to use CSE Lite.

BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.

Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
 2020-07-14 04:52:51 +00:00
Rob Barnes
009a23d5c8 soc/amd/picasso: supply SMBIOS type 17 
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.

BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none

Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
 2020-07-13 21:39:05 +00:00
Furquan Shaikh
33d9eeae5f mb/google/zork: Fix check for variant_uses_v3_schematics() 
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi
power enable") added helper functions for determining if a board uses
v3 schematics. However, it introduced a regression by adding a wrong
check for variant_uses_v3_schematics() in variant_audio_update(). This
change fixes the check to ensure that dmic_gpio is updated when
variant is not using v3 schematics.

BUG=b:161141258,b:161128964
TEST=Verified on trembyle that trackpad works again (it was broken
because of the regression).

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2020-07-13 21:23:50 +00:00