Now that SMM can write to CBMEM we can simply replay the transfer buffer
cbmem console to move it into the main cbmem console.
replay_transfer_buffer_cbmemc() relies on the EARLY_RAM linker symbols.
Since the SMM rmodule get linked with a different linker script than
bootblock/romstage it doesn't have access to these symbols. In order to
pass these symbols into SMM, we parse the bootblock.map file and
generate an early_ram.ld script. This script is then used when linking
SMM.
I replay the buffer in `smm_soc_early_init` because this call happens
before `console_init()`. `console_init()` prints the SMM header and we
want to append the verstage contents before printing the header to avoid
confusion.
BUG=b:221231786
TEST=Perform S0i3 cycles and verify PSP verstage logs now show up when
doing `cbmem -c`.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I64d33ccdee9863270cfbcaef5d7c614349bd895c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change provides hooks for the SoC so it can perform any
initialization and cleanup in the SMM handler.
For example, if we have a UART enabled firmware with DEBUG_SMI, the UART
controller could have been powered off by the OS. In this case we need
to power on the UART when entering SMM, and then power it off before we
exit. If the OS had the UART enabled when entering SMM, we should
snapshot the UART register state, and restore it on exit. Otherwise we
risk clearing some interrupt enable bits.
BUG=b:221231786, b:217968734
TEST=Build test guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I946619cd62a974a98c575a92943b43ea639fc329
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable PCIe support for mt8195.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early
stage to reduce the impact of 100ms delay.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: If6799c53b03a33be91157ea088d829beb4272976
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Log the platform boot mode reported by PSP verstage to PSP stage 1
bootloader. This helps to improve the debuggability.
BUG=b:193050286
TEST=Build and Boot to OS in Nipperkin. Ensure that the platform boot
mode is logged in the verstage logs.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I752ee56f2af48215a770d799432d02f0609757cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.
BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO. Ensure that the screen visibility gets updated
by pressing the privacy screen button.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
As part of boot time optimization, one of the culprit was CSE where
response to End Of Post (EOP) command used to take ~60ms. Earlier patch
was pushed to delay the EOP to reduce response time to ~5-7 ms. During
this stage overall platform boot time was ~1.15 seconds.
Once boot time was optimized to ~ 1 seconds, CSE EOP time again
increased to ~80 ms since coreboot used to send EOP at the time where
CSE was busy. This created some back and forth moving of sending EOP
command function within coreboot sequence.
Upon debugging using traces, it was found that coreboot used to send
EOP late where CSE was busy loading other IP payload, so it might take
more time to respond.
In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow where
FSP used to send EOP once silicon init is done and coreboot used to
rely on FSP to send this message.
Moving EOP to earlier stage (From SoC) meets the requirement and CSE EOP time
reduces from ~60 ms to ~20 ms on Brya board.
Note that once SoC code sends EOP, coreboot common code won't send it
again since common code already has check in case EOP is sent earlier.
BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Tested on Brya system before and after the changes. Observed ~40ms
savings in boot time.
Change-Id: I9401d5e36ad43cdc0dfe947aabc82528d824df9b
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Earlier while trying to optimize boot time End Of Post (EOP) time kept
increasing (~80 ms) when boot time decreased to around 1 second.
This was because CSE was busy with own firmware loading.
When EOP was moved later in boot stage it again created issue since CSE
got busy with other payload loading for OS boot, so response to EOP
got delayed by ~70-80 ms.
In order to avoid delayed response, coreboot has to send EOP in
stage when CSE is done with firmware init and it will be ready to
serve EOP as soon as possible. This also aligns with previous flow
where FSP used to send EOP once silicon init is done and coreboot used
to rely on FSP to send this message.
Moving EOP to BS_DEV_INIT boot state meets this requirement and CSE EOP
time reduces from ~60 ms to ~20 ms on Brya QS board.
Since this setting might vary for each SoC, SoCs can decide when to send
EOP in the boot sequence. This patch adds Kconfig option to send EOP via
SoC
BUG=b:211085685
BRANCH=firmware-brya-14505.B
TEST=Code compilation is fine for Brya board. Boot time test is done
using entire patchset and EOP time is reduced to ~25ms from earlier ~80ms.
Change-Id: I9c7fe6f8f3fadb68310d4a09692f51f82c737c35
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I40dc78c743f4201a11ea0c26a8af716cab42b805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I93444cdb96eaf729630b48551d0853511b584634
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The current code will write the raw value from the CMOS, which doesn't
match the respective setting in EC.
Switch argument will write the correct value, and prevent the setting
being reset.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iabeec47bf492b698f95d86aa2d08ba9caedd75f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This solved the error:
i801_smbus 0000:00:1f.1: can't derive routing for PCI INT A
i801_smbus 0000:00:1f.1: PCI INT A: not connected
i801_smbus 0000:00:1f.1: SPD Write Disable is set
i801_smbus 0000:00:1f.1: SMBus using polling
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idebd581b7ed6d193d83340b7dc94248df43525c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement is met, and the total capacitance can be tuned
externally for different boards.
BUG=b:218439447
TEST=set capid to 0xe0.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62563
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some non-SoC code might want to know whether or not the CNVi DDR RFIM
feature is enabled. Also note that future SoCs may also support this
feature. To make the CnviDdrRfim property generic, move it from
soc/intel/alderlake to drivers/wifi/generic instead.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Currently, all of the commands for building futility are printed as they
are run. This change skips printing the check for libcrypto unless the
check actually fails. This prevents the error from being displayed when
there isn't actually a problem.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9ef36c0b64f7cd69d19b8faabd165ef6651c838e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
While running Sphinx, it shows the warning "document isn't included in
any toctree" for the documents checklist.md and templates.md. These are
not meant to be listed in ToC trees.
Thus, mark them as orphaned to exclude them from ToC trees.
Change-Id: I1ff8f7c24ac9b3c3a120914c0c72ab73e85c4873
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62584
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix stylus UI behavior bug.
1) it appears the kernel's gpio_key driver is not expecting
an IRQ descriptor for the `gpio` property, therefore change
to an active-low input.
2) The wakeup event was configured backwards.
Change list
- Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW".
- Change wakeup_event_action from ASSERTED to DEASSERTED.
BUG=b:220992812
TEST=emerge-brya coreboot chromeos-bootimage and verify pass
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change will allow the SMI handler to write to the cbmem console
buffer. Normally SMIs can only be debugged using some kind of serial
port (UART). By storing the SMI logs into cbmem we can debug SMIs using
`cbmem -1`. Now that these logs are available to the OS we could also
verify there were no errors in the SMI handler.
Since SMM can write to all of DRAM, we can't trust any pointers
provided by cbmem after the OS has booted. For this reason we store the
cbmem console pointer as part of the SMM runtime parameters. The cbmem
console is implemented as a circular buffer so it will never write
outside of this area.
BUG=b:221231786
TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are
visible when running `cbmem -1`. Perform a suspend/resume cycle and
verify new SMI events are written to the cbmem console log.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.
Below table gives the size reduction from brya fmd to nissa fmd:
+----------------+-------------------+---------------+
| Region | Earlier size (KB) | New size (KB) |
+================+===================+===============+
| SI_ME | 5116 | 3772 |
+----------------+-------------------+---------------+
| RW_SECTION_A/B | 8192 | 4344 |
+----------------+-------------------+---------------+
| VBLOCK_A/B | 64 | 8 |
+----------------+-------------------+---------------+
| ME_RW_A/B* | 3008 | 1434 |
+----------------+-------------------+---------------+
| RW_LEGACY | 2048 | 1024 |
+----------------+-------------------+---------------+
| RW_ELOG | 16 | 4 |
+----------------+-------------------+---------------+
| SHARED_DATA | 8 | 4 |
+----------------+-------------------+---------------+
| VBLOCK_DEV | 8 | 0 |
+----------------+-------------------+---------------+
| RW_SPD_CACHE | 4 | 0 |
+----------------+-------------------+---------------+
| RW_NVRAM | 24 | 8 |
+----------------+-------------------+---------------+
| WP_RO | 8192 | 4096 |
+----------------+-------------------+---------------+
| GBB | 448 | 12 |
+----------------+-------------------+---------------+
*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/
BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.
Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on
ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to
ME_RW_A/B regions.
On ADL-N, this results in savings of ~665KB in each of ME_RW_A/B
regions.
FMAP REGION: ME_RW_A
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
FMAP REGION: ME_RW_B
Name Offset Type Size Comp
me_rw 0x0 raw 1275246 LZMA
(1957888 decompressed)
(empty) 0x1375c0 null 193056 none
Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
With LinuxBoot Linux relied on the legacy method of fetching the RSDP
pointer to get ACPI. This uses a more modern approach available since
2018 on the Linux kernel, which involves filling in the zero page.
This method takes precedence over any other method of fetching the
RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are
threatening that legacy code will be removed from Linux so it's best
to already adapt to that possibility.
Tested on Qemu:
- With qemu the RSDP is always in the EBDA, so checking if Linux uses
the provided pointer is better done with a forced bad entry
- With a fake bad pointer Linux correctly does not find RDSP
Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ACPI RSDP can only be found in:
- legacy BIOS region
- via UEFI service
On some systems like ARM that legacy BIOS region is not an option, so
to avoid needing UEFI it makes sense to expose the RSDP via a coreboot
table entry.
This also adds the respective unit test.
Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
