To print times with 1 us resolution just adds unnecessary noise
when comparing logs across different boots. Furthermore, just
the printk itself is 1 ms if some slow console is enabled.
Change-Id: Ibea43124a1937f404a6e71fd9431086b2b72290a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For each boot_state, report the times spent interleaved
with other console output and remove the samples arrays.
The time spent to report the times to console is not
accounted for.
Change-Id: I0c847da98901c56b356b4a933d9ae865dada98b6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
After C_ENVIRONMENT_BOOTBLOCK became mainstream, coreboot build system
starts to produce larger bootblock, conflicting with former default
offsets.
This change makes these offsets configurable before building, with
default values lower than before, to better fit the larger bootblock.
Change-Id: Ie022663a4d0df7f431865b55f7329a9ebb90863b
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37778
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent changes to the Atmel touchscreen driver in the mainline
kernel broke functionality with devices running upstream coreboot,
due relying on another driver (chromeos_laptop) which makes the
assumption that the i2c devices are be in PCI mode (as with the
stock Google firmware) rather than in ACPI mode as they are in
upstream coreboot.
Mitigate this by adding the required devicetree property so the
Atmel toushcreen driver will correctly attach without the use
of chromeos_laptop.
Test: build/boot peppy on 4.18+ kernel, verify touchscreen working
Change-Id: I05df8367886eef55b409590f75a68d98d4e5fbdf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicolò
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Provide the PM1_TMR information in the FADT even if PmTimerDisabled is
set because PM timer emulation is enabled via MSR 121h so the timer will
still work and can be used by things like Tianocore and Windows.
Porting from 662b6cb3ed (soc/intel/skylake: Always add PM1_TMR block to FADT).
Change-Id: Ie3d592623f3a84051477ffe83a0cf0daf30dd36f
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Assume that LIMIT_POWER is not requested if the ec does not support it.
Do this by checking the command code in the response message instead
of return value.
BUG=b:146165519
BRANCH=None
TEST=Boot puff with EC which does not support LIMIT_POWER param.
Change-Id: Ib2f5f69a53f204acebfab3e36aab2960eeec1204
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The gnvs structure was zeroed out already in the following files:
* src/southbridge/intel/i82801ix/lpc.c (t400 and x200)
* src/southbridge/intel/i82801gx/lpc.c (thinkcentre_a58)
Change-Id: Id7d552e1c4084a0b36b98f9627a85a75c8b90e81
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
create_coreboot_variant.sh now supports the Volteer baseboard in
addition to Hatch. The shell script and supporting python code are
moved up one level, while retaining the ${BASE}/template/* file
structure for each supported baseboard.
kconfig.py has to add slightly different text to Kconfig.name
depending on which baseboard is selected.
BRANCH=None
BUG=b:146646594
TEST=Create variants of Hatch and Volteer, check that the staged
commits are correct.
$ ./create_coreboot_variant.sh hatch sushi b:12345
src/mainboard/google/hatch/Kconfig and Kconfig.name will have new
sections for SUSHI. src/mainboard/google/hatch/variants/sushi
will have a copy of util/mainboard/google/hatch/template
$ ./create_coreboot_variant.sh volteer ripto b:12345
src/mainboard/google/volteer/Kconfig and Kconfig.name will have new
sections for RIPTO. src/mainboard/google/volteer/variants/ripto
will have a copy of util/mainboard/google/volteer/template
Also run the script with an existing board name to verify that you
can't create a variant that already exists.
Change-Id: I084b6c50bb76af0d11dc86a96b3c3c434569a0dd
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
We found the driver binding failure issue could be cleared with 100ms
of "reset_delay_ms". Needs further check with device vendor, anyway it
seems the IC need some time before communication after de-assertion of
reset.
BUG=b:129159369
BRANCH=firmware-hatch-12672.B
TEST=Verified driver bound successfully.
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Change-Id: Iccb33c13c9a390a2c971325c74c0c4ad4b08618e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If the EC doesn't support the EARLY_EC_SYNC we don't properly set power
limits to reasonable defaults and can wedge the AP by browning out at
the end of vboot.
BRANCH=none
BUG=b:146165519
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I4e683e5a1c5b453b3742a12a519cad9069e8b7f7
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37930
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
