Commit Graph

56851 Commits

Author SHA1 Message Date
Arthur Heymans
6ed0ba1e93 cbfstool: Read XIP stage alignment requirements from ELF
On x86_64 romstage can contain page tables and a page table pointer
which have an larger alignment requirement of 4096. Instead of
hardcoding it, read if from the ELF phdrs.

Change-Id: I94e4a4209b7441ecb2966a1342c3d46625771bb8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82102
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-20 19:34:14 +00:00
Roger Wang
71c9010443 mb/google/nissa/var/sundance: Increase I2C1 hold time to 126ns
According to the vendor spec, I2C1 hold time needs > 100ns.
System needs to adjust the I2C1 sda_hold value from 7 to 13,
the system will change the I2C1 hold time from 70ns to 126ns.

BUG=b:347157276

TEST=built bootleg and verified test result by EE team

Change-Id: I722ec93177b6debf6b4c99de2df68c942560a3ff
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83080
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-20 13:06:53 +00:00
Jing Tong
daea4e7934 mb/google/brox/var/lotso: enable CNVi bluetooth
Lotso's WIFI_BT is same design as brox, copy from brox.

BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on

Change-Id: I030e306dc5d9d3fcb6314bc491dbf5c9ae60bcb7
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83126
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2024-06-20 06:56:22 +00:00
Felix Singer
37c8c85b30 documentation: Fix evaluation of reStructuredText
eval_rst isn't a valid directive. Use eval-rst instead. Also, add curly
braces where necessary since the MyST parser requires them.

Change-Id: I68337354e9bd4de4b2c29d4e42c3bb22337fbe06
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-06-19 17:43:06 +00:00
Martin Roth
1eccf77a78 util: Break up spdx identifier text in scripts & makefiles
The SPDX parsers can find the SPDX identifiers in the scripts and
makefiles if they aren't broken up. This unnecessarily confuses things
when we're doing license parsing.

Change-Id: I215ed047397f342c912f1a969315fa184a124f6a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2024-06-19 17:42:43 +00:00
Jian Tong
3fc7a8f507 mb/google/brox/var/lotso: Update devicetree setting
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings.

BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on

Change-Id: Ic9a7a9062f5c6e45c5bd9617f3b2a0634b8dc1db
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83051
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-19 03:15:17 +00:00
Jing Tong
466bbc2b6d mb/google/brox/var/lotso: Update verb table from ALC256 to ALC257
Update verb table provided by Realtek on 20240614.

BUG=b:344471736
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC257
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek

Headphone detection:
Event: time 1718633617.056092, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1718633621.471708, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: time 1718633623.898046, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1718633625.743663, type 1 (EV_KEY), code 115
(KEY_VOLUMEUP), value 1
Event: time 1718633625.743678, type 1 (EV_KEY), code 115
(KEY_VOLUMEUP), value 0

Change-Id: Idde8963de9302849f87b7c262f17d9c9d99b46dc
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83109
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-19 03:15:02 +00:00
David Wu
c295d01451 mb/google/nissa/var/riven: Disable unused GPIOs based on fw_config
Disable LTE, stylus and WFC related GPIOs based on fw_config.

BUG=b:337169542
TEST=Local build successfully.

Change-Id: I91adc4e70d0d23b737d4fa6725cd96e63108f874
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18 22:03:18 +00:00
Roger Wang
9abc91cc45 mb/google/nissa/var/sundance: disable pcie port7
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.

BUG=b:328147465
TEST=Build and check S0ix function and verify FAFT sleep funciton.

Change-Id: I53f704ed11a5c63b5c079c6e60ce2fa32bbd8b1a
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-18 21:52:54 +00:00
Roger Wang
2b8367ed4b mb/google/nissa/var/pujjoga: disable pcie port7
Disable pcie port7 to prevent s0ix issue when run the FAFT sleep test.

BUG=b:335312655
TEST=Build and check S0ix function and verify FAFT sleep funciton.

Change-Id: I7918e26fe382d4d9992a0e2744a2f8894a070e36
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2024-06-18 21:52:40 +00:00
Sumeet Pawnikar
f3c6261931 MAINTAINERS: Add Intel DPTF section with Sumeet Pawnikar as maintainer
I am the one who takes care of end to end DPTF (Thermal Management)
related coreboot things across various X86 based platforms.

Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I08a1ae48bd5b66ee2f7903615e64d0bab5e0d7d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-18 19:36:53 +00:00
Roger Wang
e6d2b8a775 mb/google/nissa/var/pujjoga: Update DPTF parameters
Adjust settings as recommended by thermal team.

Update DPTF parameters based on b:346930334

BUG=b:346930334

TEST= built bootleg and verified test result by thermal team

Change-Id: I363eaa72b5190212b014fe4e2c2fca10e2a3f408
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83079
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18 13:09:19 +00:00
Roger Wang
1985cac30b mb/google/nissa/var/sundance: Update DPTF parameters
Adjust settings as recommended by thermal team.

Update DPTF parameters based on b:346932306

BUG=b:346932306

TEST= built bootleg and verified test result by thermal team

Change-Id: I6a529365249a5372dd87ef28cb9ea8d540b9cac0
Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83078
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2024-06-18 13:08:40 +00:00
Anand Vaikar
6e8d0122eb soc/amd/cezanne: Add AMD Renoir SOC support
Add AMD SOC Family 17h Renoir CPUIDs per PPR doc #55922

Renoir is similar to Cezanne with only differences in CCX count.
Cezanne has one Zen3 CCX with 8 cores per CCX compared to
the two Zen2 CCX with 4 cores per CCX. Hence, coreboot side
Cezanne SOC code should be mostly compatible with Renoir and
can be leveraged.

Change-Id: I6b43eb782527351c79b835d094a5b61103cd6642
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83099
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-18 13:08:00 +00:00
Subrata Banik
3d523c4cd8 cpu/x86: Rename paging structure variables for clarity
The following variables have been renamed:

* PDPE_table -> PDPT (Page Directory Pointer Table)
* PDE_tables -> PDT (Page Directory Table)

This change improves the consistency and clarity of the code
as per AMD Architecture Programmer's Manual document.

PML4 -> PDPT -> PDT -> 2MB Physical Page

TEST=Able to build and boot google/rex64.

Change-Id: Ib57d1d54c2c1f4fcce2315b508ed7643251a20c5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-18 08:25:24 +00:00
Subrata Banik
04fd591b08 cpu/x86: Rename PDE_table to PDPT for 1 GiB page mappings
This commit fixes an incorrect variable name in the page table setup
for 1 GiB pages.

The label PDE_table was used when it should have been PDPT, as it
represents a "Page Directory Pointer Table (PDPT)", not a "Page
Directory Table (PDT) or PDE_Table".

This change ensures correct nomenclature and consistency in the code.

PML4 -> PDPT --------> 1GB Physical Page

As per x86-64 specification, 1GB pages bypass the Page Directory Table
(PDT) level of the page table hierarchy, mapping directly from the
Page Directory Pointer (PDPT) Table to the physical page.

Change-Id: I1e1064653a265215054f31f0e4e46bf8200ca471
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83100
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2024-06-18 08:25:17 +00:00
Matt DeVillier
5acdfa23fd Revert "mb/google/brox/var/lotso: enable CNVi bluetooth"
This reverts commit 0e0bc618e3.

Reason for revert: Merged out of order, breaks tree

Change-Id: I22bd85a2008db471177257a8b779c06898b1010c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83105
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-06-17 16:05:54 +00:00
Fabian Meyer
92e372bb35 util/intelp2m: Add support for Emmitsburg macro generation
Test: Generated GPIO for ASRock Rack SPC741D8-2L2T/BCM.

Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797
Signed-off-by: Fabian Meyer <fabian.meyer@student.kit.edu>
Co-authored-by: Yussuf Khalil <yussuf.khalil@kit.edu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-06-17 14:30:28 +00:00
David Wu
2fb6eec811 mb/google/nissa/var/riven: Disable storage devices based on fw_config
Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this (it
disables all probed devices when fw_config is unprovisioned).

BUG=b:337169542
TEST=Local build successfully.

Change-Id: I3d71a35e9c0a33b72720b093b5a05eb69d5bb9f8
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83060
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-17 14:29:40 +00:00
David Wu
56d116f449 mb/google/nissa/var/riven: Add initial override devicetree
Add initial override devicetree for riven based on
the latest schematic (Riven(ZDK)_MB_Proto_0601.pdf).

1. Add eMMC DLL tuning value (copy from craask)
2. Configure I2C frequency (copy from craask)
3. Add audio codec and speaker amp settings
4. Add Elan touchscreen settings (copy from craask)
5. Add WFC and usb settings (copy from craask)
6  Add Elan and Synaptics touchpad settings (copy from craask)
7. Add WIFI6(CNVI) and WIFI7(PCIE) configuration
8. Add LTE settings (copy from craask)

BUG=b:337169542
TEST=Local build successfully.

Change-Id: I1dda3557edb44dda9c3a1efaf98437352978561c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83059
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17 14:29:11 +00:00
Angel Pons
d15a49b069 util/autoport: Factor out yes/no prompt handling
In preparation for introducing other yes/no prompts, factor out the
logic into a common function.

Change-Id: Iff1f0c6c665a5352013122fb791121a116c434f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-17 14:28:28 +00:00
Felix Held
9060994014 vc/amd/opensil/*/opensil.h: add missing device/device.h include
device/device.h provides the definition of struct device.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id1c3c09665e3eedec6055f4a0586016c5a5537bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83083
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17 14:27:30 +00:00
Angela Czubak
c5755810df mb/google/drallion: Set touchpad IRQs as wake source
Elan touchpad driver in newer linux kernels (>= 5.15) no longer
explicitly configures the touchpad as a wakeup source for devices
not using device tree. It is now assumed this information should be
extracted from ACPI, therefore we need to update drallion's devicetree
so that the device regains its lost capability.

TEST=update drallion FW and verify touchpad can cause wake up from
     suspend

Change-Id: Iff21afda144cc11a013cb72816064df1c9eb21ae
Signed-off-by: Angela Czubak <aczubak@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83070
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17 14:27:19 +00:00
CoolStar
a48a3f3ef3 ec/google/chromeec/acpi/cros_ec: Ensure GpioInt and _PRW are mutually exclusive
Under Windows ACPI, GpioInt and _PRW must be mututally exclusive within
the scope of a device, otherwise a BSOD occurs with an ACPI_BIOS_ERROR.
To enforce this, only use _PRW when EC_ENABLE_SYNC_IRQ_GPIO is not set.
If both EC_ENABLE_WAKE_PIN and EC_ENABLE_SYNC_IRQ_GPIO are set, then
ensure that the GpioInt is flagged as ExclusiveAndWake (vs just
Exclusive) so that the CREC device is still able to wake the device
as needed.

TEST=Build/boot google/{nocturne,frostflow} to Win11 w/ sync_irq_gpio
and wake_pin both enabled.

Change-Id: Ia59cce2ee12bfc8d3ac0173a7a4ec88d7079a958
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82233
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17 14:26:13 +00:00
Matt DeVillier
c98ef0dd25 mb/google/brya/base/nissa: Add default GMA panel
Enables ACPI brightness controls to be generated, and display
brightness controls to be functional under Windows.

TEST=build/boot Win11 on google/brya (craaskin), verify display
brightness controls present and functional.

Change-Id: I821b912cf52b5b89c5c9d831a5a15566b1b31639
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17 14:25:40 +00:00
Matt DeVillier
5f15771616 mb/google/brya: Add default ACPI brightness levels
Boards using the brya baseboard already generate ACPI brightness
controls via their use of the gfx/generic driver, but need the
default brightness steps in order for display brightness control
to be functional under Windows.

TEST= build/boot Windows 11 on banshee, verify brightness controls
functional.

Change-Id: I03bb7a7309476839c49d2e862a036d9e89800605
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70372
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-17 14:25:24 +00:00
Jian Tong
0e0bc618e3 mb/google/brox/var/lotso: enable CNVi bluetooth
Lotso's WIFI_BT is same design as brox, copy from brox.

BUG=b:339612353
TEST=emerge-brox coreboot chromeos-bootimage and boot on

Change-Id: I3946297db7f10a31570f773bdc5665f9f472c9fe
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83053
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-06-17 12:02:12 +00:00
Amanda Huang
ad68d05324 mb/google/trulo/var/orisa: Configure GPIO settings
Configure GPIOs according to schematic_20240607.

BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot

Change-Id: I760a7a234df43db3a557b3be9e20ff7aa5f80b72
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17 06:39:53 +00:00
David Wu
de366a5252 mb/google/nissa/var/riven: Use unified AP FW for UFS/Non-UFS SKUs
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS which intends to achieve a unified AP firmware image across UFS and non-UFS skus.

BUG=b:328580882
TEST=Local build successfully.

Change-Id: Ifcee68a3492ab4606819de0be41701f803151f66
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83061
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2024-06-17 06:34:28 +00:00
Felix Singer
a03fc30baa mb/hp/snb_ivb_laptops/8560w: Move genx_dec settings into LPC scope
Change-Id: I3cb0a39c83d6c92d604f1190538db88d97a81693
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-06-17 02:28:44 +00:00
Felix Singer
24ea4daf8f mb/hp/snb_ivb_laptops/8560w: Make use of device alias names in dt
Also, remove superfluous comments from devices which repeat their name.

Change-Id: I26f7d5155f73bcf3cb3872f206c946da5029bda8
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-06-16 17:26:41 +00:00
Nicholas Chin
090f352c2c console: Only add non-stub code to romstage if SEPARATE_ROMSTAGE=y
If both CONFIG_SEPARATE_ROMSTAGE and CONFIG_BOOTBLOCK_CONSOLE are not
set, compilation will fail with errors indicating redefinitions of
various console methods.

When BOOTBLOCK_CONSOLE is not set, the __CONSOLE_ENABLE__ macro in
include/console/console.h evaluates to zero when compiling the
bootblock, resulting in various console methods being defined as stubs
in the header. In a typical build with a separate bootblock and
romstage, this will not cause a conflict as the non-stub definitions
found in the console/*.c files are added conditionally to the bootblock
depending on CONFIG_BOOTBLOCK_CONSOLE.

When SEPARATE_ROMSTAGE is not set, the list of romstage objects gets
added to the bootblock. Since the console sources were unconditionally
added to romstage, the non-stub definitions were able to slip into the
bootblock, causing a redefinition of the stubs.

Avoid this by conditionally adding these sources to romstage depending
on CONFIG_SEPARATE_ROMSTAGE. If SEPARATE_ROMSTAGE is set, the non-stub
definitions are handled in the same way as they were before. If it is
not set, the union of bootblock and romstage objects will only include
the non-stub definitions based on CONFIG_BOOTBLOCK_CONSOLE, which uses
existing console/Makefile.mk rules for the bootblock.

TEST=qemu-i440fx builds successfully with all possible settings of
CONFIG_SEPARATE_ROMSTAGE and CONFIG_BOOTBLOCK_CONSOLE.

Change-Id: I59b3f0c52a4338b1573e0a647bc16cec4943fd7f
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83088
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-06-16 13:47:11 +00:00
Benjamin Doron
32bf60ee5c soc/intel/alderlake: Use the RPL-P IoT FSP if desired
This change also drops a duplicated config default line, which might be
why this was omitted.

Change-Id: I2b4c8b316adaadec3e49d5162b37b37629331b06
Signed-off-by: Benjamin Doron <benjamin.doron@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83086
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16 13:45:20 +00:00
Felix Singer
4cd9056e32 mb/gigabyte/ga-b75m-d3h: Make use of device alias names in dt
Also, remove superfluous comments from devices which repeat their name.

Change-Id: Ia4a9a5c5897fe78a1243e4c42a7d8753cfe039c0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-06-16 13:43:44 +00:00
Felix Singer
b4e8ccee93 mb/gigabyte/ga-b75m-d3h: Remove superfluous comments from dt
Change-Id: I20aca1a63306b0f39f97fd0b85d61cd957cb2150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83094
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16 13:43:32 +00:00
Felix Singer
70b411c44d mb/gigabyte/ga-h61m-series: Make use of device alias names in dt
Also, remove superfluous comments from devices which repeat their name.

Change-Id: I00473e44fce9197f818f5a8d131e9be31e8b0f69
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16 13:43:19 +00:00
Felix Singer
080f0bace1 mb/gigabyte/ga-h61m-series: Remove superfluous comments from dt
Change-Id: I6026498c2853f5951227ace57b7198579f342647
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83092
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16 13:43:08 +00:00
Nicholas Chin
c862608847 mb/dell/snb_ivb_latitude: Move E6430 USB config to devicetree
As of commit ee12634872 (nb/sandybridge,sb/bd82x6x: Configure USB from
southbridge devicetree) and earlier commits, the USB port configuration
should be located in the devicetree instead of the mainboard_usb_ports
array, typically located in the boards early_init.c.

TEST=USB ports still function; and the USBIRx, USBPDO, USBOCM1, and
USBOCM2 RCBA registers in the inteltool dump did not change between
an E6430 build before and after the sb/intel/bd82x6x that moved the
usb config to the devicetree.

Change-Id: Ia5aa03a5894a8ef29e863470925a223f52e0ab70
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83006
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-16 13:42:45 +00:00
Martin Roth
bbac6b9f8a .gitmodules: Use https to fetch modules
Instead of using a relative path for the submodules, specify the sub-
module URLs as pointing at coreboot.org, using https.

While the relative path works well for coreboot itself, when the repo
is forked and fetched from from anywhere other than review.coreboot.org,
this file either needs to be modified, or all the submodules need to be
checked out as well.

Change-Id: Ie4f95c70a7f194d1073dc561c9f33dcc108060cc
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2024-06-15 11:48:04 +00:00
Iru Cai
56ed345b5e mb/hp: Add Elitebook 8560w as an HP Sandy/Ivy Bridge laptop variant
The components listed in the documentation work in this port.
The MXM structure of the vendor firmware is added, which is
used by the VGA option ROM with int15h functions.

Change-Id: I15181792b1efa45a2a94d78e43c6257da1acf950
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-15 08:35:27 +00:00
Angel Pons
cb125d6f94 util/inteltool: Add more Westmere/Ironlake device IDs
The host bridge PCI device ID can be changed by the firmware. There
is no documentation about it, though. There's 'official' IDs, which
appear in spec updates and Windows drivers, and 'mysterious' IDs,
which Intel doesn't want OSes to know about and thus are not listed.

For the sake of completeness, add the PCI device IDs for Clarkdale.
Though coreboot only supports Arrandale, both of them are Ironlake.

It is possible that the Management Engine handles changing the PCI
device ID, which would not happen when using a broken ME firmware.

Change-Id: I85a48fcf0e0e62f42fe147a5d4e2d557b2143e5b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2024-06-14 15:41:26 +00:00
Sergii Dmytruk
d20cc994ba util/smmstoretool: add uint64 data type
It's in particular useful for working with variables that contain 64-bit
pointers, like CapsuleUpdateData* global variables defined by UEFI
specification.

Change-Id: I4b46b41cdc5f69d4ca189659bef1e44f64c0d554
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2024-06-14 14:19:46 +00:00
Sergii Dmytruk
dd6c3b4a61 util/smmstoretool: fix uint{16,32} not being listed by help
These data types were added during review of CB:79080 but they weren't
added to the help message.

Change-Id: I6e79d65c80c292c3f5d2a2611e602db5cc6cf374
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82610
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
2024-06-14 14:18:58 +00:00
Jincheng Li
d6c58b79e7 soc/intel/common/block: Move VTd basic definitions into header file
TEST=Build and boot on intel/archercity CRB

Change-Id: I4f9e606cf9ec01ec157ef4dd7c26f6b5eb88c7b7
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-14 13:57:03 +00:00
Seunghwan Kim
99a190105f mb/google/brya/var/xol: Turn off camera power during s0ix
Turn off camera power during s0ix to improve power consumption.

BUG=None
BRANCH=brya
TEST=built and verified GPP_A17 went to low during s0ix with a scope.

[Measurement of s0ix power consumption - 1 hour avg]
 Before this: 301.4 mW
 After this: 299.8 mW

Change-Id: Iae02d06e9f5a5988563b2b7ae36d153aecedb9d7
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83029
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2024-06-14 12:36:00 +00:00
Alper Nebi Yasak
08d7d31384 mainboard/qemu-riscv: Get top of memory from device-tree blob
Trying to probe RAM space to figure out top of memory causes an
exception on RISC-V virtual machines with recent versions of QEMU, but
we temporarily enable exception handlers for that and use it to help
detect if a RAM address is usable or not. However, QEMU docs recommend
reading device information from the device-tree blob it provides us at
the start of RAM.

A previous commit adds a library function to parse device-tree blob that
QEMU provides us. Use it to determine top of memory in RISC-V QEMU
virtual machines, but still fall back to the RAM probing approach as a
last-ditch effort.

Change-Id: I9e4a95f49ad373675939329eef40d7423a4132ab
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2024-06-14 12:35:22 +00:00
Jett Rink
d41ad724cd tpm: Add Ti50 OpenTitan DID_VID
The OpenTitan HW implements the same firmware interface as the Ti50
H1D3C hardware variant; it just has a different DID_VID. Allow this new
DID_VID to be recognized correctly.

BUG=b:324940153

Change-Id: Iaacf6d88bc6067948756c465aac1cd8b24ecae1f
Signed-off-by: Jett Rink <jettrink@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83033
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-06-14 12:33:31 +00:00
Werner Zeh
ce9562f662 Documentation/index.md: Add coreboot's blob policy
Every now and then we have discussions about blobs and how and if they
should be introduced or handled. This patch adds a clear statement on
the project's view on this topic to avoid unclear situations in the
future.

Change-Id: I20bc0b345c129ecd59aa1190647d89f6d4e07d46
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2024-06-14 08:57:13 +00:00
Subrata Banik
21c9390d97 soc/intel/adl: Skip RW CBFS ucode update if RO is locked
This patch eliminates coreboot from loading microcode from RW CBFS
(when the RO descriptor is locked, which indicates a fixed RO image)
because the kernel can already patch the microcode on BSPs and APs
while booting to OS.

This may be a chance to lower the burden on the AP FW side because
patching microcode on in-field devices is subject to firmware updates,
which are rarely published and, if required, must go through the
firmware qualification testing procedure (which is costly, unlike
kernel updates for ucode updates).

1. The FIT loads the necessary microcode from the RO during reset.
2. Reloading microcode from RW CBFS impacts boot time
   (~60ms, core-dependent).
3. The kernel can still load microcode updates.

ChromeOS devices leverage RO+RW-A/RW-B booting. The RO's microcode is
sufficient for initial boot, and the kernel can apply updates later.

BUG=none
TEST=Verified boot optimization; in-field devices skip RW-CBFS microcode
loading when RO is locked.

Change-Id: I68953d45d3624aba0a3be28bc7b266b7621ddcc4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82999
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13 14:30:31 +00:00
Matt DeVillier
4f0b2e04bc soc/intel/apollolake: Add SoC-specific microcode update check for GLK
While both APL and GLK load the CPU microcode from FIT, only GLK
supports the PRMRR/SGX feature. When this feature is supported, the
FIT microcode load will set the msr (0x08b) with the patch id/revision
one less than the revision in the microcode binary. This results in
coreboot attempting (and failing) to reload the microcode again in
ramstage. Avoid the microcode reload attempt for GLK by using a SoC-
specific microcode update check which accounts for the off-by-1 when
comparing versions.

Implementation is based on the one used for SKL and CNL, but modified
based on feedback in comments on Gerrit.

TEST=build/boot google/reef (electro) and google/octopus (ampton),
verify in cbmem console log that CPU microcode update in ramstage is
skipped due to already being up to date, and that GLK uses the
SoC-specific check and APL uses the non-specific/general one.

Change-Id: Iab97f23d4388d5057797bb13f585db821c735bd0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83037
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-06-13 11:47:48 +00:00