Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Handle older CrOS firmware which lacks a COREBOOT FMAP region
- Add support for all blobs used in CrOS firmware 2013 to current
- Put extracted blobs in their own directory
Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Without acpi name, acpi_device_path will return NULL.
<NULL>: Intel USB4 Retimer at GENERIC: 0.0
Replace with usb4_retimer_scope for the identify.
BUG=b:215742472
TEST=show below meaasge in coreboot log
\_SB.PCI0.TMD0.HR : Intel USB4 Retimer at GENERIC: 0.0
\_SB.PCI0.TMD1.HR : Intel USB4 Retimer at GENERIC: 0.0
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idfa8b204894409b11936e5f221c218daa206cc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility.
Test on the StarBook Mk IV running coreboot 4.15 with:
* Ubuntu 20.04
* Ubuntu 21.10
* MX Linux 21
* elementary OS 6
* Manjaro 21
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I491922bf55ed87c2339897099634a38f8d055876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When using the default initial core display clock frequency, Metaknight
has a rare stability issue where the startup of Chrome OS in secure mode
may hang. Slowing the initial core display clock frequency down to
172.8 MHz as per Intel recommendation avoids this problem.
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for metaknight.
BUG=None
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Commit b67c5ed [3rdparty/fsp: Update submodule pointer to newest master]
updated the FSP binaries/headers for Comet Lake, which included a change
moving PcieRpHotPlug from FSP-S to FSP-M. Unfortunately the existing
UDP in FSP-S was left in and deprecated, which allowed the change to go
unnoticed until it was discovered that hotplug wasn't working.
Since other related platforms (WHL, CFL) share the SoC code but use
different FSP packages, add the setting of the PcieRpHotPlug UPD to
romstage/FSP-M and guard it with '#if CONFIG(SOC_INTEL_COMETLAKE)'.
Test: build/boot Purism Librem 14, verify WiFi killswitch operates
as expected / WiFi is re-enabled when turning switch to on position.
Change-Id: I4e1c2ea909933ab21921e63ddeb31cefe1ceef13
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch extends `struct pad_config` to add new variable for gpio
lock action.
Additionally, it creates new GPIO PAD configuration macros that perform
GPIO pad configuration and pad lock configuration as well.
List of new macros are:
1. PAD_CFG_NF_LOCK
2. PAD_CFG_GPO_LOCK
3. PAD_CFG_GPI_LOCK
4. PAD_CFG_GPI_TRIG_OWN_LOCK
5. PAD_CFG_GPI_GPIO_DRIVER_LOCK
6. PAD_CFG_GPI_INT_LOCK
7. PAD_CFG_GPI_APIC_LOCK
8. PAD_CFG_GPI_IRQ_WAKE_LOCK
Mainboard users can use the above macros to lock the PAD after
configuration.
So far on IA chipset, the default GPIO pad lock configuration reset
type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603)
to configure the GPP PAD reset type the same as lock configuration
reset type to avoid GPP reset value misconfiguration issue.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch performs GPIO PAD lock configuration in non-smm mode.
Typically, coreboot enables SMI at latest boot phase post FSP-S,
hence, FSP-S might get chance to perform GPP lock configuration.
With this code changes, coreboot is able to perform GPIO PAD
lock configuration early in the boot flow, prior to calling FSP-S.
Also, this patch ensures to have two possible options as per GPIO
BWG to lock the GPIO PAD configuration.
1. Using SBI message with opcode 0x13
2. Using Private Configuration Register (PCR)
BUG=b:211573253, b:211950520
TEST=Able to build and boot brya variant with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For one specific type of APU, it doesn't have HDMI. When we detect
this APU, we need to explicitly disable HDMI in DDI settings,
otherwise the system would freeze.
get_cpu_count() == 4 && get_threads_per_core() == 2: This case is for
2 Core and 4 Thread CPU (2C/4T for short).
get_cpu_count() == 2: This is for 2C/2T. This is for a possible future case.
BUG=b:208677293
Change-Id: I8d0fa96818a768b7960d92821b927dbc622675ae
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
There is no wakeup source when we test function of suspend and resume.
The root cause is that the monitor enable bit of PWRAP is not configured
correctly.
BUG=b:213255218, b:214978483
TEST=receive wakeup source from MT6366 successfully
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit bd9b044a96 ("mb/system76: rtd3: Remove SrcClk pin
on CPU RP").
Previously, RTD3 expected a PCH index for the root port and did not work
with the CPU PCIe RP present on TGL, so SrcClk pin was disabled.
Set them now that RTD3 supports mapping the index for the CPU RP.
Change-Id: Ia7519b9f5a2be52cd5575615c28d20371a26996b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
