Angel Pons
c7cfe0ba54
soc/intel: Refactor xdci_can_enable() function
...
The same pattern appears on all `xdci_can_enable()` call sites. Move the
logic inside the function and take the xDCI devfn as parameter.
Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-07-01 12:14:02 +00:00
Angel Pons
8e035e3c13
src: Move select ARCH_X86 to platforms
...
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware,
have platforms select `ARCH_X86` directly instead of through per-stage
Kconfig options, effectively reversing the dependency order.
Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Patrick Rudolph <siro@das-labor.org >
2021-06-30 04:48:59 +00:00
Angel Pons
9bf9adae13
soc/intel/skylake: Use devfn_disable() to handle XDCI
...
Done for consistency with other Intel SoCs. This allows moving the
pattern inside a helper function.
Change-Id: If95c4b6c1602e56436150a931210692f14630694
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55787
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-06-25 04:22:42 +00:00
Angel Pons
7ff3f31cd1
soc/intel/skylake: Use is_devfn_enabled()
...
Use the `is_devfn_enabled()` function for the sake of brevity.
Change-Id: Ic848767799e165200f26c2d5a58fbd3b72b9c240
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55786
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-06-25 04:21:56 +00:00
Kyösti Mälkki
41a2c73b06
cpu/x86: Default to PARALLEL_MP selected
...
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2021-06-07 21:02:54 +00:00
Arthur Heymans
6419cd3335
cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=y
...
This removes the need to include this code separately on each
platform.
Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Raul Rangel <rrangel@chromium.org >
2021-05-18 16:54:21 +00:00
Patrick Georgi
40b8f01697
src: Match array format in function declarations and definitions
...
gcc 11.1 complains when we're passing a type* into a function that was
declared to get a type[], even if the ABI has identical parameter
passing for both.
To prepare for newer compilers, adapt to this added constraint.
Change-Id: I5a1b3824a85a178431177620c4c0d5fddc993b4f
Signed-off-by: Patrick Georgi <pgeorgi@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-05-13 18:34:38 +00:00
Felix Singer
1f44efc202
soc/intel/skylake: Set proper defaults in chipset devicetree
...
LPC, P2SB and Power Management controller are always needed. Thus,
enable them by default.
Change-Id: I20b8cbe536da70fccc3d11e1eedf4a5e14bfc862
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-05-10 14:14:24 +00:00
Tim Wawrzynczak
b1623f23c0
soc/intel/*: Update data types for variables holding PCH_DEVFN_* macros
...
The usage of `pci_devfn_t` here is misleading, as these intentionally
store the `PCH_DEVFN_*` macros so they can be used across `smm` and
`ramstage` without requiring the device model. Update to `unsigned int`
instead, as `pci_devfn_t` implies the data is an MMCONF-compatible PCI
devfn offset.
Change-Id: Ic8880de984e6eceda4cbe141e118f3a5fdd672a2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52808
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-05-03 16:28:53 +00:00
Felix Singer
a32a57929b
soc/intel/skylake: Remove useless help texts
...
Remove useless help texts since they don't add any more value.
Change-Id: Iabcaec1bc8abe2c4628105752e49247e946fcfe7
Signed-off-by: Felix Singer <felixsinger@posteo.net >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52786
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-05-02 19:43:32 +00:00
Timofey Komarov
756f51b662
soc/intel/skylake: Add Kconfig option for LGA1151v2
...
Provide a SOC_INTEL_SKYLAKE_LGA1151_V2 option to select correct defaults
for the combination of a Union Point PCH with LGA1151v2.
As of the year 2021 it's common for motherboards with Z370, H310C
or B365 PCHs, which are meant to be paired with Coffee Lake CPUs.
Intel provides AmberLakeFspBinPkg to support this combination,
which implements Intel FSP External Architecture Specification v2.1.
Details:
1) Provide SOC_INTEL_SKYLAKE_LGA1151_V2 option that selects
PLATFORM_USES_FSP2_1, SOC_INTEL_COMMON_SKYLAKE_BASE and
SKYLAKE_SOC_PCH_H.
2) Add Amberlake FSP support.
If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, use AbmerLakeFspBinPkg instead
of KabylakeFspBinPkg.
3) Enable Coffee Lake CPUs support.
If SOC_INTEL_SKYLAKE_LGA1151_V2 is set, select
MAINBOARD_SUPPORTS_COFFEELAKE_CPU.
4) Increase stack and heap size in CAR.
If FSP_USES_CB_STACK is set (it's selected by PLATFORM_USES_FSP2_1),
update DCACHE_BSP_STACK_SIZE and FSP_TEMP_RAM_SIZE values.
5) Update maximal number of supported CPUs.
If MAINBOARD_SUPPORTS_COFFEELAKE_CPU is set, set MAX_CPUS to 16.
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru >
Change-Id: I7b6b9c676da55088cb5a12a218ea58d349ee440c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-05-01 18:03:18 +00:00
Timofey Komarov
7e7d27bf4b
soc/intel/skylake: Add microcodes for Coffee Lake CPUs
...
The Z370, H310C and B365 PCHs use the same silicon as 200-series
PCHs and they are supported by soc/intel/skylake codebase
(not by soc/intel/cannonlake). Mentioned PCHs are meant to be paired
with Coffee Lake CPUs, so add the corresponding microcodes.
Signed-off-by: Timofey Komarov <happycorsair@yandex.ru >
Change-Id: I479c648e40c4c607d29f8cdd913fdbd6d7d7d991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-05-01 18:02:59 +00:00
Angel Pons
49c20c00e4
soc/intel: Add Z370, H310C and B365 device IDs
...
Intel document 335192-004 contains the PCI device IDs for Z370 and
H310C, but lacks the ID for B365. The ID appears on some websites:
https://linux-hardware.org/index.php?id=pci:8086-a2cc-1849-a2cc
Change-Id: Iea3c435713c46854c5271fbc266f47ba4573db52
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52703
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-04-28 14:14:46 +00:00
Angel Pons
b45a769939
soc/intel: Add Kaby Lake PCH-U base device ID
...
Taken from Intel document 334658-003 (7th Generation Intel Processor
Family I/O for U/Y Platforms and 8th Generation Intel Processor Family
I/O for U Quad Core Platforms, Datasheet - Volume 1 of 2).
Change-Id: I1d48c8868e1e5d453d599ecec835938ce09935d0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52702
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-04-28 14:14:35 +00:00
Angel Pons
9f7e08be61
soc/intel/skylake: Shorten report_platform PCH-H names
...
For brevity's sake, just print the PCH model.
Change-Id: Ib9e96683e3cb0b63a11344f3b5383292bff88e13
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52701
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-04-28 14:13:27 +00:00
Angel Pons
f530e363d1
soc/intel: Rename 200-series PCH device IDs
...
The code name for these PCHs is Union Point, abbreviated as `UPT`. There
are some 300-series Union Point PCHs (H310C, B365, Z370) which are meant
to be paired with Coffee Lake CPUs instead of Skylake or Kaby Lake CPUs,
and referring to them as `KBP` (Kaby Point, I guess) would be confusing.
Tested with BUILD_TIMELESS=1, HP 280 G2 remains identical.
Change-Id: I1a49115ae7ac37e76ce8d440910fb59926f34fac
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52700
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-04-28 14:13:20 +00:00
Angel Pons
0129393a6b
soc/intel/skylake: Drop Lewisburg PCHs from report_platform
...
These PCHs are used with Xeon-SP processors, which use different code.
Change-Id: I05f67cd57aa9f867e2fab88cd49e0384073a0b20
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52699
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Timofey Komarov <happycorsair@yandex.ru >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-04-28 14:11:28 +00:00
Michael Niewöhner
348f2a6370
soc/intel/skylake: set MSR LT_LOCK_MEMORY only when using native MP init
...
FSP takes care of setting the MSR LT_LOCK_MEMORY when SkipMpInit=0.
Thus, only set the lock when native MP init is used (SkipMpInit=1).
Change-Id: I2758e87c6370f3244416a3170cfafe6df757bb78
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-04-22 19:42:05 +00:00
Michael Niewöhner
6e64c1a4e0
soc/intel/common,skl: set MSR LT_LOCK_MEMORY once, not per thread
...
The MSR LT_LOCK_MEMORY is package-scoped, not thread-scoped. Only set it
once.
Tested on Acer ES1-572 by checking chipsec results.
Change-Id: If3d61fcbc9ab99b6c1b7b74881e6d9c6be04a498
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-04-22 19:41:29 +00:00
Angel Pons
505e383ccb
soc/intel: Move pmc_soc_set_afterg3_en() to pmutil.c
...
Commit 2c26108208th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-04-21 09:17:40 +00:00
Angel Pons
f643b63c4d
soc/intel/skylake: Move pmc_set_disb() to pmutil.c
...
To drop bad __SIMPLE_DEVICE__ usage and for consistency with newer
platforms, move pmc_set_disb() to pmutil.c and adapt it accordingly.
Change-Id: I1a137b5b3120c350a04273567b9cb18c9a42a543
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-04-21 09:17:17 +00:00
Angel Pons
e4844ce7c9
soc/intel/skylake: Move acpi_sci_irq() to acpi.c
...
Change-Id: I8bc170bd715e13d46fcedc0f796e2a99786791c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Frans Hendriks <fhendriks@eltan.com >
2021-04-21 09:17:01 +00:00
Angel Pons
8f3e1192df
soc/intel/skylake: Move SataTestMode to Kconfig
...
This option is not mainboard-specific, and should be user-visible.
Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
2021-04-20 09:19:20 +00:00
Julius Werner
62fa9f3cf9
intel: mma: Use new CBFS API
...
This patch changes the Intel MMA driver to use the new CBFS API.
Signed-off-by: Julius Werner <jwerner@chromium.org >
Change-Id: Icc11d0c2a9ec1bd7a1d6af362f849dac16375433
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Aaron Durbin <adurbin@chromium.org >
2021-04-14 01:03:33 +00:00
Angel Pons
00f53a8d9e
soc/intel/skylake: Drop unnecessary ignore_vtd option
...
It is zero for all mainboards. If one really wanted to ignore VT-d
support, a user-visible Kconfig option would be a better approach.
Change-Id: I320c10317f3fabee5443c16ebdf1ffd0e24193b8
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
2021-04-08 06:47:15 +00:00
Angel Pons
3993d38ae6
soc/intel: Hook up SOC_INTEL_DISABLE_IGD to InternalGfx UPD
...
Commit 0591348833d74cd60b8199157c1f4ath3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52100
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Felix Singer <felixsinger@posteo.net >
Reviewed-by: Nico Huber <nico.h@gmx.de >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-04-08 06:47:02 +00:00
Subrata Banik
2ccc0a4d9f
soc/intel: Rename and move MISCCFG_GPIO_PM_CONFIG_BITS definition to soc/gpio.h
...
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.
An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.
Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.
TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-27 04:23:12 +00:00
Angel Pons
f479c85227
soc/intel: Drop unused GPIO_NUM_GROUPS macro
...
This macro is unused and its value is often wrong. Drop it.
Change-Id: Id3cfaa4d2eef49eddc02833efbe14e0c5c816263
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51662
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-20 12:29:19 +00:00
Michael Niewöhner
405f229689
soc/intel/*: drop UART pad configuration from common code
...
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index.
Since all boards do pad setup on their own now, finally drop the pad
configuration from SoC common code.
Change-Id: Id03719eb8bd0414083148471ed05dea62a895126
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Lance Zhao
2021-03-12 08:48:03 +00:00
Angel Pons
d3a65deb25
soc/intel: Guard macro parameters in pm.h
...
Guard against unintended operator precedence and associativity issues.
Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:07:59 +00:00
Angel Pons
a4cd9117da
soc/intel: Factor out common smmrelocate.c
...
There are seven identical copies of the same file. One is enough.
Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:06:09 +00:00
Benjamin Doron
482d3a1f03
soc/intel/skylake: Always print ME FW SKU
...
State of ME firmware SKU is independent of power-down mitigation.
Change-Id: I014c1697213efaefcb0c2a193128a876ef905903
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-03 09:05:19 +00:00
Benjamin Doron
27af8da7cb
soc/intel/skylake: Enable compression on FSP-S
...
Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the
boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to
the boot time.
LZMA size:
fsps_lzma.bin 0xb0dc0 fsp 146578 LZMA (188416 decompressed)
LZMA decompression time:
15:starting LZMA decompress (ignore for x86) 388,716 (47,646)
16:finished LZMA decompress (ignore for x86) 406,167 (17,450)
LZ4 size:
fsps_lz4.bin 0x242dc0 fsp 147442 LZ4 (188416 decompressed)
LZ4 decompression time:
17:starting LZ4 decompress (ignore for x86) 384,736 (47,864)
18:finished LZ4 decompress (ignore for x86) 384,796 (59)
Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2021-03-03 09:04:48 +00:00
Angel Pons
6d9af0ce6e
soc/intel: Backport SMRR locking support
...
Backport commit 0cded1f116th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-03-03 09:00:32 +00:00
Angel Pons
4778590d15
soc/intel/skylake: Move gspi_early_bar_init() call
...
For consistency with newer platforms, do this in pch.c instead.
Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-03-01 19:43:22 +00:00
Angel Pons
5d98dabb4e
soc/intel: Drop bootblock_cpu_init() function
...
Just call `fast_spi_cache_bios_region()` directly instead.
Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:43:04 +00:00
Angel Pons
68fe2aa204
soc/intel/{skl,cnl}: Do not chain-include systemagent.h
...
Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:42:26 +00:00
Angel Pons
ec953face1
skylake,fsp1_1: Delete dead report_memory_config() function
...
RAM is not yet configured in bootblock. This function was copy-pasted
from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in
there can be removed as nothing else uses them.
Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:42:07 +00:00
Angel Pons
3157068bf8
soc/intel/skylake: Extract fsp_params.c out of romstage.c
...
Done for consistency with newer platforms. Also clean up includes.
Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:41:27 +00:00
Angel Pons
53496e69ec
soc/intel: Drop romstage_pch_init() function
...
It only calls `smbus_common_init()`, so just call that directly.
Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:41:17 +00:00
Angel Pons
ec1b37decc
soc/intel/{skl,icl}: Move tco_configure() to bootblock
...
Backport commit 03ed5bff5cbb50c6722760c619f6a3th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:40:57 +00:00
Angel Pons
423c9faf63
soc/intel/skylake: Drop unused function prototypes
...
Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:39:59 +00:00
Angel Pons
e178df27dd
soc/intel: Factor out common smbus.h
...
Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:39:27 +00:00
Angel Pons
19af7bc822
soc/intel/skylake: Correct SMBUS_SLAVE_ADDR definition
...
According to document 332691-003EN (SPT-H datasheet volume 2), the
hardware defaults to 0x44, which matches what newer platforms use.
Change-Id: I494587b0074ab3675c3e88676375f667e757cdf0
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50941
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:39:05 +00:00
Angel Pons
8a269deee6
soc/intel: Factor out common gpe.h
...
The definitions are identical across seven platforms. Unify them.
Change-Id: I32bbd0777f8ca9d0362d210b43e0ba8dd0c8d79b
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50940
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:38:40 +00:00
Angel Pons
6edbaa2d9f
soc/intel/skylake: Move soc_acpi_name()
...
Done for consistency with newer platforms.
Change-Id: I1250c4514e1512e748bfc65c3f9f9da4ff1ef78e
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50939
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:38:29 +00:00
Angel Pons
98f672a5ea
soc/intel: Factor out identical acpigen GPIO helpers
...
Change-Id: I27f198d403f6ba05ba72ae0652da224d4cbf323a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50938
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:37:56 +00:00
Angel Pons
6bd99f9ada
soc/intel/skylake: Clean up SD GPIO handling
...
This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:37:36 +00:00
Angel Pons
ba4cfb504c
soc/intel/skylake: Remove unused macro in cpu.h
...
Change-Id: I92c9c06c606215a4bd9b44b3b4b1f0acced8a252
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50962
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:37:21 +00:00
Angel Pons
09f06056eb
soc/intel: Include gfx.asl from northbridge
...
The iGPU is on the northbridge or system agent, not the southbridge.
Change-Id: Ic63a7ad532fd1faa8e90d44bf7269040fa901757
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-03-01 08:32:47 +00:00
