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c8c741d9f9e4d9a91ef5b86a10ece56f8cf98a70
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19 Commits

Author SHA1 Message Date
Pratik Prajapati
c8c741d9f9 soc/intel/cannonlake: Define Max PCIE Root Ports 
This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,

*** CID 1380036:  Control flow issues  (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
>>>     CID 1380036:  Control flow issues  (NO_EFFECT)
>>>     "i" is converted to an unsigned type because it's compared to an unsigned constant.
80      for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81              if (config->PcieRpEnable[i])
82                      mask |= (1 << i);

Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-09-01 19:20:58 +00:00
Nick Vaccaro
69b5cdb33c soc/intel/cannonlake: add gpio files to make 
Adds gpio.c to romstage and ramstage.
Adds select GENERIC_GPIO_LIB to CPU_SPECIFIC_OPTIONS.

Change-Id: I4931f6c6f089cc54ea168cf4a80d268d983a61de
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-09-01 17:26:56 +00:00
Lijian Zhao
d37ebddfd8 soc/intel/canonlake: Enable LPSS UART in 32bit PCI mode 
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.

Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-09-01 05:15:05 +00:00
Subrata Banik
b045d4cd7b soc/intel/{cannonlake,skylake}: Add active default value for UART_FOR_CONSOLE 
This patch to avoid build bot hang issue due to no
active default value for UART_FOR_CONSOLE kconfig
option.

Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21287
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-30 18:30:56 +00:00
Pratik Prajapati
9027e1ba2f soc/intel/cannonlake: Init UPD params based on config 
Initialize UPD params based upon config

Change-Id: Ib2ee58f8432a957ef389b40f717533e4cfe774b9
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21175
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-25 18:24:33 +00:00
Pratik Prajapati
01eda28bff soc/intel/cannonlake: Add cpu.c and MP init support 
Add initial MP init support. This boots up all CPUs.

Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21081
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-24 16:06:30 +00:00
Lijian Zhao
b3dfcb863c soc/intel/cannonlake: Enable common PMC code for CNL 
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.

Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-21 20:37:57 +00:00
Subrata Banik
ce4c9ec4f6 soc/intel/cannonlake: Add Kconfig option to select UART index 
Cannonlake SOC has two possible ways to make serial
console functional.

1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.

This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2

PCI based LPSS UART2 is by default enabled for Chrome Design.

Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-21 16:22:51 +00:00
Lijian Zhao
321111774c soc/intel/cannonlake: Add SPI flash controller driver 
Add SPI driver code for the SPI flash controller, including both
fast_spi and generic_spi.

Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.corp-partner.google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-17 21:50:58 +00:00
Lijian Zhao
8465a81e81 soc/intel/cannonlake: Add postcar stage support 
Initialize postcar frame once finish FSP memoryinit

This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534

Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-15 20:21:22 +00:00
Brandon Breitenstein
ae1548621a soc/cannonlake: Enable SMM code for Cannon Lake 
The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.

Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-08-11 16:04:42 +00:00
Lijian Zhao
dcf99b0445 soc/intel/cannonlake: Sort Kconfig for Cannonlake 
Look and feel update, sort the sequence in Kconfig.

Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-08-03 18:54:11 +00:00
Martin Roth
80358a1f47 Revert "soc/intel/cannonlake: Add postcar stage support" 
This reverts commit 399c022a8c.

This was merged too early.  I'll repost it.

Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-21 17:39:10 +00:00
Lijian Zhao
399c022a8c soc/intel/cannonlake: Add postcar stage support 
Initialize postcar frame once finish FSP memoryinit

Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-21 15:55:40 +00:00
Lijian Zhao
a77c68adf3 soc/intel/cannonlake: Make ramstage relocatable 
Relocate ramstage into CBMEM.

Change-Id: I0543d25d722c5872f4f139a98e5125a41cc40653
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-20 21:57:10 +00:00
Lijian Zhao
acfc149f7b soc/intel/cannonlake: Add microcode support 
Microcode needs to be loaded prior to FSP initialization.

Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2017-07-19 16:16:44 +00:00
Andrey Petrov
c854b49db9 soc/intel/cannonlake: Use common GPIO driver 
Change-Id: I0bbdd641244f0c7baaa2146dcfde6431bde387c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-18 19:16:56 +00:00
Andrey Petrov
3e2e0508c2 soc/intel/cannonlake: Add early CPU initialization 
Add basic CPU initialization for bootblock, as well as relevant headers.

Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-07-13 19:28:27 +00:00
Lijian Zhao
81096041b8 soc/intel/cannonlake: Add initial dummy directory 
Add Cannon Lake SoC boilerplate directory with:

 * SoC directory
 * Base Kconfig
 * Dummy cbmem.c

Change-Id: Ie28d8b56a1d1afcf1214ef734a08be6efcc8a931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2017-06-29 14:50:38 +00:00