sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
31,452 Commits 47 Branches 30 Tags
cc6809c8b1b5f726c8541b9c4bc33dcbe2536172
Commit Graph

25651 Commits

Author SHA1 Message Date
Patrick Georgi
cc6809c8b1 mb/google/octopus: disable fmap cache for all octopus devices 
Meep was just the first one to fail, but the others aren't any better.

Change-Id: I177c50cfe7593a5b2ad770ce1ab1191d2dff93d2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37163
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-25 09:16:04 +00:00
Arthur Heymans
21c9aa125c sb/intel/i82801ix: Update comment on default decoded IO ranges 
Now the comment matches what is programmed into LPC_EN.

Change-Id: Ia01cf4bd068a593fc91e9ac12d0adf42d4ee937b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36995
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-25 09:15:44 +00:00
Patrick Georgi
0bb83469ed Kconfig: comply to Linux 5.3's Kconfig language rules 
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.

Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
 2019-11-23 20:09:56 +00:00
Kyösti Mälkki
f3758b6738 AGESA,binaryPI: Move SCI enable outside table creation 
Preferably, coreboot tables creation is kept hardware-invariant.

Change-Id: I37810771090dd9b0377f9a72c7a17ef1564ccf68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36812
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-23 18:34:19 +00:00
Kyösti Mälkki
27cb3e0d31 soc/amd: Move SCI enable outside table creation 
Preferably, coreboot tables creation is kept hardware-invariant.

Change-Id: Id7f79fc959766813d60f847482567579a02db124
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
 2019-11-23 18:33:51 +00:00
Krystian Hebel
0df1cccc0a vendorcode/amd/pi/Makefile.inc: remove -fno-zero-initialized-in-bss 
This fixes issue that became visible after implementing post-CAR stage on
top of `340e4b80904f lib/cbmem_top: Add a common cbmem_top implementation`.
Compilation error was:

Forbidden global variables in romstage:
ffffff00 d top.2205

Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Change-Id: I088ac824f9b66387843ae5810fd2c75a8b16d9db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36976
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-23 17:20:06 +00:00
Peichao Wang
d0c52b72f3 mb/google/kahlee/treeya: Set touchpad hold time to 400ns 
According to SI team request, need to tune I2C bus 2 data
hold time more than 300ns

BUG=b:144736027
TEST=build firmware and measure I2C bus 2 data hold time

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Idc58a595c77eba8544f27682a284be6aac5dbe25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36945
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-23 10:55:17 +00:00
Patrick Georgi
540b2adb61 src/console: Bring back support for printf'ing 64bit ints 
commit f96d9051c2 (Remove MIPS Architecture) accidentally enabled
a MIPS special case to not support 64bit integers in printf for
all platforms.

This removes that MIPS-only special case entirely.

Change-Id: I5245bb32b45f9bd37bd012a7b15a64fba24a4cb7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-22 15:56:54 +00:00
Arthur Heymans
d5e7a6d9c5 sb/intel/ibexpeak: Decode more LPC IO ranges 
3b452e0 "nb/intel/nehalem: Move PCH init to sb/intel/ibexpeak"
introduced a regression where the GAME_L decode range was not set
up, which is used by the WACOM digitizer on the Thinkpad X201T.

Change-Id: Ie569d567a65010aa5372323f8610a1b8b5d2599d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36994
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 13:15:51 +00:00
Arthur Heymans
4debbe74ac cpu/intel/gen1/smmrelocate: Fix stale comment 
Change-Id: I91ed5f7cbcfa5c510bb8e74049ec860397d7dbba
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
 2019-11-22 10:48:29 +00:00
Arthur Heymans
1818733faa cpu/intel/smm: Drop em64t save state 
This save state is just plainly wrong in many regards and em64t100
should be used.

Checked with a model 0x17 core2 CPU.

Change-Id: I4d89691e87c91dd12b34a44b74849b18b4ac5369
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-22 10:48:11 +00:00
Felix Singer
7f8b0cd89c sb/i82801ix: Use macros instead of hard-coded IDs 
This patch replaces hard-coded PCI IDs with macros
from pci_ids.h and cleans up some code.

Change-Id: Ie6ea72ac49eb015ef5cbaa98ed2b3400072000b5
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36705
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 10:47:43 +00:00
Subrata Banik
94146009a1 soc/intel/icelake: Make CpuMpPpi implementation default for ICL 
TEST=Could able to build and boot ICL DE system

Change-Id: Icd71ec99f06434896c73cff5a52cd3a5ad6ce5f3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-22 10:44:39 +00:00
Johnny Lin
53509cf15a drivers/ipmi: Add IPMI get system GUID support 
Tested on OCP Mono Lake.

Change-Id: I541a23341ccce3d45239babb3f0a8a8c8542b226
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2019-11-22 10:43:42 +00:00
Nick Vaccaro
7aeeb9bf96 soc/intel/common/intelblocks: Define PAD_CFG0_MODE_NF7 
BUG=b:142961277
BRANCH=none
TEST=none

Change-Id: Ibe0991b2e0d13e07d65906201597f9021cfc7156
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2019-11-22 10:43:11 +00:00
Jacob Garber
06f2fcc0ff cpu/x86/smm: Use PRIxPTR to print uintptr_t 
Since 'base' is a uintptr_t, it needs the PRIxPTR format specifier. This
fixes a compilation error when targeting x86_64 or using Clang 9.0.0.

Change-Id: Ib806e2b3cbb255ef208b361744ac4547b8ba262f
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
 2019-11-22 10:42:46 +00:00
Arthur Heymans
eb2e0b56ee device/hypertransport: Drop unused code 
Change-Id: I6a8b176fa6f8832f6f7bb37118861d530fdefd5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37066
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 10:41:10 +00:00
Patrick Rudolph
07b402b3b9 mb/lenovo/t410: Fix I2C SPD address 
Use correct address for second DIMM.

Tested on Lenovo T410:
* Both DIMMs are found and are usable

Change-Id: I8bace47f04a0e185c2901695879d4d4e12d4ce6a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37105
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 10:40:13 +00:00
Shelley Chen
5a0edcbde1 mb/google/hatch/variant/kohaku: Config MEM_STRAP GPIOs 
Kohaku always used the default MEM_STRAPs in hatch baseboard.  Adding
explicit configuration for Kohaku in the event that MEM_STRAP is set
differently in the baseboard gpio file.

BUG=b:144895517
BRANCH=hatch
TEST=None
     ./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I8f7105b3925f17c1741660d84c83c5d15f398a8d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37106
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 10:40:01 +00:00
Morgan Jang
5015502414 src/drivers/ipmi: Implement BMC Get Self Test Result function 
According to IPMI SPEC, it is recommended that BIOS includes provisions
for checking and reporting on the basic health of BMC by executing
the Get Self Test Results command and checking the result.

TEST=Check the result in response data to confirm the BMC status is fine
or not.

Change-Id: I20349cec2e8e9420d177d725de2a5560d354fe47
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2019-11-22 10:39:05 +00:00
Matt DeVillier
45ecb0eba1 purism/librem_skl: add/use VBT file 
Add VBT file extracted from vendor (AMI) firmware,
use by default to ensure functional display after
resume from S3 when using libgfxinit.

Test: build/boot Librem 13v2/3/4,15v3/4 boards, verify
functional display after resume from S3 when using libgfxinit.

Change-Id: I6bc5dab60e3601d56dae4300efee255d7c58329d
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37068
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 10:37:36 +00:00
Peter Lemenkov
386d3418ef mb/lenovo/{x201,x60}/smihandler: Use mdelay instead of udelay for large values 
Change-Id: I7d20a850f8c2a1fcdee358c9e73d4c04eb3d7de8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37006
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 10:37:14 +00:00
Elyes HAOUAS
490eab46a8 arch/acpigen.h: Correct PARENT_PREFIX encoding value 
The encoding value for PARENT_PREFIX is 0x5e.
(ACPI specification version 6.3 page 1073)

Change-Id: Ibbacb8b445157b377772f09572f87f8300a278dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36652
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-22 09:09:11 +00:00
Kyösti Mälkki
f5c0d61296 intel/smm: Provide common smm_relocation_params 
Pull in all copies of smm_relocation_params structs defined
for intel platforms.

Pull in all the inlined MSR accessors to the header file.

Change-Id: I39c6cffee95433aea1a3c783b869eedfff094413
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-11-22 06:37:50 +00:00
Kyösti Mälkki
75396f67aa Makefiles: Remove -D__PRE_RAM__ 
All cases of testing for __PRE_RAM__ have been converted
to equivalent ENV_xxx definitions from <rules.h>.

Change-Id: Ib6cd598f17109cc1072818cebe4791f7410c3428
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-11-22 06:27:21 +00:00
Usha P
56715ec23f soc/intel/skylake: Refactor pch_early_init() code 
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.

TEST=Able to build and boot soraka.

Change-Id: Idf7b04edc3fce147f7857591ce7d5a0cd03f43fe
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
 2019-11-22 06:26:27 +00:00
Kyösti Mälkki
f8dc4bc022 arch/x86: Remove spinlocks inside CAR 
This was only used with amdfam10h-15h, where cache
coherency between nodes was supposed to be guaranteed
with this code. We could want a cleaner and more generic
approach for this, possibly utilising .data sections.

Change-Id: I00da5c2b0570c26f2e3bb464274485cc2c08c8f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-11-22 06:25:53 +00:00
Kyösti Mälkki
9bb16cd9c5 drivers/pc80/rtc: Remove CMOS spinlock 
This was only used with amdfam10h-15h, and only in romstage
while commentary elsewhere says concurrent CMOS and CBFS
access caused issues.

We would want a cleaner approach on this, if re-implemented.

Change-Id: I8512196cb55ff2b4542b1421a1bbae540450115a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-11-22 06:24:28 +00:00
Kyösti Mälkki
3382e53c64 cpu/amd/microcode: Remove microcode update routine 
This was only used with native amdfam10h-15h.

Change-Id: Id8e06b25c6ec716c07aee46fce10903c62b6d684
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-22 06:23:43 +00:00
Kyösti Mälkki
bd585fa89f device/pci: Reduce scope of dev_find_slot() 
We only keep it around because soc/intel debugging
still depends on it.

Change-Id: I3ea37c097bbcc3cf5c0574c7d727eae4f5bee307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
 2019-11-21 19:43:34 +00:00
Kyösti Mälkki
79ca4b55c5 arch/x86: Remove copy_and_run() 
Nothing but a wrapper for run_ramstage() with an ugly name.

Change-Id: Ie443a27cf18f829496ddadcc19c4ebec6a0b5a59
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
 2019-11-21 19:42:43 +00:00
Kyösti Mälkki
35a047c4e5 drivers/crb: Replace __RAMSTAGE_ guards 
Change-Id: Ie2e6cdddc1edb95c442a4240267fe1fd6a11d37e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36698
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-21 19:39:05 +00:00
Kyösti Mälkki
baa16e9c25 drivers/pc80/tpm: Replace __RAMSTAGE_ guards 
Change-Id: Ia6e161c3b4fc44292cdac692a2918c522680d60d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36631
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-21 19:38:17 +00:00
Arthur Heymans
de56a66e73 cpu/amd/fam10: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I3c69f158a5667783292161815f9ae61195b5e03b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36963
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-21 09:28:41 +00:00
Arthur Heymans
eef63607b8 cpu/x86/lapic/lapic_cpu_init.c: Drop unused guards 
Both model_2065x and model_206ax use the parallel mp init codepath.

Change-Id: I6440d413761361ee8b69d5c76b69409bd7528b5d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37065
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-21 09:27:16 +00:00
Elyes HAOUAS
181de282b5 Kconfig: Remove not found sources 
Change-Id: I3691a4162eecbd48321348e136f72b73da74e225
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37078
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-21 09:01:39 +00:00
Arthur Heymans
15c012181d drivers/intel/fsp1_0: Drop support 
No platform is using this.

Change-Id: I3ea6df4d9ce9043755f319f699adc189d754df1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-11-21 06:47:43 +00:00
Arthur Heymans
f67c81fc70 soc/intel/fsp_broadwell_de: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I8b6502b0894f9e2b8b1334871d7b6cde65cba7d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-11-21 06:43:29 +00:00
Arthur Heymans
433471244b mb/*/*: Remove BROADWELL_DE boards 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I3d9b6bb48bfd15c0182448f774e9af1e0c944fd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-11-21 06:42:31 +00:00
Arthur Heymans
d980211112 soc/intel/fsp_baytrail: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2019-11-21 06:41:09 +00:00
Arthur Heymans
eb5147027e mb/*/*: Drop FSP_BAYTRAIL support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
 2019-11-21 06:40:11 +00:00
Arthur Heymans
c2c634a089 nb/sb/cpu: Drop Intel Rangeley support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I41589118579988617677cf48af5401bc35b23e05
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2019-11-21 06:38:45 +00:00
Arthur Heymans
298619f6d9 mb/*/*: Drop Intel Rangeley mainboards 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
 2019-11-21 06:38:17 +00:00
Kyösti Mälkki
bc29bd0de6 device: Add back dummy HT_CHAIN_UNITID_BASE 
This should be defined by mainboard. Add a dummy
default to fix master while HyperTransport files
are still around referencing this.

Change-Id: I58188a200a2cad5fa20affee1844117ba71ac338
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37036
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-20 21:33:39 +00:00
Arthur Heymans
ffcac3eb50 nb/amd/fam10: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: If36ef0749dbb661f731fb04829bd7e2202ebb422
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-20 19:08:30 +00:00
Arthur Heymans
1ca978ee65 sb/nvidia/mcp55: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I7cd33316140f2cdc83949aa5db7e6f1565982543
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36973
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-20 19:06:28 +00:00
Arthur Heymans
185691eedb sb/nvidia/ck804: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I56cb6d0a04056b10af1e53afb697883329235c87
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36972
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-20 19:06:04 +00:00
Arthur Heymans
87bc755447 sb/broadcom/bcm21000: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I5e9250a7c7adb7dffd64422637ba760155d966d2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36971
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-20 19:05:43 +00:00
Arthur Heymans
4c9bbb9b34 sb/broadcom/bcm5785: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I2305e0d9de0d4b1768e171f4c65d07306e7c3801
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
 2019-11-20 19:05:23 +00:00
Arthur Heymans
fc20682f07 sb/amd/sr5650: Drop support 
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which platforms using this code lack.

Change-Id: I63551b9ad861fecb689036c9f26c3b0950a8b8e9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36969
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
 2019-11-20 19:04:02 +00:00