Expose a config option that allows disabling the FSP UPD which controls
Precision Time Measurement for a particular PCIe root port. Since this
is enabled by default the option is inverted to allow disabling for
a particular port while not affecting others.
BUG=b:160996445
TEST=boot on volteer with PTM disabled for the NVMe root port
Change-Id: Icb51b256eb581d942b2d30fcabfae52fa90e48d4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
The device acceptable latency field is only valid for 'endpoints',
but not for bridge devices. Set the maximum acceptable latency on
such devices to allow ASPM being enabled if supported on both sides.
Allows the PCIe link on bridge devices to go into L0s/L1.
This allows the package to enter a deeper sleep state when all links
are idle.
WARNING: This might cause issues on PCIe bridge devices that doesn't
properly support ASPM. In addition it might decrease performance.
Change-Id: I277efe0bd1448ee8bff633428aa729aeedf04e28
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
The virtual/generic device under TBT PCIe root ports has path type as
DEVICE_PATH_GENERIC. While scanning the pcie bus, the generic device
blocks its root ports configuration. This change adds device path type
check and enables ASPM for TBT root ports.
BUG=b:173207454
TEST=Built image and booted to kernel on Voxel board. Verified both of
the TBT Root ports 00:07.0 and 00:07.1 ASPM are enabled.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I82ffaeb5a8821d9034d8dae9d98d3b5953a9608b
Replace the two obsolete LPID implementations with the new PEPD device.
The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)
There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.
Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Add the _HID INT33A1 to PEPD to make Linux recognize it as "Intel Power
Engine" in the pmc core driver.
The _ADR gets dropped, because _HID and _ADR are mutually exclusive.
Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
The PEPD enum function returns a bitmask to announce supported/enabled
PEPD functions. Add a comment describing this bitmask and correct the
return value to announce function 1, 5 and 6 as supported.
Also add comments to the disabled functions 3 and 4.
Change-Id: Ib523a54f5ad695e79005aba422282e03f2bc4bed
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Windows does not comply with the Low Power Idle S0 specification and
crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does
not return at least one device constraint, even when function 1 is
announced as being not available by the enum function. Returning an
empty package does not work.
At least the following Windows versions were verified to be affected:
- Windows 8.1 x64, release 6.3.9600
- Windoes 10 x64, version 1809, build 17763.379
- Windows 10 x64, version 1903, build 18362.53
- Windows 10 x64, version 2004, build 19041.508
- Windows 10 x64, version 20H2 / 2009, build 19042.450
To make Windows work on S0ix-enabled boards, return a dummy constraint
package with a disabled dummy device.
Since the device constraints are only used for debugging low power
states in Linux and probably also in Windows, there shouldn't be any
negative effect to S0ix. Real device constraint entries could be added
at a later point, if needed.
Note: to fully prevent the BSOD mentioned above the LPIT table is
required on Windows, too. The patch for this is WIP, see CB:32350.
If you want to test this, you need to applie the whole ACPI patch
series including the hacky LPIT test implementation from CB:47242:
https://review.coreboot.org/q/topic:%22low_power_idle_fix%22
Test: no bluescreen anymore on Clevo L140CU on all Windows versions
listed above and S0ix gets detected in `powercfg -a`.
Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
PEPD function 2 is currently unused and disabled. Thus, drop the return
value, which matches the default return value.
Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
`ARG2` in the macro's names does not really provide any useful
information. Drop it and add `LPI` to clarify the relation to only
low-power idle states.
Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In
Device" and is the name Intel and vendors usually use, so let's comply.
Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Move the UUID to the condition, since there is no need to assign a name
when it is only used once. Also add a comment to make clear that the
functions inside that condition are only used by the Low Power Idle S0
functionality, while the PEPD in general can be present on boards
without S0ix capability, too. For details check CB:46469.
Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
PEPD will get included directly in the southbridge. Thus, drop the
scope around it.
Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
The various platform BARs are not always the same size across different
SOCs, so use the defined size rather than a hardcoded value.
This results in the following change on TGL which increased the MCHBAR
size to 128K:
-system 00:00: [mem 0xfedc0000-0xfeddffff] has been reserved
+system 00:00: [mem 0xfedc0000-0xfedc7fff] has been reserved
And fixes the following error output from the kernel:
resource sanity check: requesting [mem 0xfedc0000-0xfedcdfff],
which spans more than pnp 00:00 [mem 0xfedc0000-0xfedc7fff]
Change-Id: I82796c2fc81dec883f3c69ae7bdcedc7d3f16c64
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.
BUG=b:171993054
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I1f895dbdbb71a353a98272db6dc70b54e8e172a3
This SOC overrides the common PMC device and instantiates the PMC device
in the SSDT. It needs to call the common PMC function to provide the
IPC mailbox method.
The common PCIe RTD3 driver can also be enabled which will allow
mainboards to enable Runtime D3 power control for PCIe devices.
BUG=b:160996445
TEST=boot on volteer with this driver enabled for the NVMe device in the
devicetree and disassemble the SSDT to ensure the RTD3 code is present.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ifa54ec3b8cebcc2752916cc4f8616fcb6fd2fecc
This driver is for devices attached to a PCIe root port that support
Runtime D3. It creates the necessary PowerResource in the root port to
provide _ON/_OFF methods for which will turn off power and clocks to the
device when it is in the D3cold state.
The mainboard declares the driver in devicetree and provides the GPIOs
that control power/reset for the device attached to the root port and
the SRCCLK pin used for the PMC IPC mailbox to enable/disable the clock.
An additional device property is created for storage devices if it
matches the PCI storage class which is used to indicate that the storage
device should use D3 for power savings.
BUG=b:160996445
TEST=boot on volteer device with this driver enabled in the devicetree
and disassemble the SSDT to ensure this code exists.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I13e59c996b4f5e4c2657694bda9fad869b64ffde
Copy the code for CPPC entries generation, needed for Intel SpeedShift,
from SKL to common ACPI code.
SKL is going to use common ACPI code, too, in the future, so this code
duplication will vanish soon.
Test: dumped SSDT from Clevo L140CU and checked decompiled version after
enabling CPPC entries via Kconfig
Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45535
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the decision of whether or not to use mrc_cache in recovery
mode is made within the individual platforms' drivers (ie: fsp2.0,
fsp1.1, etc.). As this is not platform specific, but uses common
vboot infrastructure, the code can be unified and moved into
mrc_cache. The conditions are as follows:
1. If HAS_RECOVERY_MRC_CACHE, use mrc_cache data (unless retrain
switch is true)
2. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_BOOTBLOCK, this
means that memory training will occur after verified boot,
meaning that mrc_cache will be filled with data from executing
RW code. So in this case, we never want to use the training
data in the mrc_cache for recovery mode.
3. If !HAS_RECOVERY_MRC_CACHE && VBOOT_STARTS_IN_ROMSTAGE, this
means that memory training happens before verfied boot, meaning
that the mrc_cache data is generated by RO code, so it is safe
to use for a recovery boot.
4. Any platform that does not use vboot should be unaffected.
Additionally, we have removed the
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN config because the
mrc_cache driver takes care of invalidating the mrc_cache data for
normal mode. If the platform:
1. !HAS_RECOVERY_MRC_CACHE, always invalidate mrc_cache data
2. HAS_RECOVERY_MRC_CACHE, only invalidate if retrain switch is set
BUG=b:150502246
BRANCH=None
TEST=1. run dut-control power_state:rec_force_mrc twice on lazor
ensure that memory retraining happens both times
run dut-control power_state:rec twice on lazor
ensure that memory retraining happens only first time
2. remove HAS_RECOVERY_MRC_CACHE from lazor Kconfig
boot twice to ensure caching of memory training occurred
on each boot.
Change-Id: I3875a7b4a4ba3c1aa8a3c1507b3993036a7155fc
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46855
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update I2C address for Goodix touchscreen and add ELAN touchscreen &
Synaptics trackpad device. Follow CB:47415 to correct HID over I2C
device to be level triggerd.
BUG=b:160013582
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device.
Change-Id: I070fb0e06b588f128253270502c9c2c427c62b84
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
