9517ae9f69
soc/amd/sabrina: update pci_devs.h
...
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ic0226afd9e7fffd6bf196f06ee6c34b6b9c92f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-27 22:21:03 +00:00
6b90511da4
soc/amd/sabrina/fsp_m_params: drop sata_enable UPD write
...
There are no SATA controllers on the Sabrina SoC. The UPD field will be
removed later as a part of the initial UPD header update.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Iedefd9f150e5bcb78173288e5fc9f1bbd6b498cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2022-01-27 22:20:10 +00:00
49cb32d430
soc/amd/sabrina/include: update smi.h
...
Some of the names have slightly changed in the PPR, but I kept the
current names for consistency across all AMD SoCs in coreboot. Revision
1.50 of the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I6bda656015858a57e221b8d7819f944c21564a39
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-27 22:19:45 +00:00
039be8c7c7
soc/amd/sabrina/include/data_fabric: update IOMS0_FABRIC_ID
...
The data fabric ID table in PPR #57243 Rev 1.50 has a different IOMS0
fabric ID than Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I32890b5c03219f6ebf8180929d71ef726d382483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2022-01-27 22:19:27 +00:00
8a09cbd336
soc/amd/sabrina: drop graphics.c
...
Since we don't need to support PCI ID remapping for finding the correct
VBIOS binary for the integrated GPU, graphics.c can be dropped for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ifd5b678f472b3b5888353efd057203eb641be874
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-27 22:19:09 +00:00
283999ad53
soc/amd/sabrina/cpu: update CPUID
...
Sabrina is family 17h model A0h.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I01e02e3491fb90941c767058986da876bdf7ca1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-27 22:18:31 +00:00
b1fe9de74d
soc/amd/sabrina: add additional UART controllers
...
Compared to Cezanne there are 3 more UART controllers. Revision 1.50 of
the PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I628b1a7a0930f3409acdcabda2b864d42bf6bd23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
2022-01-27 22:18:17 +00:00
a48f29192d
soc/amd/sabrina/gpio: update GPIO definitions and gpio_event_table
...
The GPIO and GPIO MUX mapping as well as some GPIO to GEVENT mappings
have changed compared to Cezanne. Sabrina also doesn't have a remote
GPIO bank. Revision 1.50 of PPR #57243 was used as a reference.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Iabb85a3d24c881055e94400d08d01505df44a07a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com >
2022-01-27 22:14:20 +00:00
2f478b85ca
soc/amd/sabrina/include/amd_pci_int_defs: add additional UARTs
...
Compared to Cezanne there are 3 more UARTs controllers. The PCI
interrupt index table in the new SoC's PPR #57243 Rev 1.50 doesn't
contain a PIRQ mapping for UART4. The reference code has a mapping for
this and it uses PIRQ mapping index 0x77 for UART4 and not for I2C5.
Since the I2C5 controller isn't owned by the x86 side and I didn't see
any mapping of the I2C5 controller into the x86 MMIO space, this seems
very plausible. Also add the corresponding fields to the ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I44780f5bc20966e6cc9867fca609d67f2893163d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-27 22:14:05 +00:00
cea684df9f
mb/google/brya/var/taniks: Enable Bayhub LV2 driver
...
Some SKUs of google/taniks have a Bayhub LV2 card reader chip,
therefore enable the corresponding driver for the mainboard.
BUG=b:215487382
TEST=Build FW and checking SD card reader register is correct.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com >
Change-Id: I34adb122bd2edc343e894a53bc12e105f4225984
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-27 22:06:18 +00:00
648a44acbc
util/chromeos: Update extract_blobs script
...
- Handle older CrOS firmware which lacks a COREBOOT FMAP region
- Add support for all blobs used in CrOS firmware 2013 to current
- Put extracted blobs in their own directory
Change-Id: Idaa39eca3be68a9327cead9b21c35a6c7a3a8166
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2022-01-27 22:06:10 +00:00
ef8a1390b2
drivers/intel/usb4/retimer: Use usb4_retimer_scope replace dev path
...
Without acpi name, acpi_device_path will return NULL.
<NULL>: Intel USB4 Retimer at GENERIC: 0.0
Replace with usb4_retimer_scope for the identify.
BUG=b:215742472
TEST=show below meaasge in coreboot log
\_SB.PCI0.TMD0.HR : Intel USB4 Retimer at GENERIC: 0.0
\_SB.PCI0.TMD1.HR : Intel USB4 Retimer at GENERIC: 0.0
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com >
Change-Id: Idfa8b204894409b11936e5f221c218daa206cc02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-27 22:05:52 +00:00
5d48e78341
Makefile.inc: Don't ignore IASL's "multiple types" warning
...
Intel Lynx Point ASL code is fixed. So don't ignore
"Multiple types (Device object requires either a _HID or _ADR, but not both)"
warning.
Change-Id: Ie9398879a76ad3d36454772a1c23da083af14b59
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2022-01-27 16:52:30 +00:00
0015df5927
util/coreboot-configurator: Add contrib files
...
Add contrib files for:
* debian (Tested on Ubuntu 20.04, 21.10, MX Linux 21 and Debian)
* PKGBUILD (Tested on Manjaro 21)
* flatpak (Untested)
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: Ie9f0193ed28c0842661426204fc88ec00091fbae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2022-01-27 16:17:42 +00:00
9c89e3ada2
util: Add coreboot-configurator
...
A simple GUI to change settings in coreboot's CBFS, via the nvramtool utility.
Test on the StarBook Mk IV running coreboot 4.15 with:
* Ubuntu 20.04
* Ubuntu 21.10
* MX Linux 21
* elementary OS 6
* Manjaro 21
Signed-off-by: Sean Rhodes <sean@starlabs.systems >
Change-Id: I491922bf55ed87c2339897099634a38f8d055876
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2022-01-27 16:16:23 +00:00
aef6de3426
cpu/intel/socket_p: Drop 'select SSE'
...
SSE is already selected by SSE2 through model_{1067x,6fx}/Kconfig
Change-Id: I3641118905f1fcc1e34d7fe4f7ca3082c3cf0d3b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:51:35 +00:00
58e2c50d88
cpu/intel/socket_m: Drop 'select SSE'
...
SSE is already slected by SSE2 through model_6{e,f}x/Kconfig
Change-Id: Ibe215cfe6aa6d7c215dd62e1ab2966d079c2a78d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:51:24 +00:00
be35479f91
cpu/intel/socket_LGA775: Drop 'select SSE'
...
SSE is already selected by SSE2 through model_1067x/Kconfig
Change-Id: I7b16af0277dc01c5905c5990244d3738a33723b3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:51:16 +00:00
ec31cf13e2
cpu/intel/socket_FCBGA559: Drop 'select SSE'
...
SSE is already selected by SSE2 through model_106cx/Kconfig
Change-Id: I31b8345fdd901e1d05df5fa8351db3255f9cf9cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:50:38 +00:00
921b99ed4b
nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macros
...
Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:48:56 +00:00
a233eb4b0a
nb/intel/sandybridge/raminit_mrc.c: Use DDR3_SPD_SODIMM macro
...
Change-Id: Ibbb6e6d44b1415b18aa59310f4d36d61b9a2a080
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:48:35 +00:00
62b23c10e0
nb/intel/sandybridge/raminit_mrc.c: Use <smbios.h> macros
...
Use macros defined in <smbios.h> for 'ddr_type' and 'bus_width'
Change-Id: I0501147139387cd9b5c7ec6b7ba7f8a5c5bd18bb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2022-01-27 14:48:20 +00:00
30f05c4e7c
mb/google/kukui: Add DRAM support for burnet/esche
...
0x18 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B
0x19 HYNIX 4GB LP4X H54G56CYRBX247
0x1a SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL
0x1b HYNIX 8GB LP4X H54G68CYRBX248
BUG=b:165768895
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Change-Id: Ib1c09ff2b88bf121de702985680b2388c0fb8427
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2022-01-27 14:47:25 +00:00
2c7e498876
mb/google/kukui: Add dedicated memory map for kappa
...
Add a dedicated memory mapping table starting at index 0x40:
0x40 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCR
0x41 HYNIX 4GB QDP LP4X H9HCNNNCPMALHR-NEE
0x42 MICRON 4GB LP4X MT53E1G32D4NQ-046 WT:E
0x43 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:A
0x44 MICRON 4GB LP4X MT53E1G32D2NP-046 WT:B
0x45 HYNIX 4GB LP4X H54G56CYRBX247
0x46 SAMSUNG 4GB LP4X K4UBE3D4AB-MGCL
0x48 SAMSUNG 4GB LP4X K4UBE3D4AA-MGCL
0x49 MICRON 8GB LP4X MT53E2G32D4NQ-046 WT:A
0x4A HYNIX 4GB QDP LP4X H9HCNNNCPMMLXR-NEE
0x4B Micron MT29VZZZAD9GQFSM
BUG=b:162379736
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com >
Change-Id: I97f296cb8c35fd2f979a05d0b97a0562c1b472f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
2022-01-27 14:47:02 +00:00
8d6c1c2d0e
mb/google/dedede/var/metaknight: Set core display clock to 172.8 MHz
...
When using the default initial core display clock frequency, Metaknight
has a rare stability issue where the startup of Chrome OS in secure mode
may hang. Slowing the initial core display clock frequency down to
172.8 MHz as per Intel recommendation avoids this problem.
The CdClock=0xff is set in dedede baseboard,and we overwrite it as 0x0
(172.8 MHz) for metaknight.
BUG=None
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Change-Id: I987277fec2656fe6f10827bc6685d3d04093235e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com >
2022-01-27 14:46:40 +00:00
79effad1fc
mb/google/brya/variants/volmar: Init devicetree for volmar
...
Init basic override devicetree based on schematics
BUG=b:211891086
TEST=FW_NAME="volmar" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I40b364e3df2f04a6b828f4f288667b96b6e0bd22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com >
2022-01-27 14:46:21 +00:00
2bff154598
mb/google/brya/var/brask: set tcc_offset value to 10℃
...
Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:214890058
BRANCH=None
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: I86acb172ed427d45973b9360e0413978cbd46645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-27 14:46:00 +00:00
d87b0c371e
soc/intel/common/cse: Drop CSE library usage in bootblock
...
This patch drops the CSE common code block from getting compiled
in bootblock without any SoC code using heci communication so
early in the boot flow.
BUG=none
TEST=Able to build brya, purism/librem_skl without any compilation issue.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Ib4d221c6f19b60aeaf64696e64d0c4209dbf14e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
2022-01-27 10:47:26 +00:00
96eb676b5e
soc/intel/skylake: move heci_init() from bootblock to romstage
...
Aligns with all other soc/intel/common platforms calling heci_init().
Test: build/boot Purism Librem 13v2
Change-Id: I43029426c5683077c111b3382cf4c8773b3e5b20
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61378
Reviewed-by: Subrata Banik <subratabanik@google.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-27 10:46:53 +00:00
2cd3384b18
mb/google/zork/var/vilboz: Add new memory K4AAG165WB-BCWE
...
Add new ram_id:1100 for memory part K4AAG165WB-BCWE.
BUG=b:212507858
TEST=Generate new spd file and build coreboot.
Then boot from the DUT with new memory K4AAG165WB-BCWE
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com >
Change-Id: I4e409a5a5a3b3d1b0013d2c020eeb4c0aeec51ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Kangheui Won <khwon@chromium.org >
2022-01-27 06:45:34 +00:00
eb9e63f21f
src: Add missing 'void' in function definition
...
Change-Id: I7fa1f9402b177a036f08bf99c98a6191c35fa0b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2022-01-26 23:57:12 +00:00
98d76cb708
vc/amd/agesa: fix out-of-bounds read
...
Fix the out-of-bounds read issue found by Coverity.
TEST=none
Signed-off-by: Jason Nien <finaljason@gmail.com >
Change-Id: I01e134cb6b025bf7cb5030cd9378297d7f6df509
Reported-by: Coverity (CID:1376956)
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58803
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-26 22:17:06 +00:00
74b85f2e2e
soc/intel/cannonlake: Add PcieRpHotPlug config to FSP-M
...
Commit b67c5edmatt.devillier@puri.sm >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2022-01-26 21:25:19 +00:00
69d92deb6c
soc/intel/denverton_ns: Fix logging level
...
Level should match that used in print_num_status_bits().
Change-Id: I1beb65e4c141e195dd59eaa2bf55fff6e7dc910d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com >
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr >
2022-01-26 21:24:51 +00:00
6e4b81c20a
Revert "mb/google/brya/var/brask: Configure the ISOLATE pin of LAN"
...
This reverts commit 2bf2e6d1ccalan-huang@quanta.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-26 20:38:03 +00:00
d9e50b1343
util/mb/google: add support for brask
...
Add the file templates for creating a new variant of Brask.
BUG=b:215091592
TEST=new_variant.py and build coreboot pass for the new variant.
Change-Id: I67e4ed450d6033fed7419bd7c76c127ecd942fe8
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-26 19:51:03 +00:00
2e7b78bad4
mb/google/brya/var/kano: Reduce reset delay time to 20ms for ELAN TS
...
Set register "reset_delay_ms" to 20 to reduce power resume time.
BUG=b:204009580
TEST=tested on kano
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com >
Change-Id: Ib0695edd7c342c65df9138b1590281c5f442769b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2022-01-26 19:50:37 +00:00
d575c8d4ed
MAINTAINERS: add maintainers for mb/amd/chausie
...
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ie39e42407fe4677d4c8e991824588d2d598a73ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-26 17:09:15 +00:00
2e88d06d2b
MAINTAINERS: add maintainers for soc/amd/sabrina
...
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: I8630b8ac472af94bbeede2bcadf4d0a750b44e5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2022-01-26 17:09:05 +00:00
18167d4ac1
mb/google/guybrush/var/dewatt: Update Elan touchpad interrupt trigger
...
Update Elan touchpad interrupt trigger to level low from edge low to keep consistency with Synaptics touchpad. Checked with Elan PM Iris and other projects(spherion), the touchpad can be set to edge or level low trigger.
Sepherion Elan touchpad IRQ setting: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.4/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi;l=415?q=mt8192-asurada.dtsi&ss=chromiumos%2Fchromiumos%2Fcodesearch:src%2Fthird_party%2Fkernel%2F
BUG=b:214143249
TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Elan and Synaptics touchpad wakeup from s0i3 well with proto build.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com >
Change-Id: Ifac49b131cadc1f8838bb6243ad6d17feb272bd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rob Barnes <robbarnes@google.com >
2022-01-26 16:21:41 +00:00
d03b824893
mb/google/guybrush/var/dewatt: Update touchpad GPIO configuration
...
Update GPIO configuration to fix Synaptics touchpad can't wakeup system from s0i3.
BUG=b:214143249
TEST=emerge-guybrush coreboot chromeos-bootimage; Tested Synaptics touchpad wakeup from S3 with proto build.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com >
Change-Id: I29734595d37283adc6fd4a0ed17f51a5c9061796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rob Barnes <robbarnes@google.com >
2022-01-26 16:21:16 +00:00
f1b11e7fcc
soc/intel/alderlake: Add GPIO Controller device ID for ADL-N
...
Add PCH ACPI Device ID for Alder Lake N SOC GPIO Controller.
Document: Alder Lake N Platform EDS Volume 1 (Doc# 645548)
Signed-off-by: Usha P <usha.p@intel.com >
Change-Id: I6eb15751dd303b4b445cb64f25a040302e50c09d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Kangheui Won <khwon@chromium.org >
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com >
2022-01-26 16:20:48 +00:00
707aa2ae77
soc/mediatek/mt8186: Use BIT() macro for arbiter enable bit
...
Replace (1 << x) with BIT(x) in pmic_wrap.h.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com >
Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61351
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-26 09:15:59 +00:00
af2f8b9297
soc/intel/alderlake: Choose non-posted write to lock GPIO PAD
...
Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI config on Alder Lake
to instruct Pad Configuration Lock to use non-posted sideband writes as
posted write is not supported on Alder Lake while locking GPIO pads.
BUG=b:211573253, b:211950520
TEST=None
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Id8d394b97de9c328b3f75df3649d7efc782f006b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@mailbox.org >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2022-01-26 08:30:01 +00:00
393b093f71
soc/intel/alderlake: Skip FSP to unlock GPIO Pads
...
This patch makes FSP-S skip unlocking the GPIO Pads.
BUG=b:211573253, b:211950520
TEST=FSP-S debug log below:
Without this change:
UnlockGpioPads= 1
With this changes
UnlockGpioPads= 0
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I236a19a67372e9668e304d0054d477daff6a0266
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2022-01-26 08:29:46 +00:00
7e8a0e61e7
soc/intel/common/gpio: Rework PAD config macro to add lock support
...
This patch extends `struct pad_config` to add new variable for gpio
lock action.
Additionally, it creates new GPIO PAD configuration macros that perform
GPIO pad configuration and pad lock configuration as well.
List of new macros are:
1. PAD_CFG_NF_LOCK
2. PAD_CFG_GPO_LOCK
3. PAD_CFG_GPI_LOCK
4. PAD_CFG_GPI_TRIG_OWN_LOCK
5. PAD_CFG_GPI_GPIO_DRIVER_LOCK
6. PAD_CFG_GPI_INT_LOCK
7. PAD_CFG_GPI_APIC_LOCK
8. PAD_CFG_GPI_IRQ_WAKE_LOCK
Mainboard users can use the above macros to lock the PAD after
configuration.
So far on IA chipset, the default GPIO pad lock configuration reset
type is POWERGOOD hence, it's recommended as per GPIO BWG (doc: 630603)
to configure the GPP PAD reset type the same as lock configuration
reset type to avoid GPP reset value misconfiguration issue.
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: Ibf8b0a845005ad545266d995449d0aa711f45a61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
2022-01-26 08:29:35 +00:00
fe678cbd19
soc/intel/common/gpio: Perform GPIO PAD lock outside SMM
...
This patch performs GPIO PAD lock configuration in non-smm mode.
Typically, coreboot enables SMI at latest boot phase post FSP-S,
hence, FSP-S might get chance to perform GPP lock configuration.
With this code changes, coreboot is able to perform GPIO PAD
lock configuration early in the boot flow, prior to calling FSP-S.
Also, this patch ensures to have two possible options as per GPIO
BWG to lock the GPIO PAD configuration.
1. Using SBI message with opcode 0x13
2. Using Private Configuration Register (PCR)
BUG=b:211573253, b:211950520
TEST=Able to build and boot brya variant with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com >
Change-Id: I71b4e2f24303b6acb56debd581bd6bc818b6f926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60801
Reviewed-by: Nick Vaccaro <nvaccaro@google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-26 08:29:24 +00:00
a3525af1d2
mb/google/guybrush/dewatt: Add variant to disable HDMI
...
For one specific type of APU, it doesn't have HDMI. When we detect
this APU, we need to explicitly disable HDMI in DDI settings,
otherwise the system would freeze.
get_cpu_count() == 4 && get_threads_per_core() == 2: This case is for
2 Core and 4 Thread CPU (2C/4T for short).
get_cpu_count() == 2: This is for 2C/2T. This is for a possible future case.
BUG=b:208677293
Change-Id: I8d0fa96818a768b7960d92821b927dbc622675ae
Signed-off-by: Zheng Bao <fishbaozi@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
2022-01-26 04:16:34 +00:00
d4b5ad0ce3
soc/amd/cezanne,picasso,sabrina: factor out get_threads_per_core
...
This code is common to at least all Zen-based APUs (Picasso, Cezanne,
Sabrina) and is also useful outside of the SoC-specific dynamic ACPI
table generation code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de >
Change-Id: Ie96d4429fb6ed9223efed9b3c754e04052d7ca7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Rob Barnes <robbarnes@google.com >
Reviewed-by: Chris Wang <chris.wang@amd.corp-partner.google.com >
Reviewed-by: Eric Peers <epeers@google.com >
2022-01-26 04:15:11 +00:00
978930e860
soc/mediatek/mt8186: Update PWRAP arbiter enable bit
...
There is no wakeup source when we test function of suspend and resume.
The root cause is that the monitor enable bit of PWRAP is not configured
correctly.
BUG=b:213255218, b:214978483
TEST=receive wakeup source from MT6366 successfully
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com >
Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330
Reviewed-by: Yu-Ping Wu <yupingso@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2022-01-26 02:56:05 +00:00
