d925ca70d9
util: Add new memory part to LP4x list
...
Add memory part MT53E2G32D4NQ-046 to LP4x global list. Attributes
are derived from data sheets.Also, regenerate the SPD files for ADL
SoC using the newly added parts.
BUG=b:181378727
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: Ic06e9d672a2d3db2b4ea12d15b462843c90db8f6
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-03 15:50:47 +00:00
1d14ef25f3
mb/google/brya: fix BT enumeration issue
...
Current implementation exposes GPP_F4 cnvi reset pin as reset
gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven
by SoC. It should not be driven by driver.
BUG=b:180875586
Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 15:22:14 +00:00
b77cf2299c
soc/intel/common/block/smbus: Add config to use ACPI
...
Change-Id: Iafa7d40fc21e62f99dbdc2001ab6525a2a77ff50
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44865
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:36:07 +00:00
d3a65deb25
soc/intel: Guard macro parameters in pm.h
...
Guard against unintended operator precedence and associativity issues.
Change-Id: I342682a57fde9942cdf7be10756ee21c10af802a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50917
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:07:59 +00:00
b0f52fb5bf
soc/intel/cannonlake: Move gpi_clear_int_cfg() call
...
To allow unifying bootblock.c in follow-ups, move a function call.
Change-Id: I0f40ee7fd47f7f9f582f314dfcd1b4b93b1db791
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-03 09:07:04 +00:00
a4cd9117da
soc/intel: Factor out common smmrelocate.c
...
There are seven identical copies of the same file. One is enough.
Change-Id: I68c023029ec45ecfaab0e756fce774674bb02871
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50937
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:06:09 +00:00
482d3a1f03
soc/intel/skylake: Always print ME FW SKU
...
State of ME firmware SKU is independent of power-down mitigation.
Change-Id: I014c1697213efaefcb0c2a193128a876ef905903
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-03 09:05:19 +00:00
27af8da7cb
soc/intel/skylake: Enable compression on FSP-S
...
Use LZ4 algorithm to compress FSP-S. This saves ~40 KiB and reduces the
boot time by ~7 ms. LZMA would save a further ~1 KiB, but adds ~9 ms to
the boot time.
LZMA size:
fsps_lzma.bin 0xb0dc0 fsp 146578 LZMA (188416 decompressed)
LZMA decompression time:
15:starting LZMA decompress (ignore for x86) 388,716 (47,646)
16:finished LZMA decompress (ignore for x86) 406,167 (17,450)
LZ4 size:
fsps_lz4.bin 0x242dc0 fsp 147442 LZ4 (188416 decompressed)
LZ4 decompression time:
17:starting LZ4 decompress (ignore for x86) 384,736 (47,864)
18:finished LZ4 decompress (ignore for x86) 384,796 (59)
Change-Id: Idace01227cfd2312b2c4c4ea1e6aaac8c21cd6b0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com >
2021-03-03 09:04:48 +00:00
242da79a3f
soc/intel/alderlake: Log internal device wake events
...
Add wake events to the elog for: HDA, GbE, SATA, CSE, south XHCI,
south XDCI, CNVi WiFI, TCSS XHCI, TCSS XDCI, and TCSS DMA ports.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: Icd50dc7ee052cf13b703188c0fd3d8b99216cb4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2021-03-03 09:04:12 +00:00
d828aed1dd
soc/intel/alderlake: Add some helper macros for accessing TCSS DMA devices
...
Change-Id: I5cf54ae0456147c88b64bd331d4de5ca2e941f8a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47413
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:03:55 +00:00
3fca2c7922
soc/intel/alderlake: Add PCIe root port wake sources to elog
...
Log PCIe root port wake events in the elog.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Change-Id: I2867b1fa12f639cd6c49a58f698b51b089e2b483
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Subrata Banik <subrata.banik@intel.com >
2021-03-03 09:03:42 +00:00
71505f5f47
sb/intel/lynxpoint/lpc.c: Relocate lock bit write
...
This lock bit can be set later, and should also be set for LynxPoint-H.
This eases merging with Broadwell, which already sets this lock bit
after `spi_finalize_ops()` in a dedicated finalisation function.
Tested on Asrock B85M Pro4 (LynxPoint-H), the lock bit is now set.
Change-Id: I5c32127f2b4cfdfeb0e30a64e5bdda89958933cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47036
Reviewed-by: Nico Huber <nico.h@gmx.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:03:18 +00:00
bd78c5a649
AGESA boards: Captilize ASL names
...
ASL+ Optimizing Compiler/Disassembler version 20200925 remarks:
IASL build/dsdt.aml
Intel ACPI Component Architecture
ASL+ Optimizing Compiler/Disassembler version 20200925
Copyright (c) 2000 - 2020 Intel Corporation
dsdt.asl 222: Name(PSa, Package(){
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_)
dsdt.asl 228: Name(APSa, Package(){
Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA)
Execute the command below to fix all occurences:
git grep -l PSa | xargs sed -i 's/PSa/PSA/g'
Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-03-03 09:03:02 +00:00
ebf5ae5bd5
configs/config.google_volteer.build_test_purposes: Add file
...
This is meant to build-test Crashlog and various debug options.
Change-Id: Ie9bbfa538e38a4d835c1f8b0d45feb2f0fe803f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Francois Toguo Fotso <francois.toguo.fotso@intel.com >
2021-03-03 09:02:39 +00:00
4280b43473
soc/intel/tigerlake: Re-use existing define in CrashLog implementation
...
TEL_CFG_BAR variables have the same value as PCI_BASE_ADDRESS.
This fix re-uses an already existing variable in crashLog.
BUG=None
TEST=CrashLog data generated, extracted, processed, decoded sucessfully on delbin.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com >
Change-Id: If063d1ea4189dbc5a75f37d86ce158e8f1bd808d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-03-03 09:02:16 +00:00
98521c51f4
soc/intel: Retype CnviBtAudioOffload devicetree option
...
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.
Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.
Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:02:03 +00:00
68b447c2f8
mb/purism/librem_mini: Implement die_notify
...
Make the SATA LED blink when coreboot dies. GPIO functions aren't
compiled in for postcar, so add a check to prevent linker failures.
TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and
also blinding LED). Re-install RAM (and re-seat RAM a few times),
boot to OS, and observe SATA LED operating normally, as expected.
Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-03 09:01:32 +00:00
bab7f18a43
mb/*/*: Don't select PCIEXP_HOTPLUG
...
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.
Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-03-03 09:01:04 +00:00
6d9af0ce6e
soc/intel: Backport SMRR locking support
...
Backport commit 0cded1f116th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-by: Nico Huber <nico.h@gmx.de >
2021-03-03 09:00:32 +00:00
8eb3a342d1
mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device
...
Pineview does not support PEG.
Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-03-03 09:00:08 +00:00
0ba27fbc44
mb/intel/d510mo/devicetree.cb: Indent with tabs
...
This is a cosmetic change.
Make the formatting consistent with the rest of the tree.
Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
2021-03-03 08:59:53 +00:00
ebd4dfa53e
mb/gigabyte: Add GA-D510UD
...
Booted fine on the first try. Most things work properly, but I haven't
tested them thoroughly. Native raminit chokes with a DIMM in the second
slot, but the first slot works properly.
Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2021-03-03 08:59:36 +00:00
27545df163
lib/cbfs.c: Fix return value of failure to measure
...
Returning an error on a failure to measure makes the system not
bootable.
Change-Id: Ifd20e543d3b30de045c0656eccdcc494c2fb10ce
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Julius Werner <jwerner@chromium.org >
Reviewed-by: Christian Walter <christian.walter@9elements.com >
2021-03-03 08:58:48 +00:00
e8e5107b49
mb/google/dedede/var/drawcia: Re-tune override GPIO table
...
There is going to be an upcoming board version for Drawlat/man and
Drawcia. Hence apply the override GPIO table without pad termination for
board versions 6 or 8 alone.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in Drawcia.
Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Evan Green <evgreen@chromium.org >
2021-03-03 05:27:57 +00:00
7221830894
mb/google/guybrush: Add SPDs to build for Guybrush variant
...
These files were automatically generated by the lpddr4 version of
gen_part_id.go.
BUG=b:178715165
TEST=Build
Signed-off-by: Martin Roth <martin@coreboot.org >
Change-Id: I3797ba6d52248961418000614a4f7885182521a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-03 03:47:47 +00:00
dd25dffa1d
mb/google/guybrush: Add generated LPDDR4x SPDs
...
These SPDs were generated by the lpddr4 version of gen_spd.go from the
global_lp4x_mem_parts.json.txt file.
BUG=b:178715165
TEST=None
Signed-off-by: Martin Roth <martin@coreboot.org >
Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
2021-03-03 03:47:36 +00:00
4089ddb13c
util/spd_tools/lp4x: Add 2 new parts to global memory definition
...
This adds the definitions for MT53E1G32D4NQ-046 WT:E used on Majolica,
and the NT6AP256T32AV-J1 part used on Guybrush.
BUG=b:178715165
TEST=Generate SPDs
Signed-off-by: Martin Roth <martin@coreboot.org >
Change-Id: I7cd729fc72d8f44a449429e97683b2ca1f560f2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2021-03-03 03:47:23 +00:00
d5c8a15d74
google/trogdor: Fix trogdor-rev1 eDP power GPIO
...
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other
special case) or rev2 (works like CoachZ/Homestar), rev1 used the same
pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still
some people using these, so add in another special case for that.
Signed-off-by: Julius Werner <jwerner@chromium.org >
Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196
Reviewed-by: Douglas Anderson <dianders@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-02 23:14:06 +00:00
b825acb958
soc/amd/cezanne: Disable legacy DMA IO ports
...
The legacy DMA is not used by linux. This change frees up those IO
ports.
When FSP-S runs, it re-enables the legacy DMA IO region, so we need to
disable it again.
BOOTBLOCK: PMx00: 0xe3060bf3
ROMSTAGE - Before FSP: PMx00: 0xe3060bf3
ROMSTAGE - After FSP: PMx00: 0xe3060bf7
BUG=b:180949454
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I7792d1f8ea40eb1c7f6cca67e9907208884ac694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51076
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-02 22:17:20 +00:00
c8c83ce027
mb/amd/majolica: Enable required devices in devicetree
...
Most devices are now disabled by default in the chipset. Enable the
iGPU and two XHCI controllers that are required to boot the board.
BUG=b:180528708
TEST=To be tested
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095
Reviewed-by: Raul Rangel <rrangel@chromium.org >
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-02 17:28:37 +00:00
22b5ef961c
mb/google/guybrush: Set up FW_CONFIG fields
...
BUG=b:180523962
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Martin Roth <martinroth@google.com >
2021-03-02 17:11:13 +00:00
c44cc19079
mb/google/guybrush: Add eSPI configuration
...
BUG=b:180507937
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047
Reviewed-by: Martin Roth <martinroth@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-02 17:04:59 +00:00
9f13cb72c5
tests: Add lib/compute_ip_checksum-test test case
...
Signed-off-by: Jakub Czapiga <jacz@semihalf.com >
Change-Id: I61c578ec93837cb2581a1ab9e2f3db2a0dd69f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2021-03-02 17:04:44 +00:00
0b6b968f9e
tests: Add lib/crc_byte-test test case
...
Signed-off-by: Jakub Czapiga <jacz@semihalf.com >
Change-Id: I9016cd7825cb681fd200b23dd362ca24acf69192
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org >
2021-03-02 17:04:28 +00:00
855e1bc9c7
soc/amd/cezanne: Fill out pci devices in chipset.cb
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BUG=b:180528708
TEST=builds
Signed-off-by: Mathew King <mathewk@chromium.org >
Change-Id: Iecc75afd7a914651ca15b811163d3559bf73ac9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
2021-03-02 16:59:48 +00:00
37c332782a
mb/google/brya: Fix a few mistakes in brya0 overridetree
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1) Both SAR sensors had a UID of `2`, making them indistinguishable
2) No `device` underneath max98357a `chip`
Change-Id: Icf586229532819a7779652cbee73755b036dfbdc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
Reviewed-by: Furquan Shaikh <furquan@google.com >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-02 16:59:44 +00:00
a91eb90d44
soc/amd/common/blocks/lpc: Explicitly disable serial IRQ
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The serirq enable bit defaults to true, so if we want it disabled, we
need to explicitly disable it.
BUG=b:180631748
TEST=Boot majolica and see spurious IRQ 9 gone.
Signed-off-by: Raul E Rangel <rrangel@chromium.org >
Change-Id: I7f1e18f836f29cb75334dd88c91ad047f5bdfb10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Felix Held <felix-coreboot@felixheld.de >
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com >
2021-03-02 16:54:33 +00:00
3173f857b6
mb/lenovo/x200: Fix docking events
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Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, to configure a chip in
a device- or overridetree, it always needs a `device` below it.
This should fix docking events for the X200 ThinkPad.
Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067
Signed-off-by: Nico Huber <nico.h@gmx.de >
Found-by: Kevin Keijzer <kevin@quietlife.nl >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-by: Kevin Keijzer
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
2021-03-02 12:17:14 +00:00
1037e34123
mb/google/guybrush: Add option to toggle GPIO for sign of life
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Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing.
BUG=b:180721202
TEST=builds
Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb
Signed-off-by: Mathew King <mathewk@chromium.org >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com >
2021-03-02 06:31:03 +00:00
4778590d15
soc/intel/skylake: Move gspi_early_bar_init() call
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For consistency with newer platforms, do this in pch.c instead.
Change-Id: Ie7a1d3e106553388df55044be91c7837061c42da
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
2021-03-01 19:43:22 +00:00
5d98dabb4e
soc/intel: Drop bootblock_cpu_init() function
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Just call `fast_spi_cache_bios_region()` directly instead.
Change-Id: I99f6ed4cf1a5c49b078cfd05e357c2d4c26ade45
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50952
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:43:04 +00:00
43026ba819
soc/intel/cannonlake: Drop unnecessary guard
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The MRC cache driver assumes BOOT_DEVICE_MEMORY_MAPPED=y already. This
is to ease factoring out common code across seven Intel platforms.
Change-Id: I0598cb18b456e10789b2a42792fbfa2639cdd2c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50951
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:42:43 +00:00
68fe2aa204
soc/intel/{skl,cnl}: Do not chain-include systemagent.h
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Change-Id: I8f48765ad99dad49f9d94c45aa4af6aff2ed702c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50950
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:42:26 +00:00
ec953face1
skylake,fsp1_1: Delete dead report_memory_config() function
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RAM is not yet configured in bootblock. This function was copy-pasted
from Broadwell. Also, Skylake no longer uses FSP 1.1 and the stubs in
there can be removed as nothing else uses them.
Change-Id: I22cb7e63ed1e9565934296fd40771130ba91d227
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50949
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:42:07 +00:00
3157068bf8
soc/intel/skylake: Extract fsp_params.c out of romstage.c
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Done for consistency with newer platforms. Also clean up includes.
Change-Id: Ib78717c6fbd49a5bd79bd564add8849ad21fa9e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50948
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:41:27 +00:00
53496e69ec
soc/intel: Drop romstage_pch_init() function
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It only calls `smbus_common_init()`, so just call that directly.
Change-Id: I0237f52bb9b0503e83f5dbf31c4064bd0f5bae28
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50947
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:41:17 +00:00
ec1b37decc
soc/intel/{skl,icl}: Move tco_configure() to bootblock
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Backport commit 03ed5bff5cbb50c6722760c619f6a3th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50946
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:40:57 +00:00
4ace49c9a2
soc/intel/icelake: Rename pch_init() function
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There's two instances of the same function, one for the bootblock and
another for romstage. Prefix them with the stage they are executed in.
Change-Id: I35e87cd47f3cef8952481d25b54558a546aebb60
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50944
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:40:31 +00:00
423c9faf63
soc/intel/skylake: Drop unused function prototypes
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Change-Id: I1b08b31876d6c10ac155fd67d4a505e8c272a15c
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50943
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:39:59 +00:00
e178df27dd
soc/intel: Factor out common smbus.h
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Change-Id: I31bb406bd2cf371ee935aa31777307043b2ee61a
Signed-off-by: Angel Pons <th3fanbus@gmail.com >
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50942
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de >
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org >
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz >
Tested-by: build bot (Jenkins) <no-reply@coreboot.org >
2021-03-01 19:39:27 +00:00
