When 'reset_gpio' and 'enable_gpio' properties are defined in
overridetree.cb, the kernel will power on the FPMCU. If the device was
previously enabled the kernel will reset it.
To avoid situation in which the FPMCU is powered on and reset later we
leave the FPMCU powered off in coreboot and started by the kernel. This
is exactly what other boards do (e.g. brya).
TEST=Boot the board (e.g. karis) and make sure the FPMCU was booted once
(e.g. examine FPMCU console logs)
Change-Id: I5df8d9385be2621c02ccee2d36511a4e80ab87d1
Signed-off-by: Patryk Duda <patrykd@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80457
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting the EC interrupt GPIO as an APIC is able to solve many
problems that we are currently seeing:
1. Routing through the APIC make the IRQ# associated with this pin
unavailable to claim for other devices in the kernel. This is causing
EC interrupts to not work.
2. Since EC interrupt are not working, we are not able to flash the
EC from the DUT.
3. Also, the GPI_INT configuration does not allow us to set the
polarity of the GPIO, which means that it is by default set as active
high. As a result, we are seeing an excessive number of host command
interrupts to the EC. This disappears when we change the
configuration to APIC and set the polarity as INVERT.
BUG=b:319129926,b:324707182
BRANCH=None
TEST=1. After boot up, check if ec_cros_lpcs driver was successfully
registered. Look for the following string:
"cros_ec_lpcs GOOG0004:00: Chrome EC device registered"
2. Make sure can flash the EC image from the DUT
3. Make sure EC console is not getting continuous stream of host
commands.
Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80467
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.corp-partner.google.com>
Configure PMC mux in devicetree. This allows PD controllers to be
used for both video and power delivery.
Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD
display can supply power and display video output.
Change-Id: I580b148b036e62fbcab50d1ca2ab1ed021cfed6b
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure PMC mux in devicetree. This allows PD controllers to be
used for both video and power delivery.
Tested on StarBook Mk VI with Ubuntu Lunar, by checking a USB-C PD
display can supply power and display video output.
Change-Id: I9e49612d7f165a9c9604093535f7b141a4c7048c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79426
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 977b8e83cb ("mb/emulation/qemu-aarch64: Add MMU support") adds
MMU support for ARM64 QEMU VMs, but registers a limited 1GiB region for
the DRAM, with a note that ramstage should update it.
However on recent versions of QEMU "virt" VMs, accessing RAM outside
this registered region results in an exception even if the address is
backed by actual RAM. This interferes with RAM detection which catches
these exceptions, effectively limiting us to detecting a maximum 1GiB of
RAM even if more is available.
Register the entire RAM space to MMU instead of just the 1GiB, so that
probing RAM addresses can correctly detect how much RAM we have.
Change-Id: I3afbd27b91ab37304a29a62506f965ac3cfb1c06
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This tool doesn't have a makefile, when trying to compile it manually
with the given instructions it even fails to compile after fixing the
paths in the given command, and it references the non-existing
PCI_BUS_SEGN_BITS Kconfig symbol, so just drop this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8ca75db281a215bf3f194ab72a107f666dc0694e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79934
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Normally this would be done by the Intel GMA driver, but we can't have
two copies of the _DOD method, so generate the LCD backlight controls
here to allow use of this driver instead of the default GMA panel
definition.
TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness
controls functional.
Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80061
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a modification for the x230 which uses the 2nd DP from the
dock as the integrated panel's connection, which allows using a custom
eDP panel instead of the stock LVDS display.
There are several adapter boards present on the market and all of them
use the same method of enabling the custom eDP panel.
To make this work with coreboot, the internal LVDS connector should be
disabled in libgfxinit. Additionally, VBT has been modified to keep
brightness controls functional on the adapter boards that use LVDS for
the job.
The modifications done to the VBT are:
- Remove the LVDS port entry.
- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
position on the list.
- Set the DP-3 as internally connected.
This has been reported to work with the following panels:
- LP125WF2-SPB4 (1920*1080, 12.5")
- LQ125T1JW02 (2560*1440, 12.5")
- LQ133M1JW21 (1920*1080, 13.3")
- LTN133HL10-201 (1920*1080, 13.3")
- B133HAN04.6 (1920*1080, 13.3")
- B133QAN02.0 (2560*1600, 13.3")
Other eDP panels not on this list should work as well.
Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Alexei Sorokin <sor.alexei@meowr.ru>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The HDA specification defines bits 11:8 of the Configuration Default
register as a miscellaneous field for other jack information. Only bit 8
has a standard meaning, and indicates that the jack does not have
presence detect capability. Add an enum for use in the AZALIA_PIN_DESC
macro to indicate this field. Note that many vendor firmwares set bits
11:9 to non zero values despite them being reserved in the
specification, and their meaning in these cases is not well known.
Change-Id: I70cbfca8541828a1e0c7280887060c04e4c71721
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add an enum for the Display Type, which if set, can be used to generate
the Device ID value dynamically when the addr field is not set. This
will allow devicetree entries to specify the display type instead of
a hex value for the address which requires referencing the ACPI spec
to decode.
For an internal panel connected to the first port on the graphics chip,
currently an addr value of 0x80010400 is specified. Replacing the
'addr' field with the 'type' field and setting it to 'panel' will
generate the same DID value.
Change-Id: Id0294a14606b410a13fa22eeb240df9e409a7ca3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Jinlon disables the eps device if no privacy screen is present, so add
a second generic gfx device 'no_eps' to handle that case, so that ACPI
backlight controls are generated either way. Add logic to ensure only
one of the two devices is active.
TEST=build/boot Win11 on google/hatch (jinlon), ensure LCD backlight
controls present and functional on device both with and without a
privacy screen.
Change-Id: Icf20de97d26c8be76c84e87d5dc6ed1a4b6dbfbc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80178
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Puff-based Chromeboxes use a LSPCON for HDMI 2.0 output, but no driver
exists or is needed for Windows. Use the devicetree hidden keyword to
set the ACPI status to hidden for these devices, to prevent unknown
devices from being listed in Windows Device Manager.
TEST=build/boot Win11 on google/wyvern, verify no unknown devices in
Windows Device Manager for either LSPCON device.
Change-Id: Ib646e01a337b8d7baf20a886c49a8cb64d6408f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78040
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Improves code maintainability and potentially reduces redundancy by
using the IA common implementation.
Additionally, drop the unused macros from SoC local.
TEST=Build and boot successful on google/marasov.
Change-Id: I290fea99f04cfc9f18e5f1435ed07de42995869f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80403
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit streamlines code and strengthens common code robustness
by moving the following SoC-layer functions to the common layer:
- sa_get_mmcfg_size: Retrieves the MMIO (Memory-Mapped I/O)
configuration space size by reading offset
0x60 of the PCI Host Bridge (D0:F0).
- sa_get_dsm_size: Calculates the size of the DSM (Device Stolen
Memory) by reading offset 0x50 of the PCI
Host Bridge (D0:F0) to determine pre-allocated
memory for the IGD (Integrated Graphics Device).
- sa_get_gsm_size: Calculates the size of the GSM (Graphics Stolen
Memory) by reading offset 0x52 of the PCI Host
Bridge (D0:F0).
- sa_get_dpr_size: Determines the size of the DMA Protection
Range (DPR) by reading offset 0x5C of the PCI
Host Bridge (D0:F0).
TEST= Build and boot successful on google/screebo.
Change-Id: Ic00e001563ec6f0d737a445964c716b45db43327
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Goal is to use existing defines for all pins to make the file
self-documenting, but it would make lines too long, so I'll just
start with the NC pins.
TEST=Timeless binary did not change.
Change-Id: I6da02d7bc4c87cc8477d687b238e6e6c9aec62cd
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79733
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
