In preparation to merging all the other HP sandy/ivy desktops in here
as variants.
Move hda_verb.c, early_init.c, gma-mainboard.ads and data.vbt into
variant directories.
Kconfig:
Move options not common to the others under the variants instead.
devicetree:
Move XHCI to variant overridetrees (8200 gen has no USB 3)
board_info.txt:
Make it more generic. It seems to be copied from 8200 SFF and
inaccurate to Z220 anyway.
TEST: BUILD_TIMELESS=1 & Don't include .config in ROM image. CMT and
SFF ROMs are (SHA1) same as before.
Change-Id: Icce22efb8d353359781db3f03c67058d8fbe11b8
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
The GNU BFD linker makes a good guess that this section should not be
loaded, however other linkers like LLVM LD need this to be made explicit
in order for the section to have the NOBITS, rather than PROGBITS
attribute set.
Change-Id: I3ca7221d10f144f608823e0b9624533780fbf335
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80735
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Starting from MT8195, MediaTek platform supports "dram adaptive" to
automatically detect dram information, including channel, rank, die
size..., and can automatically configure EMI settings. So we can just
pass a placeholder param blob to `mt_mem_init_run` by enabling this
option.
Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive"
need to implement `get_sdram_config` to get onboard DRAM configuration
info.
TEST=emerge-geralt coreboot && emerge-asurada coreboot
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is set to y on geralt
TEST=CONFIG_MEDIATEK_DRAM_ADAPTIVE is no set on asurada
Change-Id: I05a01b1ab13fbf19b2a908c48a540a5c2e1ccbdc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Unfortunately, the datasheet for IT8629E is not public. Therefore, we
will use the functionally closest chip (i.e. IT8728F) as a reference
and try to reverse-engineer where necessary.
IT8629E seems to be very similar to IT8628E (again, no public
datasheets), as the chip id is 0x8628.
Known differences:
- LDN 0x08 (functionality is unknown)
- Supports 6 fans
Change-Id: I44d0377da11f0e118017caa4357012df9373b322
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80344
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/deku using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Iedaff8a793f1ba5d2b97352b95c4dfdd2b818ebd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80664
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Karis has RO locked, any change in the bootblock won't be
applicable for FSI'ed karis devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is
TEST=Able to build and boot google/karis using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I79171a7830b75f5c20bbe30023f2814a62743a13
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80663
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/ovis using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: I891b5a6d2c29f5d940793a4e90215265f2a4fcd8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
Ideally, we don't need SSD power sequencing at ramstage, hence, remove
the logic from ramstage.
TEST=Able to build and boot google/rex0 using NVMe without any problems.
S0ix and read/write from/to SSD are also normal.
Change-Id: Idde2f7693771f1d7e3171e51232d1bb899bfe33e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Improve SSD readiness time by enabling earlier power sequencing.
Here are the two GPIOs to look for:
* GPP_A19: Power Enable
* GPP_A20: PERST
The flow is presented as `stage (GPIO PAD/Value)` for easy
understanding:
bootblock (A20/0, A19/1)
|
v
romstage (A20/1)
|
v
ramstage (A19/1, A20/1)
Ideally, we don't need SSD power sequencing at ramstage, but due to the
fact that Screebo has RO locked, any change in the bootblock won't be
applicable for FSI'ed screebo devices. Therefore, we're keeping the
existing ramstage power sequencing flow as is.
TEST=Able to build and boot google/screebo using NVMe without any
problems. S0ix and read/write from/to SSD are also normal.
Change-Id: I0ee1fa4613178da8771c9e6b5ee871e50ea6324c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80640
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch passes the correct flag to vboot to enable SIMD crypto
acceleration on arm64 devices. This uses a core part of the ISA and
should thus be supported on all arm64 SoCs -- so we normally always
want it enabled, but there should still be a Kconfig in case a SoC wants
to use the hwcrypto interface for its own (off-CPU) crypto acceleration
engine instead. (You could also disable it to save a small amount of
code size at the cost of speed, if necessary.)
Change-Id: I3820bd6b7505202b7edb6768385ce5deb18777a4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Updating from commit id 3d37d2aa:
2024-01-15 Makefile: Support FIRMWARE_ARCH=mock for firmware unit tests
to commit id 09fcd218:
2024-02-22 Makefile: Test compiler for -Wincompatible-function-pointer-types
This brings in 26 new commits:
09fcd218 Makefile: Test compiler for -Wincompatible-function-pointer-types
00e8c2d8 tests: Run hwcrypto RSA tests for arm64
d3387824 firmware: Add vectorized modexp() implementation for arm64 (NEON)
8856e04b tests: Stop exporting ENABLE_HWCRYPTO_RSA_TESTS to test scripts
6abd9cc0 Makefile: Separate ${ARCH_DIR}, split arm/arm64, remove symlinks
e7f567d1 test_update: Skip ifdtool-dependent tests when not available
1a0f8df8 libvboot_host: Check for undefined symbols
c0806280 vboot_host: Expose dynamic library
2ff5784d vboot: Remove 2kernel.c from vboot_host library
6e472468 Add crdyshim keygen script and devkeys
8a711468 scripts/keygeneration: Move generate_ed25519_key to common.sh
57e2092d scripts/image_signing: Call futility instead of its symlinks
0fa2ea47 scripts/image_signing/make_dev_ssh.sh: Improve parameter removal
1d32db3b Makefile: Remove genfuzztestcases from runtestscripts prerequisites
f6ff822b README: Add 'futility sign' and 'futility verify' to useful utilities
a717c83d tests: Replace vbutil_{firmware,kernel} with 'futility sign'
94c82417 *.sh: Unify indentation with 2 spaces
23d25957 utility/dev_debug_vboot: Replace vbutil_firmware with 'futility verify'
fd20901f cgpt/futility: bundle as a subtool
dccc5a31 image_signing: Add support for signing Flexor kernel image
660b6675 futility/cmd_show: Add "::verified" summary to vblock parseable output
2fcff1e4 tests/*.sh: Replace vbutil_firmware with 'futility verify'
c6b13823 make_dev_firmware.sh: Replace vbutil_firmware with 'futility show'
d260d094 firmware: 2modpow_sse2: Clean up calculation of `mu`
2596679a Add -Wint-conversion and -Wincompatible-function-pointer-types
39fb6201 futility: update: Use ifdtool to unlock ME
f8016c2b make_keyblock: change to parsing key prefix
Change-Id: Ibc6daef30092b1b31f3dd08f3aed02ba31fd12d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings glinda in line with cezanne, mendocino,
phoenix and picasso. This also prepares glinda to use the common
function gpp_clk_setup_common.
Change-Id: Id66d1b7f0d8ec9a7cbd378ad6ad7d68eeab531f0
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80415
Reviewed-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
System sleep time (SLP_S0 signal asserted) is measured in ticks, for
Alder Lake soc in 122us (i.e. ~8197Hz) granularity/ticks.
BUG=b:301854636
TEST=/sys/devices/system/cpu/cpuidle/
low_power_idle_system_residency_us" will show system idle residency time
Change-Id: I449f7ed0d9ef891ae5266e8fd784a063a75e38eb
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add FSP header files for Twin Lake. Currently these are just a copy of
ADL-N headers.
BUG=none
BRANCH=firmware-nissa-15217.B
TEST=Build and boot Google/Yaviks with Twin Lake kconfig enabled
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I37579335c784866ebbf978e28936abf046a85b48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Since the ACPI code is looking for VtdBars, that only appear on
Vtd devices, search for the Vtd device in devicetree.
With the previous commit the VtdBar is now exposed as a resource
on the Vtd device and thus can easily be accessed and used.
Drop the FSP HOB parsing and just use coreboot native functions.
Allows the code to work with multiple PCI segment groups.
Change-Id: I2c752dc595ac4c901f2b3a96718e256e413c76a7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Provide a helper function to locate PCI devices on a given socket
by their PCI vendor and device IDs and functions to return
information about the current device, like the corresponding stack
and socket.
In addition add functions to return "location" information, like stack
and socket affiliation.
This becomes handy when locating devices and generating ACPI code.
Change-Id: I266360588548ba579f46b228c4d5b3ae6e39a029
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80094
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Read the VtdBar and add it to the resources of the host bridge PCI
device. The BAR is already marked as PciResourceMem32 in the parent
PCI domain.
This allows easy probing for VTD devices with enabled VtdBars in the
next commit, without the need to look up the stack HOB.
Change-Id: Id579a94e653473f3dd0dccea6e33dc64f792d028
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
If a downstream LPC device (eg, SIO function) is disabled, we shouldn't
attempt to open PMIO windows for it, as those functions often have
unset IO bases (which default to 0), resulting in false errors like:
[ERROR] LPC IO decode base 0!
TEST=build/boot purism/librem_cnl (Mini v2), verify no LPC IO errors
in cbmem log for disabled SIO functions.
Change-Id: I92c79fc01be21466976f3056242f6d1824878eab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Early EC Sync does not need to be enabled in coreboot as EFS2 is being
enabled in the EC.
BUG=b:326152804
BRANCH=None
TEST=emerge-brox coreboot
To be tested with EC sync enabled
Change-Id: I08bdbe9f3dcea837b0b148adc137c03d3461877a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80689
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The lower bit of the BAR might be used for something else,
like enable bits, so mask the lower 12 bits and align all
base address to 4K.
Confirmed that all BARs have a minimum alignment of 4K, so that
masking the lower bits doesn't change the reported address.
The alignment of the VTD BARs is:
- VTD_MMCFG_BASE_CSR 64 MiB
- VTD_MMIOL_CSR 1 MiB
- VTD_NCMEM_BASE_CSR 64 MiB
- VTD_TSEG_BASE_CSR 1 MiB
- VTD_BAR_CSR 4 KiB
Change-Id: I9a7b963c0074246616968dd15c147f4916297d59
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
IOAT logics are optimized out for non-IOAT platforms where
CONFIG(HAVE_IOAT_DOMAINS) as false.
This patch puts CONFIG(HAVE_IOAT_DOMAINS) check together ahead
of is_ioat_iio_stack_res() check in the corresponding if
statement to fulfill the optimization outs.
TEST=intel/archercity CRB
Change-Id: I2d16c6ff5320bc9195a1033b6d55e3d997b19b88
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80683
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
K3KL8L80CM-MGCT 0 (0000)
K3KL6L60GM-MGCT 1 (0001)
H58G56AK6BX069 2 (0010)
H9JCNNNBK3MLYR-N6E 3 (0011)
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: I00ae3efe8e554f44cee5a27ac88c5d65eb95f7fb
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
The cmocka problem of sanitizing XML strings has been fixed in CB:80382.
Therefore the helper macros UX_LOCALES_GET_TEXT_FOUND_TEST() and
UX_LOCALES_GET_TEXT_NOT_FOUND_TEST() can be merged into one.
TEST=make unit-tests JUNIT_OUTPUT=y -j
Change-Id: Ic3199e2a061550282fb08122943994c835845543
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
The Rotation Matrix allows the specification of a 3x3 matrix
representing the orientation of devices, such as accelerometers.
Each value in the matrix can be one of -1, 0, or 1, indicating the
transformation applied to the device's axes.
It is expected by Linux and required for the OS to interpret
the data from the device correctly. It is used by various drivers,
mainly in `iio/accel`.
It was tested on Ubuntu, by rotating the device and verifying the
orientation was correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id4a940d999a0e300a6fe21269f18bab6e3c0523c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80179
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This adds an optimization to lzma decode to also read from the boot
medium in chunks of 8 bytes if that is the general purpose register
length instead of always 4 bytes. It depends on the cache / memory / spi
controller whether this is faster, but it's likely to be either the same
or faster.
TESTED
- google/vilboz: cached boot medium
64bit before - 32bit - 64bit after
load FSP-M: 35,674 - 35,595 - 34,690
load ramstage: 42,134 - 43,378 - 40,882
load FSP-S: 24,954 - 25,496 - 24,368
- foxconn/g41m: uncached boot medium for testing
64bit before - 32bit - 64bit after
load ramstage: 51,164 - 51,872 - 51,894
Change-Id: I890c075307c0aec877618d9902ea352ae42a3bfa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
