Some LDNs do not implement the activate bit at all, e.g. ITE GPIO LDNs
are an example where the LDN is always active. The pnp_generic.asl can
be used to describe the GPIO LDN resources configured by the platform,
however the register 0x30 is always 0 for these LDNs, so OS will not
claim the reported resource for the GPIO device, because _STA will
return inactive LDN.
Add SUPERIO_PNP_NO_DIS macro to generate _STA method returning an
always active LDN and skip _DIS generation. Define the SUPERIO_PNP_NO_DIS
for SIOs which use the pnp_generic.asl preserving the previous states,
except the ITE GPIO LDNs.
Change-Id: Ieb827fdffe7660b875cba6ca99b0560b4cab66b4
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80496
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Several older ChromeOS boards have issues with fan control on cold boot
and/or on S3 resume, so add functionality to allow those boards to
programmatically enable auto fan control.
TEST=build/boot google/link, verify fan ramps up/down accordingly with
CPU load.
Change-Id: I08a8562531f8af0c71230477d0221d536443f096
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Commit a662777b6f ("pnp_device: don't treat missing PNP_MSC devicetree
entry as error") lowered the log level for every resource without the
assigned bit set except for the IRQ0 and IRQ1 PNP device resources.
Commit df84fff80f ("device/pnp_device: Demote unassigned resource
printk to NOTICE") lowered the log level for the IRQ0 and IRQ1 PNP
device resources to a lower log level than for the other warnings that
are less likely a problem. Fix this regression by using the BIOS_NOTICE
log level for all PNP resources that don't have the IORESOURCE_ASSIGNED
bit set.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I232e60ef7ae672e18cc1837b8e6a0427d01c142b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80774
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No Windows driver exists or is needed, so hide to prevent an unknown
device from being listed in Windows Device Manager. Same change was
made for frostflow variant previously.
TEST=build/boot Win11 on skyrim, verify unknown device for the
fingerprint reader no longer present.
Change-Id: Ia700aa4ccd478bc734db012e1419e566a5dcf493
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80711
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though it has an 'amd_' prefix, the amd_pci_domain_fill_ssdt
implementation doesn't contain any AMD-specific code and can also be
used by other SoCs. So factor it out, move the implementation to
src/acpi/acpigen_pci_root_resource_producer.c, and rename it to
pci_domain_fill_ssdt. When a SoC now assigns pci_domain_fill_ssdt to its
domain operation's acpi_fill_ssdt function pointer, the PCI domain
resource producer information will be added to the SSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7bd8568cf0b7051c74adbedfe0e416a0938ccb99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80464
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The M700 / M900 Tiny boards are USFF PCs that come with Skylake LGA1151
processors. M700 comes with B150 chipset, M900 comes with Q170 and is
vPro capable.
There is an onboard discrete TPM 1.2. Intel PTT fTPM can also be enabled
in vendor FW, but for now it's not used here.
LPSS UART for debugging is available on pins 17,18 on the underside of
the mainboard, but it is not enabled by default.
Tested unit is M900 with i5-6500T. Boots to Fedora 38 w/ kernel 6.5.5
and Windows 11.
Tested and working:
- Serial port (via optional module)
- Rear DisplayPort connectors
- Graphics w/ libgfxinit
- Ethernet
- SATA
- NVMe
- Internal speaker, front combo jack, rear line-out
- Discrete TPM 1.2
- USB ports (Port 1 untested, apparently broken on my unit)
- M.2 2230 Wi-Fi slot (needs ASPM L1s disabled)
- S3 suspend
- ME disable via NVRAM setting
Untested:
- Front mic input
- Optional expansion headers: DisplayPort, USB, PS/2, SATA / PCIe
Change-Id: I6786e068ec03c8bf243e1767cd7b9d50512ea77f
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The processor may be a Pentium or 6/7th generation Core i3/i5/i7.
This port was tested on an i5-7400.
Working:
- Can boot Ubuntu 22.04.1 (Linux 6.5.0) using payloads:
- SeaBIOS
- TianoCore EDK 2
- Internal flashing (from coreboot)
- PEG
- PCIe
- SATA
- M.2 SSD
- M.2 WLAN (+ Bluetooth)
- LAN
- USB
- Memory card reader
- CPU fan
- VGA (DP bridge)
- Display ports
- Audio (output)
- COM1
- TPM
Not Working:
- SuperIO related things
- Power button LED
- PCIe clock related things and AER issues (LiveCD)
- Some drm issue when using EDK 2 and libgfxinit (LiveCD)
- ME cleaner
Untested:
- Audio (input)
Won't Test:
- COM2 header
- LPT header
- PS/2 keyboard and mouse
Thanks to Nico Huber and everyone else on the IRC for helping me write
my first port!
Change-Id: I551753aecfbd2c0ee57d85bb22cb943eb21af3cc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80343
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This changes the location to be expressed as a combination of ORs. This
allows aliases for special locations.
For example, `AZALIA_REAR_PANEL` is easier to read than
`AZALIA_EXTERNAL_PRIMARY_CHASSIS, AZALIA_SPECIAL7`.
References:
- Intel High Definition Audio Specification, rev. 1.0a, page 180,
Table 110. Location.
Change-Id: I5a61a37ed70027700f07f1532c500f04d7a16ce1
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
We were keeping 2 copies of the same thing (albeit there were some
slight differences). As azalia_device.h is used much more in the
codebase this was kept as the base and then some of the nice features
of azalia.h were incorporated.
The significant changes are:
- All enum names now use the `AZALIA_` prefix.
This also drops the AzaliaPinConfiguration enum as it was never used
since added in 2013.
Change-Id: Ie874b083a18963679981a9cd2b25d123890d628e
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80695
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The location is specified to be in range of 29:24, which is further
divided into upper bits (location2) [5:4] and lower bits (location1)
[3:0].
This also corrects the resulting values of clevo/l140mu.
References:
- Intel High Definition Audio Specification, rev. 1.0a, page 178,
Figure 74. Configuration Data Structure.
TEST=Timeless build using AZALIA_PIN_DESC() and without now produce the
same binary.
Change-Id: Ia5a3431b70783cb88e866d0fd8ea5530100f3d52
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80727
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When updating the Makefiles, to keep from having to update two files at
the same time, import Makefile.mk into the external Makefile. This
allows the bulk of the settings to be in a single location.
While I'm here, I adjusted the print statements to match the rest of
coreboot.
Change-Id: Id5b869f49b34b22e6a02fc086e7b42975141a87e
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Commit 8dc95ddbd4 ("emulation/qemu-i440fx: use fw_cfg_dma for
fw_cfg_read") adds DMA support to interface with the QEMU firmware
configuration device, and uses it to read from the "files" exposed by
the device. However, the file selection step still uses port-based IO.
Use DMA for fw_cfg file selection when possible, as a step towards
porting this driver to other architectures.
Change-Id: I46f9915e6df04d371c7084815f16034c7e9879d4
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This reverts commit 99bf23c9e7.
This patch causes the boot regression at depthcharge with below
error signature. Able to boot to OS after reverting this patch.
```
Starting depthcharge on Rex...
WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
fw_config match found: AUDIO=MAX98360_ALC5682I_I2S
Looking for NVMe Controller 0x30069a60 @ 00:06:00
libc/lp_vboot.c:25 vboot_get_context(): vboot workbuf could not be initialized,
error: 0x10080030
Ready for GDB connection.
```
Change-Id: I8d49e2dc49cd2935a9d8023c989869ec9558039e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80775
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Change-Id: I1dcad4ba3fbc0295d74e1bf832cce95f014fd7bf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80095
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of manually crafting S:B:D:F numbers for each PCI device
search for the devices by PCI vendor and device ID.
This adds PCI multi-segment support without any further code
modifications, since the correct PCI segment will be stored in the
devicetree.
Intel Document-ID: 735086
Intel Document-ID: 612246
Tested: On SPR 4S all PCU on all 4 sockets could be found and locked.
Change-Id: I06694715cba76b101165f1cef66d161b0f896b26
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80093
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow for more flexibility like generating page tables at runtime or
page tables that are part of the ramstage, add a parameter to
sipi_vector.S and smm_stub.S so that APs use the same page tables as the
BSP during their initialization.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I1250ea6f63c65228178ee66e06d988dadfcc2a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80335
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
This patch introduces an API for reading "feature_device_info" VPD
data. This information is essential for correctly differentiating
ChromeOS product segments (e.g., Chromebook-Plus vs. standard
Chromebook models).
BUG=b:324107408
TEST=Build and boot successful on google/yahiko with this change.
Change-Id: I8d49e2dc49cd2935a9d8023c989869eb9558039d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Port fix from Alder Lake to not set/reset IOM MCTP during
D3 cold entry or exit.
Ports 5008d34003 ("soc/intel/adl: Remove IOM Mctp command from TCSS
ASL"):
> Recently as part of s0ix hang issue, it was found that sending IOM
> MCTP command as part of TCSS D3 Cold enter-exit sequence created an
> issue.
> We discovered that due to change in hardware sequence, ADL should not
> set/reset IOM MCTP during D3 cold entry or exit. This patch removes
> the bit setting from ASL file to prevent hang in the system.
> This patch also removes obsolete Pcode mailbox communication which
> is no longer required for ADL.
> BUG=b:220796339
> BRANCH=firmware-brya-14505.B
> TEST=Check if hang issue is resolved with the CL and no other
> regression
> observed
> https://review.coreboot.org/c/coreboot/+/62861
Test: build/boot drobit to Win11. Verify TCSS XHCI power management
working and USB Root Hub doesn't Code 43 in device manager
Change-Id: I40a537fd2b0c821caf282f52aaff1874f54325f1
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80719
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current implementation assumes that the endpoint device is connected
directly to the PCIe Root Port, which does not always have to be true.
In a case where there is a PCIe switch between the endpoint and the
root port, the Max Payload Size capability may differ across the
devices in the chain and coreboot will not set a correct Max Payload
Size. This results in a PCIe device malfunction in pre-OS environment,
e.g. if the Ethernet NICs are connected behind a PCIe switch, the iPXE
fails to obtain the DHCP configuration.
Fix this by traversing the topology and programming the highest common
Max Payload Size in the given PCIe device chain during enumeration.
Once finished, the root port has the highest common Max Payload Size
supported by all the devices in the chain. So at the end of root port
bus scan, propagate the root port's Max Payload Size to all downstream
devices to keep Max Payload Size in sync within the whole chain.
TEST=Perform successful dhcp command in iPXE on the NIC connected to
the PCIe root port via ASMedia ASM1806 PCIe switch and again on the
NIC connected directly to the PCIe root port.
Change-Id: I24386dc208363b7d94fea46dec25c231a3968225
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
The QEMU firmware configuration driver can help initialize SMBIOS tables
using the table data that QEMU provides over the device. While doing so,
it reads from the device "file" manually using port-based IO.
Use the fw_cfg_read() helper function to read the SMBIOS-related file,
so that the driver is easier to port the driver to other architectures.
Change-Id: I18e60b8e9de34f2b0ff67af4113beec1d7467329
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80367
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Parts of the QEMU firmware configuration device driver refers to SMBIOS
related kconfig values. These depend on GENERATE_SMBIOS_TABLES and are
undefined if it isn't enabled, causing a build error.
Cover the SMBIOS-related region in this driver with an #if directive
checking the necessary config option. This is mostly to help port the
driver to non-x86 architectures where support for generating SMBIOS
tables isn't there yet.
Change-Id: I3ff388d4574eb52686a5dda3dcbc3d64a7ce6f7b
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80366
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Often times not all available resources are used on a PNP function, so
those resources not being specified is intentional, not an error. Keep
the printk but demote it so it doesn't pollute a normal cbmem log.
TEST=build/boot purism/librem_cnl (Mini v2), verify errors in cbmem
related to RTC IO/IRQ not being assigned are no longer present.
Change-Id: I3d9f22a06088596e14680190aede2d69880001fa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80645
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Don't attempt to open a PMIO window for a resource which doesn't have
the IORESOURCE_ASSIGNED flag set, since there is no point in doing so
and there's a high likelihood that the base address is 0, which will
throw an error.
TEST=build/boot purism/librem_cnl (Mini v2), ensure no errors in cbmem
log for attempting to open a PMIO window for unaassigned resources with
base address 0.
Change-Id: Ifba14a8f134ba12d5f5e9fdbac775d4f82b4c4de
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Refer to the reference board of nivviks, and update devicetree settings
via glassway schematic of ca24a_r10_240108_v3_mb_gsen_gmr.pdf.
BUG=b:319071869
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.
Change-Id: Ibbb10a373bd5fa52a0833b81133517d2a088536b
Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80742
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
