In northcluster.c, the set_resources member of struct device_operations
is set to NULL. That causes this message on the console:
PCI: 00:00.0 missing set_resources
Eliminate that warning by setting set_resources=DEVICE_NOOP.
Change-Id: I4c6c07fd40b180ca44fe67c4a4d07318df10c40f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: https://review.coreboot.org/14366
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
An unsigned enum expression is always strictly positive;
Comparison with '>= 0' is a tautology, hence remove it.
Change-Id: I910d672f8a27d278c2a2fe1e4f39fc61f2c5dbc5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: https://review.coreboot.org/8207
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
To avoid diverging too much on an actively developed code base, keep
the changes to a separate commit that can be downstreamed more easily:
- removed unused includes
- gave kevin board a "Kevin" part number
- marked RW_LEGACY as CBFS region (to follow up upstream changes)
- moved romstage entry point to SoC code (instead of encouraging
per-board copy pasta)
Change-Id: Ief0c8db3c4af96fe2be2e2397d8874ad06fb6f1f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
[pg: separated out from the combined commit that added both SoC and
board. Added board_info.txt that will be added downstream, too.]
Change-Id: I7facce7b98a5d19fb77746b1aee67fff74da8150
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/14279
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
gcc doesn't like these because they're undefined behavior, so use
zeroptr instead. For the loop that just does a number of writes (0..4),
use zeroptr + i.
Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain
ud2 anymore and to look reasonable where zeroptr was used.
Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14345
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Some ld versions seem to merge the .zeroptr section (NOLOAD, address 0)
with some debug sections (NOLOAD, address 0) which makes the build
explode when the debug sections are then stripped (including the zeroptr
symbol).
Just define zeroptr to be 0, no sections needed, to avoid this
"optimization".
Checked the objdump -dS of code using it that the accesses look sane.
Change-Id: Ia7cb3e5eae87076caf479d5ae9155a02f74b5663
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14344
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Testing dev->chip == NULL when dev == NULL doesn't make sense (and gcc
thinks that's undefined behavior which should be rewarded with a trap).
Change-Id: I801ce3d6b791fdf96b23333432dee394aa2e2ddf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Initial files to support Camelback Mountain CRB. This board uses
Broadwell-DE code which is based on FSP 1.0. Change is based on
Broadwell-DE Gold release.
Windows 7 and Fedora 21 have been verified using SeaBIOS payload,
also Fedora 21 with U-Boot payload.
Change-Id: Ie249588b79430084adeebbcdd8b483d936c655e3
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14015
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
As Aaron pointed out, the old definition made the compiler emit two
memory accesses, to 0 (for derefencing) and then reading at whatever
address could be read from there.
Change-Id: I5cdd53f5bd2d2397c43f09f3e5fa46be08744b01
Found-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14342
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On specific revisions of the ASUS KGPE-D16 (> 1.03G) there is a
high (< 1:10) chance of lockup from spurious HW monitor IRQs
during LPC configuration. This was originally erroneously identified
as a bug within the SP5100 southbridge due to serial console buffering
moving the hang slightly before HW monitor setup. It is currently
unknown how changing the CBFS layout / code size was able to alter
the frequency of the lockup occuring; this odd characteristic made
debugging extremely difficult, and it also indicates testing
across multiple PCB revisions will be neded to verify that the
bug has been completely resolved.
It is highly likely that the KCMA-D8 is also affected. As there
does not seem to be a reason to keep the HW monitor IRQ enabled,
simply disable it on both mainboards.
This configuration has passed burn-on power cycle testing with
no lockups noted. All other tests noted a lockup in under 25
power cycles or so, with failure typically occuring in under 5
power cycles; the affected Rev. 1.04 KGPE-D16 has cycled 25 times
times using this patch with only one failure finally noted. This
final failure may have in fact been related to SP5100 Erratum 18
as the frequency is more in line with the errata document guidelines.
Change-Id: Ie9f4f37d2c7dfad0a02daff8b75cd2a1e6f1b09a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14333
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
cat /sys/power/state should show supported sleep states as freeze and
mem where freeze is "Suspend to Idle" and mem is "Suspend to RAM"
Change-Id: Ia72aaf6642dcdc9106c1992af3cf6cb21a8fff4a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/14285
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Initial files to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.
Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14014
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Iea1a4b8f7df08d2ae694401211b0b664f5980b02
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14327
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I151d058615290e528d9d1738c17804f6b9cc8dce
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14321
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The way this was implemented before was causing ACPI failures. There
was also a basic misunderstanding of what the AddressMax field was used
for. In this case, because it's a fixed address, it should be the same
as the AddressMin field.
Getting rid of the addition in the field solves the ACPI output problem.
Change-Id: Idec2bf0ed27ae694e98f141087cdf22401937178
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
The driver interface function derives the driver specific pointer from
the API provided handle, no need to use the handle in the local
functions.
BRANCH=none
BUG=none
TEST=SPI interface with the flash ROM is still working properly.
Change-Id: I7725b658365473c733698ca050e780d1dd5072d9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a2b42779785623bd1234ab2dfb0b4db76c890fc7
Original-Change-Id: I9d657dc23540e9eac52d2dbfc551ed32b7fa98f0
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/338090
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/14318
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
3288 and 3399 use the same pwm controller.
With this patch in place it is easy to add support for 3399.
BRANCH=none
BUG=none
TEST=booted veyron_jerry to kernel login prompt
Change-Id: If8f5697b4003d078b46de3fa3cebad6c8310a688
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: acf6132619167743c0c991b75f0f49c8d0e51ca7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: I79428f9ec71017ad8f3ad67dac1468178ccc3a1e
Original-Reviewed-on: https://chromium-review.googlesource.com/338019
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14336
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Both SOCs use the same base i2c controller, the difference mostly
being the number of interfaces and distribution of the interfaces'
registers between register files.
Upload check was complaining about misspelled labels, fixed them to
pacify the check.
With this patch in place it is easy to add support for 3399.
BUG=none
BRANCH=none
TEST=brought up veyron_mickey all the way to booting the kernel. It
properly recognized the TPM and the edid of the panel, proving
that i2c interface is operational.
Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754
Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/337971
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/14335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin board can be booted to
Linux login propmt.
Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/13915
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is based on t420s. Tested on a T420 without discrete GPU.
There is no support for nvidia gpu and optimus.
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: Ie9405966e56180ac1c43a3c5b83181ee500177c8
Reviewed-on: https://review.coreboot.org/11765
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We already have the ability to add a pxe rom to cbfs, but it needs to be
configured and built separately.
This moves the existing Kconfig options for PXE from device/Kconfig and
the top level Makefile.inc to payloads, and adds the option to download
and build iPXE as part of the coreboot build process.
This configures the serial output of iPXE to match coreboot's serial
port configuration by editing the .h files. iPXE doesn't give any
real build-time method of setting these configuration options.
Change-Id: I3d77b2c6845b7f5f644440f6910c3b4533a0d415
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14085
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Id6d11d1cea3ebde4adf63e3d98ac603d85591d5b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14331
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I61938b42c5aa75d1c7706a1c5ae45dace6704c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14330
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I9689bf4ccc5f639bd98d6277bdd27afe4bb4295b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14329
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I7a19ed8cf16b9424190800940d2b8ec1a96c5ce9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14328
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I4572eec52bf834e4fac7bc5b54ceb591a0173a69
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14326
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I5e5180ec4303a121609b4acffb284daea6b08379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14325
Reviewed-by: Myles Watson <mylesgw@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: Ied67c5079a7f49594edb39caf61fe7f386c3f80d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14323
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update all of the license headers to make sure they are compliant
with coreboot's license header policy.
Change-Id: I260c1ae8d0f7306dd0c72c9ca05f0789cd915a61
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14322
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The following series always needs to access the functions
provided pci_rom.c.
Remove the dependency to CONFIG_VGA_ROM_RUN and depend on
CONFIG_PCI instead.
Change-Id: I6ed7ff5380edc7cd88dc1c71b43b1129a3de0f52
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This updates FSP UPD headers that adds new fields. Importantly
there are new FSPS UPD fields that allow to specify some BARs.
They are needed by FSP SiliconInit API to work properly.
Change-Id: Ie268c57c66b4d8fd6e00835916004058ff05762e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14217
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Certain security features on the platform use IMRs. Unfortunately
this memory is unusable for OS or firware. This patch marks IMR
regions as unusable.
Change-Id: I4803c41c699a9cb3349de2b7e0910a0a37cf8e59
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14245
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The ACPI base address was being programmed sepearately from
the other BARs in the PMC device. Group all the programming
together so there isn't separate paths for programming the
relevant BARs.
Change-Id: Ib17684397fc19c42b39d066f981c01a886d65235
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14320
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Restructure the nvm_is_write_protected routine to eliminate the dead
code error.
TEST=Build and run on Kunimitsu
Change-Id: Ia9170e27d4be3a34760555c48c1635c16f06e6a3
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14337
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
ACPI aware OS will need _PRT table to get desired interrupt
resource assigned and make device driver working. The logical
device within SOC gets fixed interrupt line.
Change-Id: I75141bd62ca2594b74983dff54912e0b20458b9a
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14243
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
