The OC pin was set to 0, which isn't connected. All USB ports are
connected to OC1.
This solves a strange issue where the Lite can't be powered on without
the charger connected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I700ddde291f0e4be6e3787e2da13f6d3ece736b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Based on the constraints for CML.
Fixes the following warnings in Linux on system76/oryp8 and
system76/gaze16, which have an NVIDIA GPU on the bridge.
pcieport 0000:00:01.0: can't derive routing for PCI INT A
pcieport 0000:00:01.0: can't derive routing for PCI INT B
This, in turn, resolves an IRQ conflict with the PCH HDA device that
would cause a stack trace on every boot and on S3 suspend.
irq 10: nobody cared (try booting with the "irqpoll" option)
<snip>
[<00000000fb84c354>] azx_interrupt [snd_hda_codec]
Disabling IRQ #10
Change-Id: Ibc968aaa7bf0259879097ff69d2543dcfa2e5e4b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Checkpatch was looking for a 65 character length, but format-patch adds
the text "Subject: [PATCH] " before the actual subject. Checkpatch
needs to account for that when looking at the line length.
Lines 2863 & 2864 have their indentation fixed as well.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2f2ee6e0f1b14ae6393ed7e64ba1266aa9debc7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The commit message wasn't being parsed because there's no filename
associated with it in the patch output. This change adds the "filename"
for the commit message in Gerrit for any errors that have a line number
but no filename.
calculations is intentionally misspelled as cacluations as a test.
Change-Id: Ie7a2ef06419c7090c8e44b3b734b1edf966597cc
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
In the last coreboot leadership meeting, the doxygen documentation was
declared to be dead. Remove it.
Doxygen style comments can still be added to files, and we may generate
doxygen based documentation, but it won't be for the entire project, but
instead just for those individual areas where it is being maintained.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8983a20793786a18d2331763660842fea836aa2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
With CBFS verification, cbfstool (CB:41121) needs bootblock to be
present in coreboot.pre in order to locate the metadata hash stored in
it. Therefore we have to ensure that bootblock is added to CBFS before
other CBFS files are added.
To solve the problem, create the 'add_bootblock' function, and call it
in the coreboot.pre recipe. Because bootblock.bin is now a prerequisite
of coreboot.pre, it will get built even if CONFIG_BOOTBLOCK_IN_CBFS=n.
BUG=b:233263447
TEST=emerge-guybrush coreboot
TEST=emerge-corsola coreboot chromeos-bootimage
TEST=cbfstool image-kingler.bin print -v
TEST=Kingler booted successfully
BRANCH=none
Change-Id: I385deb8231e44310ee139c3f69f449e75b92b2be
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Change-Id: I520a936b4c3a8997ba2c6bea0126b3bbcc5d68ce
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the mainboard starlabs/laptop/tgl, since
it is obsolete now.
Change-Id: I49bbd4a776b4e6c55cb373bbf88a3ca076342e3e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or overriden
by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Also, remove related code from the following mainboards, since it is
obsolete now.
* siemens/chili
* starlabs/laptop/cml
Change-Id: I173b87da5ce76549672c50ba30204cd77be8b82f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the Kconfig option `FSP_HYPERTHREADING` to common Intel Kconfig so
that it can be reused by other SoCs. Since not all SoCs support
hyperthreading, make it conditional on `HAVE_HYPERTHREADING`. SoCs
supporting hyperthreading need to select it so that `FSP_HYPERTHREADING`
is available.
Change-Id: I892d48b488cbf828057f0e9be9edc4352c58bbe7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add support for Alder Lake as a separate parsing profile, copying the
existing 'Cannon' profile and adjusting for differences in reset mapping
and GPIO macro generation.
TEST=Generate GPIO macros for MSI PRO Z690-A
Change-Id: I5871394bcb0636c2c803607ffb129441aa934417
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
On Guybrush, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771033
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1c68fce817a2a98ce0e8f1d9771d6c630dd5e88a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On Skyrim, the power and lid switches are managed by the EC
and coreboot and the AP have no control over them within this
context. Remove unused GPIO's to prevent coreboot warnings
about resampling at boot.
BUG=b:233771163
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie369bb7d430bd0dd1f1c1f41bf543a9b18e34db1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64644
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Guybrush, there wasn't a need for a sleep GPIO table.
Remove the TODO and filler table and function to reduce
unnecessary function calls/overhead. Missed changes
to variant.h in initial commit(already merged)
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idba1a9eeea5ea5f5922281668ec17c4f065a654d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64643
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch skips sending DISCONNECT IPC command to PMC if system resumes
from S3.
coreboot notice DISCONNECT IPC command getting timedout during S3
resume if system has AC connected behind Type-C hub. This impacts
system resume time. Please refer TA# 730910 for more information.
coreboot need not send the DISCONNECT IPC command when system resumes
from S3 state.
TEST=Verified system boots to OS and verfied below tests on Gimble
1. coreboot doesn't send the DISCONNECT during S3 resume
2. After S3 resume, system detects the pen drive with Superspeed
3. After system resumes from S3, hot-plug the pen drive, system detects
the pen drive
3. System sends IPC commands when system boots from S0 or S5.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6ad006ae8677919c7dfeca8eec0af11454a2e89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The FSP includes a UPD to set the DPA (Dynamic Periodicity
Alteration) PreWake value, which can be used to set the maximum
pre-wake randomization time in "micro-ticks". This patch adds
support for configuring that value.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I08897c590a88aba058cb9e364185ea0794e1e7c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add support for MB level dll tuning.
This patch sets the eMMC dll tuning parameters to default values needed.
There was issue observed on some eMMC devices which failed to boot in
HS400 mode.EV team suggested the intermediate eMMC dll tuning parameters
that needs to be set. We observed these values helped to fix the issue.
While we get the verified default values set from FSP directly, adding
it here to use it as the custom dll values needed.
BUG=b:230403441
TEST=Build and boot nivviks board. Verify the eMMC dll parameters are
overridden.
[INFO ] usha: After override dll_params
[INFO ] usha: emmc_tx_cmd_cntl=505
[INFO ] usha: emmc_tx_data_cntl1=909
[INFO ] usha: emmc_tx_data_cntl2=1c2a2828
[INFO ] usha: emmc_rx_cmd_data_cntl1=1c1b1d3c
[INFO ] usha: emmc_rx_cmd_data_cntl2=10049
[INFO ] usha: emmc_rx_strobe_cntl=11515
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I27771b663ce9808e5a5ef4b36c136ad78f924376
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Since the FIT pointer is patched at runtime there is no guarantee that
the pre-defined one will match the patched one. Add a check and print a
warning at runtime if both addresses (pre-defined and patched) do not
match as in this case an offline computed hash for the bootblock will
differ from the runtime one.
Change-Id: Ib1b02ec43af183caa9f5b08b3c485879b423c40f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Before TXE releases the CPU out of reset a pointer to the constructed
FIT in SRAM is patched into the loaded bootblock at offset 4G - 64B.
Since this patched bootblock gets measured during runtime it will not
match the one that is potentially measured from the coreboot image.
This patch adds a dedicated fit.c file for Apollo Lake where the FIT
pointer is already set to the address TXE will be using at runtime.
Test=Compare sha256 sum from coreboot runtime and coreboot.rom of the
bootblock and make sure they match.
Change-Id: Ia0fd2a19517c70f50ef37e6a2dc2408bae28df10
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On Apollo Lake the bootblock is stitched into the IBBL IFWI region at
build time. At execution time TXE loads this IBBL into a shared SRAM
(which is read-only in this phase) and maps it at 4 GiB - 32 KiB. Then
the CPU starts to operate from this shared SRAM as it were flash space.
In order to provide a reliable CRTM init, the real executed bootblock
code needs to be measured into TPM if VBOOT is selected. This patch adds
the needed code to do this.
Change-Id: Ifb3f798de638a85029ebfe0d1b65770029297db3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On platforms where the bootblock is not included in CBFS anymore
(because it is part of another firmware section (IFWI or a different
CBFS), the CRTM measurement fails.
This patch adds a new function to provide a way at SoC level to measure
the bootblock. Following patches will add functionality to retrieve the
bootblock from the SoC related location and measure it from there.
In this way the really executed code will be measured.
Change-Id: I6d0da1e95a9588eb5228f63151bb04bfccfcf04b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the boot flash MMIO window to the resources to report this region as
reserved to the OS. This is done to stay consistent with the reserved
memory ranges by coreboot and make the OS aware of them.
As x86 systems preserves the upper 16 MiB below 4G for BIOS flash
decoding use the complete window for reporting independent of the
actually used SPI flash size. This will block the preserved MMIO window.
Change-Id: Ib3a77e9233c3c63bad4de926670edb4545ceaddf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add DPTF passive and critical policies for ADL-N Nivviks design.
Temperature threshold for triggering Passive Policy is set to 75C and Critical Policy is set to 85C respectively for TSR0/1.
BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board.
Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
Change-Id: I5c9b9e8c2489c7da501ca136e2aa6fbc764bf400
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64466
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All non x86 platforms use bootblock in FMAP (see Makefile.inc). Add a
build time check for that so that all the other possibilities (CBFS or
other places for the bootblock) are dropped at build time.
Change-Id: Ic18336a0b79b5d319c2cdfecb7e1eeb89d241206
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
