[WIP] mb/system76/oryp4: Add System76 Oryx Pro 4

Change-Id: I879352c61e041ffefa87e1307e2b650a30f826a4
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
---ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS

.gitignore

@@ -33,7 +33,6 @@ tags
 .clang_complete
 .cache
 compile_commands.json
-.vscode/
 
 # Cross-compile toolkits
 xgcc/

.gitmodules

@@ -61,7 +61,3 @@
 	path = 3rdparty/stm
 	url = ../STM
 	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = ../goswid
-	branch = trunk

AUTHORS

@@ -108,7 +108,6 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
-Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

Documentation/RFC/intel-gpio-cleanup.md

@@ -51,7 +51,7 @@ index 28e78fb366..0cce41b316 100644
 @@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
                 /* Patch GPIO settings for SoC specifically */
                 soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
-
+ 
 -               if (CONFIG(DEBUG_GPIO))
 +               if (soc_pad_conf != pad_conf)
                         printk(BIOS_DEBUG,

Documentation/acpi/devicetree.md

@@ -1,4 +1,82 @@
-# Driver Devicetree Entries
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+### Naming and referencing devices
+
+When declaring a device, it can optionally be given an alias that can be
+referred to elsewhere. This is particularly useful to declare a device in one
+device tree while allowing its configuration to be more easily changed in an
+overlay. For instance, the AMD Picasso SoC definition
+(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
+by default:
+
+```
+chip soc/amd/picasso
+	device domain 0 on
+		...
+		device pci 00.2 alias iommu off end
+		...
+	end
+end
+```
+
+A device based on this SoC can override the configuration for the IOMMU without
+duplicating addresses, as in
+`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
+
+```
+chip soc/amd/picasso
+	device domain 0
+		...
+		device ref iommu on end
+		...
+	end
+end
+```
+
+In this example the override simply enables the IOMMU, but it could also
+set additional properties (or even add child devices) inside the IOMMU `device`
+block.
+
+---
+
+It is important to note that devices that use `device ref` syntax to override
+previous definitions of a device by alias must be placed at **exactly the same
+location in the device tree** as the original declaration. If not, this will
+actually create another device rather than overriding the properties of the
+existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
+were written as follows:
+
+```
+chip soc/amd/picasso
+	# NOTE: not inside domain 0!
+	device ref iommu on end
+end
+```
+
+Then this would leave the SoC's IOMMU disabled, and instead create a new device
+with no properties as a direct child of the SoC.
+
+## Device drivers
 
 Let's take a look at an example entry from
 ``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
@@ -9,7 +87,6 @@ device pci 15.0 on
 		register "hid" = ""ELAN0000""
 		register "desc" = ""ELAN Touchpad""
 		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
 		register "wake" = "GPE0_DW0_21"
 		device i2c 15 on end
 	end
@@ -141,31 +218,6 @@ find the names in your SoC's header file.  The ACPI_* macros are defined in
 Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
 This is often done in a mainboard-specific file named ``gpio.c``.
 
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. While no
-boards in the tree currently implement this, it has been used in downstream
-forks without issue for some time now.
-
 ### wake
 
 The last register is:
@@ -232,7 +284,7 @@ Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
 
 ## Notes
 
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/acpi/index.md

@@ -10,3 +10,7 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
+
+## devicetree
+
+- [Adding devices to a device tree](devicetree.md)

Documentation/acronyms.md

@@ -278,7 +278,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* edk2 - EFI Development Kit 2
+* EDK2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was

Documentation/community/forums.md

@@ -31,7 +31,7 @@ topics, including community and technical matters that benefit from
 an official decision.
 
 We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
+best with [Google Meet](https://meet.google.com/syn-toap-agu),
 using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
 for the agenda and meeting minutes. Neither the video conference nor
 the document require a Google account to participate, although editing

Documentation/contributing/coding_style.md

@@ -1002,7 +1002,7 @@ The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
 <https://duckduckgo.com/?q=isbn+0-13-110362-8> or
-<https://www.google.com/search?q=isbn+0-13-110362-8>
+<https://www.google.com/search?q=isbn+0-13-110362-8.
 
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.

Documentation/contributing/project_ideas.md

@@ -87,7 +87,7 @@ across architectures.
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
+to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
 yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a

Documentation/distributions.md

@@ -37,15 +37,15 @@ firmware binaries on [GitHub](https://pcengines.github.io).
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
 built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
+use Tianocore as the payload and include an NVRAM option to disable the
+Intel Management Engine.
 
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and
 servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
+distribution of coreboot, EDK2, and System76 firmware applications.
 
 ### Purism
 
@@ -76,7 +76,7 @@ trustworthiness for all.
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

Documentation/drivers/cbfs_smbios.md

@@ -1,65 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt

Documentation/drivers/dptf.md

@@ -43,7 +43,7 @@ This policy monitors the temperature of participants and controls fans to spin
 at varying speeds. These speeds are defined by the platform, and will be enabled
 depending on the various temperatures reported by participants.
 
-## Note about units
+# Note about units
 
 ACPI uses unusual units for specifying various physical measurements. For
 example, temperatures are specified in 10ths of a degree K, and time is measured
@@ -69,7 +69,7 @@ data was a 0). The following Methods were removed:
 2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
    specified in the devicetree entries or by calling the DPTF acpigen API).
 
-## ACPI Tables
+# ACPI Tables
 
 DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
 application. We will discuss the more important ones here.
@@ -108,7 +108,7 @@ various informational properties.
 This table describes performance states supported by a participant (typically
 the battery charger).
 
-## ACPI Methods
+# ACPI Methods
 
 The Active and Passive policies also provide for short Methods to define
 different kinds of temperature thresholds.
@@ -141,7 +141,7 @@ a "graceful shutdown".
 
 These are optional, and are enabled by selecting the Critical Policy.
 
-## How to use the devicetree entries
+# How to use the devicetree entries
 
 The `drivers/intel/dptf` chip driver is organized into several sections:
 - Policies
@@ -151,7 +151,7 @@ The `drivers/intel/dptf` chip driver is organized into several sections:
 The Policies section (`policies.active`, `policies.passive`, and
 `policies.critical`) is where the components of each policy are defined.
 
-### Active Policy
+## Active Policy
 
 Each Active Policy is defined in terms of 4 parts:
 1) A Source (this is implicitly defined as TFN1, the system fan)
@@ -182,7 +182,7 @@ the CPU's active cooling capability). When the CPU temperature first crosses
 rest of the table (note that it *must* be defined from highest temperature/
 percentage on down to the lowest).
 
-### Passive Policy
+## Passive Policy
 
 Each Passive Policy is defined in terms of 5 parts:
 1) Source - The device that can be throttled
@@ -201,7 +201,7 @@ This example sets up a policy to begin throttling the charger performance when
 temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
 The Priority is defaulted to 100 in this case.
 
-### Critical Policy
+## Critical Policy
 
 Each Critical Policy is defined in terms of 3 parts:
 1) Source - A device that can trigger a critical event
@@ -218,7 +218,7 @@ register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
 This example sets up a policy wherein ACPI will cause the system to shutdown
 (in a "graceful" manner) when the CPU temperature reaches 75C.
 
-### Power Limits
+## Power Limits
 
 Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
 that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
@@ -244,7 +244,7 @@ This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
 over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
 increments of 200 mW.
 
-### Charger Performance
+## Charger Performance
 
 The battery charger can be a large contributor of unwanted heat in a system that
 has one. Controlling the rate of charging is another tool that DPTF uses to enact
@@ -266,7 +266,7 @@ register "controls.charger_perf[3]" = "{   8,  500 }"
 In this example, when DPTF decides to throttle the charger, it has four different
 performance states to choose from.
 
-### Fan Performance
+## Fan Performance
 
 When using DPTF, the system fan (`TFN1`) is the device responsible for actively
 cooling the other temperature sensors on the mainboard. A fan speed table can be
@@ -298,21 +298,21 @@ increment of 10 percentage points. This is common when specifying fine-grained
 control of the fan, wherein DPTF will interpolate between the percentages in the
 table for a given temperature threshold.
 
-### Options
+## Options
 
-#### Fan
+### Fan
 1) Fine-grained control - a boolean (see Fan Performance section above)
 2) Step-size - Recommended minimum step size (in percentage points) to adjust
    the fan speed when using fine-grained control (ranges from 1 - 9).
 3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
    fan device if a low fan speed is detected.
 
-#### Temperature sensors
+### Temperature sensors
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
 
-### OEM Variables
+## OEM Variables
 Platform vendors can define an array of OEM-specific values as OEM variables
 to be used under DPTF policy. There are total six OEM variables available.
 These can be used in AP policy for more specific actions. These OEM variables

Documentation/drivers/index.md

@@ -4,14 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code across platforms.
 
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
-
 * [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
 * [SoundWire](soundwire.md)
+* [SMMSTOREv2](smmstorev2.md)
 * [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)

Documentation/drivers/ipmi_kcs.md

@@ -42,15 +42,6 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/retimer.md

@@ -1,6 +1,6 @@
 # USB4 Retimers
 
-## Introduction
+# Introduction
 As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
 newer revisions of the spec), it becomes more difficult to maintain signal
 integrity for longer traces. Devices such as retimers and redrivers can be used
@@ -17,7 +17,7 @@ by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
 this is a digital component, it may have firmware.
 
 
-## Driver Usage
+# Driver Usage
 
 Some operating systems may have the ability to update firmware on USB4 retimers,
 and ultimately will need some way to power the device on and off so that its new

Documentation/drivers/smmstorev2.md

@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
+EDK2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

Documentation/getting_started/devicetree.md

@@ -1,87 +0,0 @@
-# Adding new devices to a device tree
-
-## Introduction
-
-ACPI exposes a platform-independent interface for operating systems to perform
-power management and other platform-level functions.  Some operating systems
-also use ACPI to enumerate devices that are not immediately discoverable, such
-as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
-the way that coreboot uses the concept of a "device tree" to generate ACPI
-tables for usage by the operating system.
-
-## Devicetree and overridetree (if applicable)
-
-For mainboards that are organized around a "reference board" or "baseboard"
-model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
-typically a devicetree.cb file that all boards share, and any differences for a
-specific board ("variant") are captured in the overridetree.cb file.  Any
-settings changed in the overridetree take precedence over those in the main
-devicetree.  Note, not all mainboards will have the devicetree/overridetree
-distinction, and may only have a devicetree.cb file.  Or you can always just
-write the ASL (ACPI Source Language) code yourself.
-
-### Naming and referencing devices
-
-When declaring a device, it can optionally be given an alias that can be
-referred to elsewhere. This is particularly useful to declare a device in one
-device tree while allowing its configuration to be more easily changed in an
-overlay. For instance, the AMD Picasso SoC definition
-(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
-by default:
-
-```
-chip soc/amd/picasso
-	device domain 0 on
-		...
-		device pci 00.2 alias iommu off end
-		...
-	end
-end
-```
-
-A device based on this SoC can override the configuration for the IOMMU without
-duplicating addresses, as in
-`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
-
-```
-chip soc/amd/picasso
-	device domain 0
-		...
-		device ref iommu on end
-		...
-	end
-end
-```
-
-In this example the override simply enables the IOMMU, but it could also
-set additional properties (or even add child devices) inside the IOMMU `device`
-block.
-
----
-
-It is important to note that devices that use `device ref` syntax to override
-previous definitions of a device by alias must be placed at **exactly the same
-location in the device tree** as the original declaration. If not, this will
-actually create another device rather than overriding the properties of the
-existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
-were written as follows:
-
-```
-chip soc/amd/picasso
-	# NOTE: not inside domain 0!
-	device ref iommu on end
-end
-```
-
-Then this would leave the SoC's IOMMU disabled, and instead create a new device
-with no properties as a direct child of the SoC.
-
-## Device drivers
-
-Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
-
-## Notes
-
- - **All fields that are left unspecified in the devicetree are initialized to
-   zero.**

Documentation/getting_started/index.md

@@ -6,4 +6,3 @@
 * [Kconfig](kconfig.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
-* [Adding devices to a device tree](devicetree.md)

Documentation/index.md

@@ -26,7 +26,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, edk2, which provides UEFI services,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -1,4 +1,4 @@
-# Pademelon board
+# Padmelon board
 
 ## Specs (with Merlin Falcon SOC)
 
@@ -18,7 +18,7 @@
 
 ## Mainboard
 
-![mainboard][pademelon]
+![mainboard][padmelon]
 
 Three items are marked in this picture
 1. dediprog header
@@ -27,7 +27,7 @@ Three items are marked in this picture
 
 ## Back panel
 
-![back panel][pademelon_io]
+![back panel][padmelon_io]
 
 * The lower serial port is UART A (debug serial)
 
@@ -65,9 +65,9 @@ Three items are marked in this picture
 
 ```eval_rst
 +----------------------------+----------------------------------------+
-|pademelon.jpg               | Motherboard with components identified |
+|padmelon.jpg                | Motherboard with components identified |
 +----------------------------+----------------------------------------+
-|pademelon_io.jpg            | Back panel picture                     |
+|padmelon_io.jpg             | Back panel picture                     |
 +----------------------------+----------------------------------------+
 ```
 
@@ -76,5 +76,5 @@ Three items are marked in this picture
 [Merlin Falcon BKDG][merlinfalcon]
 
 [merlinfalcon]: ../../../soc/amd/family15h.md
-[pademelon]: pademelon.jpg
-[pademelon_io]: pademelon_io.jpg
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -37,7 +37,7 @@ easy to remove and reflash.
 
 ## Working
 
-- PS/2 keyboard with SeaBIOS & edk2 (in Mint 18.3/19.1)
+- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
 
 - Rear/front headphones connector audio & mic
 
@@ -57,7 +57,7 @@ easy to remove and reflash.
        port 3        port 5         port 1             port 8
        port 4        port 6         port 2             port 7
 
-- NVME SSD boot on PCIe-x16/x8/4x slot using edk2
+- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
   (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
 
 - CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
@@ -89,7 +89,7 @@ easy to remove and reflash.
 - If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
   as IGP's UMA could be reconfigured by the blob
 
-- Using edk2 + a PCIe GPU under Windows crashes with an
+- Using TianoCore + a PCIe GPU under Windows crashes with an
   ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
   works perfectly
 
@@ -105,9 +105,9 @@ easy to remove and reflash.
 
 ## Not working
 
-- PS/2 keyboard in Win10 using edk2 (please see [Known issues])
-- PS/2 mouse using edk2
-- PCIe graphics card on Windows and edk2 (throws critical ACPI_BIOS_ERROR)
+- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
+- PS/2 mouse using Tianocore
+- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
 
 ## Native raminit compatibility
 

Documentation/mainboard/facebook/monolith.md

@@ -104,11 +104,11 @@ solution. Wires need to be connected to be able to flash using an external progr
 - SMBus
 - Initialization with FSP
 - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
-- edk2 payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
+- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
 - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
 - eMMC
 
-All of the above has been briefly tested by booting Linux from eMMC using the edk2 payload
+All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
 and LinuxBoot.
 
 SeaBios has been checked to the extend that it runs to the boot selection and provides display

Documentation/mainboard/hp/folio_9480m.md

@@ -130,7 +130,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 - Arch Linux with Linux 5.8.9
 - Memory initialization with mrc.bin version 1.6.1 Build 2
 - Graphics initialization with libgfxinit
-- Payload: SeaBIOS, edk2
+- Payload: SeaBIOS, Tianocore
 - EC firmware
   - KBC Revision 92.15 from OEM firmware version 01.33
   - KBC Revision 92.17 from OEM firmware version 01.50

Documentation/mainboard/hp/z220_sff.md

@@ -44,17 +44,8 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.
 
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
-otherwise there's not enough space near the flash.
-
-In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
-be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
-interfere.
-
-## Side note
-The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
-that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
-even interchangeable, so should do coreboot images built for them.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
 
 ## Technology
 
@@ -75,6 +66,5 @@ even interchangeable, so should do coreboot images built for them.
 ```
 
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
-[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -11,7 +11,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [G43T-AM3](acer/g43t-am3.md)
 
 ## AMD
-- [pademelon](amd/pademelon/pademelon.md)
+- [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
@@ -146,6 +146,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
+- [Rotundu](opencellular/rotundu.md)
 
 ## PC Engines
 

Documentation/mainboard/kontron/mal10.md

@@ -45,7 +45,7 @@ make
 ```
 ## Payloads
 - SeaBIOS
-- edk2
+- Tianocore
 - Linux as payload
 
 ## Flashing coreboot

Documentation/mainboard/opencellular/rotundu.md

@@ -0,0 +1,76 @@
+# Rutundu
+
+This page describes how to run coreboot on the [Rotundu] compute board
+from [OpenCellular].
+
+## TODO
+
+* Configure UART
+* EC interface
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25Q128    |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit.
+Directly connecting a Pomona test-clip on the flash is also possible.
+
+**Closeup view of SOIC-8 flash IC**
+
+![][rotundu_flash]
+
+[rotundu_flash]: rotundu_flash.jpg
+
+**SPI header**
+
+![][rotundu_header2]
+
+[rotundu_header2]: rotundu_header2.jpg
+
+**SPI header pinout**
+
+Dediprog compatible pinout.
+
+![][rotundu_j16]
+
+[rotundu_j16]: rotundu_j16.png
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Baytrail                                   |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Rotundu]: https://github.com/Telecominfraproject/OpenCellular
+[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/purism/librem_14.md

@@ -92,7 +92,7 @@ located underneath the Wi-Fi module, below the left cooling fan.
 
  * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
  * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), and Heads payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * M.2 storage (NVMe, SATA III)

Documentation/mainboard/purism/librem_mini.md

@@ -107,7 +107,7 @@ desoldering it from the mainboard.
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
    (no libgfxinit support yet)
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe

Documentation/payloads.md

@@ -23,11 +23,13 @@ When chainloaded from GRUB2, the following menuentry could be used:
         module /vgaroms/seavgabios.bin
     }
 
-## edk2
+## Tianocore
 
-[edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,
-cross-platform firmware development environment for the UEFI and UEFI
-Platform Initialization (PI) specifications.
+[Tianocore](https://www.tianocore.org) is the open source reference
+implementation of the UEFI Specifications that modern firmware for PCs is
+based on. There were various projects in the past to make it suitable as a
+coreboot payload, but these days this function is available directly in the
+UefiPayloadPkg part of its source tree.
 
 ## GRUB2
 

Documentation/releases/boards_supported_on_branches.md

@@ -42,449 +42,249 @@ Branch created, builder configured
 
 ## [4.13 Release](coreboot-4.13-relnotes.md)
 Tag only
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | intel/cannonlake_rvp        | INTEL_CANNONLAKE       | 2017-07-19 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
+
 
 ## [4.12 Release](coreboot-4.12-relnotes.md)
 
 Branch created, builder configured
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | bap/ode_e21XX               | AMD_PI_00730F01        | 2016-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/toucan-af           | AMD_FAMILY14           | 2013-03-02 | half     |
-+-----------------------------+------------------------+------------+----------+
 | ocp/sonorapass              | INTEL_COOPERLAKE_SP    | 2020-05-01 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
+
 
 ## [4.11 Release](coreboot-4.11-relnotes.md)
 
 Branch created, builder configured
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | adi/rcc-dff                 | INTEL_FSP_RANGELEY     | 2016-06-08 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | advansus/a785e-i            | AMD_AMDFAM10           | 2011-05-07 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | amd/bettong                 | AMD_PI_00660F01        | 2015-06-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/bimini_fam10            | AMD_AMDFAM10           | 2011-01-01 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/db-ft3b-lc              | AMD_PI_00730F01        | 2016-07-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/gardenia                | AMD_STONEYRIDGE_FP4    | 2016-12-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/lamar                   | AMD_PI_00630F01        | 2015-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/mahogany_fam10          | AMD_AMDFAM10           | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/olivehillplus           | AMD_PI_00730F01        | 2014-09-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/serengeti_cheetah_fam10 | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | amd/tilapia_fam10           | AMD_AMDFAM10           | 2010-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/torpedo                 | AMD_FAMILY12           | 2011-06-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | asus/kcma-d8                | AMD_AMDFAM10           | 2016-02-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/kfsn4-dre              | AMD_AMDFAM10           | 2015-01-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/kgpe-d16               | AMD_AMDFAM10           | 2015-10-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a785-m               | AMD_AMDFAM10           | 2010-09-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a785t-m              | AMD_AMDFAM10           | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a78-em               | AMD_AMDFAM10           | 2010-12-06 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m5a88-v                | AMD_AMDFAM10           | 2011-10-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | avalue/eax-785e             | AMD_AMDFAM10           | 2011-09-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | esd/atom15                  | INTEL_FSP_BAYTRAIL     | 2015-12-04 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | facebook/watson             | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server   |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma785gm            | AMD_AMDFAM10           | 2012-04-23 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma785gmt           | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma78gm             | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | google/urara                | IMGTEC_PISTACHIO       | 2015-03-27 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl165_g6_fam10           | AMD_AMDFAM10           | 2010-09-24 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iei/kino-780am2-fam10       | AMD_AMDFAM10           | 2010-09-13 | half     |
-+-----------------------------+------------------------+------------+----------+
 | intel/bayleybay_fsp         | INTEL_FSP_BAYTRAIL     | 2014-05-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/littleplains          | INTEL_FSP_RANGELEY     | 2015-11-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/minnowmax             | INTEL_FSP_BAYTRAIL     | 2014-08-11 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | intel/mohonpeak             | INTEL_FSP_RANGELEY     | 2014-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | jetway/pa78vm5              | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9652_fam10            | AMD_AMDFAM10           | 2010-03-01 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | ocp/monolake                | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | ocp/wedge100s               | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | opencellular/rotundu        | INTEL_FSP_BAYTRAIL     | 2018-06-26 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_bdx1             | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL     | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL_MD  | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dmr_fam10      | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8qme_fam10      | AMD_AMDFAM10           | 2010-02-03 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8scm_fam10      | AMD_AMDFAM10           | 2011-03-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2912_fam10            | AMD_AMDFAM10           | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m850               | VIA_NANO               | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m850               | VIA_VX900              | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.10 Release](coreboot-4.10-relnotes.md)
 Branch created
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | cubietech/cubieboard        | ALLWINNER_A10          | 2014-01-08 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.9 Release](coreboot-4.9-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | pcengines/alix1c            | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix1c            | AMD_LX                 | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix2d            | AMD_GEODE_LX           | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix2d            | AMD_LX                 | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | aaeon/pfm-540i_revb         | AMD_GEODE_LX           | 2011-06-29 | half     |
-+-----------------------------+------------------------+------------+----------+
 | amd/db800                   | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/dbm690t                 | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/f2950                   | AMD_GEODE_LX           | 2016-07-17 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | amd/mahogany                | AMD_AMDK8              | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/norwich                 | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/pistachio               | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/serengeti_cheetah       | AMD_AMDK8              | 2009-08-12 | server   |
-+-----------------------------+------------------------+------------+----------+
 | artecgroup/dbe61            | AMD_GEODE_LX           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | asrock/939a785gmh           | AMD_AMDK8              | 2010-04-05 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8n_e                  | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8v-e_deluxe           | AMD_AMDK8              | 2010-11-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8v-e_se               | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/k8v-x                  | AMD_AMDK8              | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/kfsn4-dre_k8           | AMD_AMDK8              | 2015-10-30 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2n-e                  | AMD_AMDK8              | 2010-12-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2v                    | AMD_AMDK8              | 2010-11-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2v-mx_se              | AMD_AMDK8              | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | bachmann/ot200              | AMD_GEODE_LX           | 2012-07-13 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | bcom/winnetp680             | VIA_C7                 | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | broadcom/blast              | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | digitallogic/msm800sev      | AMD_GEODE_LX           | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga_2761gxdk        | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/m57sli             | AMD_AMDK8              | 2009-10-03 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | google/purin                | BROADCOM_CYGNUS        | 2015-04-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rotor                | MARVELL_MVMAP2315      | 2016-09-13 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/zoombini             | INTEL_CANNONLAKE       | 2017-09-28 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl145_g1                 | AMD_AMDK8              | 2010-08-20 | server   |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl145_g3                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iei/pcisa-lx-800-r10        | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | iei/pm-lx2-800-r10          | AMD_GEODE_LX           | 2012-10-28 | half     |
-+-----------------------------+------------------------+------------+----------+
 | iei/pm-lx-800-r11           | AMD_GEODE_LX           | 2012-07-06 | half     |
-+-----------------------------+------------------------+------------+----------+
 | intel/cougar_canyon2        | INTEL_FSP_IVYBRIDGE    | 2013-12-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/stargo2               | INTEL_FSP_IVYBRIDGE    | 2015-11-10 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8_htx               | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | jetway/j7f2                 | VIA_C7                 | 2014-01-19 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | kontron/kt690               | AMD_AMDK8              | 2009-10-15 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/hurricane-lx        | AMD_GEODE_LX           | 2010-09-10 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/literunner-lx       | AMD_GEODE_LX           | 2010-09-07 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/roadrunner-lx       | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/spacerunner-lx      | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lowrisc/nexys4ddr           | LOWRISC_LOWRISC        | 2016-10-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms7135                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms7260                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9185                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9282                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | nvidia/l1_2pvv              | AMD_AMDK8              | 2009-10-07 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/sitemp_g1p1         | AMD_AMDK8              | 2011-05-11 | half     |
-+-----------------------------+------------------------+------------+----------+
 | sunw/ultra40                | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | sunw/ultra40m2              | AMD_AMDK8              | 2015-11-10 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dme            | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dmr            | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | technexion/tim5690          | AMD_AMDK8              | 2009-10-13 | half     |
-+-----------------------------+------------------------+------------+----------+
 | technexion/tim8690          | AMD_AMDK8              | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | traverse/geos               | AMD_GEODE_LX           | 2010-05-20 | half     |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2912                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-cn                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m700               | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/pc2500e                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/vt8454c                 | VIA_C7                 | 2009-08-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | winent/mb6047               | AMD_AMDK8              | 2013-10-19 | half     |
-+-----------------------------+------------------------+------------+----------+
 | winent/pl6064               | AMD_GEODE_LX           | 2010-02-24 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | winnet/g170                 | VIA_C7                 | 2017-08-28 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.7 Release](coreboot-4.7-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | abit/be6-ii_v2_0            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | amd/dinar                   | AMD_FAMILY15           | 2012-02-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/rumba                   | AMD_GEODE_GX2          | 2009-08-29 | half     |
-+-----------------------------+------------------------+------------+----------+
 | asus/dsbf                   | INTEL_I5000            | 2012-07-14 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/mew-am                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/mew-vm                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | a-trend/atc-6220            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | a-trend/atc-6240            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | azza/pt-6ibd                | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | biostar/m6tba               | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | compaq/deskpro_en_sff_p600  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | dmp/vortex86ex              | DMP_VORTEX86EX         | 2013-07-05 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | ecs/p6iwp-fe                | INTEL_I82810           | 2010-06-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga-6bxc            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga-6bxe            | INTEL_I440BX           | 2010-05-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | hp/e_vectra_p2706t          | INTEL_I82810           | 2009-10-20 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | intel/d810e2cb              | INTEL_I82810           | 2010-06-21 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | intel/eagleheights          | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/mtarvon               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/truxton               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwave/iWRainbowG6           | INTEL_SCH              | 2010-12-18 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lanner/em8510               | INTEL_I855             | 2010-08-30 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | lippert/frontrunner         | AMD_GEODE_GX2          | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | mitac/6513wu                | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6119                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6147                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6156                  | INTEL_I440BX           | 2009-10-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6178                  | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | nec/powermate2000           | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | nokia/ip530                 | INTEL_I440BX           | 2010-04-19 | server   |
-+-----------------------------+------------------------+------------+----------+
 | rca/rm4100                  | INTEL_I82830           | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | soyo/sy-6ba-plus-iii        | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8qgi            | AMD_FAMILY15           | 2011-07-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8scm            | AMD_FAMILY15           | 2012-11-30 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/x7db8            | INTEL_I5000            | 2012-06-23 | server   |
-+-----------------------------+------------------------+------------+----------+
 | thomson/ip1000              | INTEL_I82830           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s1846                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s8226                  | AMD_FAMILY15           | 2012-10-04 | server   |
 | wyse/s50                    | AMD_GEODE_GX2          | 2010-05-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.6](coreboot-4.6-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | bifferos/bifferboard        | RDC_R8610              | 2012-03-27 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/cosmos               | MARVELL_BG4CD          | 2015-04-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/bakersport_fsp        | INTEL_FSP_BAYTRAIL     | 2014-08-11 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.5](coreboot-4.5-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | google/enguarde             | INTEL_BAYTRAIL         | 2016-09-21 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/falco                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/guado                | INTEL_BROADWELL        | 2016-01-12 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/ninja                | INTEL_BAYTRAIL         | 2016-05-31 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/panther              | INTEL_HASWELL          | 2014-07-12 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/peppy                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/rikku                | INTEL_BROADWELL        | 2016-06-16 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/samus                | INTEL_BROADWELL        | 2014-08-29 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/tidus                | INTEL_BROADWELL        | 2016-01-21 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.4](coreboot-4.4-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | google/bolt                 | INTEL_HASWELL          | 2013-12-12 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rush                 | NVIDIA_TEGRA132        | 2015-01-26 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rush_ryu             | NVIDIA_TEGRA132        | 2015-03-05 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/slippy               | INTEL_HASWELL          | 2013-11-24 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/amenia                | INTEL_APOLLOLAKE       | 2016-04-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.3](coreboot-4.3-relnotes.md)
@@ -496,51 +296,28 @@ Branch created
 ## [4.2](coreboot-4.2-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | arima/hdama                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | digitallogic/adl855pc       | INTEL_I855             | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
 | ibm/e325                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | ibm/e326                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | intel/sklrvp                | INTEL_SKYLAKE          | 2015-07-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8s2                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8x                  | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | newisys/khepri              | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2735                  | INTEL_E7501            | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2850                  | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2875                  | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2881                  | AMD_AMDK8              | 2009-09-23 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2885                  | AMD_AMDK8              | 2009-10-08 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2891                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2892                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2895                  | AMD_AMDK8              | 2009-09-22 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s4880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s4882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.1](coreboot-4.1-relnotes.md)

Documentation/releases/coreboot-4.15-relnotes.md

@@ -52,9 +52,9 @@ Deprecations and incompatible changes
 
 Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
 updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
-to build from upstream edk2 master. Drop the EDK2_USE_8254_TIMER Kconfig
+to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
 option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
-that we're only building from a single edk2 package/target.
+that we're only building from a single Tianocore package/target.
 
 ### Remove old lp4x and ddr4 versions of spd_tools
 

Documentation/releases/coreboot-4.18-relnotes.md

@@ -1,190 +1,51 @@
-Upcoming release - coreboot 4.18 release
-========================================================================
+Upcoming release - coreboot 4.18
+================================
 
-The 4.18 release is quite late, but is now planned for October 16, 2022.
+The 4.18 release is planned for August 2022.
 
-In the past 4 months since the 4.17 release, the coreboot project has
-merged more than 1800 commits from over 200 different authors. Over 50
-of those authors submitted their first patches.
+Update this document with changes that should be in the release notes.
 
-Welcome and thank you to all of our new contributors, and of course the
-work of all of the seasoned contributors is greatly appreciated.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here
 
 
-Significant or interesting changes
-----------------------------------
-
-### sconfig: Allow to specify device operations
-
-Currently we only have runtime mechanisms to assign device operations to
-a node in our devicetree (with one exception: the root device). The most
-common method is to map PCI IDs to the device operations with a `struct
-pci_driver`. Another accustomed way is to let a chip driver assign them.
-
-For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
-ID lists grew very large and are incredibly error-prone. Often, IDs are
-missing and sometimes IDs are added almost mechanically without checking
-the code for compatibility. Maintaining these lists in a central place
-also reduces flexibility.
-
-Now, for onboard devices it is actually unnecessary to assign the device
-operations at runtime. We already know exactly what operations should be
-assigned. And since we are using chipset devicetrees, we have a perfect
-place to put that information.
-
-This patch adds a simple mechanism to `sconfig`. It allows us to speci-
-fy operations per device, e.g.
-
-device pci 00.0 alias system_agent on
-	ops system_agent_ops
-end
-
-The operations are given as a C identifier. In this example, we simply
-assume that a global `struct device_operations system_agent_ops` exists.
 
 
-### Set touchpads to use detect (vs probed) flag
-
-Historically, ChromeOS devices have worked around the problem of OEMs
-using several different parts for touchpads/touchscreens by using a
-ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
-to indicate that the device may or may not be present, and that the
-driver should probe to confirm device presence.
-
-Since release 4.18, coreboot  supports detection for i2c devices at
-runtime when creating the device entries for the ACPI/SSDT tables,
-rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
-in the tree from using the 'probed' flag to the 'detect' flag.
-
-Touchscreens require more involved power sequencing, which will be done
-at some future time, after which they will switch over as well.
 
 
-### Add SBOM (Software Bill of Materials) Generation
-
-Firmware is typically delivered as one large binary image that gets
-flashed. Since this final image consists of binaries and data from a
-vast number of different people and companies, it's hard to determine
-what all the small parts included in it are. The goal of the software
-bill of materials (SBOM) is to take a firmware image and make it easy to
-find out what it consists of and where those pieces came from.
-
-Basically, this answers the question, who supplied the code that's
-running on my system right now? For example, buyers of a system can use
-an SBOM to perform an automated vulnerability check or license analysis,
-both of which can be used to evaluate risk in a product. Furthermore,
-one can quickly check to see if the firmware is subject to a new
-vulnerability included in one of the software parts (with the specified
-version) of the firmware.
-
-Further reference:
-https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
-
-- Add Makefile.inc to generate and build coswid tags
-- Add templates for most payloads, coreboot, intel-microcode,
-  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
-  intel ME and compiler (gcc,clang,other)
-- Add Kconfig entries to optionally supply a path to CoSWID tags
-  instead of using the default CoSWID tags
-- Add CBFS entry called SBOM to each build via Makefile.inc
-- Add goswid utility tool to generate SBOM data
 
 
-Additional coreboot changes
----------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Allocator v4 is not yet ready, but received significant work.
-* Console: create an [smbus console driver](https://doc.coreboot.org/technotes/console.html)
-* pciexp_device: Numerous updates and fixes
-* Update checkpatch to match Linux v5.19
-* Continue updating ACPI to ASL 2.0 syntax
-* arch/x86: Add a common romstage entry point
-* Documentation: Add a list of [acronyms](https://doc.coreboot.org/acronyms.html)
-* Start hooking up ops in devicetree
-* Large amounts of general code cleanup and improvement, as always
-* Work to make sure all files have licenses
-
-
-Payloads
---------
-
-### EDK II (TianoCore)
-
-coreboot uses TianoCore interchangeably with EDK II, and whilst the
-meaning is generally clear, it's not the payload it uses.
-Consequentially, TianoCore has been renamed to EDK II (2).
-
-The option to use the already deprecated CorebootPayloadPkg has been
-removed.
-
-Recent changes to both coreboot and EDK means that UefiPayloadPkg seems
-to work on all hardware. It has been tested on:
-
-* Intel Core 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 8th, 9th, 10th,
-  11th and 12th generation processors
-* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
-* AMD Stoney Ridge and Picasso
-
-CorebootPayloadPkg can still be found [here](https://github.com/MrChromebox/edk2/tree/coreboot_fb).
-
-The recommended option to use is `EDK2_UEFIPAYLOAD_MRCHROMEBOX` as
-`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SoC.
-
-
-New Mainboards
---------------
-
-* AMD Birman
-* AMD Pademelon renamed from Padmelon
-* Google Evoker
-* Google Frostflow
-* Google Gaelin4ADL
-* Google Geralt
-* Google Joxer
-* Google Lisbon
-* Google Magikarp
-* Google Morthal
-* Google Pujjo
-* Google Rex 0
-* Google Shotzo
-* Google Skolas
-* Google Tentacruel
-* Google Winterhold
-* Google Xivu
-* Google Yaviks
-* Google Zoglin
-* Google Zombie
-* Google Zydron
-* MSI PRO Z690-A WIFI DDR4
-* Siemens MC APL7
-
-
-Removed Mainboards
-------------------
-
-* Google Brya4ES
-
-
-Updated SoCs
-------------
-
-* Added Intel Meteor Lake
-* Added Mediatek Mt8188
-* Renamed AMD Sabrina to Mendocino
-* Added AMD Morgana
 
 
 Plans for Code Deprecation
 --------------------------
 
+
+### Intel Icelake
+
+Intel Icelake code will be removed following the 4.19 release, planned
+for November 2022. This consists of the Intel Icelake SOC and Intel
+Icelake RVP mainboard
+
+Intel Icelake is unmaintained. Also, the only user of this platform ever
+was the CRB board. From the looks of it the code never was ready for
+production as only engineering sample CPUIDs are supported. This reduces
+the maintanence overhead for the coreboot project.
+
+
 ### LEGACY_SMP_INIT
 
 Legacy SMP init will be removed from the coreboot master branch
 immediately following this release. Anyone looking for the latest
-version of the code should find it on the 4.18 branch or tag.
+version of the code should find it on the 4.18 branch.
 
 This also includes the codepath for SMM_ASEG. This code is used to start
 APs and do some feature programming on each AP, but also set up SMM.
@@ -193,44 +54,3 @@ cover all use cases of LEGACY_SMP_INIT, with little code changes. The
 reason for deprecation is that having 2 codepaths to do the virtually
 the same increases maintenance burden on the community a lot, while also
 being rather confusing.
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics
-----------
-
-- Total Commits: 1819
-- Average Commits per day: 13.44
-- Total lines added: 150195
-- Average lines added per commit: 82.57
-- Number of patches adding more than 100 lines: 127
-- Average lines added per small commit: 38.38
-- Total lines removed: 33788
-- Average lines removed per commit: 18.58
-- Total difference between added and removed: 116407

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,64 +0,0 @@
-Upcoming release - coreboot 4.19
-========================================================================
-
-The 4.19 release is planned for January 2023.
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-Significant changes
--------------------
-
-### Add significant changes here
-
-
-
-Additional coreboot changes
----------------------------
-
-* One or two line change comments go here
-
-
-
-Payloads
---------
-
-### Payload changes go here
-
-
-
-Plans for Code Deprecation
---------------------------
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard

Documentation/releases/coreboot-4.6-relnotes.md

@@ -55,15 +55,15 @@ is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
 
 ### UEFI support: A long road to go
 
-coreboot can be used with the edk2 UEFI implementation which
+coreboot can be used with the Tianocore EDK2 UEFI implementation which
 is open source and available at Github. Sadly it is not currently
 integrated into the coreboot build. This has several reasons:
 
-* edk2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
-* Incompatibilities with code inside the edk2 which has not been updated.
+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the EDK2 which has not been updated.
 
 We started to make progress with the integration into our sources and
-the hope is that by the end of the summer, we finally support the edk2
+the hope is that by the end of the summer, we finally support the EDK2
 payload out-of-the- box. See the current patch state at
 http://review.coreboot.org/#/c/15057/
 

Documentation/releases/coreboot-4.7-relnotes.md

@@ -84,7 +84,7 @@ General changes
 
 * Integrate me_cleaner
 * Add flashconsole implementation
-* Build edk2 UEFI payload from upstream source
+* Build Tianocore UEFI payload from upstream source
 * Remove CMOS NVRAM configurable baud rates
 * A common mrc_cache driver to store romstage settings in SPI flash
 

Documentation/releases/coreboot-4.8.1-relnotes.md

@@ -71,7 +71,7 @@ detection
 Payloads
 --------
 * Bumped SeaBIOS to 1.11.1
-* Improved edk2 integration
+* Improved TianoCore integration
 
 Security
 --------

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.19 - Jan 2023](coreboot-4.19-relnotes.md)
+* [4.18 - Aug 2022](coreboot-4.18-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,7 +15,6 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.18 - Oct 2022](coreboot-4.18-relnotes.md)
 * [4.17 - May 2022](coreboot-4.17-relnotes.md)
 * [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -1,7 +1,6 @@
 # vboot-enabled devices
 
 ## AMD
-- Birman
 - Chausie
 - Majolica
 
@@ -36,6 +35,7 @@
 - Anahera4ES
 - Brask
 - Brya 0
+- Brya4ES
 - Felwinter
 - Gimble
 - Gimble4ES
@@ -46,8 +46,6 @@
 - Primus4ES
 - Redrix
 - Redrix4ES
-- Skolas
-- Skolas4ES
 - Taeko
 - Taeko4ES
 - Taniks
@@ -57,26 +55,12 @@
 - Crota
 - Moli
 - Kinox
-- Craask
-- Osiris
-- Mithrax
-- Kuldax
-- Joxer
-- Pujjo
-- Xivu
-- Gaelin4ADL
-- Yaviks
-- Lisbon
-- Zydron
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
-- Steelix
 - Krabby
-- Tentacruel
-- Magikarp
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -88,6 +72,7 @@
 - Terra (ASUS Chromebook C202SA/C300SA/C301SA)
 - Ultima (Lenovo Yoga 11e G3)
 - Wizpig
+- Daisy (Samsung Chromebook (2012))
 - Drallion
 - Eve (Google Pixelbook)
 - Fizz
@@ -95,7 +80,6 @@
 - Endeavour
 - Foster
 - Gale (Google WiFi)
-- Geralt
 - Asuka (Dell Chromebook 13 3380)
 - Caroline (Samsung Chromebook Pro)
 - Cave (Asus Chromebook Flip C302SA)
@@ -113,25 +97,34 @@
 - Nipperkin
 - Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
+- Ambassador
+- Dooly
 - Dratini (HP Pro c640 Chromebook)
+- Duffy Legacy (32MB)
+- Duffy (ASUS Chromebox 4)
+- Faffy (ASUS Fanless Chromebox)
+- Genesis
 - Hatch
 - Helios (ASUS Chromebook Flip C436FA)
 - Helios_Diskswap
 - Jinlon (HP Elite c1030 Chromebook)
+- Kaisa Legacy (32MB)
+- Kaisa (Acer Chromebox CXI4)
 - Kindred (Acer Chromebook 712)
 - Kohaku (Samsung Galaxy Chromebook)
+- Moonbuggy
 - Mushu
 - Nightfury (Samsung Galaxy Chromebook 2)
+- Noibat (HP Chromebox G3)
 - Palkia
+- Puff
+- Scout
+- Wyvern (CTL Chromebox CBx2)
 - Herobrine
 - Herobrine_Rev0
 - Senor
 - Piglin
 - Hoglin
-- Villager
-- Evoker
-- Zoglin
-- Zombie
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
@@ -171,26 +164,14 @@
 - Elm (Acer Chromebook R13)
 - Hana (Lenovo N23 Yoga Chromebook)
 - Parrot (Acer C7/C710 Chromebook)
+- Peach Pit (Samsung Chromebook 2 11\")
 - Atlas (Google Pixelbook Go)
 - Poppy
 - Nami
 - Nautilus (Samsung Chromebook Plus V2, V2 LTE)
 - Nocturne (Google Pixel Slate)
-- Rammus
+- Rammus (Asus Chromebook C425, Flip C433, Flip C434)
 - Soraka (HP Chromebook x2)
-- Ambassador
-- Dooly
-- Duffy Legacy (32MB)
-- Duffy (ASUS Chromebox 4)
-- Faffy (ASUS Fanless Chromebox)
-- Genesis
-- Kaisa Legacy (32MB)
-- Kaisa (Acer Chromebox CXI4)
-- Moonbuggy
-- Noibat (HP Chromebox G3)
-- Puff
-- Scout
-- Wyvern (CTL Chromebox CBx2)
 - Banjo (Acer Chromebook 15 (CB3-531))
 - Candy (Dell Chromebook 11 3120)
 - Clapper (Lenovo N20 Chromebook)
@@ -212,13 +193,8 @@
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
-- Rex 0
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
-- Skyrim
-- Winterhold
-- Morthal
-- Frostflow
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -246,25 +222,6 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Delbin (ASUS Chromebook Flip CX5)
-- Eldrid
-- Halvor
-- Lindar
-- Malefor
-- Terrador
-- Todor
-- Trondo
-- Volteer
-- Volteer2
-- Volteer2_Ti50
-- Voxel (Acer Chromebook Spin 713 (CP713-3W))
-- Elemi (HP Pro c640 G2 Chromebook)
-- Voema
-- Drobit (ASUS Chromebook CX9400)
-- Copano (ASUS Chromebook Flip CX5400)
-- Collis
-- Volet
-- Chronicler
 - Dalboz
 - Vilboz (Lenovo 100e/300e Gen3 AMD)
 - Ezkinil (Acer Chromebook Spin 514)
@@ -277,7 +234,6 @@
 - Gumboz (HP Chromebook x360 14a)
 
 ## HP
-- Z220 CMT Workstation
 - Z220 SFF Workstation
 
 ## Intel
@@ -288,7 +244,6 @@
 - Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
-- Raptorlake silicon with Alderlake-P RVP and Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11
@@ -315,8 +270,6 @@
 - Whitetip Mountain 2 CRB
 
 ## Lenovo
-- ThinkPad T440p
-- ThinkPad W541
 - ThinkPad T400
 - ThinkPad T500
 - ThinkPad R400
@@ -328,6 +281,7 @@
 - ThinkPad T430
 - ThinkPad T430s
 - ThinkPad T431s
+- ThinkPad T440p
 - ThinkPad T520
 - ThinkPad W520
 - ThinkPad T530
@@ -345,9 +299,6 @@
 - ThinkPad X230s
 - ThinkPad X60 / X60s / X60t
 
-## MSI
-- PRO Z690-A WIFI DDR4
-
 ## OpenCellular
 - Elgon (GBCv2)
 
@@ -362,11 +313,6 @@
 - MC APL4
 - MC APL5
 - MC APL6
-- MC APL7
-
-## Star Labs
-- Star Labs Lite Mk III (N5000)
-- Star Labs Lite Mk IV (N5030)
 
 ## Supermicro
 - X11SSH-TF

Documentation/soc/amd/psp_integration.md

@@ -117,23 +117,14 @@ implementations currently use combo tables.
 +--------------+---------------+------------------+----------------------------+
 | Size         | 0x04          | 32               | Size of PSP entry in bytes |
 +--------------+---------------+------------------+----------------------------+
-| Location /   | 0x08          | 62               | Location: Physical Address |
+| Location /   | 0x08          | 64               | Location: Physical Address |
 | Value        |               |                  | of SPIROM location where   |
 |              |               |                  | corresponding PSP entry    |
 |              |               |                  | located.                   |
 |              |               |                  |                            |
-|              |               |                  | Value: 62-bit value for the|
+|              |               |                  | Value: 64-bit value for the|
 |              |               |                  | PSP Entry                  |
 +--------------+---------------+------------------+----------------------------+
-| Address Mode | 0x0F[7:6]     | 2                | 00: x86 Physical address   |
-|              |               |                  | 01: offset from start of   |
-|              |               |                  |     BIOS (flash offset)    |
-|              |               |                  | 02: offset from start of   |
-|              |               |                  |     directory header       |
-|              |               |                  | 03: offset from start of   |
-|              |               |                  |     partition              |
-+--------------+---------------+------------------+----------------------------+
-
 ```
 ### PSP Directory Table Types
 
@@ -181,10 +172,6 @@ implementations currently use combo tables.
 *   Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
     This is mandatory in order to support encrypted firmware.
 
-**0x22**: PSP Token Unlock data
-*   Used to support time-bound Secure Debug unlock during boot.  This entry may
-    be omitted if the Token Unlock debug feature is not required.
-
 **0x24**: Security policy binary
 *   A security policy is applied to restrict the untrusted access to security
     sensitive regions.
@@ -213,6 +200,10 @@ implementations currently use combo tables.
 **0x52**: PSP boot loader usermode OEM application
 *   Supported only in certain SKUs.
 
+**0x22**: PSP Token Unlock data
+*   Used to support time-bound Secure Debug unlock during boot.  This entry may
+    be omitted if the Token Unlock debug feature is not required.
+
 ### Firmware Version of Binaries
 
 Every firmware binary contains 256 bytes of a PSP Header, which includes
@@ -311,25 +302,15 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
 +--------------+---------------+------------------+----------------------------+
 | SubProgram   | 0x03[2:0]     | 3                | Specify the SubProgram     |
 +--------------+---------------+------------------+----------------------------+
-| RomId        | 0x03[4:3]     | 2                | Which SPI device the       |
-|              |               |                  | content is placed in       |
-+--------------+---------------+------------------+----------------------------+
-| Writeable    | 0x03[5]       | 1                | Region is writable or read |
-|              |               |                  | only                       |
-+--------------+---------------+------------------+----------------------------+
-| Reserved     | 0x03[7:6]     | 2                | Reserved - Set to zero     |
+| Reserved     | 0x03[7:3]     | 5                | Reserved - Set to zero     |
 +--------------+---------------+------------------+----------------------------+
 | Size         | 0x04          | 32               | Memory Region Size         |
 +--------------+---------------+------------------+----------------------------+
-| Source       | 0x08          | 62               | Physical Address of SPIROM |
+| Source       | 0x08          | 64               | Physical Address of SPIROM |
 | Address      |               |                  | location where the data for|
 |              |               |                  | the corresponding entry is |
 |              |               |                  | located                    |
 +--------------+---------------+------------------+----------------------------+
-| Entry Address| 0x0F[7:6]     | 2                | Same as Entry Address Mode |
-| Mode         |               |                  | in PSP directory table     |
-|              |               |                  | entry fields               |
-+--------------+---------------+------------------+----------------------------+
 | Destination  | 0x10          | 64               | Destination Address of     |
 | Address      |               |                  | memory location where the  |
 |              |               |                  | data for the corresponding |

Documentation/technotes/console.md

@@ -1,66 +0,0 @@
-# coreboot Console
-
-coreboot supports multiple ways to access its console.
-https://www.coreboot.org/Console_and_outputs
-
-
-## SMBus Console
-
-SMBus is a two-wire interface which is based on the principles of
-operation of I2C. SMBus, was first was designed to allow a battery to
-communicate with the charger, the system host, and/or other
-power-related components in the system.
-
-Enable the SMBus console with `CONSOLE_I2C_SMBUS` Kconfig. Set
-`CONSOLE_I2C_SMBUS_SLAVE_ADDRESS` and
-`CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER` configuration values of the
-slave I2C device which you will use to capture I2C packets.
-
-Modern computer Random Access Memory (RAM) slot has SMBus in it
-according to the JEDEC standards. We can use a breakout-board to expose
-those SMBus pins. Some mainboard have SMBus pins in the PCIe slot as
-well.
-
-This feature has been tested on the following platforms:
-```eval_rst
-+------------------------------------+
-| Tested platforms                   |
-+====================================+
-| GA-H61M-S2PV + Intel Ivy Bridge    |
-+---------------------+---------------
-```
-
-A minimal DDR3 DIMM breakout board PCB design with only the
-SDA(Data line) and SCL(Clock line) pins of I2C/SMBus can be found
-[here](https://github.com/drac98/ram-breakout-board).
-See the PCB layout [here](https://archive.org/details/ddr3-dimm-F_Cu)
-
-NOTE:
-To capture the I2C packets, an I2C slave device is required. The easiest
-way to capture the log message is to use a I2C to UART converter chip
-with a UART to USB converter chip. The setup would be as follows.
-```text
-+---------+    +-------------+    +-------------+
-+   PC    +----+ UART to USB +----+ I2C to UART |
-+---------+    +-------------+    +-------------+
-                                              | |
-------------------------------------------------+--  System Management
-----------------------------------------------+----  Bus
-```
-
-Watch this [video](https://youtu.be/Q0dK41n9db8) to see how it is set
-up. A backup of the video is available
-[here](https://web.archive.org/web/20220916172605/https://www.youtube.com/watch?v=Q0dK41n9db8)
-
-If you are using any of the `SC16IS740/750/760` I2C to UART converter
-chip, you can enable the `SC16IS7XX_INIT` option to initialize the chip.
-
-If not we can use other I2C slave devices like an Arduino or a
-Beagleboard.
-* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/latest/i2c/slave-interface.html)
-* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/beaglebone-black-and-arduino-uno-i2c-communication-using-c/29990/8)
-
-This feature was added as part of a GSoC 2022 project. Checkout the
-following blog posts for more details.
-* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38273691a8ac)
-* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f24)

Documentation/technotes/index.md

@@ -5,4 +5,3 @@
 * [Unit testing coreboot](2020-03-unit-testing-coreboot.md)
 * [Unit Test Code Coverage](2021-05-code-coverage.md)
 * [Address Sanitizer](asan.md)
-* [coreboot Consoles](console.md)

Documentation/tutorial/flashing_firmware/ext_standalone.md

@@ -19,45 +19,5 @@ It is possible to set the onboard flash on hold and use another flash chip.
 Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC
 low, and /HOLD of your replacement flash IC high.
 
-### SPI header
-Some boards feature a pin header which is connected to the SPI bus. This can
-also be used to connect a secondary flash chip.
-
-#### HP boards
-Many HP desktop mainboards have a 2x8 or 2x10 block of header pins which
-can be used to connect a second flash chip. One pin is connected to the
-onboard flash's /CS pin, and another is connected to the chipset's /CS
-pin. Normally a jumper cap is placed between these pins, allowing the
-chipset to access the onboard flash. To use this header, remove this
-jumper and connect all lines except /CS one-to-one with the
-corresponding pin on the header. The secondary flash chip's /CS line
-should be connected to the chipset /CS pin on the header. By doing this
-the secondary SPI flash, rather than the onboard flash, will respond to
-accesses from the chipset.
-
-![][hp_spi_header_pinout]
-
-![][hp_spi_header_mainboard]
-
-Note that on boards where this header is unpopulated, a jumper resistor
-will be populated nearby which serves the purpose of the jumper cap. One
-end should have continuity with the /CS pin on the flash, and the other
-end should have continuity with the chipset /CS pin on the unpopulated
-header. It may also be possible to find this resistor through visual
-inspection of the traces on the /CS pins. This resistor should be
-desoldered if you wish to solder a pin header to the board and connect a
-secondary flash, otherwise the onboard flash will always respond to
-accesses.
-
-#### Other boards
-Other boards may have similar headers, but will likely use a different
-pinout than the ones explicitly mentioned here. Usually such a header
-will be located near the onboard SPI flash. If schematics are available,
-the pinout for the header will likely be found in it, but it could also
-be determined using a multimeter in continuity mode to map out the
-connections between the SPI flash and the header.
-
 
 [EM100Pro]: https://www.dediprog.com/product/EM100Pro
-[hp_spi_header_pinout]: hp_spi_header.svg
-[hp_spi_header_mainboard]: hp_spi_header_mb.jpg

Documentation/tutorial/flashing_firmware/hp_spi_header.svg

@@ -1,109 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-
-<svg
-   width="40.266247mm"
-   height="20.267391mm"
-   viewBox="0 0 40.266247 20.267391"
-   version="1.1"
-   id="svg5"
-   xmlns="http://www.w3.org/2000/svg"
-   xmlns:svg="http://www.w3.org/2000/svg">
-  <defs
-     id="defs2" />
-  <g
-     id="layer1"
-     transform="translate(0.1322915,0.1322915)">
-    <path
-       style="fill:none;stroke:#000000;stroke-width:0.264583"
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-       id="path500" />
-    <path
-       style="fill:none;stroke:#000000;stroke-width:0.264583"
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-       id="path506" />
-    <path
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-       d="m 0,0 c 3.3327445,0 6.6654889,0 9.9982334,0 0,6.6676027 0,13.335205 0,20.002808"
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-    <path
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-       y="6.3107877"
-       id="text676"><tspan
-         x="22.156124"
-         y="6.3107877">VCC</tspan></text>
-    <text
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-       id="text730"><tspan
-         id="tspan728"
-         x="31.972855"
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-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
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-       id="text734"><tspan
-         id="tspan732"
-         x="32.398666"
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-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
-       x="22.770041"
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-       id="text738"><tspan
-         id="tspan736"
-         x="22.770041"
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-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
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-       y="16.286804"
-       id="text742"><tspan
-         id="tspan740"
-         x="13.605446"
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-    <text
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-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
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-       y="6.1998558"
-       id="text746"><tspan
-         id="tspan744"
-         x="2.5204566"
-         y="6.1998558">/CS</tspan></text>
-    <text
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-       font-size="2.5px"
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-       y="14.500522"
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-         id="tspan748"
-         x="5.0321894"
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-         y="17.146358"
-         id="tspan752">chipset</tspan></text>
-  </g>
-</svg>

Documentation/tutorial/part3.md

@@ -23,10 +23,10 @@ though TDD has a different work flow of building tests first, followed
 by the code that satisfies them, the process of writing tests and adding
 them to the tree is the same.
 
-## Analysis of unit under test
-First of all, it is necessary to precisely establish what we want to
-test in a particular module. Usually this will be an externally exposed
-API, which can be used by other modules.
+## Analysis of unit under test First of all, it is necessary to
+precisely establish what we want to test in a particular module. Usually
+this will be an externally exposed API, which can be used by other
+modules.
 
 ```eval_rst
 .. admonition:: i2c-test example

Documentation/util/ifdtool/layout.md

@@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 +------------+------------------+-----------+-------------------------------------------+
 | 4          | Platform Data    | SI_PDR    |                                           |
 +------------+------------------+-----------+-------------------------------------------+
-| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this     |
+| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this    |
 |            |                  |           | region; EC firmware is stored in BIOS     |
 |            |                  |           | region of flash                           |
 +------------+------------------+-----------+-------------------------------------------+

LICENSES/BSD-2-Clause-Patent.txt

@@ -1,49 +0,0 @@
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
-  notice, this list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in the
-  documentation and/or other materials provided with the distribution.
-
-Subject to the terms and conditions of this license, each copyright
-holder and contributor hereby grants to those receiving rights under
-this license a perpetual, worldwide, non-exclusive, no-charge,
-royalty-free, irrevocable (except for failure to satisfy the conditions
-of this license) patent license to make, have made, use, offer to sell,
-sell, import, and otherwise transfer this software, where such license
-applies only to those patent claims, already acquired or hereafter
-acquired, licensable by such copyright holder or contributor that are
-necessarily infringed by:
-
-(a) their Contribution(s) (the licensed copyrights of copyright holders
-   and non-copyrightable additions of contributors, in source or binary
-   form) alone;
-or
-(b) combination of their Contribution(s) with the work of authorship to
-   which such Contribution(s) was added by such copyright holder or
-   contributor, if, at the time the Contribution is added, such addition
-   causes such combination to be necessarily infringed. The patent
-   license shall not apply to any other combinations which include the
-   Contribution.
-
-Except as expressly stated above, no rights or licenses from any
-copyright holder or contributor is granted under this license, whether
-expressly, by implication, estoppel or otherwise.
-
-DISCLAIMER
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/BSD-2-Clause.txt

@@ -1,23 +0,0 @@
-Copyright (c) <year> <owner>.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/BSD-4-Clause-UC.txt

@@ -1,31 +0,0 @@
-Copyright [various years] The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. All advertising materials mentioning features or use of this software
-   must display the following acknowledgement: This product includes
-   software developed by the University of California, Berkeley and its
-   contributors.
-4. Neither the name of the University nor the names of its contributors
-   may be used to endorse or promote products derived from this software
-   without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ''AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/CC-PDDC.txt

@@ -1,28 +0,0 @@
-The person or persons who have associated work with this document (the
-"Dedicator" or "Certifier") hereby either (a) certifies that, to the
-best of his knowledge, the work of authorship identified is in the
-public domain of the country from which the work is published, or (b)
-hereby dedicates whatever copyright the dedicators holds in the work of
-authorship identified below (the "Work") to the public domain. A
-certifier, moreover, dedicates any copyright interest he may have in the
-associated work, and for these purposes, is described as a "dedicator"
-below.
-
-A certifier has taken reasonable steps to verify the copyright status of
-this work. Certifier recognizes that his good faith efforts may not
-shield him from liability if in fact the work certified is not in the
-public domain.
-
-Dedicator makes this dedication for the benefit of the public at large
-and to the detriment of the Dedicator's heirs and successors. Dedicator
-intends this dedication to be an overt act of relinquishment in
-perpetuity of all present and future rights under copyright law, whether
-vested or contingent, in the Work. Dedicator understands that such
-relinquishment of all rights includes the relinquishment of all rights
-to enforce (by lawsuit or otherwise) those copyrights in the Work.
-
-Dedicator recognizes that, once placed in the public domain, the Work
-may be freely reproduced, distributed, transmitted, used, modified,
-built upon, or otherwise exploited by anyone for any purpose, commercial
-or non-commercial, and in any way, including by methods that have not
-yet been invented or conceived.

LICENSES/HPND-sell-variant.txt

@@ -1,18 +0,0 @@
-Permission to use, copy, modify, distribute, and sell this software and
-its documentation for any purpose is hereby granted without fee,
-provided that the above copyright notice appears in all copies, and that
-both that the copyright notice and this permission notice appear in
-supporting documentation, and that the name of <copyright holder> <or
-related entities> not be used in advertising or publicity pertaining to
-distribution of the software without specific, written prior permission
-. <copyright holder> makes no representations about the suitability of
-this software for any purpose. It is provided "as is" without express or
-implied warranty.
-
-<copyright holder> DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
-SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS . IN NO EVENT SHALL <copyright holder> BE LIABLE FOR ANY
-SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
-RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF
-CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSES/HPND.txt

@@ -1,20 +0,0 @@
-<copyright notice>
-
-Permission to use, copy, modify and distribute this software and its
-documentation for any purpose and without fee is hereby granted,
-provided that the above copyright notice appear in all copies, and that
-both that the copyright notice and this permission notice appear in
-supporting documentation , and that the name of <copyright holder> <or
-related entities> not be used in advertising or publicity pertaining to
-distribution of the software without specific, written prior permission.
-<copyright holder> makes no representations about the suitability of
-this software for any purpose. It is provided "as is" without express or
-implied warranty.
-
-<copyright holder> DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
-SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS . IN NO EVENT SHALL <copyright holder> BE LIABLE FOR ANY
-SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
-RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF
-CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSES/exceptions/GCC-exception-3.1.txt

@@ -1,74 +0,0 @@
-GCC RUNTIME LIBRARY EXCEPTION
-
-Version 3.1, 31 March 2009
-
-General information: http://www.gnu.org/licenses/gcc-exception.html
-
-Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>
-
-Everyone is permitted to copy and distribute verbatim copies of this
-license document, but changing it is not allowed.
-
-This GCC Runtime Library Exception ("Exception") is an additional
-permission under section 7 of the GNU General Public License, version 3
-("GPLv3"). It applies to a given file (the "Runtime Library") that bears
-a notice placed by the copyright holder of the file stating that the
-file is governed by GPLv3 along with this Exception.
-
-When you use GCC to compile a program, GCC may combine portions of
-certain GCC header files and runtime libraries with the compiled
-program. The purpose of this Exception is to allow compilation of
-non-GPL (including proprietary) programs to use, in this way, the header
-files and runtime libraries covered by this Exception.
-
-0. Definitions.
-
-  A file is an "Independent Module" if it either requires the Runtime
-  Library for execution after a Compilation Process, or makes use of an
-  interface provided by the Runtime Library, but is not otherwise based
-  on the Runtime Library.
-
-  "GCC" means a version of the GNU Compiler Collection, with or without
-  modifications, governed by version 3 (or a specified later version) of
-  the GNU General Public License (GPL) with the option of using any
-  subsequent versions published by the FSF.
-
-  "GPL-compatible Software" is software whose conditions of propagation,
-  modification and use would permit combination with GCC in accord with
-  the license of GCC.
-
-  "Target Code" refers to output from any compiler for a real or virtual
-  target processor architecture, in executable form or suitable for
-  input to an assembler, loader, linker and/or execution phase.
-  Notwithstanding that, Target Code does not include data in any format
-  that is used as a compiler intermediate representation, or used for
-  producing a compiler intermediate representation.
-
-  The "Compilation Process" transforms code entirely represented in
-  non-intermediate languages designed for human-written code, and/or in
-  Java Virtual Machine byte code, into Target Code. Thus, for example,
-  use of source code generators and preprocessors need not be considered
-  part of the Compilation Process, since the Compilation Process can be
-  understood as starting with the output of the generators or
-  preprocessors.
-
-  A Compilation Process is "Eligible" if it is done using GCC, alone or
-  with other GPL-compatible software, or if it is done without using any
-  work based on GCC. For example, using non-GPL-compatible Software to
-  optimize any GCC intermediate representations would not qualify as an
-  Eligible Compilation Process.
-
-1. Grant of Additional Permission.
-
-   You have permission to propagate a work of Target Code formed by
-   combining the Runtime Library with Independent Modules, even if such
-   propagation would otherwise violate the terms of GPLv3, provided that
-   all Target Code was generated by Eligible Compilation Processes. You
-   may then convey such a combination under terms of your choice,
-   consistent with the licensing of the Independent Modules.
-
-2. No Weakening of GCC Copyleft.
-
-  The availability of this Exception does not imply any general
-  presumption that third-party software is unaffected by the copyleft
-  requirements of the license of GCC.

LICENSES/exceptions/Linux-syscall-note.txt

@@ -1,12 +0,0 @@
-NOTE! This copyright does *not* cover user programs that use kernel
-services by normal system calls - this is merely considered normal use
-of the kernel, and does *not* fall under the heading of "derived work".
-Also note that the GPL below is copyrighted by the Free Software
-Foundation, but the instance of code that it refers to (the Linux
-kernel) is copyrighted by me and others who actually wrote it.
-
-Also note that the only valid version of the GPL as far as the kernel is
-concerned is _this_ particular version of the license (ie v2, not v2.2
-or v3.x or whatever), unless explicitly otherwise stated.
-
-Linus Torvalds

MAINTAINERS

@@ -138,30 +138,15 @@ Maintainers List (try to look for most precise areas first)
 ################################################################################
 
 AMD family 17h and 19h reference boards
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
-F:	src/mainboard/amd/bilby/
 F:	src/mainboard/amd/chausie/
 F:	src/mainboard/amd/majolica/
 F:	src/mainboard/amd/mandolin/
 
-AMD reference boards outside of family 17h and 19h
-L:	amd_coreboot_org_changes@googlegroups.com
-F:	src/mainboard/amd/gardenia/
-F:	src/mainboard/amd/inagua/
-F:	src/mainboard/amd/olivehill/
-F:	src/mainboard/amd/pademelon/
-F:	src/mainboard/amd/parmer/
-F:	src/mainboard/amd/persimmon/
-F:	src/mainboard/amd/south_station/
-F:	src/mainboard/amd/thatcher/
-F:	src/mainboard/amd/union_station/
-
-
-
 APPLE MAINBOARDS
 M:	Evgeny Zinoviev <me@ch1p.io>
 S:	Maintained
@@ -263,20 +248,14 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/gigabyte/ga-h61m-series/
 
-GOOGLE REX MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
-M:	Kapil Porwal <kapilporwal@google.com>
-S:	Maintained
-F:	src/mainboard/google/rex/
 
 GOOGLE BRYA MAINBOARDS
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/brya/
 
 GOOGLE HATCH MAINBOARDS
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/hatch/
 
@@ -286,6 +265,7 @@ S:	Supported
 F:	src/mainboard/google/panther/
 
 GOOGLE VOLTEER MAINBOARDS
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/volteer/
@@ -304,15 +284,6 @@ F:	src/mainboard/google/parrot/
 F:	src/mainboard/google/slippy/
 F:	src/mainboard/google/stout/
 
-GOOGLE AMD-BASED MAINBOARDS
-M:	Martin Roth <martin.roth@amd.corp-partner.google.com>
-M:	Jason Nien <jason.nien@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
-F:	src/mainboard/google/kahlee/
-F:	src/mainboard/google/zork/
-F:	src/mainboard/google/guybrush/
-F:	src/mainboard/google/skyrim/
 
 
 HP 280 G2 MAINBOARD
@@ -391,11 +362,7 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/msi/h81m-p33/
 
-MSI MS-7D25 MAINBOARDS
-M:	Michał Żygowski <michal.zygowski@3mdeb.com>
-M:	Michał Kopeć <michal.kopec@3mdeb.com>
-S:	Maintained
-F:	src/mainboard/msi/ms7d25/
+
 
 OCP DELTALAKE MAINBOARD
 M:	Arthur Heymans <arthur@aheymans.xyz>
@@ -466,7 +433,7 @@ F:	src/mainboard/prodrive/hermes/
 
 
 PURISM MAINBOARDS
-M:	Jonathon Hall <jonathon.hall@puri.sm>
+M:	Matt DeVillier <matt.devillier@puri.sm>
 S:	Supported
 F:	src/mainboard/purism/
 
@@ -564,8 +531,7 @@ F:	src/include/cpu/x86/
 ################################################################################
 
 CHROME EC
-M:	Boris Mittelberg <bmbm@google.com>
-M:	Caveh Jalali <caveh@chromium.org>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/ec/google/chromeec/
 
@@ -616,7 +582,6 @@ F:	src/northbridge/intel/x4x/
 ################################################################################
 
 AMD SUPPORT
-L:	amd_coreboot_org_changes@googlegroups.com
 F:	src/vendorcode/amd/
 F:	src/cpu/amd/
 F:	src/northbridge/amd/
@@ -650,64 +615,57 @@ F:	src/drivers/intel/fsp2_0/
 ################################################################################
 
 AMD Cezanne
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
 
 AMD common SoC code
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/common/
 
 AMD Picasso
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Maintained
-F:	src/soc/amd/picasso/
-F:	src/vendorcode/amd/fsp/picasso/
-
-AMD Mendocino
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
-F:	src/soc/amd/mendocino/
-F:	src/vendorcode/amd/fsp/mendocino/
+S:	Maintained
+F:	src/soc/amd/picasso/
+F:	src/vendorcode/amd/fsp/picasso/
+
+AMD Sabrina
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
+M:	Felix Held <felix-coreboot@felixheld.de>
+M:	Jason Glenesk <jason.glenesk@gmail.com>
+M:	Raul E Rangel <rrangel@chromium.org>
+M:	Fred Reitberger <reitbergerfred@gmail.com>
+M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
+S:	Maintained
+F:	src/soc/amd/sabrina/
+F:	src/vendorcode/amd/fsp/sabrina/
 
 AMD Stoneyridge
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Odd Fixes
 F:	src/soc/amd/stoneyridge/
 
-INTEL METEORLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
-M:	Kapil Porwal <kapilporwal@google.com>
-S:	Maintained
-F:	src/soc/intel/meteorlake/
-
 INTEL ALDERLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/soc/intel/alderlake/
 
@@ -739,8 +697,7 @@ S:	Maintained
 F:	src/soc/intel/elkhartlake/
 
 INTEL TIGERLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/soc/intel/tigerlake/
 
@@ -881,7 +838,7 @@ F:	src/drivers/aspeed/ast2050/
 
 ACPI
 M:	Lance Zhao <lance.zhao@gmail.com>
-M:	Tim Wawrzynczak <inforichland@gmail.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Supported
 F:	src/acpi/
 F:	src/arch/x86/acpi/

Makefile.inc

@@ -93,7 +93,6 @@ subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
 subdirs-y += src/security
 subdirs-y += payloads payloads/external
-subdirs-$(CONFIG_SBOM) += src/sbom
 
 subdirs-y += site-local
 subdirs-y += util/checklist util/testing
@@ -153,7 +152,7 @@ int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(wor
 int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1))))
 int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + \( \( $$B - \( $$A % $$B \) \) % $$B \) )
 int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - \( $$A % $$B \) )
-file-size=$(strip $(shell wc -c "$1" | cut -f 1 -d ' '))
+file-size=$(strip $(shell cat $1 | wc -c))
 tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
 toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
 ws_to_under=$(shell echo '$1' | tr ' \t' '_')
@@ -443,7 +442,7 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
 CFLAGS_common += -Wnull-dereference -Wreturn-type
-CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
+CFLAGS_common += -Wlogical-op -Wduplicated-cond
 # cf. commit f69a99db (coreboot: x86: enable gc-sections)
 CFLAGS_common += -Wno-unused-but-set-variable
 endif

configs/config.facebook_fbg1701.sbom

@@ -1,6 +0,0 @@
-CONFIG_INCLUDE_COREBOOT_SBOM=y
-CONFIG_INCLUDE_PAYLOAD_SBOM=y
-CONFIG_INCLUDE_ME_SBOM=y
-CONFIG_INCLUDE_MICROCODE_SBOM=y
-CONFIG_VENDOR_FACEBOOK=y
-CONFIG_BOARD_FACEBOOK_FBG1701=y

configs/config.msi_ms7d25

@@ -1,7 +1,7 @@
 CONFIG_VENDOR_MSI=y
 CONFIG_CBFS_SIZE=0x1000000
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_EDK2_BOOT_TIMEOUT=3
+CONFIG_TIANOCORE_BOOT_TIMEOUT=3
 CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y
 CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
 CONFIG_PCIEXP_HOTPLUG=y
@@ -9,13 +9,11 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_POST_DEVICE_PCI_PCIE=y
 CONFIG_POST_IO_PORT=0x80
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git"
-CONFIG_EDK2_TAG_OR_REV="origin/dasharo"
-CONFIG_EDK2_CBMEM_LOGGING=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-CONFIG_EDK2_SD_MMC_TIMEOUT=1000
+CONFIG_PAYLOAD_TIANOCORE=y
+CONFIG_TIANOCORE_REPOSITORY="https://github.com/Dasharo/edk2.git"
+CONFIG_TIANOCORE_TAG_OR_REV="origin/dasharo"
+CONFIG_TIANOCORE_CBMEM_LOGGING=y
+CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=y
+CONFIG_TIANOCORE_SD_MMC_TIMEOUT=1000
 CONFIG_TPM2=y
 CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y
-CONFIG_DRIVERS_GENERIC_CBFS_UUID=y

configs/config.prodrive_hermes

@@ -1,7 +1,7 @@
 # Settings used by Prodrive to build coreboot for the Hermes
 CONFIG_VENDOR_PRODRIVE=y
 CONFIG_BOARD_PRODRIVE_HERMES=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Technologies B.V."
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Prodrive Techonologies B.V."
 CONFIG_POST_IO=y
 CONFIG_USE_LEGACY_8254_TIMER=y
 CONFIG_HERMES_USES_SPS_FIRMWARE=y

configs/config.system76_gaze15

@@ -1,5 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_GAZE15=y
-CONFIG_PAYLOAD_EDK2=y
+CONFIG_PAYLOAD_TIANOCORE=y
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y

configs/config.system76_lemp9

@@ -1,5 +1,5 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_LEMP9=y
-CONFIG_PAYLOAD_EDK2=y
+CONFIG_PAYLOAD_TIANOCORE=y
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y

configs/config.system76_oryp5

@@ -1,6 +1,6 @@
 CONFIG_VENDOR_SYSTEM76=y
 CONFIG_BOARD_SYSTEM76_ORYP5=y
-CONFIG_PAYLOAD_EDK2=y
+CONFIG_PAYLOAD_TIANOCORE=y
 CONFIG_POST_IO=n
 CONFIG_RUN_FSP_GOP=y
 CONFIG_SMMSTORE=y

payloads/Makefile.inc

@@ -24,7 +24,7 @@ payloads/external/U-Boot \
 payloads/external/Memtest86Plus \
 payloads/external/iPXE \
 payloads/external/tint \
-payloads/external/edk2 \
+payloads/external/tianocore \
 payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
 payloads/external/Yabits \

payloads/coreinfo/cbfs_module.c

@@ -68,7 +68,7 @@ static struct cbfile *firstfile(void)
 
 static struct cbfile *nextfile(struct cbfile *f)
 {
-	f = (struct cbfile *)((u8 *)f + ALIGN_UP(ntohl(f->len) + ntohl(f->offset),
+	f = (struct cbfile *)((u8 *)f + ALIGN(ntohl(f->len) + ntohl(f->offset),
 			      ntohl(header->align)));
 	return getfile(f);
 }

payloads/external/.gitignore

@@ -3,7 +3,7 @@ FILO/filo/
 GRUB2/grub2/
 LinuxBoot/linuxboot/
 SeaBIOS/seabios/
-edk2/workspace
+tianocore/tianocore/
 tint/tint/
 U-Boot/u-boot/
 Memtest86Plus/memtest86plus/

payloads/external/Makefile.inc

@@ -152,37 +152,35 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D
 		DEPTHCHARGE_REVISION_ID=$(CONFIG_DEPTHCHARGE_REVISION_ID) \
 		OVERRIDE_DEFCONFIG=$(CONFIG_LP_DEFCONFIG_OVERRIDE)
 
-# edk2
+# Tianocore
 
-$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
-	$(MAKE) -C payloads/external/edk2 UefiPayloadPkg \
+$(obj)/UEFIPAYLOAD.fd tianocore: $(DOTCONFIG)
+	$(MAKE) -C payloads/external/tianocore all \
 		HOSTCC="$(HOSTCC)" \
 		CC="$(HOSTCC)" \
-		CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \
-		CONFIG_EDK2_TAG_OR_REV=$(CONFIG_EDK2_TAG_OR_REV) \
-		CONFIG_EDK2_UEFIPAYLOAD=$(CONFIG_EDK2_UEFIPAYLOAD) \
-		CONFIG_EDK2_REPO_OFFICIAL=$(CONFIG_EDK2_REPO_OFFICIAL) \
-		CONFIG_EDK2_REPO_MRCHROMEBOX=$(CONFIG_EDK2_REPO_MRCHROMEBOX) \
-		CONFIG_EDK2_REPO_CUSTOM=$(CONFIG_EDK2_REPO_CUSTOM) \
-		CONFIG_EDK2_CUSTOM_BUILD_PARAMS=$(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) \
-		CONFIG_EDK2_DEBUG=$(CONFIG_EDK2_DEBUG) \
-		CONFIG_EDK2_RELEASE=$(CONFIG_EDK2_RELEASE) \
-		CONFIG_EDK2_VERBOSE_BUILD=$(CONFIG_EDK2_VERBOSE_BUILD) \
-		CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \
-		CONFIG_EDK2_BOOTSPLASH_FILE=$(CONFIG_EDK2_BOOTSPLASH_FILE) \
-		CONFIG_EDK2_BOOT_MANAGER_ESCAPE=$(CONFIG_EDK2_BOOT_MANAGER_ESCAPE) \
-		CONFIG_EDK2_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT) \
-		CONFIG_EDK2_CBMEM_LOGGING=$(CONFIG_EDK2_CBMEM_LOGGING) \
-		CONFIG_EDK2_FOLLOW_BGRT_SPEC=$(CONFIG_EDK2_FOLLOW_BGRT_SPEC) \
-		CONFIG_EDK2_FULL_SCREEN_SETUP=$(CONFIG_EDK2_FULL_SCREEN_SETUP) \
-		CONFIG_EDK2_HAVE_EFI_SHELL=$(CONFIG_EDK2_HAVE_EFI_SHELL) \
-		CONFIG_EDK2_PRIORITIZE_INTERNAL=$(CONFIG_EDK2_PRIORITIZE_INTERNAL) \
-		CONFIG_EDK2_PS2_SUPPORT=$(CONFIG_EDK2_PS2_SUPPORT) \
-		CONFIG_EDK2_SERIAL_SUPPORT=$(CONFIG_EDK2_SERIAL_SUPPORT) \
-		CONFIG_EDK2_SD_MMC_TIMEOUT=$(CONFIG_EDK2_SD_MMC_TIMEOUT) \
+		CONFIG_TIANOCORE_REPOSITORY=$(CONFIG_TIANOCORE_REPOSITORY) \
+		CONFIG_TIANOCORE_TAG_OR_REV=$(CONFIG_TIANOCORE_TAG_OR_REV) \
+		CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
+		CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
+		CONFIG_TIANOCORE_CUSTOM=$(CONFIG_TIANOCORE_CUSTOM) \
+		CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS=$(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS) \
+		CONFIG_TIANOCORE_COREBOOTPAYLOAD=$(CONFIG_TIANOCORE_COREBOOTPAYLOAD) \
+		CONFIG_TIANOCORE_DEBUG=$(CONFIG_TIANOCORE_DEBUG) \
+		CONFIG_TIANOCORE_RELEASE=$(CONFIG_TIANOCORE_RELEASE) \
+		CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
+		CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+		CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE=$(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE) \
+		CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
+		CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \
+		CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC=$(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC) \
+		CONFIG_TIANOCORE_HAVE_EFI_SHELL=$(CONFIG_TIANOCORE_HAVE_EFI_SHELL) \
+		CONFIG_TIANOCORE_PRIORITIZE_INTERNAL=$(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL) \
+		CONFIG_TIANOCORE_PS2_SUPPORT=$(CONFIG_TIANOCORE_PS2_SUPPORT) \
+		CONFIG_TIANOCORE_SERIAL_SUPPORT=$(TIANOCORE_SERIAL_SUPPORT) \
+		CONFIG_TIANOCORE_SD_MMC_TIMEOUT=$(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) \
+		CONFIG_TIANOCORE_USE_8254_TIMER=$(CONFIG_TIANOCORE_USE_8254_TIMER) \
 		CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
 		CONFIG_ECAM_MMCONF_LENGTH=$(CONFIG_ECAM_MMCONF_LENGTH) \
-		CONFIG_SMMSTORE_V2=$(CONFIG_SMMSTORE_v2) \
 		GCC_CC_x86_32=$(GCC_CC_x86_32) \
 		GCC_CC_x86_64=$(GCC_CC_x86_64) \
 		GCC_CC_arm=$(GCC_CC_arm) \
@@ -192,6 +190,7 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG)
 		OBJCOPY_arm=$(OBJCOPY_arm) \
 		OBJCOPY_arm64=$(OBJCOPY_arm64) \
 		MFLAGS= MAKEFLAGS=
+	mv payloads/external/tianocore/output/UEFIPAYLOAD.fd $@
 
 # FILO
 

payloads/external/edk2/Kconfig

@@ -1,217 +0,0 @@
-if PAYLOAD_EDK2
-
-config PAYLOAD_FILE
-	string "edk2 binary"
-	default "$(obj)/UEFIPAYLOAD.fd" if EDK2_UEFIPAYLOAD
-	help
-	  The result of a UefiPayloadPkg build
-
-config EDK2_UEFIPAYLOAD
-	bool "Build UefiPayloadPkg"
-	default y
-	help
-	  Build the standard UefiPayloadPkg
-
-choice
-	prompt "Tianocore's EDK II payload"
-	default EDK2_REPO_MRCHROMEBOX
-	help
-	  Select which type of payload edk2 will build (default is UefiPayload)
-	  UefiPayload: MrChromebox's customized fork of edk2 which works on most
-	  x86_64 devices
-	  Upstream: Use upstream edk2 payload from https://github.com/tianocore/edk2
-
-config EDK2_REPO_MRCHROMEBOX
-	bool "MrChromebox' edk2 fork"
-	help
-	  Select this option to build using MrChromebox's custom edk2 fork,
-	  which incorporates fixes/improvements from System 76's and 9elements' trees.
-
-config EDK2_REPO_OFFICIAL
-	bool "Official edk2 repository"
-	help
-	  Select this option if you want to use the official edk2 repository to build
-	  edk2.
-
-	  Please note, this option will not work on any SOC without modification.
-
-config EDK2_REPO_CUSTOM
-	bool "Specify your own repository"
-	help
-	  Specify your own edk2 repository and branch to use.
-
-endchoice
-
-config EDK2_REPOSITORY
-	string "URL to git repository for edk2"
-	default "https://github.com/mrchromebox/edk2" if EDK2_REPO_MRCHROMEBOX
-	default "https://github.com/tianocore/edk2" if EDK2_REPO_OFFICIAL
-	default "" if EDK2_REPO_CUSTOM
-	help
-	  coreboot supports an array of build options which can be found below. These options
-	  will only have an effect if the relevant options exist in the target repository.
-
-config EDK2_TAG_OR_REV
-	string "Insert a commit's SHA-1 or a branch name"
-	default "origin/uefipayload_202207" if EDK2_REPO_MRCHROMEBOX
-	default "origin/master" if EDK2_REPO_OFFICIAL
-	default "" if EDK2_REPO_CUSTOM
-	help
-	  The commit's SHA-1 or branch name of the revision to use. This must exist in
-	  EDK2_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
-	  "origin/uefipayload_202202"
-
-choice
-	prompt "edk2 build"
-	default EDK2_RELEASE
-	help
-	  Select whether to generate a debug or release build for
-	  edk2; default is to generate a release build.
-
-config EDK2_DEBUG
-	bool "Generate edk2 debug build"
-	help
-	  Generate a debug build.
-
-config EDK2_RELEASE
-	bool "Generate edk2 release build"
-	help
-	  Generate a release build.
-
-endchoice
-
-config EDK2_VERBOSE_BUILD
-	bool "Output verbose build log for troubleshooting build failures"
-	help
-	  Switch off the `-q` (quiet) and `-s` (silent) build arguments which makes the
-	  build log extremely verbose. This can be used to troubleshoot failed builds
-	  which are usually down to missing tools or toolchain.
-
-config EDK2_ABOVE_4G_MEMORY
-	bool "Enable above 4G memory"
-	default n
-	help
-	  Select this option to enable Above 4G Decode. This will allow the
-	  payload to use all of the memory, rather than an maximum of 4G.
-
-	  Disabling memory above 4G is useful for bootloaders that are not
-	  fully 64-bit aware such as Qubes R4.0.4 bootloader.
-
-config EDK2_BOOTSPLASH_FILE
-	string "edk2 Bootsplash path and filename"
-	default "Documentation/coreboot_logo.bmp"
-	help
-	  The path and filename of the file to use as graphical bootsplash
-	  image. If this option is not configured, the default
-	  coreboot logo (European Brown Hare) will used.
-
-	  You can use any image format supported by imagemagick, a list of which
-	  can be found [here](https://imagemagick.org/script/formats.php).
-
-	  The build process will automatically convert this to the format that
-	  edk2 requires, which is an uncompressed BMP, in BMP3 format. It does
-	  this using imagemagick (`convert splosh.bmp BMP3:splash.bmp`).
-
-	  The newly formatted file will be the dimensions size as the original
-	  one.
-
-	  The build process will automatically do this conversion, so it can
-	  be supplied with any format that imagemagick can process (which is
-	  pretty much any!).
-
-	  This image will also be used as the BGRT boot image, which may
-	  persist through your OS boot process.
-
-	  See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and
-	  Microsoft's documentation on BGRT positioning:
-	  Docs/Windows/Windows Drivers/Bring up guide/Boot screen components
-
-	  Accordingly, the image used should be no taller/wider than 40% of
-	  the display panel's native pixel height/width (or resolution set).
-
-	  If an absolute path is not given, the path will assumed to be
-	  relative to the coreboot root directory.
-
-config EDK2_BOOT_MANAGER_ESCAPE
-	bool "Use Escape key for Boot Manager"
-	default n
-	help
-	  Use Escape as the hot-key to access the Boot Manager. This replaces
-	  the default key of F2.
-
-config EDK2_BOOT_TIMEOUT
-	int "Set the timeout for boot menu prompt"
-	default 2
-	help
-	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
-	  For boards with an internal display, the default value of 2s is generally sufficient.
-	  For boards with an external display, a value of 5s is generally sufficient.
-
-config EDK2_CBMEM_LOGGING
-	bool "Enable edk2 logging to CBMEM"
-	help
-	  Select this option if you want to enable edk2 logging to CBMEM.
-	  You may want to increase the default cbmem buffer size when selecting
-	  this option, especially if using a debug (vs release) build.
-	  Selecting this option will increase the payload size in CBFS by 0x10000.
-
-config EDK2_FOLLOW_BGRT_SPEC
-	bool "Center logo 38.2% from the top of screen"
-	default n
-	help
-	  Follow the BGRT Specification implemented by Microsoft and
-	  the Boot Logo 38.2% will be vertically centered 38.2% from
-	  the top of the display.
-
-config EDK2_FULL_SCREEN_SETUP
-	bool "Use the full screen for the edk2 frontpage"
-	default y
-	help
-	  Allow edk2 to use the full screen to display the frontpage
-	  (aka "Boot Menu"). With this option disable, it will be
-	  limited to 640x480.
-
-config EDK2_HAVE_EFI_SHELL
-	bool "Include EFI Shell"
-	default y
-	help
-	  Include the EFI shell Binary
-
-config EDK2_PRIORITIZE_INTERNAL
-	bool "Prioritize internal boot devices"
-	default y
-	help
-	  Prioritize internal boot devices over external devices
-
-config EDK2_PS2_SUPPORT
-	bool "Support PS/2 Keyboards"
-	default y
-	help
-	  Include support for PS/2 keyboards
-
-config EDK2_SD_MMC_TIMEOUT
-	int "Timeout in ms for initializing SD and eMMC devices"
-	default 10
-	help
-	  The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
-	  Most only require 10ms, but certain readers can take 1s.
-
-config EDK2_SERIAL_SUPPORT
-	bool "Support serial output"
-	default y if EDK2_DEBUG
-	default n
-	help
-	  Enable serial port output in edk2. Serial output limits the performance of edk2's
-	  FrontPage.
-
-config EDK2_CUSTOM_BUILD_PARAMS
-	string "edk2 additional custom build parameters"
-	default "-D VARIABLE_SUPPORT=SMMSTORE" if EDK2_REPO_MRCHROMEBOX && SMMSTORE_V2
-	help
-	  edk2 has build options that are not modified by coreboot, and these can be
-	  found in `UefiPayloadPkg/UefiPayloadPkg.dsc`. Forks may also support
-	  additional build options that should have been upstreamed but have not.
-
-	  This option can support both macros `-D` and Pcds `--pcd`.
-
-endif

payloads/external/edk2/Makefile

@@ -1,238 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-# force the shell to bash - the edksetup.sh script doesn't work with dash
-export SHELL := env bash
-
-project_name = edk2
-export WORKSPACE := $(CURDIR)/workspace
-export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY)))
-export PACKAGES_PATH := $(EDK2_PATH)
-
-ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
-BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc
-endif
-BUILD_STR += -t COREBOOT
-BUILD_STR += -D BOOTLOADER=COREBOOT
-ifneq ($(CONFIG_EDK2_VERBOSE_BUILD),y)
-BUILD_STR += -q
-ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y)
-BUILD_STR += -s
-endif
-endif
-
-#
-# EDK II has the following build options relevant to coreboot:
-#
-#
-# OPTION			= DEFAULT_VALUE
-#
-# ABOVE_4G_MEMORY		= TRUE
-ifneq ($(CONFIG_EDK2_ABOVE_4G_MEMORY),y)
-BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
-endif
-# BOOTSPLASH_IMAGE		= FALSE
-ifneq ($(CONFIG_EDK2_BOOTSPLASH_FILE),)
-BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
-endif
-# BOOT_MANAGER_ESCAPE		= FALSE
-ifeq ($(CONFIG_EDK2_BOOT_MANAGER_ESCAPE),y)
-BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE
-endif
-# BUILD_TARGETS			= DEBUG
-ifeq ($(CONFIG_EDK2_DEBUG),y)
-RELEASE_STR = DEBUG
-else
-RELEASE_STR = RELEASE
-endif
-# DISABLE_SERIAL_TERMINAL	= FALSE
-ifneq ($(CONFIG_EDK2_SERIAL_SUPPORT),y)
-BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
-endif
-# FOLLOW_BGRT_SPEC		= FALSE
-ifeq ($(CONFIG_EDK2_FOLLOW_BGRT_SPEC),y)
-BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
-endif
-# PCIE_BASE_ADDRESS		= 0
-ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
-BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
-endif
-# PCIE_BASE_LENGTH		= 0
-ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
-BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH)
-endif
-# PRIORITIZE_INTERNAL		= FALSE
-ifeq ($(CONFIG_EDK2_PRIORITIZE_INTERNAL),y)
-BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
-endif
-# PS2_KEYBOARD_ENABLE		= FALSE
-ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y)
-BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
-endif
-# PLATFORM_BOOT_TIMEOUT		= 3
-ifneq ($(CONFIG_EDK2_BOOT_TIMEOUT),)
-BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_EDK2_BOOT_TIMEOUT)
-endif
-# SIO_BUS_ENABLE		= FALSE
-ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y)
-BUILD_STR += -D SIO_BUS_ENABLE=TRUE
-endif
-# SHELL_TYPE			= BUILD_SHELL
-ifneq ($(CONFIG_EDK2_HAVE_EFI_SHELL),y)
-BUILD_STR += -D SHELL_TYPE=NONE
-endif
-# USE_CBMEM_FOR_CONSOLE		= FALSE
-ifeq ($(CONFIG_EDK2_CBMEM_LOGGING),y)
-BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
-endif
-# SD_MMC_TIMEOUT		= 1000000
-ifneq ($(CONFIG_EDK2_SD_MMC_TIMEOUT),)
-BUILD_STR += -D SD_MMC_TIMEOUT=$(shell echo $$(( $(CONFIG_EDK2_SD_MMC_TIMEOUT) * 1000)) )
-endif
-
-#
-# EDKII has the below PCDs that are relevant to coreboot:
-#
-# Allows EDKII to use the full framebuffer
-ifeq ($(CONFIG_EDK2_FULL_SCREEN_SETUP),y)
-BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
-BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
-BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
-BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
-endif
-
-bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
-
-ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),)
-BUILD_STR += $(CONFIG_EDK2_CUSTOM_BUILD_PARAMS)
-endif
-
-all: UefiPayloadPkg
-
-$(WORKSPACE):
-	mkdir $(WORKSPACE)
-
-$(EDK2_PATH): $(WORKSPACE)
-	if [ ! -d "$(EDK2_PATH)" ]; then \
-		git clone --recurse-submodules $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \
-	fi
-	cd $(EDK2_PATH); \
-		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \
-		if [ -e UefiPayloadPkg/ShimLayer/UniversalPayload.o ]; then \
-			rm UefiPayloadPkg/ShimLayer/UniversalPayload.o; \
-		fi; \
-		echo "    Fetching new commits from $(CONFIG_EDK2_REPOSITORY)"; \
-		git fetch origin 2>/dev/null; \
-		if ! git rev-parse --verify -q $(CONFIG_EDK2_TAG_OR_REV) >/dev/null; then \
-			echo "    $(CONFIG_EDK2_TAG_OR_REV) is not a valid git reference"; \
-			exit 1; \
-		fi; \
-		if git status --ignore-submodules=dirty | grep -q clean; then \
-			echo "    Checking out $(project_name) revision $(CONFIG_EDK2_TAG_OR_REV)"; \
-			git checkout --detach $(CONFIG_EDK2_TAG_OR_REV) -f; \
-		else \
-			echo "    Working directory not clean; will not overwrite"; \
-		fi; \
-		git submodule update --init --checkout
-
-logo: $(EDK2_PATH)
-	case "$(CONFIG_EDK2_BOOTSPLASH_FILE)" in \
-		"") ;; \
-		/*) convert -background None $(CONFIG_EDK2_BOOTSPLASH_FILE) \
-			BMP3:$(EDK2_PATH)/MdeModulePkg/Logo/Logo.bmp;; \
-		*) convert -background None $(top)/$(CONFIG_EDK2_BOOTSPLASH_FILE) \
-			BMP3:$(EDK2_PATH)/MdeModulePkg/Logo/Logo.bmp;; \
-	esac \
-
-checktools:
-	echo -n "EDK2: Checking uuid-dev:"
-	echo "#include <uuid/uuid.h>" > libtest.c
-	echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
-	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo "    Found!" || \
-		( echo "    Not found!"; \
-			echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
-	rm -rf libtest.c libtest
-	echo -n "EDK2: Checking nasm:"
-	type nasm > /dev/null 2>&1 && echo "        Found!" || \
-		( echo "        Not found!"; echo "ERROR: Please install nasm."; exit 1 )
-	echo -n "EDK2: Checking imagemagick:"
-	-convert -size 1x1 xc: test.png &> /dev/null;
-	if [ -f test.png ]; then \
-		rm test.png && echo " Found!"; \
-	else \
-		echo " Not found!"; \
-		echo "ERROR: Please install imagemagick"; \
-		exit 1; \
-	fi
-
-print:
-	echo "   ##### $(project_name) Build Summary #####"
-	echo "   Repository:     $(CONFIG_EDK2_REPOSITORY)"
-	echo "   Branch:         $(CONFIG_EDK2_TAG_OR_REV)"
-	echo " $(BUILD_STR)" | \
-		sed -e 's/--/-/g' -e 's/-/\n   /g' | sort | sed \
-		-e 's/a /Architecture:   /g' \
-		-e 's/b /Release:        /g' \
-		-e 's/D /Option:         /g' \
-		-e 's/pcd /Pcd:            /g' \
-		-e 's/p /Payload:        /g' \
-		-e 's/q /Build:          Quiet/' \
-		-e 's/s /Build:          Silent/' \
-		-e 's/t /Toolchain:      /'
-
-prep: $(EDK2_PATH) clean checktools logo
-	cd $(WORKSPACE); \
-		source $(EDK2_PATH)/edksetup.sh; \
-		unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \
-		grep -q "COREBOOT" $(EDK2_PATH)/Conf/tools_def.txt; \
-		if [ $$? -ne 0 ]; then \
-			cat ../tools_def.txt >> $(EDK2_PATH)/Conf/tools_def.txt; \
-		fi; \
-
-$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd: \
-	prep print
-	cd $(WORKSPACE); \
-		source $(EDK2_PATH)/edksetup.sh; \
-		echo -n "EDK2: Building... "; \
-		build -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR) \
-			-y $(WORKSPACE)/Build/UefiPayloadPkgX64/UEFIPAYLOAD.txt; \
-		if [ ! -f $@ ]; then \
-			echo "Failed!"; \
-			exit 1; \
-		fi
-		echo "Success!"; \
-
-$(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \
-	prep print
-	cd $(WORKSPACE); \
-		source $(EDK2_PATH)/edksetup.sh; \
-		echo -n "EDK2: Building... "; \
-		$(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR)
-		if [ ! -f $@ ]; then \
-			echo "Failed!"; \
-			exit 1; \
-		fi
-		echo "Success!"; \
-
-$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \
-		$(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf prep
-	cd $(WORKSPACE)/Build/UefiPayloadPkgX64 && \
-		$(OBJCOPY) -I binary UniversalPayload.elf -O elf32-i386 -B i386 \
-			$(EDK2_PATH)/UefiPayloadPkg/ShimLayer/UniversalPayload.o; \
-	cd $(WORKSPACE) && \
-		source $(EDK2_PATH)/edksetup.sh; \
-		build -p UefiPayloadPkg/UefiPayloadPkg.dsc -b $(RELEASE_STR) -a IA32 -a X64 \
-			-m UefiPayloadPkg/ShimLayer/ShimLayer.inf \
-			-t COREBOOT -D BOOTLOADER=COREBOOT -D SHIMLAYER=TRUE \
-			-y $(WORKSPACE)/Build/UefiPayloadPkgX64/ShimLayer.txt
-
-UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd
-	mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \
-		../../../build/UEFIPAYLOAD.fd
-
-clean:
-	test -d $(WORKSPACE) && (cd $(WORKSPACE); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
-
-distclean:
-	rm -rf $(WORKSPACE)
-
-.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg clean distclean

payloads/external/skiboot/Makefile

@@ -32,6 +32,5 @@ distclean: clean
 clean:
 	# Redefine RM because it's used like `$(RM) non-existent-file`
 	# Also ignore useless messages about removing test files
-	[ ! -d $(skiboot_dir) ] || \
-	        $(MAKE) -C $(skiboot_dir) RM="rm -rf" CROSS="$(skiboot_cross)" clean > /dev/null
+	[ ! -d $(skiboot_dir) ] || $(MAKE) -C $(skiboot_dir) RM="rm -rf" clean > /dev/null
 	rm -rf $(build_dir)

payloads/external/tianocore/Kconfig

@@ -0,0 +1,208 @@
+if PAYLOAD_TIANOCORE
+
+config PAYLOAD_FILE
+	string "Tianocore binary"
+	default "$(obj)/UEFIPAYLOAD.fd"
+	help
+	  The result of a UefiPayloadPkg build
+
+choice
+	prompt "Tianocore payload"
+	default TIANOCORE_UEFIPAYLOAD
+	help
+	  Select which type of payload Tianocore will build (default is UefiPayload)
+	  UefiPayload: MrChromebox's customized fork of Tianocore which works on most
+	  x86_64 devices
+	  Upstream: Use upstream Tianocore payload from https://github.com/tianocore/edk2
+	  CorebootPayload: MrChromebox's customized fork of the deprecated CorebootPayloadPkg
+	  Tianocore build target. It may work better on some older hardware (eg, x230)
+	  which does not work properly with the UefiPayloadPkg options.
+
+config TIANOCORE_UEFIPAYLOAD
+	bool "UEFIPayload"
+	help
+	  Select this option to build using MrChromebox's custom Tianocore fork,
+	  which incorporates fixes/improvements from System 76's and 9elements' trees.
+
+config TIANOCORE_UPSTREAM
+	bool "Upstream"
+	help
+	  Select this option if you want to use upstream EDK2 to build Tianocore.
+
+config TIANOCORE_COREBOOTPAYLOAD
+	bool "CorebootPayload"
+	help
+	  Select this option to build using MrChromebox's older (now deprecated)
+	  CorebootPayloadPkg-based Tianocore branch
+
+config TIANOCORE_CUSTOM
+	bool "Custom"
+	help
+	  Specify your own edk2 repository and branch to use.
+
+endchoice
+
+config TIANOCORE_REPOSITORY
+	string "URL to git repository for edk2"
+	default "https://github.com/tianocore/edk2" if TIANOCORE_UPSTREAM
+	default "https://github.com/mrchromebox/edk2" if TIANOCORE_UEFIPAYLOAD || TIANOCORE_COREBOOTPAYLOAD
+	help
+	  coreboot supports an array of build options which can be found below. These options
+	  will only have an effect if the relevant options exist in the target repository.
+
+config TIANOCORE_TAG_OR_REV
+	string "Insert a commit's SHA-1 or a branch name"
+	default "origin/uefipayload_202107" if TIANOCORE_UEFIPAYLOAD
+	default "origin/master" if TIANOCORE_UPSTREAM
+	default "origin/coreboot_fb" if TIANOCORE_COREBOOTPAYLOAD
+	help
+	  The commit's SHA-1 or branch name of the revision to use. This must exist in
+	  TIANOCORE_REPOSITORY, and in the case of a branch name, prefixed with origin i.e.
+	  "origin/uefipayload_202202"
+
+choice
+	prompt "Tianocore build"
+	default TIANOCORE_RELEASE
+	help
+	  Select whether to generate a debug or release build for
+	  Tianocore; default is to generate a release build.
+
+config TIANOCORE_DEBUG
+	bool "Generate Tianocore debug build"
+	help
+	  Generate a debug build.
+
+config TIANOCORE_RELEASE
+	bool "Generate Tianocore release build"
+	help
+	  Generate a release build.
+
+endchoice
+
+if TIANOCORE_UEFIPAYLOAD || TIANOCORE_CUSTOM || TIANOCORE_UPSTREAM
+
+config TIANOCORE_ABOVE_4G_MEMORY
+	bool "Enable above 4G memory"
+	default n
+	help
+	  Select this option to enable Above 4G Decode. This will allow the
+	  payload to use all of the memory, rather than an maximum of 4G.
+
+	  Disabling memory above 4G is useful for bootloaders that are not
+	  fully 64-bit aware such as Qubes R4.0.4 bootloader.
+
+
+config TIANOCORE_BOOTSPLASH_FILE
+	string "Tianocore Bootsplash path and filename"
+	default "bootsplash.bmp"
+	help
+	  Select this option if you have a bootsplash image that you would
+	  like to be used. If this option is not selected, the default
+	  coreboot logo (European Brown Hare) will used.
+
+	  The path and filename of the file to use as graphical bootsplash
+	  image. The file must be an uncompressed BMP, in BMP 3 format.
+
+	  Linux can create these with the below command:
+	      `convert splosh.bmp BMP3:splash.bmp`
+
+	  This image will also be used as the BGRT boot image, which may
+	  persist through your OS boot process.
+
+	  See ACPI spec 6.3, 5.2.22 Boot Graphics Resource Table (BGRT), and
+	  Microsoft's documentation on BGRT positioning:
+	  Docs/Windows/Windows Drivers/Bring up guide/Boot screen components
+
+	  Accordingly, the image used should be no taller/wider than 40% of
+	  the display panel's native pixel height/width (or resolution set).
+
+	  If an absolute path is not given, the path will assumed to be
+	  relative to the coreboot root directory.
+
+config TIANOCORE_BOOT_MANAGER_ESCAPE
+	bool "Use Escape key for Boot Manager"
+	default n
+	help
+	  Use Escape as the hot-key to access the Boot Manager. This replaces
+	  the default key of F2.
+
+config TIANOCORE_BOOT_TIMEOUT
+	int "Set the timeout for boot menu prompt"
+	default 2
+	help
+	  The length of time in seconds for which the boot splash/menu prompt will be displayed.
+	  For boards with an internal display, the default value of 2s is generally sufficient.
+	  For boards with an external display, a value of 5s is generally sufficient.
+
+config TIANOCORE_CBMEM_LOGGING
+	bool "Enable Tianocore logging to CBMEM"
+	help
+	  Select this option if you want to enable Tianocore logging to CBMEM.
+	  You may want to increase the default cbmem buffer size when selecting
+	  this option, especially if using a debug (vs release) build.
+	  Selecting this option will increase the payload size in CBFS by 0x10000.
+
+config TIANOCORE_FOLLOW_BGRT_SPEC
+	bool "Center logo 38.2% from the top of screen"
+	default n
+	help
+	  Follow the BGRT Specification implemented by Microsoft and
+	  the Boot Logo 38.2% will be vertically centered 38.2% from
+	  the top of the display.
+
+config TIANOCORE_HAVE_EFI_SHELL
+	bool "Include EFI Shell"
+	default y
+	help
+	  Include the EFI shell Binary
+
+config TIANOCORE_PRIORITIZE_INTERNAL
+	bool "Prioritize internal boot devices"
+	default y
+	help
+	  Prioritize internal boot devices over external devices
+
+config TIANOCORE_PS2_SUPPORT
+	bool "Support PS/2 Keyboards"
+	default y
+	help
+	  Include support for PS/2 keyboards
+
+config TIANOCORE_SD_MMC_TIMEOUT
+	int "Timeout in ms for initializing SD and eMMC devices"
+	default 10
+	help
+	  The amount of time allowed to initialize the SD Card reader and/or eMMC drive.
+	  Most only require 10ms, but certain readers can take 1s.
+
+config TIANOCORE_SERIAL_SUPPORT
+	bool "Support serial output"
+	default y if TIANOCORE_DEBUG
+	default n
+	help
+	  Enable serial port output in edk2. Serial output limits the performance of edk2's
+	  FrontPage.
+
+endif
+
+if TIANOCORE_COREBOOTPAYLOAD
+
+config TIANOCORE_USE_8254_TIMER
+	bool "TianoCore 8254 Timer"
+	help
+	  Use 8254 Timer for legacy support.
+
+endif
+
+if TIANOCORE_CUSTOM
+
+config TIANOCORE_CUSTOM_BUILD_PARAMS
+	string "TianoCore additional custom build parameters"
+	help
+	  Custom TianoCore forks may have different sets of parameters passed
+	  to build command. You may specify additional parameters to the custom
+	  TianoCore build
+
+endif
+
+endif

payloads/external/tianocore/Kconfig.name

@@ -1,9 +1,9 @@
-config PAYLOAD_EDK2
-	bool "edk2 payload"
+config PAYLOAD_TIANOCORE
+	bool "Tianocore payload"
 	depends on ARCH_X86 || ARCH_ARM64
 	help
 	  Select this option if you want to build a coreboot image
-	  with a edk2 payload. If you don't know what this is
+	  with a Tianocore payload. If you don't know what this is
 	  about, just leave it enabled.
 
 	  See https://coreboot.org/Payloads for more information.

payloads/external/tianocore/Makefile

@@ -0,0 +1,191 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# force the shell to bash - the edksetup.sh script doesn't work with dash
+export SHELL := env bash
+
+project_name = Tianocore
+project_dir = $(CURDIR)/$(word 3,$(subst /, ,$(CONFIG_TIANOCORE_REPOSITORY)))
+
+BUILD_STR = -a IA32 -a X64 -t COREBOOT
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+BUILD_STR += -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
+else
+BUILD_STR += -p UefiPayloadPkg/UefiPayloadPkg.dsc
+endif
+BUILD_STR += -D BOOTLOADER=COREBOOT -q
+
+#
+# EDK II has the following build options relevant to coreboot:
+#
+#
+# OPTION			= DEFAULT_VALUE
+#
+# ABOVE_4G_MEMORY		= TRUE
+ifneq ($(CONFIG_TIANOCORE_ABOVE_4G_MEMORY),y)
+BUILD_STR += -D ABOVE_4G_MEMORY=FALSE
+endif
+# BOOTSPLASH_IMAGE		= FALSE
+ifneq ($(CONFIG_TIANOCORE_BOOTSPLASH_FILE),)
+BUILD_STR += -D BOOTSPLASH_IMAGE=TRUE
+endif
+# BOOT_MANAGER_ESCAPE		= FALSE
+ifeq ($(CONFIG_TIANOCORE_BOOT_MANAGER_ESCAPE),y)
+BUILD_STR += -D BOOT_MANAGER_ESCAPE=TRUE
+endif
+# BUILD_TARGETS			= DEBUG
+ifeq ($(CONFIG_TIANOCORE_RELEASE),y)
+BUILD_STR += -b RELEASE
+endif
+# DISABLE_SERIAL_TERMINAL	= FALSE
+ifneq ($(CONFIG_TIANOCORE_SERIAL_SUPPORT),y)
+BUILD_STR += -D DISABLE_SERIAL_TERMINAL=TRUE
+endif
+# FOLLOW_BGRT_SPEC		= FALSE
+ifeq ($(CONFIG_TIANOCORE_FOLLOW_BGRT_SPEC),y)
+BUILD_STR += -D FOLLOW_BGRT_SPEC=TRUE
+endif
+# PCIE_BASE_ADDRESS		= 0
+ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
+BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
+endif
+# PCIE_BASE_LENGTH		= 0
+ifneq ($(CONFIG_ECAM_MMCONF_LENGTH),)
+BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize=$(CONFIG_ECAM_MMCONF_LENGTH)
+endif
+# PRIORITIZE_INTERNAL		= FALSE
+ifeq ($(CONFIG_TIANOCORE_PRIORITIZE_INTERNAL),y)
+BUILD_STR += -D PRIORITIZE_INTERNAL=TRUE
+endif
+# PS2_KEYBOARD_ENABLE		= FALSE
+ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
+BUILD_STR += -D PS2_KEYBOARD_ENABLE=TRUE
+endif
+# PLATFORM_BOOT_TIMEOUT		= 3
+ifneq ($(CONFIG_TIANOCORE_BOOT_TIMEOUT),)
+BUILD_STR += -D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
+endif
+# SIO_BUS_ENABLE		= FALSE
+ifeq ($(CONFIG_TIANOCORE_PS2_SUPPORT),y)
+BUILD_STR += -D SIO_BUS_ENABLE=TRUE
+endif
+# SHELL_TYPE			= BUILD_SHELL
+ifneq ($(CONFIG_TIANOCORE_HAVE_EFI_SHELL),y)
+BUILD_STR += -D SHELL_TYPE=NONE
+endif
+# USE_CBMEM_FOR_CONSOLE		= FALSE
+ifeq ($(CONFIG_TIANOCORE_CBMEM_LOGGING),y)
+BUILD_STR += -D USE_CBMEM_FOR_CONSOLE=TRUE
+endif
+# SD_MMC_TIMEOUT		= 1000000
+ifneq ($(CONFIG_TIANOCORE_SD_MMC_TIMEOUT),)
+BUILD_STR += -D SD_MMC_TIMEOUT=$(call int-multiply, $(CONFIG_TIANOCORE_SD_MMC_TIMEOUT) 1000)
+endif
+#
+# EDKII has the below PCDs that are revalant to coreboot:
+#
+# Allows EDKII to use the full framebuffer
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow=0
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn=0
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow=0
+BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn=0
+#
+# The below are legacy options only available in CorebootPayloadPkg:
+#
+# PCIE_BASE			= 0
+ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
+ifneq ($(CONFIG_ECAM_MMCONF_BASE_ADDRESS),)
+BUILD_STR += -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS)
+endif
+# USE_HPET_TIMER		= FALSE
+ifeq ($(CONFIG_TIANOCORE_USE_8254_TIMER),y)
+BUILD_STR += -D USE_HPET_TIMER=TRUE
+endif
+endif # CONFIG_TIANOCORE_COREBOOTPAYLOAD
+
+bootloader = $(word 8,$(subst /, ,$(BUILD_STR)))
+
+ifeq ($(CONFIG_TIANOCORE_CUSTOM),y)
+ifneq ($(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS),)
+BUILD_STR += $(CONFIG_TIANOCORE_CUSTOM_BUILD_PARAMS)
+endif
+endif
+
+all: clean build
+
+$(project_dir):
+	echo "    Cloning $(project_name) from $(CONFIG_TIANOCORE_REPOSITORY)"
+	git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
+		cd $(project_dir);
+
+update: $(project_dir)
+	if [ ! -d "$(project_dir)" ]; then \
+		git clone $(CONFIG_TIANOCORE_REPOSITORY) $(project_dir); \
+	fi
+	cd  $(project_dir); \
+		echo "    Fetching new commits from $(CONFIG_TIANOCORE_REPOSITORY)"; \
+		git fetch origin 2>/dev/null; \
+		if ! git rev-parse --verify -q $(CONFIG_TIANOCORE_TAG_OR_REV) >/dev/null; then \
+			echo "    $(CONFIG_TIANOCORE_TAG_OR_REV) is not a valid git reference"; \
+			exit 1; \
+		fi; \
+		if git status --ignore-submodules=dirty | grep -q clean; then \
+			echo "    Checking out $(project_name) revision $(CONFIG_TIANOCORE_TAG_OR_REV)"; \
+			git checkout --detach $(CONFIG_TIANOCORE_TAG_OR_REV) -f; \
+		else \
+			echo "    Working directory not clean; will not overwrite"; \
+		fi; \
+		git submodule update --init --checkout
+
+checktools:
+	echo "Checking uuid-dev..."
+	echo "#include <uuid/uuid.h>" > libtest.c
+	echo "int main(int argc, char **argv) { (void) argc; (void) argv; return 0; }" >> libtest.c
+	$(HOSTCC) $(HOSTCCFLAGS) libtest.c -o libtest >/dev/null 2>&1 && echo " found uuid-dev." || \
+		( echo " Not found."; echo "ERROR: please_install uuid-dev (libuuid-devel)"; exit 1 )
+	rm -rf libtest.c libtest
+	echo "Checking nasm..."
+	type nasm > /dev/null 2>&1 && echo " found nasm." || \
+		( echo " Not found."; echo "Error: Please install nasm."; exit 1 )
+
+build: update checktools
+	echo "   ##### $(project_name) Build Summary #####"
+	echo "   Repository:     $(CONFIG_TIANOCORE_REPOSITORY)"
+	echo "   Branch:         $(CONFIG_TIANOCORE_TAG_OR_REV)"
+	echo " $(BUILD_STR)" | \
+		sed 's/-/\n   /g' | sort | sed \
+		-e 's/a /Architecture:   /g' \
+		-e 's/b /Release:        /g' \
+		-e 's/D /Option:         /g' \
+		-e 's/p /Payload:        /g' \
+		-e 's/q /Build:          Quiet/' \
+		-e 's/t /Toolchain:      /'
+	unset CC; $(MAKE) -C $(project_dir)/BaseTools 2>&1
+	if [ -n "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" ]; then \
+		echo "    Copying custom bootsplash image"; \
+		case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \
+			/*) convert $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+			*) convert $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
+				BMP3:$(project_dir)/MdeModulePkg/Logo/Logo.bmp;; \
+		esac \
+	fi; \
+	cd $(project_dir); \
+		export EDK_TOOLS_PATH=$(project_dir)/BaseTools; \
+		export WORKSPACE=$(project_dir); \
+		. ./edksetup.sh BaseTools; \
+		grep -q "COREBOOT" $(project_dir)/Conf/tools_def.txt; \
+		if [ $$? -ne 0 ]; then \
+			cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \
+		fi; \
+		build $(BUILD_STR); \
+		mkdir -p $(project_dir)/../output
+		mv $(project_dir)/Build/$(bootloader)*/*/FV/UEFIPAYLOAD.fd $(project_dir)/../output/UEFIPAYLOAD.fd; \
+		git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true
+
+clean:
+	test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0
+
+distclean:
+	rm -rf */
+
+.PHONY: all update checktools config build clean distclean

payloads/external/tianocore/tools_def.txt

@@ -15,7 +15,7 @@
 #
 
 #The following has been adapted from the BaseTools/Conf/tools_def.template file
-#and is used to direct the edk2 build to use coreboot's crossgcc toolchain
+#and is used to direct the Tianocore build to use coreboot's crossgcc toolchain
 #rather than the host machine's toolchain
 
 DEFINE COREBOOT_IA32_PREFIX    = ENV(GCC_CC_x86_32)

payloads/libpayload/Kconfig

@@ -418,11 +418,6 @@ config PCIE_MEDIATEK
 	depends on PCI && !PCI_IO_OPS
 	default n
 
-config PCIE_QCOM
-	bool "Support for PCIe devices on Qualcomm platforms"
-	depends on PCI && !PCI_IO_OPS
-	default n
-
 config NVRAM
 	bool "Support for reading/writing NVRAM bytes"
 	depends on ARCH_X86 # for now

payloads/libpayload/arch/x86/Makefile.inc

@@ -32,7 +32,7 @@ head.o-y += head.S
 libc-y += main.c sysinfo.c
 libc-y += timer.c coreboot.c util.S
 libc-y += exec.S virtual.c
-libc-y += selfboot.c cache.c
+libc-y += selfboot.c
 libc-y += exception_asm.S exception.c
 libc-y += delay.c
 

payloads/libpayload/arch/x86/cache.c

@@ -1,134 +0,0 @@
-/*
- *
- * Copyright 2022 Google LLC
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- */
-
-#include <stdint.h>
-
-#include <arch/cache.h>
-#include <arch/cpuid.h>
-
-unsigned int dcache_line_bytes(void)
-{
-	/*
-	 * The value returned in EBX[15:8] is in 8-byte increments.
-	 * Cache line size is EBX[15:8] * 8
-	 */
-	return (cpuid_ebx(1) & 0xff00) >> 5;
-}
-
-static inline int cpu_supports_wbnoinvd(void)
-{
-	return (cpuid_ebx(0x80000008) >> 9) & 1;
-}
-
-static inline int cpu_supports_clwb(void)
-{
-	return (cpuid_ebx(7) >> 24) & 1;
-}
-
-static inline int cpu_supports_clflushopt(void)
-{
-	return (cpuid_sub_leaf_ebx(7, 0) >> 23) & 1;
-}
-
-static inline int cpu_supports_clflush(void)
-{
-	return (cpuid_ebx(1) >> 19) & 1;
-}
-
-inline void dcache_invalidate_all(void)
-{
-	asm volatile("invd" ::: "memory");
-}
-
-inline void dcache_clean_invalidate_all(void)
-{
-	asm volatile("wbinvd" ::: "memory");
-}
-
-inline void dcache_clean_all(void)
-{
-	if (cpu_supports_wbnoinvd()) {
-		asm volatile(
-			"sfence\n\t"
-			"wbnoinvd\n\t"
-		::: "memory");
-	} else {
-		dcache_clean_invalidate_all();
-	}
-}
-
-void dcache_clean_by_mva(void const *addr, size_t len)
-{
-	unsigned long line, linesize;
-
-	linesize = dcache_line_bytes();
-	line = (uintptr_t)addr & ~(linesize - 1);
-
-	if (cpu_supports_clwb()) {
-		asm volatile("sfence");
-		while (line < (uintptr_t)addr + len) {
-			asm volatile("clwb (%0)" : : "r"(line) : "memory");
-			line += linesize;
-		}
-	} else {
-		dcache_clean_invalidate_by_mva(addr, len);
-	}
-}
-
-void dcache_invalidate_by_mva(void const *addr, size_t len)
-{
-	/*
-	 * x86 doesn't have a "invalidate without clean" for a cache line, fall
-	 * back to both.
-	 */
-	dcache_clean_invalidate_by_mva(addr, len);
-}
-
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
-{
-	unsigned long line, linesize;
-
-	linesize = dcache_line_bytes();
-	line = (uintptr_t)addr & ~(linesize - 1);
-
-	if (cpu_supports_clflushopt()) {
-		asm volatile("sfence");
-		while (line < (uintptr_t)addr + len) {
-			asm volatile("clflushopt (%0)" ::"r"(line) : "memory");
-			line += linesize;
-		}
-	} else if (cpu_supports_clflush()) {
-		asm volatile("sfence");
-		while (line < (uintptr_t)addr + len) {
-			asm volatile("clflush (%0)" : : "r"(line) : "memory");
-			line += linesize;
-		}
-	} else {
-		dcache_clean_invalidate_all();
-	}
-}

payloads/libpayload/configs/config.herobrine

@@ -3,5 +3,3 @@ CONFIG_LP_ARCH_ARM64=y
 CONFIG_LP_TIMER_ARM64_ARCH=y
 CONFIG_LP_SERIAL_CONSOLE=y
 CONFIG_LP_QUALCOMM_QUPV3_SERIAL_CONSOLE=y
-CONFIG_LP_PCI=y
-CONFIG_LP_PCIE_QCOM=y

payloads/libpayload/drivers/Makefile.inc

@@ -37,7 +37,6 @@ libc-$(CONFIG_LP_PCI) += pci_map_bus_ops.c
 endif
 
 libc-$(CONFIG_LP_PCIE_MEDIATEK) += pcie_mediatek.c
-libc-$(CONFIG_LP_PCIE_QCOM) += pci_qcom.c
 
 libc-$(CONFIG_LP_SPEAKER) += speaker.c
 

payloads/libpayload/drivers/pci_qcom.c

@@ -1,126 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <libpayload.h>
-#include <pci.h>
-
-/*
- * iATU Unroll-specific register definitions
- */
-#define PCIE_ATU_UNR_REGION_CTRL1	0x00
-#define PCIE_ATU_UNR_REGION_CTRL2	0x04
-#define PCIE_ATU_UNR_LOWER_BASE		0x08
-#define PCIE_ATU_UNR_UPPER_BASE		0x0C
-#define PCIE_ATU_UNR_LIMIT		0x10
-#define PCIE_ATU_UNR_LOWER_TARGET	0x14
-#define PCIE_ATU_UNR_UPPER_TARGET	0x18
-#define PCIE_ATU_REGION_INDEX0		0x0
-#define PCIE_ATU_TYPE_CFG0		0x4
-#define PCIE_ATU_TYPE_CFG1		0x5
-#define PCIE_ATU_ENABLE			BIT(31)
-#define ATU_CTRL2			PCIE_ATU_UNR_REGION_CTRL2
-#define ATU_ENABLE			PCIE_ATU_ENABLE
-
-#define PCIE_ATU_BUS(x)			(((x) & 0xff) << 24)
-#define PCIE_ATU_DEV(x)			(((x) & 0x1f) << 19)
-#define PCIE_ATU_FUNC(x)		(((x) & 0x7) << 16)
-#define LINK_WAIT_IATU_US		1000
-#define LINK_WAIT_MAX_IATU_RETRIES	5
-
-/* Register address builder */
-#define PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(region) ((region) << 9)
-
-#define lower_32_bits(n)		((u32)(n))
-#define upper_32_bits(n)		((u32)(((n) >> 16) >> 16))
-
-/*
- * ATU & endpoint config space base address offsets relative to
- * PCIe controller base address.
- */
-#define QCOM_ATU_BASE_OFFSET		0x1000
-#define QCOM_EP_CFG_OFFSET		0x100000
-#define QCOM_EP_CFG_SIZE		0x1000    /* 4K */
-
-static void dw_pcie_writel_iatu(void *atu_base, unsigned short index,
-				uint32_t reg, uint32_t val)
-{
-	uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
-
-	write32(atu_base + offset + reg, val);
-}
-
-static uint32_t dw_pcie_readl_iatu(void *atu_base, unsigned short index,
-				   uint32_t reg)
-{
-	uint32_t offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
-
-	return read32(atu_base + offset + reg);
-}
-
-static void dw_pcie_prog_outbound_atu(void *atu_base, unsigned short index,
-				      unsigned int type, uint64_t cfg_addr,
-				      uint64_t pcie_addr, uint32_t cfg_size)
-{
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LOWER_BASE,
-			    lower_32_bits(cfg_addr));
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_UPPER_BASE,
-			    upper_32_bits(cfg_addr));
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LIMIT,
-			    lower_32_bits(cfg_addr + cfg_size - 1));
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_LOWER_TARGET,
-			    lower_32_bits(pcie_addr));
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_UPPER_TARGET,
-			    upper_32_bits(pcie_addr));
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_REGION_CTRL1, type);
-	dw_pcie_writel_iatu(atu_base, index, PCIE_ATU_UNR_REGION_CTRL2,
-			    PCIE_ATU_ENABLE);
-	/*
-	 * Make sure ATU enable takes effect before any subsequent config
-	 * and I/O accesses.
-	 */
-	if (retry(LINK_WAIT_MAX_IATU_RETRIES,
-		  (dw_pcie_readl_iatu(atu_base, index, ATU_CTRL2) & ATU_ENABLE),
-		  udelay(LINK_WAIT_IATU_US)))
-		return;
-
-	printf("outbound iATU is couldn't be enabled after 5ms\n");
-}
-
-/* Get PCIe MMIO configuration space base address */
-uintptr_t pci_map_bus(pcidev_t dev)
-{
-	unsigned int atu_type, busdev;
-	uint32_t config_size;
-	void *cntrlr_base, *config_base, *atu_base;
-	unsigned int current_bus = PCI_BUS(dev);
-	unsigned int devfn = (PCI_SLOT(dev) << 3) | PCI_FUNC(dev);
-	static pcidev_t current_dev;
-
-	/*
-	 * Extract PCIe controller base from coreboot and derive the ATU and
-	 * endpoint config base addresses from it.
-	 */
-	cntrlr_base = (void *)lib_sysinfo.pcie_ctrl_base;
-	config_base = (void *)cntrlr_base + QCOM_EP_CFG_OFFSET;
-	config_size = (uint32_t)QCOM_EP_CFG_SIZE;
-	atu_base = (void *)cntrlr_base + QCOM_ATU_BASE_OFFSET;
-
-	/*
-	 * Cache the dev. For same dev, ATU mapping is not needed for each
-	 * request.
-	 */
-	if (current_dev == dev)
-		goto out;
-
-	current_dev = dev;
-
-	busdev = PCIE_ATU_BUS(current_bus)   |
-		 PCIE_ATU_DEV(PCI_SLOT(dev)) |
-		 PCIE_ATU_FUNC(PCI_FUNC(dev));
-
-	atu_type = current_bus == 1 ? PCIE_ATU_TYPE_CFG0 : PCIE_ATU_TYPE_CFG1;
-
-	dw_pcie_prog_outbound_atu(atu_base, PCIE_ATU_REGION_INDEX0, atu_type,
-				  (uint64_t)config_base, busdev, config_size);
-out:
-	return (uintptr_t)config_base + (QCOM_EP_CFG_SIZE * devfn);
-}

payloads/libpayload/drivers/udc/chipidea.c

@@ -221,10 +221,10 @@ static void advance_endpoint(struct chipidea_pdata *p, int endpoint, int in_dir)
 
 	job->tds = tds;
 	job->td_count = td_count;
+
 	dcache_clean_by_mva(tds, sizeof(struct td) * td_count);
+	dcache_clean_by_mva(job->data, job->length);
 	dcache_clean_by_mva(qh, sizeof(*qh));
-	if (!dma_coherent(job->data))
-		dcache_clean_by_mva(job->data, job->length);
 
 	debug("priming EP %d-%d with %zx bytes starting at %x (%p)\n", endpoint,
 		in_dir, job->length, tds[0].page0, job->data);
@@ -240,7 +240,7 @@ static void handle_endpoint(struct usbdev_ctrl *this, int endpoint, int in_dir)
 	struct job *job = SIMPLEQ_FIRST(&p->job_queue[endpoint][in_dir]);
 	SIMPLEQ_REMOVE_HEAD(&p->job_queue[endpoint][in_dir], queue);
 
-	if (in_dir && !dma_coherent(job->data))
+	if (in_dir)
 		dcache_invalidate_by_mva(job->data, job->length);
 
 	int length = job->length;

payloads/libpayload/drivers/usb/dwc2.h

@@ -17,6 +17,6 @@
 #include <usb/usb.h>
 
 hci_t *dwc2_init(void *bar);
-void dwc2_rh_init(usbdev_t *dev);
+void dwc2_rh_init (usbdev_t *dev);
 
 #endif

payloads/libpayload/drivers/usb/ehci.c

@@ -119,17 +119,17 @@ static void dump_qh(ehci_qh_t *cur)
 }
 #endif
 
-static void ehci_start(hci_t *controller)
+static void ehci_start (hci_t *controller)
 {
 	EHCI_INST(controller)->operation->usbcmd |= HC_OP_RS;
 }
 
-static void ehci_stop(hci_t *controller)
+static void ehci_stop (hci_t *controller)
 {
 	EHCI_INST(controller)->operation->usbcmd &= ~HC_OP_RS;
 }
 
-static void ehci_reset(hci_t *controller)
+static void ehci_reset (hci_t *controller)
 {
 	short count = 0;
 	ehci_stop(controller);
@@ -148,7 +148,7 @@ static void ehci_reset(hci_t *controller)
 	usb_debug("ehci_reset(): reset failed!\n");
 }
 
-static void ehci_reinit(hci_t *controller)
+static void ehci_reinit (hci_t *controller)
 {
 }
 
@@ -174,7 +174,7 @@ static int ehci_set_periodic_schedule(ehci_t *ehcic, int enable)
 	return 0;
 }
 
-static void ehci_shutdown(hci_t *controller)
+static void ehci_shutdown (hci_t *controller)
 {
 	detach_controller(controller);
 
@@ -192,7 +192,7 @@ static void ehci_shutdown(hci_t *controller)
 	free(controller);
 }
 
-enum { EHCI_OUT = 0, EHCI_IN = 1, EHCI_SETUP = 2 };
+enum { EHCI_OUT=0, EHCI_IN=1, EHCI_SETUP=2 };
 
 /* returns handled bytes. assumes that the fields it writes are empty on entry */
 static int fill_td(qtd_t *td, void* data, int datalen)
@@ -341,7 +341,7 @@ static int ehci_process_async_schedule(
 	return result;
 }
 
-static int ehci_bulk(endpoint_t *ep, int size, u8 *src, int finalize)
+static int ehci_bulk (endpoint_t *ep, int size, u8 *src, int finalize)
 {
 	int result = 0;
 	u8 *end = src + size;
@@ -430,7 +430,7 @@ oom:
 }
 
 /* FIXME: Handle control transfers as 3 QHs, so the 2nd stage can be >0x4000 bytes */
-static int ehci_control(usbdev_t *dev, direction_t dir, int drlen, void *setup,
+static int ehci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup,
 			 int dalen, u8 *src)
 {
 	u8 *data = src;
@@ -771,11 +771,11 @@ static u8 *ehci_poll_intr_queue(void *const queue)
 }
 
 hci_t *
-ehci_init(unsigned long physical_bar)
+ehci_init (unsigned long physical_bar)
 {
 	int i;
-	hci_t *controller = new_controller();
-	controller->instance = xzalloc(sizeof(ehci_t));
+	hci_t *controller = new_controller ();
+	controller->instance = xzalloc(sizeof (ehci_t));
 	controller->reg_base = (uintptr_t)physical_bar;
 	controller->type = EHCI;
 	controller->start = ehci_start;
@@ -791,7 +791,7 @@ ehci_init(unsigned long physical_bar)
 	controller->create_intr_queue = ehci_create_intr_queue;
 	controller->destroy_intr_queue = ehci_destroy_intr_queue;
 	controller->poll_intr_queue = ehci_poll_intr_queue;
-	init_device_entry(controller, 0);
+	init_device_entry (controller, 0);
 
 	EHCI_INST(controller)->capabilities = phys_to_virt(physical_bar);
 	EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(physical_bar) + EHCI_INST(controller)->capabilities->caplength);
@@ -848,23 +848,23 @@ ehci_init(unsigned long physical_bar)
 
 	controller->devices[0]->controller = controller;
 	controller->devices[0]->init = ehci_rh_init;
-	controller->devices[0]->init(controller->devices[0]);
+	controller->devices[0]->init (controller->devices[0]);
 
 	return controller;
 }
 
 #if CONFIG(LP_USB_PCI)
 hci_t *
-ehci_pci_init(pcidev_t addr)
+ehci_pci_init (pcidev_t addr)
 {
 	hci_t *controller;
 	u32 reg_base;
 
 	u16 pci_command = pci_read_config16(addr, PCI_COMMAND);
-	pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO;
+	pci_command = (pci_command | PCI_COMMAND_MEMORY) & ~PCI_COMMAND_IO ;
 	pci_write_config16(addr, PCI_COMMAND, pci_command);
 
-	reg_base = pci_read_config32(addr, USBBASE);
+	reg_base = pci_read_config32 (addr, USBBASE);
 
 	/* default value for frame length adjust */
 	pci_write_config8(addr, FLADJ, FLADJ_framelength(60000));

payloads/libpayload/drivers/usb/ehci.h

@@ -32,9 +32,9 @@
 #include <pci.h>
 #include <usb/usb.h>
 
-hci_t *ehci_pci_init(pcidev_t addr);
-hci_t *ehci_init(unsigned long physical_bar);
+hci_t *ehci_pci_init (pcidev_t addr);
+hci_t *ehci_init (unsigned long physical_bar);
 
-void ehci_rh_init(usbdev_t *dev);
+void ehci_rh_init (usbdev_t *dev);
 
 #endif