[WIP] mb/system76/oryp4: Add System76 Oryx Pro 4

Change-Id: I879352c61e041ffefa87e1307e2b650a30f826a4
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
---ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS

.gitignore

@@ -33,7 +33,6 @@ tags
 .clang_complete
 .cache
 compile_commands.json
-.vscode/
 
 # Cross-compile toolkits
 xgcc/

.gitmodules

@@ -61,7 +61,3 @@
 	path = 3rdparty/stm
 	url = ../STM
 	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = ../goswid
-	branch = trunk

AUTHORS

@@ -108,7 +108,6 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
-Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

Documentation/Makefile

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 #
 # Makefile for coreboot paper.
 # hacked together by Stefan Reinauer <stepan@openbios.org>

Documentation/Makefile.sphinx

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 # Makefile for Sphinx documentation
 #
 

Documentation/RFC/intel-gpio-cleanup.md

@@ -51,7 +51,7 @@ index 28e78fb366..0cce41b316 100644
 @@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
                 /* Patch GPIO settings for SoC specifically */
                 soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
-
+ 
 -               if (CONFIG(DEBUG_GPIO))
 +               if (soc_pad_conf != pad_conf)
                         printk(BIOS_DEBUG,

Documentation/acpi/devicetree.md

@@ -0,0 +1,290 @@
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+### Naming and referencing devices
+
+When declaring a device, it can optionally be given an alias that can be
+referred to elsewhere. This is particularly useful to declare a device in one
+device tree while allowing its configuration to be more easily changed in an
+overlay. For instance, the AMD Picasso SoC definition
+(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
+by default:
+
+```
+chip soc/amd/picasso
+	device domain 0 on
+		...
+		device pci 00.2 alias iommu off end
+		...
+	end
+end
+```
+
+A device based on this SoC can override the configuration for the IOMMU without
+duplicating addresses, as in
+`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
+
+```
+chip soc/amd/picasso
+	device domain 0
+		...
+		device ref iommu on end
+		...
+	end
+end
+```
+
+In this example the override simply enables the IOMMU, but it could also
+set additional properties (or even add child devices) inside the IOMMU `device`
+block.
+
+---
+
+It is important to note that devices that use `device ref` syntax to override
+previous definitions of a device by alias must be placed at **exactly the same
+location in the device tree** as the original declaration. If not, this will
+actually create another device rather than overriding the properties of the
+existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
+were written as follows:
+
+```
+chip soc/amd/picasso
+	# NOTE: not inside domain 0!
+	device ref iommu on end
+end
+```
+
+Then this would leave the SoC's IOMMU disabled, and instead create a new device
+with no properties as a direct child of the SoC.
+
+## Device drivers
+
+Let's take a look at an example entry from
+``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
+
+```
+device pci 15.0 on
+	chip drivers/i2c/generic
+		register "hid" = ""ELAN0000""
+		register "desc" = ""ELAN Touchpad""
+		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+		register "wake" = "GPE0_DW0_21"
+		device i2c 15 on end
+	end
+end # I2C #0
+```
+
+When this entry is processed during ramstage, it will create a device in the
+ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
+generation routines in coreboot actually generate the raw bytecode that
+represents the device's structure, but looking at ASL code is easier to
+understand; see below for what the disassembled bytecode looks like:
+
+```
+Scope (\_SB.PCI0.I2C0)
+{
+    Device (D015)
+    {
+        Name (_HID, "ELAN0000")  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
+        Method (_STA, 0, NotSerialized)  // _STA: Status
+        {
+            Return (0x0F)
+        }
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                0x00, ResourceConsumer, , Exclusive, )
+            Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+            {
+                0x0000002D,
+            }
+        })
+        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
+        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+        {
+            0x15, // GPE #21
+            0x03  // Sleep state S3
+        })
+    }
+}
+```
+
+You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
+names/methods in the Device's scope.
+
+## Utilizing a device driver
+
+The device driver must be enabled for your build.  There will be a CONFIG option
+in the Kconfig file in the directory that the driver is in (e.g.,
+``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
+CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
+mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
+to be compiled into your build.
+
+## Diving into the above example:
+
+Let's take a look at how the devicetree language corresponds to the generated
+ASL.
+
+First, note this:
+
+```
+    chip drivers/i2c/generic
+```
+
+This means that the device driver we're using has a corresponding structure,
+located at ``src/drivers/i2c/generic/chip.h``, named **struct
+drivers_i2c_generic_config** and it contains many properties you can specify to
+be included in the ACPI table.
+
+### hid
+
+```
+    register "hid" = ""ELAN0000""
+```
+
+This corresponds to **const char *hid** in the struct.  In the ACPI ASL, it
+translates to:
+
+```
+    Name (_HID, "ELAN0000") // _HID: Hardware ID
+```
+
+under the device.  **This property is used to match the device to its driver
+during enumeration in the OS.**
+
+### desc
+
+```
+    register "desc" = ""ELAN Touchpad""
+```
+
+corresponds to **const char *desc** and in ASL:
+
+```
+    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
+```
+
+### irq
+
+It also adds the interrupt,
+
+```
+    Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+    {
+        0x0000002D,
+    }
+```
+
+which comes from:
+
+```
+    register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+```
+
+The GPIO pin IRQ settings control the "Level", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (level means it is a level-triggered
+interrupt as opposed to edge-triggered; active low means the interrupt is
+triggered when the signal is low).
+
+Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
+will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
+source.  Also note that the IRQ names are SoC-specific, and you will need to
+find the names in your SoC's header file.  The ACPI_* macros are defined in
+``src/arch/x86/include/acpi/acpi_device.h``.
+
+Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
+This is often done in a mainboard-specific file named ``gpio.c``.
+
+### wake
+
+The last register is:
+
+```
+    register "wake" = "GPE0_DW0_21"
+```
+
+which indicates that the method of waking the system using the touchpad will be
+through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
+this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
+elsewhere in the devicetree.
+
+The last bit of the definition of that device includes:
+
+```
+    device i2c 15 on end
+```
+
+which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
+meaning it will be exposed in the ACPI table.  The PCI device that the
+controller is located in determines which I2C bus the device is expected to be
+found on.  In this example, this is I2C bus 0.  This also determines the ACPI
+"Scope" that the device names and methods will live under, in this case
+"\_SB.PCI0.I2C0".
+
+## Other auto-generated names
+
+(see [ACPI specification
+6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
+for more details on ACPI methods)
+
+### _S0W (S0 Device Wake State)
+_S0W indicates the deepest S0 sleep state this device can wake itself from,
+which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
+
+### _PRW (Power Resources for Wake)
+_PRW indicates the power resources and events required for wake.  There are no
+dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
+as well as the deepest sleep state supporting waking the system (3), which is
+S3.
+
+### _STA (Status)
+The _STA method is generated automatically, and its values, 0xF, indicates the
+following:
+
+    Bit [0] – Set if the device is present.
+    Bit [1] – Set if the device is enabled and decoding its resources.
+    Bit [2] – Set if the device should be shown in the UI.
+    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
+
+### _CRS (Current resource settings)
+The _CRS method is generated automatically, as the driver knows it is an I2C
+controller, and so specifies how to configure the controller for proper
+operation with the touchpad.
+
+```
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                    0x00, ResourceConsumer, , Exclusive, )
+```
+
+## Notes
+
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/acpi/index.md

@@ -10,3 +10,7 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
+
+## devicetree
+
+- [Adding devices to a device tree](devicetree.md)

Documentation/acronyms.md

@@ -11,7 +11,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 `acpihelp _XXX`
 * 2FA - [**Two-factor Authentication**](https://en.wikipedia.org/wiki/Multi-factor_authentication)
 * 4G - In coreboot, this typically refers to the 4 gibibyte boundary of 32-bit addressable memory space.
-  Better abbreviated as 4GiB
 * 5G - Telecommunication: [**Fifth-Generation Cellular Network**](https://en.wikipedia.org/wiki/5G)
 
 ## A
@@ -46,10 +45,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ALIB - AMD: ACPI-ASL Library
 * ALS - [**Ambient Light Sensor**](https://en.wikipedia.org/wiki/Ambient_light_sensor)
 * ALU - [**Arithmetic Logic Unit**](https://en.wikipedia.org/wiki/Arithmetic_logic_unit)
-* AMBA - ARM: [**Advanced Microcontroller Bus
-  Architecture**](https://en.wikipedia.org/wiki/Advanced_Microcontroller_Bus_Architecture):
-  An open standard to connect and manage functional blocks in an SoC
-  (System on a Chip)
 * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
 * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
   SBI: Sideband Interface
@@ -58,8 +53,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * AOAC - AMD: Always On, Always Connected
 * AP - Application processor - The main processor on the board (as
   opposed to the embedded controller or other processors that may be on
-  the system), any cores in the processor chip that aren't the BSP (Boot
-  Strap Processor).
+  the system), any cores in processor chip that isn’t the BSP - Boot
+  Strap Processor.
 * APCB - AMD: AMD PSP Customization Block
 * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
 * APIC - [**Advanced Programmable Interrupt
@@ -128,7 +123,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   stored as a single object, this was co-opted by the open source
   communities to mean any proprietary binary file that is not available
   as source code.
-* BM - [**Bus Master**](https://en.wikipedia.org/wiki/Bus_mastering)
 * BMC - [**Baseboard Management Controller**](https://en.wikipedia.org/wiki/Intelligent_Platform_Management_Interface#Baseboard_management_controller)
 * BMP - [**Bitmap**](https://en.wikipedia.org/wiki/BMP_file_format)
 * BOM - [**Bill of Materials**](https://en.wikipedia.org/wiki/Bill_of_materials)
@@ -171,8 +165,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CID - [**Coverity ID**](https://en.wikipedia.org/wiki/Coverity)
 * CIM - [**Common Information Model**](https://www.dmtf.org/standards/cim)
 * CISC - [**Complex Instruction Set Computer**](https://en.wikipedia.org/wiki/Complex_instruction_set_computer)
-* CL - ChangeList - Another name for a patch or commit.  This seems to be
-  Perforce notation.
+* CL - Change List - A git patch in gerrit
 * CLK - Clock - Used when there isn't enough room for 2 additional
   characters - similar to RST, for people who hate vowels.
 * CML - Intel: [**Comet Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/comet_lake)
@@ -187,7 +180,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
 * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
 * CPLD - [**Complex Programmable Logic Device**](https://en.wikipedia.org/wiki/Complex_programmable_logic_device)
-* CPPC - AMD: Collaborative Processor Performance Controls
 * CPS - Characters Per Second
 * CPU - [**Central Processing
   Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
@@ -204,14 +196,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CSI - MIPI: [**Camera Serial
   Interface**](https://en.wikipedia.org/wiki/Camera_Serial_Interface)
 * CSME - Intel: Converged Security and Management Engine
-* CTLE - Intel: Continuous Time Linear Equalization
 * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
-* CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
+* CZN - AMD: Cezanne - CPU Family 19h, Model 50h
 
 
 ## D
 
-* D$ - Data Cache
 * D-States - [**ACPI Device power
   states**](https://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface#Device_states)
   D0-D3 - These are device specific power states, with each higher
@@ -233,8 +223,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DDC - [**Display Data Channel**](https://en.wikipedia.org/wiki/Display_Data_Channel)
 * DDI -  Intel: Digital Display Interface
 * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
-* DEVAPC - Mediatek: Device Access Permission Control
-* DFP - USB: Downstream Facing port
 * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
 * DID - Device Identifier
 * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
@@ -247,7 +235,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Graphics Card, Sound Card. DMA is an essential feature of all modern
   computers, as it allows devices of different speeds to communicate
   without subjecting the CPU to a massive interrupt load.
-* DMI - Direct Media Interface is a link/bus between CPU and PCH.
 * DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
 * DMIC - Digital Microphone
 * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
@@ -256,7 +243,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DNV - Intel: [**Denverton**](https://en.wikichip.org/wiki/intel/cores/denverton)
 * DOS - Disk Operating System
 * DP - DisplayPort
-* DPM - Mediatek: DRAM Power Manager
 * DPTF - Intel: Dynamic Power and Thermal Framework
 * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
 * DRTM - Dynamic Root of Trust for Measurement
@@ -264,10 +250,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   data-in pin is generally referred to as D, and the data-out pin is Q,
   thus the IO Data signal lines are referred to as DQ lines.
 * DQS - Memory: Data Q Strobe - Data valid signal for DDR memory.
-* DRM - [**Digital Rights
-  Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
-* DRP - USB: Port than can be switched between either a Downstream facing (DFP) or
-  an Upstream Facing (UFP).
+* DRM - [**Digital Rights Management**](https://en.wikipedia.org/wiki/Digital_rights_management)
 * DRQ - DMA Request
 * DRTU - Intel: Diagnostics and Regulatory Testing Utility
 * DSDT - The [**Differentiated System Descriptor
@@ -279,15 +262,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DSL - [**Digital subscriber line**](https://en.wikipedia.org/wiki/Digital_subscriber_line)
 * DSP - [**Digital Signal Processor**](https://en.wikipedia.org/wiki/Digital_signal_processor)
 * DTB - U-Boot: Device Tree Binary
-* dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
-  vs Integrated TPMs or fTPMs (Firmware TPMs).
+* dTPM - Discrete Trusted Platform Module
 * DTS - U-Boot: Device Tree Source
 * DVFS - ARM: Dynamic Voltage and Frequency Scaling
 * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
 * DVT - Production Timeline: Design Validation Test
-* DW - DesignWare: A portfolio of silicon IP blocks for sale by the
-  Synopsys company.  Includes blocks like USB, MIPI, PCIe, HDMI, SATA,
-  I2c, memory controllers and more.
+* DW - DesignWare
 * DXE - UEFI:  [**Driver Execution Environment**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface#DXE_%E2%80%93_Driver_Execution_Environment_)
 * DXIO - AMD: Distributed CrossBar I/O
 
@@ -298,12 +278,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* edk2 - EFI Development Kit 2
+* EDK2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was
   backwards compatible with FPM (Fast Page Mode) memory.
-* eDP - [**Embedded DisplayPort**](https://en.wikipedia.org/wiki/DisplayPort#eDP)
+* EDP - [**Embedded DisplayPort**](DisplayPort)
 * EDS - Intel: External Design Specification
 * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
   electrical erasable programmable ROM).
@@ -360,9 +340,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
 * FSP - Intel: Firmware Support Package
 * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
-* fTPM - Firmware TPM (Trusted Platform Module).  This is a TPM that is
-  based in firmware instead of actual hardware.  It typically runs in
-  some sort of TEE (Trusted Execution Environment).
+* FTPM - Firmware TPM
 
 
 ## G
@@ -378,7 +356,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Real Time Clock, and maybe a few other registers running.
 * GART - AMD: [**Graphics Address Remapping Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
 * GATT - Graphics Aperture Translation Table
-* GDT - [Global Descriptor Table](https://wiki.osdev.org/Global_Descriptor_Table)
 * GLK - Intel: [**Gemini Lake**](https://en.wikichip.org/wiki/intel/cores/gemini_lake)
 * GMA - Intel: [**Graphics Media
   Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
@@ -430,7 +407,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## I
 
-* I$ - Instruction Cache
 * I2C - **Inter-Integrated Circuit** is a bidirectional 2-wire bus for
   communication generally between different ICs on a circuit board.
   * [https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html](https://www.esacademy.com/en/library/technical-articles-and-documents/miscellaneous/i2c-bus.html)
@@ -452,7 +428,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IDSEL/AD - Initialization Device SELect/Address and Data. Each PCI
   slot has a signal called IDSEL. It is used to differentiate between
   the different slots.
-* IDT - [Interrupt Descriptor Table](https://en.wikipedia.org/wiki/Interrupt_descriptor_table)
 * IF - AMD: [**Infinity
   Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
   is a superset of AMD's earlier Hypertransport interconnect.
@@ -564,9 +539,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MCU - Memory Control Unit
 * MCU - [**MicroController
   Unit**](https://en.wikipedia.org/wiki/Microcontroller)
-* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MDFIO - Intel: Multi-Die Fabric IO
-* MDN - AMD: Mendocino
 * ME - Intel: Management Engine
 * MEI - Intel: ME Interface (Previously known as HECI)
 * Memory training - the process of finding the best speeds, voltages,
@@ -605,7 +578,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   OS software writers to produce SMP-capable machines and OSes in a
   vendor-independent manner. Version 1.1 of the spec was released in
   1994, and the 1.4 version was released in 1995.  This has been
-  generally superseded by the ACPI tables.
+  generally been
+  https://en.wikipedia.org/wiki/MultiProcessor_Specification by the ACPI
+  tables.
 * MRC - Intel: Memory Reference Code
 * MSB - Most Significant Bit
 * MSI - Message Signaled Interrupt
@@ -613,13 +588,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MT/s - MegaTransfers per second
 * MTL - Intel: Meteor Lake
 * MTL - ARM: MHU Transport Layer
-* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
-  allows to set the cache behaviour on memory access in x86. Basically,
-  it tells the CPU how to cache certain ranges of memory
-  (e.g. write-through, write-combining, write-back...). Memory ranges
-  are specified over physical address ranges. In Linux, they are visible
-  over `/proc/mtrr` and they can be modified there. For further
-  information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
+* MTRR - [**Memory Type and Range
+  Register**](http://en.wikipedia.org/wiki/MTRR)
 
 
 ## N
@@ -651,8 +621,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 * ODH - GPIOs: Open Drain High - High is driven to the reference voltage, low is a high-impedance state
 * ODL - GPIOs: Open Drain Low - Low is driven to ground, High is a high-impedance state.
-* ODM - [**Original Design Manufacturer**](https://en.wikipedia.org/wiki/Original_design_manufacturer)
-* OEM - [**Original Equipment Manufacturer**](https://en.wikipedia.org/wiki/Original_equipment_manufacturer)
+* ODM - Original Design Manufacturer
+* OEM - Original Equipment Manufacturer
 * OHCI - [**Open Host Controller
   Interface**](https://en.wikipedia.org/wiki/Host_Controller_Interface_%28USB%29)
   - non-proprietary USB Host controller for USB 1.1 (May also refer to
@@ -673,9 +643,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PAT - [**Page Attribute
   Table**](https://en.wikipedia.org/wiki/Page_attribute_table) This can
   be used independently or in combination with MTRR to setup memory type
-  access ranges. Allows more finely-grained control than MTRR. Compared to MTRR,
-  which sets memory types by physical address ranges, PAT sets them at Page
-  level.
+  access ranges. Allows more finely-grained control than MTRR.
 * PAT - Intel: [**Performance Acceleration
   Technology**](https://en.wikipedia.org/wiki/Performance_acceleration_technology)
 * PATA - Parallel Advanced Technology Attachment - A renaming of ATA
@@ -701,7 +669,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   function's configuration space from 256 bytes to 4K.
 * PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
 * PCMCIA: Personal Computer Memory Card International Association
-* PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
+* PCO - AMD: Picasso
 * PCR: TPM: Platform Configuration Register
 * PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage.  Setting it low drives it to ground through a resistor.
 * PD - Power Delivery - This is a specification for communicating power
@@ -869,7 +837,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
   Memory)
 * SEV - AMD: Secure Encrypted Virtualization
-* SF - Snoop Filter
 * Shadow RAM - RAM which content is copied from ROM residing at the same
   address for speedup purposes.
 * Shim - A small piece of code whose only purpose is to act as an
@@ -906,7 +873,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SPI - [**Serial Peripheral
   Interface**](https://en.wikipedia.org/wiki/Serial_Peripheral_Interface)
 * SPL - AMD: Security Patch Level
-* SPM - Mediatek: System Power Manager
 * SPMI - MIPI: System Power Management Interface
 * SRAM - Static Random Access Memory
 * SSD - Solid State Drive
@@ -923,9 +889,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
 * SSI-TEB - Physical board format: [**SSI Thin Electronics
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
-* SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
 * STAPM - AMD: Skin Temperature Aware Power Management
-* STB - AMD: Smart Trace Buffer
 * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
   (SIO) device provides a system with any of a number of different
   peripherals.  Most common are: A PS/2 Keyboard and mouse port, LPT
@@ -945,8 +909,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TDMA - Time-Division Multiple Access
 * TDP - [**Thermal Design
   Power**](https://en.wikipedia.org/wiki/Thermal_design_power)
-* TEE - [**Trusted Execution
-  Environment**](https://en.wikipedia.org/wiki/Trusted_execution_environment)
+* TEE - Trusted Execution Environment
 * TFTP - Network Protocol: Trivial File Transfer Protocol
 * TGL - Intel: Tigerlake
 * THC - Touch Host Controller
@@ -956,7 +919,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TLA - Three Letter Acronym
 * TLB - [**Translation Lookside
   Buffer**](https://en.wikipedia.org/wiki/Translation_lookaside_buffer)
-* TME - Intel: Total Memory Encryption
 * TOCTOU - Time-Of-Check to Time-Of-Use
 * TOLUM - Top of Low Usable Memory
 * ToM - Top of Memory
@@ -965,7 +927,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TSC - [**Time Stamp
   Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
 * TSEG - TOM (Top of Memory) Segment
-* TSR - Temperature Sensor
 * TWAIN - Technology without an interesting name.
 * TX - Transmit
 * TXE - Intel: Trusted eXecution Engine
@@ -979,7 +940,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * UDK - UEFI: UEFI Development Kit
 * UDP - User Datagram Protocol
 * UEFI - Unified Extensible Firmware Interface
-* UFP - USB: Upstream Facing Port
 * UFS - Universal Flash storage
 * UHCI - USB: [**Universal Host Controller
   Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29%23UHCI)
@@ -1029,7 +989,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   tablets, it's on the the side away from the screen.
 * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
 * WLAN - Wireless LAN (Local Area Network)
-* WWAN - Telecommunication: Wireless WAN (Wide Area Network)
 * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
 * WO - Write-only
 * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)

Documentation/community/forums.md

@@ -31,7 +31,7 @@ topics, including community and technical matters that benefit from
 an official decision.
 
 We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
+best with [Google Meet](https://meet.google.com/syn-toap-agu),
 using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
 for the agenda and meeting minutes. Neither the video conference nor
 the document require a Google account to participate, although editing

Documentation/contributing/coding_style.md

@@ -66,7 +66,7 @@ case 'm':
 case 'K':
 case 'k':
 	mem <<= 10;
-	__fallthrough;
+	/* fall through */
 default:
 	break;
 }
@@ -818,9 +818,9 @@ Function return values and names
 
 Functions can return values of many different kinds, and one of the most
 common is a value indicating whether the function succeeded or failed.
-Such a value can be represented as an error-code integer (`CB_ERR_xxx`
-(negative number) = failure, `CB_SUCCESS` (0) = success) or a "succeeded"
-boolean (0 = failure, non-zero = success).
+Such a value can be represented as an error-code integer (-Exxx =
+failure, 0 = success) or a "succeeded" boolean (0 = failure, non-zero
+= success).
 
 Mixing up these two sorts of representations is a fertile source of
 difficult-to-find bugs. If the C language included a strong distinction
@@ -832,84 +832,21 @@ If the name of a function is an action or an imperative command,
 the function should return an error-code integer.  If the name
 is a predicate, the function should return a "succeeded" boolean.
 
-For example, "add work" is a command, and the `add_work()` function
-returns 0 for success or `CB_ERR` for failure. In the same way, "PCI
-device present" is a predicate, and the `pci_dev_present()` function
+For example, "add work" is a command, and the add_work() function
+returns 0 for success or -EBUSY for failure. In the same way, "PCI
+device present" is a predicate, and the pci_dev_present() function
 returns 1 if it succeeds in finding a matching device or 0 if it
 doesn't.
 
+All EXPORTed functions must respect this convention, and so should all
+public functions. Private (static) functions need not, but it is
+recommended that they do.
+
 Functions whose return value is the actual result of a computation,
 rather than an indication of whether the computation succeeded, are not
 subject to this rule. Generally they indicate failure by returning some
 out-of-range result. Typical examples would be functions that return
-pointers; they use NULL to report failure.
-
-Error handling, assertions and die()
------------------------------
-
-As firmware, coreboot has no means to let the user interactively fix things when
-something goes wrong. We either succeed to boot or the device becomes a brick
-that must be recovered through complicated external means (e.g. a flash
-programmer). Therefore, coreboot code should strive to continue booting
-wherever possible.
-
-In most cases, errors should be handled by logging a message of at least
-`BIOS_ERR` level, returning out of the function stack for the failed feature,
-and then continuing execution. For example, if a function reading the EDID of an
-eDP display panel encounters an I2C error, it should print a "cannot read EDID"
-message and return an error code. The calling display initialization function
-knows that without the EDID there is no way to initialize the display correctly,
-so it will also immediately return with an error code without running its
-remaining code that would initialize the SoC's display controller. Exeuction
-returns further up the function stack to the mainboard initialization code
-which continues booting despite the failed display initialization, since
-display functionality is non-essential to the system. (Code is encouraged but
-not required to use `enum cb_err` error codes to return these errors.)
-
-coreboot also has the `die()` function that completely halts execution. `die()`
-should only be used as a last resort, since it results in the worst user
-experience (bricked system). It is generally preferrable to continue executing
-even after a problem was encountered that might be fatal (e.g. SPI clock
-couldn't be configured correctly), because a slight chance of successfully
-booting is still better than not booting at all. The only cases where `die()`
-should be used are:
-
-1. There is no (simple) way to continue executing. For example, when loading the
-   next stage from SPI flash fails, we don't have any more code to execute. When
-   memory initialization fails, we have no space to load the ramstage into.
-
-2. Continuing execution would pose a security risk. All security features in
-   coreboot are optional, but when they are configured in the user must be able
-   to rely on them. For example, if CBFS verification is enabled and the file
-   hash when loading the romstage doesn't match what it should be, it is better
-   to stop execution than to jump to potentially malicious code.
-
-In addition to normal error logging with `printk()`, coreboot also offers the
-`assert()` macro. `assert()` should be used judiciously to confirm that
-conditions are true which the programmer _knows_ to be true, in order to catch
-programming errors and incorrect assumptions. It is therefore different from a
-normal `if ()`-check that is used to actually test for things which may turn
-out to be true or false based on external conditions. For example, anything
-that involves communicating with hardware, such as whether an attempt to read
-from SPI flash succeeded, should _not_ use `assert()` and should instead just
-be checked with a normal `if ()` and subsequent manual error handling. Hardware
-can always fail for various reasons and the programmer can never 100% assume in
-advance that it will work as expected. On the other hand, if a function takes a
-pointer parameter `ctx` and the contract for that function (as documented in a
-comment above its declaration) specifies that this parameter should point to a
-valid context structure, then adding an `assert(ctx)` line to that function may
-be a good idea. The programmer knows that this function should never be called
-with a NULL pointer (because that's how it is specified), and if it was actually
-called with a NULL pointer that would indicate a programming error on account of
-the caller.
-
-`assert()` can be configured to either just print an error message and continue
-execution (default), or call `die()` (when `CONFIG_FATAL_ASSERTS` is set).
-Developers are encouraged to always test their code with this option enabled to
-make assertion errors (and therefore bugs) more easy to notice. Since assertions
-thus do not always stop execution, they should never be relied upon to be the
-sole guard against conditions that really _need_ to stop execution (e.g.
-security guarantees should never be enforced only by `assert()`).
+pointers; they use NULL or the ERR_PTR mechanism to report failure.
 
 Headers and includes
 ---------------
@@ -1065,7 +1002,7 @@ The C Programming Language, Second Edition by Brian W. Kernighan and
 Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
 (paperback), 0-13-110370-9 (hardback). URL:
 <https://duckduckgo.com/?q=isbn+0-13-110362-8> or
-<https://www.google.com/search?q=isbn+0-13-110362-8>
+<https://www.google.com/search?q=isbn+0-13-110362-8.
 
 
 The Practice of Programming by Brian W. Kernighan and Rob Pike.

Documentation/contributing/project_ideas.md

@@ -87,7 +87,7 @@ across architectures.
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
+to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
 yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a

Documentation/distributions.md

@@ -37,15 +37,15 @@ firmware binaries on [GitHub](https://pcengines.github.io).
 
 [Star Labs](https://starlabs.systems/) offers a range of laptops designed and
 built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
+use Tianocore as the payload and include an NVRAM option to disable the
+Intel Management Engine.
 
 ### System76
 
 [System76](https://system76.com/) manufactures Linux laptops, desktops, and
 servers. Some models are sold with [System76 Open
 Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
+distribution of coreboot, EDK2, and System76 firmware applications.
 
 ### Purism
 
@@ -76,7 +76,7 @@ trustworthiness for all.
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

Documentation/drivers/cbfs_smbios.md

@@ -1,143 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS Serial Number
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information and type 2 Baseboard Information called Serial Number. It
-is a null-terminated string field assumed to be unique per platform. Certain
-mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
-data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
-provide an option to populate the Serial Numbers from CBFS for boards that
-can't generate the it from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `Serial number in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the serial number:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
-```
-
-Where `serial_file.txt` is the unterminated string representation of the SMBIOS
-type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
-partitions you will have to specify the RW regions where the file is going to
-be added too. By default the RW CBFS partitions are truncated, so the files
-would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the Serial Number from running system (if it exists) using one
-of the following commands:
-
-```shell
-# Type 1
-echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
-# OR Type 2
-echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
-```
-
-Ensure the file does not end with whitespaces like LF and/or CR. The above
-commands will not add any whitespaces. The driver automatically terminates the
-Serial Number with the NULL character. If the CBFS file is not present, the
-driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
-option.
-
-Please note that this driver provides `smbios_mainboard_serial_number` hook
-overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
-build option. If you wish to populate only type 2 Serial Number field your
-board code needs to implement `smbios_system_serial_number`, otherwise the weak
-implementation of `smbios_system_serial_number` will call
-`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
-implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
-has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
-if the board does not implement its own `smbios_system_serial_number`.
-
-There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
-populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
-implementation (returns empty string). If you wish to populate type 3 Serial
-Number, your board code should override the default
-`smbios_chassis_serial_number` weak implementation.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt

Documentation/drivers/dptf.md

@@ -43,7 +43,7 @@ This policy monitors the temperature of participants and controls fans to spin
 at varying speeds. These speeds are defined by the platform, and will be enabled
 depending on the various temperatures reported by participants.
 
-## Note about units
+# Note about units
 
 ACPI uses unusual units for specifying various physical measurements. For
 example, temperatures are specified in 10ths of a degree K, and time is measured
@@ -69,7 +69,7 @@ data was a 0). The following Methods were removed:
 2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
    specified in the devicetree entries or by calling the DPTF acpigen API).
 
-## ACPI Tables
+# ACPI Tables
 
 DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
 application. We will discuss the more important ones here.
@@ -108,7 +108,7 @@ various informational properties.
 This table describes performance states supported by a participant (typically
 the battery charger).
 
-## ACPI Methods
+# ACPI Methods
 
 The Active and Passive policies also provide for short Methods to define
 different kinds of temperature thresholds.
@@ -141,7 +141,7 @@ a "graceful shutdown".
 
 These are optional, and are enabled by selecting the Critical Policy.
 
-## How to use the devicetree entries
+# How to use the devicetree entries
 
 The `drivers/intel/dptf` chip driver is organized into several sections:
 - Policies
@@ -151,7 +151,7 @@ The `drivers/intel/dptf` chip driver is organized into several sections:
 The Policies section (`policies.active`, `policies.passive`, and
 `policies.critical`) is where the components of each policy are defined.
 
-### Active Policy
+## Active Policy
 
 Each Active Policy is defined in terms of 4 parts:
 1) A Source (this is implicitly defined as TFN1, the system fan)
@@ -182,7 +182,7 @@ the CPU's active cooling capability). When the CPU temperature first crosses
 rest of the table (note that it *must* be defined from highest temperature/
 percentage on down to the lowest).
 
-### Passive Policy
+## Passive Policy
 
 Each Passive Policy is defined in terms of 5 parts:
 1) Source - The device that can be throttled
@@ -201,7 +201,7 @@ This example sets up a policy to begin throttling the charger performance when
 temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
 The Priority is defaulted to 100 in this case.
 
-### Critical Policy
+## Critical Policy
 
 Each Critical Policy is defined in terms of 3 parts:
 1) Source - A device that can trigger a critical event
@@ -218,7 +218,7 @@ register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
 This example sets up a policy wherein ACPI will cause the system to shutdown
 (in a "graceful" manner) when the CPU temperature reaches 75C.
 
-### Power Limits
+## Power Limits
 
 Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
 that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
@@ -244,7 +244,7 @@ This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
 over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
 increments of 200 mW.
 
-### Charger Performance
+## Charger Performance
 
 The battery charger can be a large contributor of unwanted heat in a system that
 has one. Controlling the rate of charging is another tool that DPTF uses to enact
@@ -266,7 +266,7 @@ register "controls.charger_perf[3]" = "{   8,  500 }"
 In this example, when DPTF decides to throttle the charger, it has four different
 performance states to choose from.
 
-### Fan Performance
+## Fan Performance
 
 When using DPTF, the system fan (`TFN1`) is the device responsible for actively
 cooling the other temperature sensors on the mainboard. A fan speed table can be
@@ -298,21 +298,21 @@ increment of 10 percentage points. This is common when specifying fine-grained
 control of the fan, wherein DPTF will interpolate between the percentages in the
 table for a given temperature threshold.
 
-### Options
+## Options
 
-#### Fan
+### Fan
 1) Fine-grained control - a boolean (see Fan Performance section above)
 2) Step-size - Recommended minimum step size (in percentage points) to adjust
    the fan speed when using fine-grained control (ranges from 1 - 9).
 3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
    fan device if a low fan speed is detected.
 
-#### Temperature sensors
+### Temperature sensors
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
 
-### OEM Variables
+## OEM Variables
 Platform vendors can define an array of OEM-specific values as OEM variables
 to be used under DPTF policy. There are total six OEM variables available.
 These can be used in AP policy for more specific actions. These OEM variables

Documentation/drivers/dt_entries.md

@@ -1,309 +0,0 @@
-# Driver Devicetree Entries
-
-Let's take a look at an example entry from
-``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
-
-```
-device pci 15.0 on
-	chip drivers/i2c/generic
-		register "hid" = ""ELAN0000""
-		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
-		register "wake" = "GPE0_DW0_21"
-		device i2c 15 on end
-	end
-end # I2C #0
-```
-
-When this entry is processed during ramstage, it will create a device in the
-ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
-generation routines in coreboot actually generate the raw bytecode that
-represents the device's structure, but looking at ASL code is easier to
-understand; see below for what the disassembled bytecode looks like:
-
-```
-Scope (\_SB.PCI0.I2C0)
-{
-    Device (D015)
-    {
-        Name (_HID, "ELAN0000")  // _HID: Hardware ID
-        Name (_UID, Zero)  // _UID: Unique ID
-        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
-        Method (_STA, 0, NotSerialized)  // _STA: Status
-        {
-            Return (0x0F)
-        }
-        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-        {
-            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-            {
-                0x0000002D,
-            }
-        })
-        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
-        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
-        {
-            0x15, // GPE #21
-            0x03  // Sleep state S3
-        })
-    }
-}
-```
-
-You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
-names/methods in the Device's scope.
-
-## Utilizing a device driver
-
-The device driver must be enabled for your build.  There will be a CONFIG option
-in the Kconfig file in the directory that the driver is in (e.g.,
-``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
-CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
-mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
-to be compiled into your build.
-
-## Diving into the above example:
-
-Let's take a look at how the devicetree language corresponds to the generated
-ASL.
-
-First, note this:
-
-```
-    chip drivers/i2c/generic
-```
-
-This means that the device driver we're using has a corresponding structure,
-located at ``src/drivers/i2c/generic/chip.h``, named **struct
-drivers_i2c_generic_config** and it contains many properties you can specify to
-be included in the ACPI table.
-
-### hid
-
-```
-    register "hid" = ""ELAN0000""
-```
-
-This corresponds to **const char \*hid** in the struct.  In the ACPI ASL, it
-translates to:
-
-```
-    Name (_HID, "ELAN0000") // _HID: Hardware ID
-```
-
-under the device.  **This property is used to match the device to its driver
-during enumeration in the OS.**
-
-### desc
-
-```
-    register "desc" = ""ELAN Touchpad""
-```
-
-corresponds to **const char \*desc** and in ASL:
-
-```
-    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
-```
-
-### irq
-
-It also adds the interrupt,
-
-```
-    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-    {
-        0x0000002D,
-    }
-```
-
-which comes from:
-
-```
-    register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-```
-
-The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
-means it is a level-triggered interrupt as opposed to
-edge-triggered; active low means the interrupt is triggered when the signal is
-low).
-
-Also note that the IRQ names are SoC-specific, and you will need to
-find the names in your SoC's header file.  The ACPI_* macros are defined in
-``src/arch/x86/include/acpi/acpi_device.h``.
-
-Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
-This is often done in a mainboard-specific file named ``gpio.c``.
-
-AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
-GPIO controller needs to be used directly. You can do this by setting the
-`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
-
-i.e.,
-```
-register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
-```
-
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
-mainboards in the tree to implement this are google/skyrim and google/guybrush.
-This feature has also been used in downstream forks without issue for some time
-now on several other boards.
-
-### wake
-
-The last register is:
-
-```
-    register "wake" = "GPE0_DW0_21"
-```
-
-which indicates that the method of waking the system using the touchpad will be
-through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
-this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
-elsewhere in the devicetree.
-
-### device
-
-The last bit of the definition of that device includes:
-
-```
-    device i2c 15 on end
-```
-
-which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
-meaning it will be exposed in the ACPI table.  The PCI device that the
-controller is located in determines which I2C bus the device is expected to be
-found on.  In this example, this is I2C bus 0.  This also determines the ACPI
-"Scope" that the device names and methods will live under, in this case
-"\_SB.PCI0.I2C0".
-
-## Wake sources
-
-The ACPI spec defines two methods to describe how a device can wake the system.
-Only one of these methods should be used, otherwise duplicate wake events will
-be generated.
-
-### Using GPEs as a wake source
-
-The `wake` property specified above is used to tell the ACPI subsystem that the
-device can use a GPE to wake the system. The OS can control whether to enable
-or disable the wake source by unmasking/masking off the GPE.
-
-The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
-generally done by a mainboard specific `gpio.c` file that defines the GPIO
-using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
-`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
-file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
-`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
-GPEs (the rest are available as `tier-2` GPEs).
-
-Windows has a large caveat when using this method. If you use the `gpio_irq`
-property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
-to define a `GPE`, Windows will
-[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
-complaining about an invalid ACPI configuration.
-> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
-
-In order to avoid this error, you should use the `irq` property instead. AMD
-platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
-feasible. The other option is to use a wake capable GPIO as described below.
-
-### Using GPIO interrupts as a wake source
-
-The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
-`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
-`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
-
-This method has a few caveats:
-* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
-  the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
-  system. Instead you need to use the `gpio_irq` property, or a `GPE` as
-  described above.
-* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
-  means the platform specific GPIO controller driver must implement the
-  `irq_set_wake` callback. For AMD systems this wasn't
-  [implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
-  until linux v5.15. If the controller doesn't define this callback, it's
-  possible for the firmware to manually set the `wake` bit on the GPIO. This is
-  often done in a mainboard-specific file named `gpio.c`. This is not
-  recommended because then it's not possible for the OS to disable the wake
-  source.
-* As of
-  [linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
-  the ACPI subsystem doesn't take the interrupt `wake` bit into account when
-  deciding on which power state to put the device in before suspending the
-  system. This means that if you define a power resource for a device via
-  `has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
-  device into D3Cold. i.e., power off the device.
-
-## Other auto-generated names
-
-(see [ACPI specification
-6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
-for more details on ACPI methods)
-
-### _S0W (S0 Device Wake State)
-\_S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
-D3Hot means the `PR3` power resources are still on and the device is still
-responsive on the bus. For i2c devices this is generally the same state as `D0`.
-
-### \_PRW (Power Resources for Wake)
-\_PRW indicates the power resources and events required for wake.  There are no
-dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
-as well as the deepest sleep state supporting waking the system (3), which is
-S3.
-
-### \_STA (Status)
-The \_STA method is generated automatically, and its values, 0xF, indicates the
-following:
-
-    Bit [0] – Set if the device is present.
-    Bit [1] – Set if the device is enabled and decoding its resources.
-    Bit [2] – Set if the device should be shown in the UI.
-    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
-
-### \_CRS (Current resource settings)
-The \_CRS method is generated automatically, as the driver knows it is an I2C
-controller, and so specifies how to configure the controller for proper
-operation with the touchpad.
-
-```
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                    0x00, ResourceConsumer, , Exclusive, )
-```
-
-## Notes
-
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)

Documentation/drivers/index.md

@@ -4,14 +4,9 @@ The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
 they allow to easily reuse existing code across platforms.
 
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
-
 * [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
 * [SoundWire](soundwire.md)
+* [SMMSTOREv2](smmstorev2.md)
 * [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)

Documentation/drivers/ipmi_kcs.md

@@ -42,15 +42,6 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/retimer.md

@@ -1,6 +1,6 @@
 # USB4 Retimers
 
-## Introduction
+# Introduction
 As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
 newer revisions of the spec), it becomes more difficult to maintain signal
 integrity for longer traces. Devices such as retimers and redrivers can be used
@@ -17,7 +17,7 @@ by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
 this is a digital component, it may have firmware.
 
 
-## Driver Usage
+# Driver Usage
 
 Some operating systems may have the ability to update firmware on USB4 retimers,
 and ultimately will need some way to power the device on and off so that its new

Documentation/drivers/smmstorev2.md

@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
+EDK2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

Documentation/external_docs.md

@@ -1,114 +0,0 @@
-# External Resources
-
-This is a list of resources that could be useful to coreboot developers.
-These are not endorsed or officially recommended by the coreboot project,
-but simply listed here in the hopes that someone will find something
-useful.
-
-Please add any helpful or informational links and sections as you see fit.
-
-## Articles
-
-* External Interrupts in the x86 system.
-  * [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
-  * [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
-  * [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
-* System address map initialization in x86/x64 architecture.
-  * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
-  * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
-  * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
-* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
-
-
-## General Information
-
-* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
-* [Interface BUS](http://www.interfacebus.com/)
-* Open course material for a variety of topics such as assembly, firmware,
-  security, debugging, and more.
-  * [Open Security Training](https://opensecuritytraining.info/Training.html),
-  * [Open Security Training 2](https://p.ost2.fyi/)
-
-
-## Firmware Specifications & Information
-
-* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
-* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
-* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
-
-
-### ACPI
-
-* [ACPI Specs](https://uefi.org/acpi/specs)
-* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
-* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
-* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
-
-
-### Security
-
-* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
-
-
-## Hardware information
-
-* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
-* [Sandpile](https://www.sandpile.org/)
-* [CPU-World](https://www.cpu-world.com/index.html)
-* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
-
-
-### Hardware Specifications & Standards
-
-* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
-* [eMMC](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
-* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
-  [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
-* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
-* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
-* [Memory](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
-* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
-* [PCI / PCIe / M.2](https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED)
-* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
-* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
-* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
-* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
-* [USB](https://www.usb.org/documents) - USB Implementers Forum
-* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
-
-
-### Chip Vendor Documentation
-
-* AMD
-  * [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
-  * [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
-* ARM
-  * [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
-* Intel
-  * [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
-  * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
-  * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
-  * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
-
-* Rockchip
-  * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
-
-
-## Software
-
- * [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
- * [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
- * [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
- * [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
- * [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
- * [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
-* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
-* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
-
-
-## Infrastructure software
-
-* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
-* [GNU Make](https://www.gnu.org/software/make/manual/)

Documentation/getting_started/devicetree.md

@@ -1,87 +0,0 @@
-# Adding new devices to a device tree
-
-## Introduction
-
-ACPI exposes a platform-independent interface for operating systems to perform
-power management and other platform-level functions.  Some operating systems
-also use ACPI to enumerate devices that are not immediately discoverable, such
-as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
-the way that coreboot uses the concept of a "device tree" to generate ACPI
-tables for usage by the operating system.
-
-## Devicetree and overridetree (if applicable)
-
-For mainboards that are organized around a "reference board" or "baseboard"
-model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
-typically a devicetree.cb file that all boards share, and any differences for a
-specific board ("variant") are captured in the overridetree.cb file.  Any
-settings changed in the overridetree take precedence over those in the main
-devicetree.  Note, not all mainboards will have the devicetree/overridetree
-distinction, and may only have a devicetree.cb file.  Or you can always just
-write the ASL (ACPI Source Language) code yourself.
-
-### Naming and referencing devices
-
-When declaring a device, it can optionally be given an alias that can be
-referred to elsewhere. This is particularly useful to declare a device in one
-device tree while allowing its configuration to be more easily changed in an
-overlay. For instance, the AMD Picasso SoC definition
-(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
-by default:
-
-```
-chip soc/amd/picasso
-	device domain 0 on
-		...
-		device pci 00.2 alias iommu off end
-		...
-	end
-end
-```
-
-A device based on this SoC can override the configuration for the IOMMU without
-duplicating addresses, as in
-`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
-
-```
-chip soc/amd/picasso
-	device domain 0
-		...
-		device ref iommu on end
-		...
-	end
-end
-```
-
-In this example the override simply enables the IOMMU, but it could also
-set additional properties (or even add child devices) inside the IOMMU `device`
-block.
-
----
-
-It is important to note that devices that use `device ref` syntax to override
-previous definitions of a device by alias must be placed at **exactly the same
-location in the device tree** as the original declaration. If not, this will
-actually create another device rather than overriding the properties of the
-existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
-were written as follows:
-
-```
-chip soc/amd/picasso
-	# NOTE: not inside domain 0!
-	device ref iommu on end
-end
-```
-
-Then this would leave the SoC's IOMMU disabled, and instead create a new device
-with no properties as a direct child of the SoC.
-
-## Device drivers
-
-Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
-
-## Notes
-
- - **All fields that are left unspecified in the devicetree are initialized to
-   zero.**

Documentation/getting_started/index.md

@@ -6,4 +6,3 @@
 * [Kconfig](kconfig.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
-* [Adding devices to a device tree](devicetree.md)

Documentation/index.md

@@ -26,7 +26,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, edk2, which provides UEFI services,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 
@@ -197,5 +197,4 @@ Contents:
 * [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
 * [Acronyms & Definitions](acronyms.md)
-* [External Resources](external_docs.md)
 * [Documentation License](documentation_license.md)

Documentation/lib/fw_config.md

@@ -383,7 +383,7 @@ training.  This example expects that the default value of this `register` is set
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
+	if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED))
 		mupd->ExampleFeature = false;
 }
 ```

Documentation/mainboard/amd/pademelon/pademelon.md

@@ -1,80 +0,0 @@
-# Pademelon board
-
-## Specs (with Merlin Falcon SOC)
-
-* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
-  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
-* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
-  code is specific for Merlin Falcon SOC. Some specs will change if not
-  using Merlin Falcon.
-* One half mini PCI-Express slot on back side of mainboard
-* One PCI Express® 3.0 x8 slot
-* Two SATA3 ports with 6Gb/s data transfer rate
-* Two USB 2.0 ports at rear panel
-* Two USB 3.0 ports at rear panel
-* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
-* 6-channel High-Definition audio from Realtek ALC662 codec
-* One soldered down SPI flash with dediprog header
-
-## Mainboard
-
-![mainboard][pademelon]
-
-Three items are marked in this picture
-1. dediprog header
-2. memory dimms, address 0xA0 and 0xA4
-3. SATA cables connected to motherboard
-
-## Back panel
-
-![back panel][pademelon_io]
-
-* The lower serial port is UART A (debug serial)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+--------------------+
-| Type                | Value              |
-+=====================+====================+
-| Socketed flash      | no                 |
-+---------------------+--------------------+
-| Model               | Macronix MX256435E |
-+---------------------+--------------------+
-| Size                | 8 MiB              |
-+---------------------+--------------------+
-| Flash programming   | dediprog header    |
-+---------------------+--------------------+
-| Package             | SOIC-8             |
-+---------------------+--------------------+
-| Write protection    | No                 |
-+---------------------+--------------------+
-```
-
-## Technology
-
-```eval_rst
-+---------------+------------------------------+
-| Fan control   | Using fintek F81803A         |
-+---------------+------------------------------+
-| CPU           | Merlin Falcon (see reference)|
-+---------------+------------------------------+
-```
-
-## Description of pictures within this document
-
-```eval_rst
-+----------------------------+----------------------------------------+
-|pademelon.jpg               | Motherboard with components identified |
-+----------------------------+----------------------------------------+
-|pademelon_io.jpg            | Back panel picture                     |
-+----------------------------+----------------------------------------+
-```
-
-## Reference
-
-[Merlin Falcon BKDG][merlinfalcon]
-
-[merlinfalcon]: ../../../soc/amd/family15h.md
-[pademelon]: pademelon.jpg
-[pademelon_io]: pademelon_io.jpg

Documentation/mainboard/amd/padmelon/padmelon.md

@@ -0,0 +1,80 @@
+# Padmelon board
+
+## Specs (with Merlin Falcon SOC)
+
+* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
+  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
+* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
+  code is specific for Merlin Falcon SOC. Some specs will change if not
+  using Merlin Falcon.
+* One half mini PCI-Express slot on back side of mainboard
+* One PCI Express® 3.0 x8 slot
+* Two SATA3 ports with 6Gb/s data transfer rate
+* Two USB 2.0 ports at rear panel
+* Two USB 3.0 ports at rear panel
+* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
+* 6-channel High-Definition audio from Realtek ALC662 codec
+* One soldered down SPI flash with dediprog header
+
+## Mainboard
+
+![mainboard][padmelon]
+
+Three items are marked in this picture
+1. dediprog header
+2. memory dimms, address 0xA0 and 0xA4
+3. SATA cables connected to motherboard
+
+## Back panel
+
+![back panel][padmelon_io]
+
+* The lower serial port is UART A (debug serial)
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------------------+
+| Type                | Value              |
++=====================+====================+
+| Socketed flash      | no                 |
++---------------------+--------------------+
+| Model               | Macronix MX256435E |
++---------------------+--------------------+
+| Size                | 8 MiB              |
++---------------------+--------------------+
+| Flash programming   | dediprog header    |
++---------------------+--------------------+
+| Package             | SOIC-8             |
++---------------------+--------------------+
+| Write protection    | No                 |
++---------------------+--------------------+
+```
+
+## Technology
+
+```eval_rst
++---------------+------------------------------+
+| Fan control   | Using fintek F81803A         |
++---------------+------------------------------+
+| CPU           | Merlin Falcon (see reference)|
++---------------+------------------------------+
+```
+
+## Description of pictures within this document
+
+```eval_rst
++----------------------------+----------------------------------------+
+|padmelon.jpg                | Motherboard with components identified |
++----------------------------+----------------------------------------+
+|padmelon_io.jpg             | Back panel picture                     |
++----------------------------+----------------------------------------+
+```
+
+## Reference
+
+[Merlin Falcon BKDG][merlinfalcon]
+
+[merlinfalcon]: ../../../soc/amd/family15h.md
+[padmelon]: padmelon.jpg
+[padmelon_io]: padmelon_io.jpg

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -37,7 +37,7 @@ easy to remove and reflash.
 
 ## Working
 
-- PS/2 keyboard with SeaBIOS & edk2 (in Mint 18.3/19.1)
+- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
 
 - Rear/front headphones connector audio & mic
 
@@ -57,7 +57,7 @@ easy to remove and reflash.
        port 3        port 5         port 1             port 8
        port 4        port 6         port 2             port 7
 
-- NVME SSD boot on PCIe-x16/x8/4x slot using edk2
+- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
   (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
 
 - CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
@@ -89,7 +89,7 @@ easy to remove and reflash.
 - If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
   as IGP's UMA could be reconfigured by the blob
 
-- Using edk2 + a PCIe GPU under Windows crashes with an
+- Using TianoCore + a PCIe GPU under Windows crashes with an
   ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
   works perfectly
 
@@ -105,9 +105,9 @@ easy to remove and reflash.
 
 ## Not working
 
-- PS/2 keyboard in Win10 using edk2 (please see [Known issues])
-- PS/2 mouse using edk2
-- PCIe graphics card on Windows and edk2 (throws critical ACPI_BIOS_ERROR)
+- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
+- PS/2 mouse using Tianocore
+- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
 
 ## Native raminit compatibility
 

Documentation/mainboard/facebook/monolith.md

@@ -104,11 +104,11 @@ solution. Wires need to be connected to be able to flash using an external progr
 - SMBus
 - Initialization with FSP
 - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4)
-- edk2 payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
+- TianoCore payload (commit 860a8d95c2ee89c9916d6e11230f246afa1cd629)
 - LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7)
 - eMMC
 
-All of the above has been briefly tested by booting Linux from eMMC using the edk2 payload
+All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload
 and LinuxBoot.
 
 SeaBios has been checked to the extend that it runs to the boot selection and provides display

Documentation/mainboard/hp/folio_9480m.md

@@ -130,7 +130,7 @@ The board can be debugged with EHCI debug. The EHCI debug port is the USB port o
 - Arch Linux with Linux 5.8.9
 - Memory initialization with mrc.bin version 1.6.1 Build 2
 - Graphics initialization with libgfxinit
-- Payload: SeaBIOS, edk2
+- Payload: SeaBIOS, Tianocore
 - EC firmware
   - KBC Revision 92.15 from OEM firmware version 01.33
   - KBC Revision 92.17 from OEM firmware version 01.50

Documentation/mainboard/hp/z220_sff.md

@@ -44,17 +44,8 @@ The SPI flash can be accessed using [flashrom].
 External programming with an SPI adapter and [flashrom] does work, but it powers the
 whole southbridge complex. You need to supply enough current through the programming adapter.
 
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder, as
-otherwise there's not enough space near the flash.
-
-In both case, if ME has not been completely disabled, ME/AMT Flash Override jumper had better
-be temporary closed for flashing to disable the locking of regions, and prevent ME to run and
-interfere.
-
-## Side note
-The mainboard of [HP Compaq Elite 8300 SFF] is very similar to the one of Z220 SFF, except
-that Compaq Elite 8300 uses Q77 instead of C216 for its PCH, and their boot firmwares are
-even interchangeable, so should do coreboot images built for them.
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
 
 ## Technology
 
@@ -75,6 +66,5 @@ even interchangeable, so should do coreboot images built for them.
 ```
 
 [HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
-[HP Compaq Elite 8300 SFF]: https://support.hp.com/us-en/document/c03345460
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -11,7 +11,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [G43T-AM3](acer/g43t-am3.md)
 
 ## AMD
-- [pademelon](amd/pademelon/pademelon.md)
+- [padmelon](amd/padmelon/padmelon.md)
 
 ## ASRock
 
@@ -146,6 +146,7 @@ The boards in this section are not real mainboards, but emulators.
 ## Open Cellular
 
 - [Elgon](opencellular/elgon.md)
+- [Rotundu](opencellular/rotundu.md)
 
 ## PC Engines
 
@@ -185,7 +186,6 @@ The boards in this section are not real mainboards, but emulators.
 - [StarLite Mk III](starlabs/lite_glk.md)
 - [StarLite Mk IV](starlabs/lite_glkr.md)
 - [StarBook Mk V](starlabs/starbook_tgl.md)
-- [StarBook Mk VI](starlabs/starbook_adl.md)
 - [Flashing devices](starlabs/common/flashing.md)
 
 ## Supermicro
@@ -202,10 +202,8 @@ The boards in this section are not real mainboards, but emulators.
 - [Bonobo Workstation 14](system76/bonw14.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
-- [Darter Pro 8](system76/darp8.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
-- [Galago Pro 6](system76/galp6.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
 - [Lemur Pro 9](system76/lemp9.md)

Documentation/mainboard/kontron/mal10.md

@@ -45,7 +45,7 @@ make
 ```
 ## Payloads
 - SeaBIOS
-- edk2
+- Tianocore
 - Linux as payload
 
 ## Flashing coreboot

Documentation/mainboard/ocp/deltalake.md

@@ -26,12 +26,12 @@ host up to 4 Delta Lake servers (blades) in one sled.
 
 The Yosemite-V3 system is in mass production. Meta, Intel and partners
 jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
-solution. The OSF solution reached production quality for some use cases
-in July, 2021.
+solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
+OSF solution reached production quality for some use cases in July, 2021.
 
 ## How to build
 
-OSF code base is publicly available at
+OSF code base is public at
 https://github.com/opencomputeproject/OpenSystemFirmware
 
 Run following commands to build Delta Lake OSF image from scratch:
@@ -42,21 +42,19 @@ The Delta Lake OSF code base leverages [osf-builder] to sync down coreboot,
 Linux kernel and u-root code from their upstream repo, and sync down needed
 binary blobs. [osf-builder] also provides the top level build system.
 
-Besides coreboot, the Delta Lake OSF solution includes following components:
-- FSP blob: The blobs (Intel Cooper Lake Scalable Processor Firmware Support Package)
-  is downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
-- Microcode: downloaded from github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
-- ME ignition binary: downloaded from
+Delta Lake server OSF solution requires following binary blobs:
+- FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
+  can be downloaded from https://github.com/intel/FSP/tree/master/CedarIslandFspBinPkg.
+- Microcode: Available through github.com/intel/Intel-Linux-Processor-Microcode-Data-Files.
+  coreboot.org mirrors this repo and by default the correct binary is included.
+- ME binary: Ignition binary can be downloaded from
 	https://github.com/tianocore/edk2-non-osi/tree/master/Silicon/Intel/PurleySiliconBinPkg/MeFirmware
 - ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
 - Payload: LinuxBoot is necessary when LinuxBoot is used as the coreboot payload.
-  U-root as initramfs, is used in the joint development. It is built
+  U-root as initramfs, is used in the joint development. It can be built
   following [All about u-root].
 
-The Delta Lake OSF solution is updated periodically to newer versions of
-upstream coreboot code base and other components.
-
-## How to verify Delta Lake OSF image
+## Flashing coreboot
 
 To do in-band FW image update, use [flashrom]:
     flashrom -p internal:ich_spi_mode=hwseq -c "Opaque flash chip" --ifd \
@@ -72,21 +70,6 @@ To power off/on the host:
 To connect to console through SOL (Serial Over Lan):
     sol-util slotx
 
-## How to work on coreboot for Delta Lake
-After the OSF image for Delta Lake is built and verified, under
-OpenSystemFirmware/Wiwynn/deltalake directory:
-    cd src/osf-builder/projects/craterlake/coreboot
-
-Run "git remote -v" to confirm the origin is from coreboot upstream repo.
-
-Run "git branch -v" to know the confirmed working coreboot commit ID for the
-Delta Lake OSF solution.
-
-Fetch down the tip of coreboot upstream repo, run "make" to build a new OSF
-image for Delta Lake, verify that it works.
-
-Now you are in a familiar coreboot environment, happy coding!
-
 ## Firmware configurations
 [ChromeOS VPD] is used to store most of the firmware configurations.
 RO_VPD region holds default values, while RW_VPD region holds customized

Documentation/mainboard/opencellular/rotundu.md

@@ -0,0 +1,76 @@
+# Rutundu
+
+This page describes how to run coreboot on the [Rotundu] compute board
+from [OpenCellular].
+
+## TODO
+
+* Configure UART
+* EC interface
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | W25Q128    |
++---------------------+------------+
+| Size                | 16 MiB     |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+The GBCv1 board does have a pinheader to flash the SOIC-8 in circuit.
+Directly connecting a Pomona test-clip on the flash is also possible.
+
+**Closeup view of SOIC-8 flash IC**
+
+![][rotundu_flash]
+
+[rotundu_flash]: rotundu_flash.jpg
+
+**SPI header**
+
+![][rotundu_header2]
+
+[rotundu_header2]: rotundu_header2.jpg
+
+**SPI header pinout**
+
+Dediprog compatible pinout.
+
+![][rotundu_j16]
+
+[rotundu_j16]: rotundu_j16.png
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| SoC              | Intel Baytrail                                   |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
++------------------+--------------------------------------------------+
+```
+
+[Rotundu]: https://github.com/Telecominfraproject/OpenCellular
+[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/purism/librem_14.md

@@ -92,7 +92,7 @@ located underneath the Wi-Fi module, below the left cooling fan.
 
  * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
  * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), and Heads payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * M.2 storage (NVMe, SATA III)

Documentation/mainboard/purism/librem_mini.md

@@ -107,7 +107,7 @@ desoldering it from the mainboard.
 
  * External displays via HDMI/DisplayPort with VGA option ROM or FSP/GOP init
    (no libgfxinit support yet)
- * SeaBIOS (1.14), edk2 (CorebootPayloadPkg), Heads (Purism downstream) payloads
+ * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), Heads (Purism downstream) payloads
  * Ethernet, m.2 2230 Wi-Fi
  * System firmware updates via flashrom
  * PCIe NVMe

Documentation/mainboard/starlabs/common/building.md

@@ -1,30 +0,0 @@
-## Building coreboot
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-
-#### StarBook series:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-#### StarLite series:
-* Intel Flash Descriptor file (descriptor.bin)
-* IFWI Image (ifwi.rom)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the [StarLabsLtd/blobs](https://github.com/StarLabsLtd/blobs) repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image, where the last two words represent the
-series and processor i.e. `lite_glkr`:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
-make
-```

Documentation/mainboard/starlabs/labtop_cml.md

@@ -41,7 +41,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_cml
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -38,7 +38,26 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+
+The below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_labtop_kbl
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/lite_glk.md

@@ -37,7 +37,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glk
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/lite_glkr.md

@@ -37,7 +37,26 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* IFWI Image (ifwi.rom)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_lite_glkr
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/starlabs/starbook_adl.md

@@ -1,88 +0,0 @@
-# StarBook Mk V
-
-## Specs
-
-- CPU (full processor specs available at https://ark.intel.com)
-    - Intel i7-1260P (Alder Lake)
-    - Intel i3-1220P (Alder Lake)
-- EC
-    - ITE IT5570E
-    - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
-    - Battery
-    - Charger, using AC adapter or USB-C PD
-    - Suspend / resume
-- GPU
-    - Intel® Iris® Xe Graphics
-    - GOP driver is recommended, VBT is provided
-    - eDP 14-inch 1920x1080 LCD
-    - HDMI video
-    - USB-C DisplayPort video
-- Memory
-    - 2 x DDR4 SODIMM
-- Networking
-    - AX210 2230 WiFi / Bluetooth
-- Sound
-    - Realtek ALC269-VB6
-    - Internal speakers
-    - Internal microphone
-    - Combined headphone / microphone 3.5-mm jack
-    - HDMI audio
-    - USB-C DisplayPort audio
-- Storage
-    - M.2 PCIe SSD
-    - RTS5129 MicroSD card reader
-- USB
-    - 1920x1080 CCD camera
-    - USB 3.1 Gen 2 (left)
-    - USB 3.1 Gen 2 Type-A (left)
-    - USB 3.1 Gen 1 Type-A (right)
-    - USB 2.0 Type-A (right)
-
-## Building coreboot
-
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
-
-### Preliminaries
-
-Prior to building coreboot the following files are required:
-* Intel Flash Descriptor file (descriptor.bin)
-* Intel Management Engine firmware (me.bin)
-* ITE Embedded Controller firmware (ec.bin)
-
-The files listed below are optional:
-- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
-
-These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
-
-### Build
-
-The following commands will build a working image:
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | W25Q256.V  |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-
-Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -40,7 +40,27 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
+### Preliminaries
+
+Prior to building coreboot the following files are required:
+* Intel Flash Descriptor file (descriptor.bin)
+* Intel Management Engine firmware (me.bin)
+* ITE Embedded Controller firmware (ec.bin)
+
+The files listed below are optional:
+- Splash screen image in Windows 3.1 BMP format (Logo.bmp)
+
+These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo.
+
+### Build
+
+The following commands will build a working image:
+
+```bash
+make distclean
+make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_tgl
+make
+```
 
 ## Flashing coreboot
 

Documentation/mainboard/system76/darp8.md

@@ -1,82 +0,0 @@
-# Syste76 Darter Pro 8 (darp8)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1240P
-  - Intel Core i7-1260P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 15.6" 1920x1080@60Hz LCD
-  - 1x HDMI
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 65W+ chargers
-  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - M.2 PCIe NVMe Gen 4 SSD
-  - M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 1x USB 3.2 (Gen 2) Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Winbond             |
-+---------------------+---------------------+
-| Model               | W25Q256.V           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U19) is above the left DIMM slot.

Documentation/mainboard/system76/galp6.md

@@ -1,61 +0,0 @@
-# System76 Galago Pro 6 (galp6)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1240P
-  - Intel Core i7-1260P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 90W+ chargers
-  - 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 32.49cm x 22.5cm x 1.82cm, 1.45kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U43) is left of the wireless card.

Documentation/payloads.md

@@ -23,11 +23,13 @@ When chainloaded from GRUB2, the following menuentry could be used:
         module /vgaroms/seavgabios.bin
     }
 
-## edk2
+## Tianocore
 
-[edk2](https://github.com/tianocore/tianocore.github.io/wiki/Getting-Started-with-EDK-II) is an open-source modern, feature-rich,
-cross-platform firmware development environment for the UEFI and UEFI
-Platform Initialization (PI) specifications.
+[Tianocore](https://www.tianocore.org) is the open source reference
+implementation of the UEFI Specifications that modern firmware for PCs is
+based on. There were various projects in the past to make it suitable as a
+coreboot payload, but these days this function is available directly in the
+UefiPayloadPkg part of its source tree.
 
 ## GRUB2
 

Documentation/releases/boards_supported_on_branches.md

@@ -12,59 +12,16 @@ desired.
 
 Currently, [jenkins](https://qa.coreboot.org), our continuous
 integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-4.16, and 4.18 branches.  Builders for other branches can be created on
+and 4.16 branches.  Builders for other branches can be created on
 request.  Likewise, some releases are only marked with tags, and
 branches would need to be created to push new code to.  These branches
 can also be created on request.
 
 Patches can be backported from the master branch to any of these other
-branches as needed. The coreboot project may take care of backporting
+branches as needed. The coreboot project will take care of backporting
 critical security fixes, but other patches will need to handled by
 anyone using that release.
 
-
-## [4.18 Release](coreboot-4.18-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| amd/inagua                    | AMD_FAMILY14           | 2011-02-14 | eval      |
-| amd/olivehill                 | AMD_FAMILY16_KB        | 2013-08-05 | eval      |
-| amd/parmer                    | AMD_FAMILY15_TN        | 2012-07-22 | eval      |
-| amd/persimmon                 | AMD_FAMILY14           | 2011-02-14 | eval      |
-| amd/south_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-| amd/thatcher                  | AMD_FAMILY15_TN        | 2012-08-02 | eval      |
-| amd/union_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-| asrock/e350m1                 | AMD_FAMILY14           | 2011-02-24 | mini      |
-| asrock/imb-a180               | AMD_FAMILY16_KB        | 2013-08-27 | mini      |
-| asus/a88xm-e                  | AMD_FAMILY15_TN        | 2020-08-13 | desktop   |
-| asus/am1i-a                   | AMD_FAMILY16_KB        | 2018-01-14 | mini      |
-| asus/f2a85-m                  | AMD_FAMILY15_TN        | 2013-03-22 | desktop   |
-| bap/ode_e20XX                 | AMD_FAMILY16_KB        | 2015-05-27 | eval      |
-| biostar/a68n_5200             | AMD_FAMILY16_KB        | 2017-10-14 | eval      |
-| biostar/am1ml                 | AMD_FAMILY16_KB        | 2015-04-10 | mini      |
-| elmex/pcm205400               | AMD_FAMILY14           | 2016-09-29 | sbc       |
-| gizmosphere/gizmo2            | AMD_FAMILY16_KB        | 2014-12-09 | eval      |
-| gizmosphere/gizmo             | AMD_FAMILY14           | 2014-01-03 | half      |
-| hp/abm                        | AMD_FAMILY16_KB        | 2015-01-05 | mini      |
-| hp/pavilion_m6_1035dx         | AMD_FAMILY15_TN        | 2014-03-28 | laptop    |
-| jetway/nf81-t56n-lf           | AMD_FAMILY14           | 2014-02-16 | mini      |
-| lenovo/g505s                  | AMD_FAMILY15_TN        | 2014-11-27 | laptop    |
-| lippert/frontrunner-af        | AMD_FAMILY14           | 2013-03-02 | half      |
-| msi/ms7721                    | AMD_FAMILY15_TN        | 2016-11-22 | desktop   |
-| pcengines/apu1                | AMD_FAMILY14           | 2015-02-23 | half      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
-
-## [4.17 Release](coreboot-4.17-relnotes.md)
-No Branch or builder
-
-* No platforms maintained on this release
-
-
 ## [4.16 Release](coreboot-4.16-relnotes.md)
 Branch created, builder configured
 
@@ -85,449 +42,249 @@ Branch created, builder configured
 
 ## [4.13 Release](coreboot-4.13-relnotes.md)
 Tag only
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | intel/cannonlake_rvp        | INTEL_CANNONLAKE       | 2017-07-19 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
+
 
 ## [4.12 Release](coreboot-4.12-relnotes.md)
 
 Branch created, builder configured
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | bap/ode_e21XX               | AMD_PI_00730F01        | 2016-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/toucan-af           | AMD_FAMILY14           | 2013-03-02 | half     |
-+-----------------------------+------------------------+------------+----------+
 | ocp/sonorapass              | INTEL_COOPERLAKE_SP    | 2020-05-01 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
+
 
 ## [4.11 Release](coreboot-4.11-relnotes.md)
 
 Branch created, builder configured
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | adi/rcc-dff                 | INTEL_FSP_RANGELEY     | 2016-06-08 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | advansus/a785e-i            | AMD_AMDFAM10           | 2011-05-07 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | amd/bettong                 | AMD_PI_00660F01        | 2015-06-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/bimini_fam10            | AMD_AMDFAM10           | 2011-01-01 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/db-ft3b-lc              | AMD_PI_00730F01        | 2016-07-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/gardenia                | AMD_STONEYRIDGE_FP4    | 2016-12-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/lamar                   | AMD_PI_00630F01        | 2015-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/mahogany_fam10          | AMD_AMDFAM10           | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/olivehillplus           | AMD_PI_00730F01        | 2014-09-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/serengeti_cheetah_fam10 | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | amd/tilapia_fam10           | AMD_AMDFAM10           | 2010-04-23 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/torpedo                 | AMD_FAMILY12           | 2011-06-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | asus/kcma-d8                | AMD_AMDFAM10           | 2016-02-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/kfsn4-dre              | AMD_AMDFAM10           | 2015-01-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/kgpe-d16               | AMD_AMDFAM10           | 2015-10-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a785-m               | AMD_AMDFAM10           | 2010-09-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a785t-m              | AMD_AMDFAM10           | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m4a78-em               | AMD_AMDFAM10           | 2010-12-06 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m5a88-v                | AMD_AMDFAM10           | 2011-10-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | avalue/eax-785e             | AMD_AMDFAM10           | 2011-09-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | esd/atom15                  | INTEL_FSP_BAYTRAIL     | 2015-12-04 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | facebook/watson             | INTEL_FSP_BROADWELL_DE | 2018-06-26 | server   |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma785gm            | AMD_AMDFAM10           | 2012-04-23 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma785gmt           | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ma78gm             | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | google/urara                | IMGTEC_PISTACHIO       | 2015-03-27 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl165_g6_fam10           | AMD_AMDFAM10           | 2010-09-24 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iei/kino-780am2-fam10       | AMD_AMDFAM10           | 2010-09-13 | half     |
-+-----------------------------+------------------------+------------+----------+
 | intel/bayleybay_fsp         | INTEL_FSP_BAYTRAIL     | 2014-05-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/camelbackmountain_fsp | INTEL_FSP_BROADWELL_DE | 2016-04-15 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/littleplains          | INTEL_FSP_RANGELEY     | 2015-11-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/minnowmax             | INTEL_FSP_BAYTRAIL     | 2014-08-11 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | intel/mohonpeak             | INTEL_FSP_RANGELEY     | 2014-07-30 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | jetway/pa78vm5              | AMD_AMDFAM10           | 2010-08-17 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9652_fam10            | AMD_AMDFAM10           | 2010-03-01 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | ocp/monolake                | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | ocp/wedge100s               | INTEL_FSP_BROADWELL_DE | 2018-05-05 | server   |
-+-----------------------------+------------------------+------------+----------+
 | opencellular/rotundu        | INTEL_FSP_BAYTRAIL     | 2018-06-26 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_bdx1             | INTEL_FSP_BROADWELL_DE | 2016-04-29 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL     | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/mc_tcu3             | INTEL_FSP_BAYTRAIL_MD  | 2015-03-05 | misc     |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dmr_fam10      | AMD_AMDFAM10           | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8qme_fam10      | AMD_AMDFAM10           | 2010-02-03 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8scm_fam10      | AMD_AMDFAM10           | 2011-03-28 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2912_fam10            | AMD_AMDFAM10           | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m850               | VIA_NANO               | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m850               | VIA_VX900              | 2013-06-10 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.10 Release](coreboot-4.10-relnotes.md)
 Branch created
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | cubietech/cubieboard        | ALLWINNER_A10          | 2014-01-08 | sbc      |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.9 Release](coreboot-4.9-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | pcengines/alix1c            | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix1c            | AMD_LX                 | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix2d            | AMD_GEODE_LX           | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
 | pcengines/alix2d            | AMD_LX                 | 2010-08-31 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.8.1 Release](coreboot-4.8.1-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | aaeon/pfm-540i_revb         | AMD_GEODE_LX           | 2011-06-29 | half     |
-+-----------------------------+------------------------+------------+----------+
 | amd/db800                   | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/dbm690t                 | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/f2950                   | AMD_GEODE_LX           | 2016-07-17 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | amd/mahogany                | AMD_AMDK8              | 2010-03-16 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/norwich                 | AMD_GEODE_LX           | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/pistachio               | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/serengeti_cheetah       | AMD_AMDK8              | 2009-08-12 | server   |
-+-----------------------------+------------------------+------------+----------+
 | artecgroup/dbe61            | AMD_GEODE_LX           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | asrock/939a785gmh           | AMD_AMDK8              | 2010-04-05 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8n_e                  | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8v-e_deluxe           | AMD_AMDK8              | 2010-11-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/a8v-e_se               | AMD_AMDK8              | 2009-10-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/k8v-x                  | AMD_AMDK8              | 2011-12-02 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/kfsn4-dre_k8           | AMD_AMDK8              | 2015-10-30 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2n-e                  | AMD_AMDK8              | 2010-12-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2v                    | AMD_AMDK8              | 2010-11-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/m2v-mx_se              | AMD_AMDK8              | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | bachmann/ot200              | AMD_GEODE_LX           | 2012-07-13 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | bcom/winnetp680             | VIA_C7                 | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | broadcom/blast              | AMD_AMDK8              | 2009-10-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | digitallogic/msm800sev      | AMD_GEODE_LX           | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga_2761gxdk        | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/m57sli             | AMD_AMDK8              | 2009-10-03 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | google/purin                | BROADCOM_CYGNUS        | 2015-04-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rotor                | MARVELL_MVMAP2315      | 2016-09-13 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/zoombini             | INTEL_CANNONLAKE       | 2017-09-28 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl145_g1                 | AMD_AMDK8              | 2010-08-20 | server   |
-+-----------------------------+------------------------+------------+----------+
 | hp/dl145_g3                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iei/pcisa-lx-800-r10        | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | iei/pm-lx2-800-r10          | AMD_GEODE_LX           | 2012-10-28 | half     |
-+-----------------------------+------------------------+------------+----------+
 | iei/pm-lx-800-r11           | AMD_GEODE_LX           | 2012-07-06 | half     |
-+-----------------------------+------------------------+------------+----------+
 | intel/cougar_canyon2        | INTEL_FSP_IVYBRIDGE    | 2013-12-04 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/stargo2               | INTEL_FSP_IVYBRIDGE    | 2015-11-10 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8_htx               | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | jetway/j7f2                 | VIA_C7                 | 2014-01-19 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | kontron/kt690               | AMD_AMDK8              | 2009-10-15 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/hurricane-lx        | AMD_GEODE_LX           | 2010-09-10 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/literunner-lx       | AMD_GEODE_LX           | 2010-09-07 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/roadrunner-lx       | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lippert/spacerunner-lx      | AMD_GEODE_LX           | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lowrisc/nexys4ddr           | LOWRISC_LOWRISC        | 2016-10-28 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms7135                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms7260                  | AMD_AMDK8              | 2009-10-07 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9185                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms9282                  | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | nvidia/l1_2pvv              | AMD_AMDK8              | 2009-10-07 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | siemens/sitemp_g1p1         | AMD_AMDK8              | 2011-05-11 | half     |
-+-----------------------------+------------------------+------------+----------+
 | sunw/ultra40                | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | sunw/ultra40m2              | AMD_AMDK8              | 2015-11-10 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dme            | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8dmr            | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | technexion/tim5690          | AMD_AMDK8              | 2009-10-13 | half     |
-+-----------------------------+------------------------+------------+----------+
 | technexion/tim8690          | AMD_AMDK8              | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | traverse/geos               | AMD_GEODE_LX           | 2010-05-20 | half     |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2912                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-cn                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/epia-m700               | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/pc2500e                 | VIA_C7                 | 2009-09-25 | mini     |
-+-----------------------------+------------------------+------------+----------+
 | via/vt8454c                 | VIA_C7                 | 2009-08-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | winent/mb6047               | AMD_AMDK8              | 2013-10-19 | half     |
-+-----------------------------+------------------------+------------+----------+
 | winent/pl6064               | AMD_GEODE_LX           | 2010-02-24 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | winnet/g170                 | VIA_C7                 | 2017-08-28 | mini     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.7 Release](coreboot-4.7-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | abit/be6-ii_v2_0            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | amd/dinar                   | AMD_FAMILY15           | 2012-02-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | amd/rumba                   | AMD_GEODE_GX2          | 2009-08-29 | half     |
-+-----------------------------+------------------------+------------+----------+
 | asus/dsbf                   | INTEL_I5000            | 2012-07-14 | server   |
-+-----------------------------+------------------------+------------+----------+
 | asus/mew-am                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | asus/mew-vm                 | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | a-trend/atc-6220            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | a-trend/atc-6240            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | azza/pt-6ibd                | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | biostar/m6tba               | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | compaq/deskpro_en_sff_p600  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | dmp/vortex86ex              | DMP_VORTEX86EX         | 2013-07-05 | sbc      |
-+-----------------------------+------------------------+------------+----------+
 | ecs/p6iwp-fe                | INTEL_I82810           | 2010-06-09 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga-6bxc            | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | gigabyte/ga-6bxe            | INTEL_I440BX           | 2010-05-14 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | hp/e_vectra_p2706t          | INTEL_I82810           | 2009-10-20 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | intel/d810e2cb              | INTEL_I82810           | 2010-06-21 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | intel/eagleheights          | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/mtarvon               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/truxton               | INTEL_I3100            | 2009-09-25 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwave/iWRainbowG6           | INTEL_SCH              | 2010-12-18 | half     |
-+-----------------------------+------------------------+------------+----------+
 | lanner/em8510               | INTEL_I855             | 2010-08-30 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | lippert/frontrunner         | AMD_GEODE_GX2          | 2009-10-08 | half     |
-+-----------------------------+------------------------+------------+----------+
 | mitac/6513wu                | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6119                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6147                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6156                  | INTEL_I440BX           | 2009-10-13 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | msi/ms6178                  | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | nec/powermate2000           | INTEL_I82810           | 2009-08-28 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | nokia/ip530                 | INTEL_I440BX           | 2010-04-19 | server   |
-+-----------------------------+------------------------+------------+----------+
 | rca/rm4100                  | INTEL_I82830           | 2009-10-07 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | soyo/sy-6ba-plus-iii        | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8qgi            | AMD_FAMILY15           | 2011-07-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/h8scm            | AMD_FAMILY15           | 2012-11-30 | server   |
-+-----------------------------+------------------------+------------+----------+
 | supermicro/x7db8            | INTEL_I5000            | 2012-06-23 | server   |
-+-----------------------------+------------------------+------------+----------+
 | thomson/ip1000              | INTEL_I82830           | 2009-10-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s1846                  | INTEL_I440BX           | 2009-08-26 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s8226                  | AMD_FAMILY15           | 2012-10-04 | server   |
 | wyse/s50                    | AMD_GEODE_GX2          | 2010-05-08 | settop   |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.6](coreboot-4.6-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | bifferos/bifferboard        | RDC_R8610              | 2012-03-27 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/cosmos               | MARVELL_BG4CD          | 2015-04-09 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/bakersport_fsp        | INTEL_FSP_BAYTRAIL     | 2014-08-11 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.5](coreboot-4.5-relnotes.md)
 Tag only
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | google/enguarde             | INTEL_BAYTRAIL         | 2016-09-21 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/falco                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/guado                | INTEL_BROADWELL        | 2016-01-12 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/ninja                | INTEL_BAYTRAIL         | 2016-05-31 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/panther              | INTEL_HASWELL          | 2014-07-12 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/peppy                | INTEL_HASWELL          | 2013-11-25 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/rikku                | INTEL_BROADWELL        | 2016-06-16 | half     |
-+-----------------------------+------------------------+------------+----------+
 | google/samus                | INTEL_BROADWELL        | 2014-08-29 | laptop   |
-+-----------------------------+------------------------+------------+----------+
 | google/tidus                | INTEL_BROADWELL        | 2016-01-21 | half     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.4](coreboot-4.4-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | google/bolt                 | INTEL_HASWELL          | 2013-12-12 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rush                 | NVIDIA_TEGRA132        | 2015-01-26 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/rush_ryu             | NVIDIA_TEGRA132        | 2015-03-05 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | google/slippy               | INTEL_HASWELL          | 2013-11-24 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | intel/amenia                | INTEL_APOLLOLAKE       | 2016-04-20 | eval     |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.3](coreboot-4.3-relnotes.md)
@@ -539,51 +296,28 @@ Branch created
 ## [4.2](coreboot-4.2-relnotes.md)
 Branch created
 
-```eval_rst
-+-----------------------------+------------------------+------------+----------+
 | Vendor/Board                | Processor              | Date added | Brd type |
-+=============================+========================+============+==========+
+|-----------------------------|------------------------|------------|----------|
 | arima/hdama                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | digitallogic/adl855pc       | INTEL_I855             | 2009-10-09 | half     |
-+-----------------------------+------------------------+------------+----------+
 | ibm/e325                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | ibm/e326                    | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | intel/sklrvp                | INTEL_SKYLAKE          | 2015-07-17 | eval     |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8s2                 | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | iwill/dk8x                  | AMD_AMDK8              | 2009-10-09 | server   |
-+-----------------------------+------------------------+------------+----------+
 | newisys/khepri              | AMD_AMDK8              | 2009-10-07 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2735                  | INTEL_E7501            | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2850                  | AMD_AMDK8              | 2009-09-25 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2875                  | AMD_AMDK8              | 2009-09-25 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2881                  | AMD_AMDK8              | 2009-09-23 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2885                  | AMD_AMDK8              | 2009-10-08 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2891                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2892                  | AMD_AMDK8              | 2009-09-22 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s2895                  | AMD_AMDK8              | 2009-09-22 | desktop  |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s4880                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
 | tyan/s4882                  | AMD_AMDK8              | 2009-10-08 | server   |
-+-----------------------------+------------------------+------------+----------+
-```
 
 
 ## [4.1](coreboot-4.1-relnotes.md)

Documentation/releases/checklist.md

@@ -4,73 +4,56 @@
 
 # coreboot Release Process
 
-This document describes our release process and all prerequisites to
-implement it successfully.
-
+This document describes our release process and all prerequisites to implement
+it successfully.
 
 ## Purpose of coreboot releases
-Our releases aren't primarily a vehicle for code that is stable across
-all boards: The logistics of testing the more than 100 boards that are
-spread out all continents (except Antarctica, probably) on a given tree
-state are prohibitive for project of our size.
+Our releases aren't primarily a vehicle for code that is stable across all
+boards: The logistics of testing the more than 100 boards that are spread out
+all continents (except Antarctica, probably) on a given tree state are
+prohibitive for project of our size.
 
-Instead, the releases are regular breakpoints that serve multiple
-purposes: They support cooperation between multiple groups (corporations
-or otherwise) in that it's easier to keep source trees synchronized
-based on a limited set of commits. They allow a quick assessment of the
-age of any given build or source tree based on its git version (4.8-1234
-was merged into master a few months after 4.8, which came out in April
-of 2018. 4.0-21718's age is harder to guess).
+Instead, the releases are regular breakpoints that serve multiple purposes:
+They support cooperation between multiple groups (corporations or otherwise)
+in that it's easier to keep source trees synchronized based on a limited set
+of commits. They allow a quick assessment of the age of any given build or
+source tree based on its git version (4.8-1234 was merged into master a few
+months after 4.8, which came out in April 2018. 4.0-21718's age is harder to
+guess).
 
-And finally we use releases to as points in time where we remove old
-code: Once we decide that a certain part of coreboot gets in the way of
-future development, we announce on the next release that we intend to
-remove that part - and everything that depends on it - after the
-following release. So removing feature FOO will be announced in release
-X for release X+1. The first commit after X+1 is fair game for such
-removal.
+And finally we use releases to as points in time where we remove old code:
+Once we decide that a certain part of coreboot gets in the way of future
+development, we announce on the next release that we intend to remove that
+part - and everything that depends on it - after the following release.
+So removing feature FOO will be announced in release X for release
+X+1. The first commit after X+1 is fair game for such removal.
 
-Together with our 3 months release horizon, this provides time to plan
+Together with our 6 months release horizon, this provides time to plan
 any migrations necessary to keep older boards in the tree by bringing
 them up to current standards.
 
-## coreboot release team
-To avoid issues of blocking the release on a single person, a release
-team has been formed. Please see the `COREBOOT RELEASES` section of the
-MAINTAINERS file for the current members.
-
-These individuals work together to make sure releases are done on time,
-follow the steps of this document, and update the release processes and
-scripts.
-
-
 ## Needed credentials & authorizations
-
-### coreboot admins only
 * Website access is required to post the release files to the website.
-
-### All release team members
-* IRC topic access is required to update the topic.
+* IRC admin access is required to update the topic.
 * Git access rights are needed to post the tag.
 * Blog post access is needed to do the blog post.
 * A PGP key is required to sign the release tarballs and git tag.
 
-Most of the steps in the release process can be done by anyone on the
-release team. Only adding the files to the website needs to be done
-by a coreboot administrator.
+This set of required credentials implies that releases can only be done
+by a coreboot admin.
 
 ## When to release
-Releases are done roughly on a 3-month schedule. If a release is
-delayed, the next release will still be 3 months after the last release.
+Releases are done roughly on a 6-month schedule, ideally around end
+of April and end of October (can be a bit earlier or delay into May
+or November).
 
+We initially followed a 3 month release schedule, but we found that to
+be more frequent than was needed, so we scaled it back to twice a year.
 
 ## Checklist
-
 ### ~2 weeks prior to release
 - [ ] Announce upcoming release to mailing list, ask people to test and
       to update release notes.
-- [ ] Start marking patches that should to go into the release with a
-      tag "coreboot_release_X.yy"
 
 ### ~1 week prior to release
 - [ ] Send reminder email to mailing list, ask for people to test,
@@ -83,53 +66,28 @@ delayed, the next release will still be 3 months after the last release.
 - [ ] Finalize release notes as much as possible
 - [ ] Prepare release notes template for following release
 - [ ] Update `Documentation/releases/index.md`
-- [ ] Check which branches need to be released. Any branch with changes
-      should get a new release. Announce these branch releases and
-      prepare release notes.
-
-### Day before release
-- [ ] Make sure patches with tags for the release are merged.
-- [ ] Announce to IRC that the release will be tomorrow and ask for
-      testing.
 - [ ] Run `util/vboot_list/vboot_list.sh` script to update the list of
       boards supported by vboot.
 
 ### Day of release
-- [ ] Review the full documentation about doing the release below.
-- [ ] Select a commit ID to base the release upon.
+- [ ] Select a commit ID to base the release upon, announce to IRC,
+      ask for testing.
 - [ ] Test the commit selected for release.
-- [ ] Submit last pre-release release notes.
-- [ ] Run the release script.
+- [ ] Submit release notes
+- [ ] Create new release notes doc template for the next version.
+- [ ] Fill in the release date, remove "Upcoming release" and other filler
+      from the current release notes.
+- [ ] Run release script.
 - [ ] Test the release from the actual release tarballs.
-- [ ] Push signed Tag to repo. *This is the actual release step.*
-      Once this patch is pushed, the release itself has been done.
-      everything after this step is packaging and delivering the
-      release.
-
+- [ ] Push signed Tag to repo.
 - [ ] Announce that the release tag is done on IRC.
-- [ ] Update the topic in the IRC channel that the release is done.
-
-- [ ] Do the final release notes - Fill in the release date, remove
-      "Upcoming release" and other filler from the current release
-      notes.
-- [ ] ADMIN: Upload release files to web server.
-- [ ] ADMIN: Upload the final release notes to the web server.
-- [ ] ADMIN: Upload crossgcc sources to web server.
-- [ ] Create coreboot-sdk and coreboot-jenkins-node docker images
-      based on the release ID and push them to dockerhub. These
-      can be used as release builders.
-
-### Week following the release
+- [ ] Upload release files to web server.
+- [ ] Also extract the release notes and place them on the web server.
+- [ ] Upload crossgcc sources to web server.
 - [ ] Update download page to point to files, push to repo.
-- [ ] Write and publish blog post with release final notes. Branch
-      releases notes should be included in the same post.
-- [ ] Remove code that was announced it was going to be removed.
-- [ ] Update `Documentation/releases/boards_supported_on_branches.md`
-
-### Creating a branch
-- [ ] Branches are named 4.xx_branch to differentiate from the tags.
-      Instructions on creating branches are listed below.
-
+- [ ] Write and publish blog post with release notes.
+- [ ] Update the topic in the IRC channel that the release is done.
+- [ ] Announce the release to the mailing list.
 
 ## Pre-Release tasks
 Announce the upcoming release to the mailing list release 2 weeks ahead
@@ -144,30 +102,29 @@ People should be encouraged to provide additions to the release notes.
 
 The final release notes will reside in coreboot's Documentation/releases
 directory, so asking for additions to that through the regular Gerrit
-process works as well. Note that git requires lots of conflict
-resolution on heavily edited text files though.
+process works as well. Note that git requires lots of conflict resolution
+on heavily edited text files though.
 
 Frequently, we will want to wait until particular things are in the
-release. Once those are in, you can select the commit ID that you want
-to use for your release. For the 4.6 release, we waited until we had
+release.  Once those are in, you can select the commit ID that you want
+to use for your release.  For the 4.6 release, we waited until we had
 time to do the release, then pulled in a few patches that we wanted
-to have in the release. The release was based on the final of those
+to have in the release.  The release was based on the final of those
 patches to be pulled in.
 
 When a release candidate has been selected, announce the commit ID to
 the #coreboot IRC channel, and request that it get some testing, just
 to make sure that everything is sane.
 
-
 ## Generate the release
 After the commit for the release has been selected and verified, run the
-release script - util/release/build-release. This will download a new
+release script - util/release/build-release.  This will download a new
 tree, checkout the commit that you specified, download the submodules,
 create a tag, then generate and sign the tarballs.
 
-**Be prepared to type in your PGP key’s passphrase.**
+Be prepared to type in your PGP key’s passphrase.
 
-```text
+````
 usage: util/release/build-release <version> [commit id] [username] [gpg key id]
 Tags a new coreboot version and creates a tar archive
 
@@ -175,41 +132,37 @@ version:    New version name to tag the tree with
 commit id:  check out this commit-id after cloning the coreboot tree
 username:   clone the tree using ssh://USERNAME - defaults to https://
 gpg key id: used to tag the version, and generate a gpg signature
-```
+````
 
-After running the script, you should have a new directory for the
-release, along with 4 files: 2 tarballs, and 2 signature files.
+After running the script, you should have a new directory for the release,
+along with 4 files - 2 tarballs, and 2 signature files.
 
-```text
+````
 drwxr-xr-x   9 martin martin      4096 Apr 30 19:57 coreboot-4.6
 -rw-r--r--   1 martin martin  29156788 Apr 30 19:58 coreboot-4.6.tar.xz
 -rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-4.6.tar.xz.sig
 -rw-r--r--   1 martin martin   5902076 Apr 30 19:58 coreboot-blobs-4.6.tar.xz
 -rw-r--r--   1 martin martin       836 Apr 30 19:58 coreboot-blobs-4.6.tar.xz.sig
-```
+````
 
 Here’s the command that was used to generate the 4.6 release:
-```bash
-util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
-```
-
+````
+% util/release/build-release 4.6 db508565 Gaumless 3E4F7DF7
+````
 
 ## Test the release from the tarballs
 * Run “make what-jenkins-does” and verify that everything is building.
 * Build and test qemu
-```bash
-cp configs/config.emulation_qemu_x86_i440fx .config
-make olddefconfig
-make
-qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
-```
+  ````
+  cp configs/config.emulation_qemu_x86_i440fx .config; make olddefconfig; make
+  qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
+  ````
 * Build and test any other platforms you can.
-* Compare the directory from the tarballs to the coreboot repo to make
-  sure nothing went wrong.
+* Compare the directory from the tarballs to the coreboot repo to make sure nothing went wrong.
 * Push the tag to git
 
 A good tag will look like this:
-````text
+````
 % git show 4.6
 tag 4.6
 Tagger: Martin Roth <martinroth@google.com>
@@ -230,44 +183,33 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
 ...
 ````
 
-When you used the script to generate the release, a signed tag was
-generated in the tree that was downloaded. From the coreboot-X.Y tree,
-just run: `git push origin X.Y`. In case you pushed the wrong tag
-already, you have to force push the new one.
+When you used the script to generate the release, a signed tag was generated in the
+tree that was downloaded. From the coreboot-X.Y tree, just run: `git push origin X.Y`.
+In case you pushed the wrong tag already, you have to force push the new one.
 
 You will need write access for tags to the coreboot git repo to do this.
 
-
 ## After the release is tagged in git
 Announce that the release has been tagged - this lets people know that
-they should update their trees to grab the new tag. Until they do this,
+they should update their trees to grab the new tag.  Until they do this,
 the version number in build.h will still be based on the previous tag.
 
 Copy the tarballs and .sig files generated by the script to
 the coreboot server, and put them in the release directory at
 `/srv/docker/www.coreboot.org-staticfiles/releases/`
 
-````bash
-# Update the sha256sum file
-sha256sum -b coreboot-*.tar.xz > sha256suma.txt
-
-# make sure the two new files are present (and nothing else has changed)
-diff sha256sum.txt sha256suma.txt
-
-mv sha256suma.txt sha256sum.txt
+````
+% sha256sum -b coreboot-*.tar.xz > sha256suma.txt # Update the sha256sum file
+% diff sha256sum.txt sha256suma.txt # make sure that the two new files are present (and that nothing else has changed)
+% mv sha256suma.txt sha256sum.txt
 ````
 
 People can now see the release tarballs on the website at
 <https://www.coreboot.org/releases/>
 
-The downloads page is the official place to download the releases from,
-and it needs to be updated with links to the new release tarballs and
-.sig files. It can be found at:
-<https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
-
-Here is an example commit to change it:
-<https://review.coreboot.org/c/homepage/+/19515>
+The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at <https://review.coreboot.org/cgit/homepage.git/tree/downloads.html>
 
+Here is an example commit to change it: <https://review.coreboot.org/c/homepage/+/19515>
 
 ## Upload crossgcc sources
 Sometimes the source files for older revisions of
@@ -277,32 +219,24 @@ sources used by the crossgcc scripts that are part of coreboot releases.
 
 Run
 
-````bash
-util/crossgcc/buildgcc -u
+````
+% util/crossgcc/buildgcc -u
 ````
 
 This will output the set of URLs that the script uses to download the
 sources. Download them yourself and copy them into the crossgcc-sources
 directory on the server.
 
-
 ## After the release is complete
-Post the final release notes on <https://blogs.coreboot.org>
-
+Post the release notes on <https://blogs.coreboot.org>
 
 ## Making a branch
 At times we will need to create a branch, generally for patch fixes.
-When making a branch, do NOT name it the same as the release tag: X.Y -
-this creates trouble when trying to check it out, as git can’t tell
-whether you want the tag or the branch. Instead, name it X.Y\_branch:
-```bash
-git checkout 4.8
-git checkout -b 4.8_branch
-git push origin 4.8_branch
-```
+When making a branch, do NOT name it the same as the release tag: X.Y - this creates trouble when trying to check it out, as git can’t tell whether you want the tag or the branch.
+Instead, name it X.Y\_branch: `git checkout 4.8; git checkout -b 4.8_branch; git push origin 4.8_branch`
 
 You can then cherry-pick changes and push them up to the branch:
-````bash
+````
 git cherry-pick c6d134988c856d0025153fb885045d995bc8c397
 git push origin HEAD:refs/for/4.8_branch
 ````

Documentation/releases/coreboot-4.15-relnotes.md

@@ -52,9 +52,9 @@ Deprecations and incompatible changes
 
 Drop the deprecated COREBOOTPAYLOAD option, and replace it with MrChromebox's
 updated UefiPayloadPkg option. Simplify the Kconfig options to make it easier
-to build from upstream edk2 master. Drop the EDK2_USE_8254_TIMER Kconfig
+to build from upstream edk2 master. Drop the TIANOCORE_USE_8254_TIMER Kconfig
 option since it applies only to CorebootPayloadPkg. Clean up the Makefile now
-that we're only building from a single edk2 package/target.
+that we're only building from a single Tianocore package/target.
 
 ### Remove old lp4x and ddr4 versions of spd_tools
 

Documentation/releases/coreboot-4.17-relnotes.md

@@ -296,36 +296,6 @@ noting, but not needing a full description.
 * sandybridge & gm45: Support setting PCI bars above 4G
 
 
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the V4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the V4
-allocator.
-
-
 Plans for Code Deprecation
 --------------------------
 

Documentation/releases/coreboot-4.18-relnotes.md

@@ -1,190 +1,51 @@
-coreboot 4.18 release
-========================================================================
+Upcoming release - coreboot 4.18
+================================
 
-The 4.18 release was quite late, but was completed on October 16, 2022.
+The 4.18 release is planned for August 2022.
 
-In the 4 months since the 4.17 release, the coreboot project has merged
-more than 1800 commits from over 200 different authors. Over 50 of those
-authors submitted their first patches.
+Update this document with changes that should be in the release notes.
 
-Welcome and thank you to all of our new contributors, and of course the
-work of all of the seasoned contributors is greatly appreciated.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+
+Significant changes
+-------------------
+
+### Add significant changes here
 
 
-Significant or interesting changes
-----------------------------------
-
-### sconfig: Allow to specify device operations
-
-Currently we only have runtime mechanisms to assign device operations to
-a node in our devicetree (with one exception: the root device). The most
-common method is to map PCI IDs to the device operations with a `struct
-pci_driver`. Another accustomed way is to let a chip driver assign them.
-
-For very common drivers, e.g. those in soc/intel/common/blocks/, the PCI
-ID lists grew very large and are incredibly error-prone. Often, IDs are
-missing and sometimes IDs are added almost mechanically without checking
-the code for compatibility. Maintaining these lists in a central place
-also reduces flexibility.
-
-Now, for onboard devices it is actually unnecessary to assign the device
-operations at runtime. We already know exactly what operations should be
-assigned. And since we are using chipset devicetrees, we have a perfect
-place to put that information.
-
-This patch adds a simple mechanism to `sconfig`. It allows us to speci-
-fy operations per device, e.g.
-
-device pci 00.0 alias system_agent on
-	ops system_agent_ops
-end
-
-The operations are given as a C identifier. In this example, we simply
-assume that a global `struct device_operations system_agent_ops` exists.
 
 
-### Set touchpads to use detect (vs probed) flag
-
-Historically, ChromeOS devices have worked around the problem of OEMs
-using several different parts for touchpads/touchscreens by using a
-ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
-to indicate that the device may or may not be present, and that the
-driver should probe to confirm device presence.
-
-Since release 4.18, coreboot  supports detection for i2c devices at
-runtime when creating the device entries for the ACPI/SSDT tables,
-rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
-in the tree from using the 'probed' flag to the 'detect' flag.
-
-Touchscreens require more involved power sequencing, which will be done
-at some future time, after which they will switch over as well.
 
 
-### Add SBOM (Software Bill of Materials) Generation
-
-Firmware is typically delivered as one large binary image that gets
-flashed. Since this final image consists of binaries and data from a
-vast number of different people and companies, it's hard to determine
-what all the small parts included in it are. The goal of the software
-bill of materials (SBOM) is to take a firmware image and make it easy to
-find out what it consists of and where those pieces came from.
-
-Basically, this answers the question, who supplied the code that's
-running on my system right now? For example, buyers of a system can use
-an SBOM to perform an automated vulnerability check or license analysis,
-both of which can be used to evaluate risk in a product. Furthermore,
-one can quickly check to see if the firmware is subject to a new
-vulnerability included in one of the software parts (with the specified
-version) of the firmware.
-
-Further reference:
-https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
-
-- Add Makefile.inc to generate and build coswid tags
-- Add templates for most payloads, coreboot, intel-microcode,
-  amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
-  intel ME and compiler (gcc,clang,other)
-- Add Kconfig entries to optionally supply a path to CoSWID tags
-  instead of using the default CoSWID tags
-- Add CBFS entry called SBOM to each build via Makefile.inc
-- Add goswid utility tool to generate SBOM data
 
 
-Additional coreboot changes
----------------------------
 
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Allocator v4 is not yet ready, but received significant work.
-* Console: create an [smbus console driver](https://doc.coreboot.org/technotes/console.html)
-* pciexp_device: Numerous updates and fixes
-* Update checkpatch to match Linux v5.19
-* Continue updating ACPI to ASL 2.0 syntax
-* arch/x86: Add a common romstage entry point
-* Documentation: Add a list of [acronyms](https://doc.coreboot.org/acronyms.html)
-* Start hooking up ops in devicetree
-* Large amounts of general code cleanup and improvement, as always
-* Work to make sure all files have licenses
-
-
-Payloads
---------
-
-### EDK II (TianoCore)
-
-coreboot uses TianoCore interchangeably with EDK II, and whilst the
-meaning is generally clear, it's not the payload it uses.
-Consequentially, TianoCore has been renamed to EDK II (2).
-
-The option to use the already deprecated CorebootPayloadPkg has been
-removed.
-
-Recent changes to both coreboot and EDK means that UefiPayloadPkg seems
-to work on all hardware. It has been tested on:
-
-* Intel Core 2nd, 3rd, 4th, 5th, 6th, 7th, 8th, 8th, 9th, 10th,
-  11th and 12th generation processors
-* Intel Small Core BYT, BSW, APL, GLK and GLK-R processors
-* AMD Stoney Ridge and Picasso
-
-CorebootPayloadPkg can still be found [here](https://github.com/MrChromebox/edk2/tree/coreboot_fb).
-
-The recommended option to use is `EDK2_UEFIPAYLOAD_MRCHROMEBOX` as
-`EDK2_UEFIPAYLOAD_OFFICIAL` will no longer work on any SoC.
-
-
-New Mainboards
---------------
-
-* AMD Birman
-* AMD Pademelon renamed from Padmelon
-* Google Evoker
-* Google Frostflow
-* Google Gaelin4ADL
-* Google Geralt
-* Google Joxer
-* Google Lisbon
-* Google Magikarp
-* Google Morthal
-* Google Pujjo
-* Google Rex 0
-* Google Shotzo
-* Google Skolas
-* Google Tentacruel
-* Google Winterhold
-* Google Xivu
-* Google Yaviks
-* Google Zoglin
-* Google Zombie
-* Google Zydron
-* MSI PRO Z690-A WIFI DDR4
-* Siemens MC APL7
-
-
-Removed Mainboards
-------------------
-
-* Google Brya4ES
-
-
-Updated SoCs
-------------
-
-* Added Intel Meteor Lake
-* Added Mediatek Mt8188
-* Renamed AMD Sabrina to Mendocino
-* Added AMD Morgana
 
 
 Plans for Code Deprecation
 --------------------------
 
+
+### Intel Icelake
+
+Intel Icelake code will be removed following the 4.19 release, planned
+for November 2022. This consists of the Intel Icelake SOC and Intel
+Icelake RVP mainboard
+
+Intel Icelake is unmaintained. Also, the only user of this platform ever
+was the CRB board. From the looks of it the code never was ready for
+production as only engineering sample CPUIDs are supported. This reduces
+the maintanence overhead for the coreboot project.
+
+
 ### LEGACY_SMP_INIT
 
 Legacy SMP init will be removed from the coreboot master branch
 immediately following this release. Anyone looking for the latest
-version of the code should find it on the 4.18 branch or tag.
+version of the code should find it on the 4.18 branch.
 
 This also includes the codepath for SMM_ASEG. This code is used to start
 APs and do some feature programming on each AP, but also set up SMM.
@@ -193,96 +54,3 @@ cover all use cases of LEGACY_SMP_INIT, with little code changes. The
 reason for deprecation is that having 2 codepaths to do the virtually
 the same increases maintenance burden on the community a lot, while also
 being rather confusing.
-
-
-Plans to move platform support to a branch:
--------------------------------------------
-After the 4.18 release in November 2022, we plan to move support for any
-boards still requiring RESOURCE_ALLOCATOR_V3 to the 4.18 branch.  V4 was
-introduced more than a year ago and with minor changes most platforms
-were able to work just fine with it. A major difference is that V3 uses
-just one continuous region below 4G to allocate all PCI memory BAR's. V4
-uses all available space below 4G and if asked to, also above 4G too.
-This makes it important that SoC code properly reports all fixed
-resources.
-
-Currently only AGESA platforms have issues with it. On Gerrit both
-attempts to fix AMD AGESA codebases to use V4 and compatibility modes
-inside the V4 allocator have been proposed, but both efforts seem
-stalled. See the (not yet merged) documentation
-[CR:43603](https://review.coreboot.org/c/coreboot/+/43603) on it's
-details. It looks like properly reporting all fixed resources is the
-issue.
-
-At this point, we are not specifying which platforms this will include
-as there are a number of patches to fix these issues in flight.
-Hopefully, all platforms will end up being migrated to the v4 resource
-allocator so that none of the platforms need to be supported on the
-branch.
-
-Additionally, even if the support for the platform is moved to a branch,
-it can be brought back to ToT if they're fixed to support the v4
-allocator.
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained. Also, the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of it the
-code was never ready for production as only engineering sample CPUIDs
-are supported. This reduces the maintanence overhead for the coreboot
-project.
-
-Intel Icelake code will be removed with release 4.19 and any maintenence
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed.  Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from commit d2d9021543 to f4c97ea131
------------------------------------------------
-
-- Total Commits: 1822
-- Average Commits per day: 13.38
-- Total lines added: 150578
-- Average lines added per commit: 82.64
-- Number of patches adding more than 100 lines: 128
-- Average lines added per small commit: 38.44
-- Total lines removed: 33849
-- Average lines removed per commit: 18.58
-- Total difference between added and removed: 116729
-- Total authors: 202
-- New authors: 52
-
-
-Known Issues
-------------
-
-A couple of issues were discovered immediately following the release
-that will be fixed in a follow-on point release in the upcoming weeks.
-
-A pair of changes ([CB:67754](https://review.coreboot.org/67754) and
-[CB:67662](https://review.coreboot.org/67662)) which merged shortly
-before the 4.18 release have created an issue on Intel Apollo Lake
-platform boards which prevents SMM/SMI from functioning; this affects
-only Apollo Lake (but not Gemini Lake) devices.
-See [CB:68599](https://review.coreboot.org/68599) for the fix.
-
-Another issue applies to all Intel-based boards with onboard I2C TPMs
-when verified boot is not enabled. The I2C buses don’t get initialized
-until after the TPM, causing timeouts, TPM initialization failures, and
-long boot times.  See [CB:68550](https://review.coreboot.org/68550) for
-the fix.

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,233 +0,0 @@
-Upcoming release - coreboot 4.19
-========================================================================
-
-The 4.19 release is planned for the 16th of January 2023.
-
-Since the last release, the coreboot project has merged over 1600
-commits from over 150 authors. Of those authors, around 25 were
-first-time committers to the coreboot project.
-
-As always, we are very grateful to all of the contributors for helping
-to keep the project going. The coreboot project is different from many
-open source projects in that we need to keep constantly updating the
-codebase to stay relevant with the latest processors and technologies.
-It takes constant effort to just stay afloat, let alone improve the
-codebase. Thank you very much to everyone who has contributed, both in
-this release and in previous times.
-
-The 4.20 release is planned for the 20th of April, 2023.
-
-
-Significant or interesting changes
-----------------------------------
-
-
-### Show all Kconfig options in saved config file; compress same
-
-The coreboot build system automatically adds a 'config' file to CBFS
-that lists the exact Kconfig configuration that the image was built
-with. This is useful to reproduce a build after the fact or to check
-whether support for a specific feature is enabled in the image.
-
-This file has been generated using the 'savedefconfig' Kconfig command,
-which generates the minimal .config file that is needed to produce the
-required config in a coreboot build. This is fine for reproduction, but
-bad when you want to check if a certain config was enabled, since many
-options get enabled by default or pulled in through another option's
-'select' statement and thus don't show up in the defconfig.
-
-Instead coreboot now includes a larger .config instead. In order to save
-some space, all of the comments disabling options are removed from the
-file, except for those included in the defconfig.
-
-We can also LZMA compress the file since it is never read by firmware
-itself and only intended for later re-extraction via cbfstool, which
-always has LZMA support included.
-
-
-### Toolchain updates
-
-* Upgrade LLVM from 15.0.0 to 15.0.6
-* Upgrade CMake from 3.24.2 to 3.25.0
-* Upgrade IASL from 20220331 to 20221020
-* Upgrade MPFR from 4.1.0 to 4.1.1
-
-
-### Finished the conversion to ASL 2.0 syntax
-
-Until recently, coreboot still contained lots of code using the legacy
-ASL syntax. However, all ASL code was ported over to make use of the ASL
-2.0 syntax and from this point on new ASL code should make use of it.
-
-
-Additional coreboot changes
----------------------------
-
-* Significant work was done to enable and build-test clang builds.
-* Added touchscreen power sequencing and runtime detection.
-* A number of patches were added to clean up and improve SMBIOS.
-* Work is in progress to unify and extend coreboot post codes.
-* Clean up for header includes is in progress with help from IWYU.
-* IOAPIC code has been reworked.
-* Support was added to superiotool for the NCT6687D-W chip.
-* Work is progressing to switch return values to enum cb_err instead of
-  bool or other pass/fail indicators.
-* Clang builds are now working for most boards and are being
-  build-tested.
-* 64-bit coreboot support is in progress and is working on a number of
-  platforms.
-* A driver for EC used on various Clevo laptops was added.
-* Native Intel Lynxpoint code was added to replace the MRC.bin.
-* Work continued for the process of adding ops structures to the
-  devicetree.
-* The crossgcc tool can now download the source packages, which are
-  needed to build the coreboot toolchain, from coreboot’s own mirror if
-  desired.
-* A document with useful external resources related to firmware
-  development was added at Documentation/external_docs.md.
-
-
-New Mainboards
---------------
-
-* AMD: Mayan for Phoenix SoC
-* GIGABYTE: GA-H61M-DS2
-* Google: Crystaldrift
-* Google: Gladios
-* Google: Dibbi
-* Google: Gaelin
-* Google: Marasov
-* Google: Markarth
-* Google: Omnigul
-* Google: Voltorb
-* Intel: Meteorlake-P RVP
-* MSI: PRO Z690-A (WIFI)
-* Siemens: MC_EHL3
-* Star Labs: StarBook Mk VI (i3-1220P and i7-1260P)
-* System76: darp8
-* System76: galp6
-
-
-Removed Mainboards
-------------------
-
-* AMD: Inagua
-* AMD: Olive Hill
-* AMD: Parmer
-* AMD: Persimmon
-* AMD: Southstation
-* AMD: Thatcher
-* AMD: Unionstation
-* ASROCK: E350M1
-* ASROCK: IMB-A180
-* ASUS: A88XM-E
-* ASUS: AM1I-A
-* ASUS: F2A85-M
-* ASUS: F2A85-M LE
-* ASUS: F2A85-M PRO
-* BAP: ODE_e20xx
-* Biostar: A68N-5200
-* Biostar: AM1ML
-* ELMEX: pcm205400
-* ELMEX: pcm205401
-* GizmoSphere: Gizmo
-* GizmoSphere: Gizmo2
-* Google: Morthal
-* HP: ABM
-* HP: Pavilion m6 1035dx
-* Jetway: NF81_T56N_LF
-* Lenovo: AMD G505s
-* LiPPERT: FrontRunner-AF aka ADLINK CoreModule2-GF
-* LiPPERT: Toucan-AF aka cExpress-GFR (+W83627DHG SIO)
-* MSI: MS-7721 (FM2-A75MA-E35)
-* PC Engines: APU1
-
-
-Updated SoCs
-------------
-
-* Added soc/amd/glinda
-* Renamed soc/amd/morgana to soc/amd/phoenix
-* Removed cpu/amd/agesa/family14
-* Removed cpu/amd/agesa/family15tn
-* Removed cpu/amd/agesa/family16kb
-
-
-Updated Chipsets
-----------------
-
-* Removed northbridge/amd/agesa/family14
-* Removed northbridge/amd/agesa/family15tn
-* Removed northbridge/amd/agesa/family16kb
-* Removed southbridge/amd/agesa/hudson
-* Removed southbridge/amd/cimx/sb800
-
-
-Payloads
---------
-
-* Updated GRUB from 2.04 to 2.06
-* Updated SeaBIOS 1.16.0 to 1.16.1
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-
-### Intel Icelake SoC & Icelake RVP mainboard
-
-Intel Icelake is unmaintained and the only user of this platform ever
-was the Intel CRB (Customer Reference Board). From the looks of the
-code, it was never ready for production as only engineering sample
-CPUIDs are supported.
-
-Intel Icelake code will be removed following 4.19 and any maintenance
-will be done on the 4.19 branch. This consists of the Intel Icelake SoC
-and Intel Icelake RVP mainboard.
-
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-failed. Also, the only user of this platform ever was the Galileo
-board.
-
-Thus, to reduce the maintenance overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.18 to the 4.19 release
---------------------------------------------
-
-- Total Commits: 1608
-- Average Commits per day: 17.39
-- Total lines added: 93786
-- Average lines added per commit: 58.32
-- Number of patches adding more than 100 lines: 80
-- Average lines added per small commit: 38.54
-- Total lines removed: 768014
-- Total difference between added and removed: -674228
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-
-| #   | Subject                                                         |
-|-----|-----------------------------------------------------------------|
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-| 446 | Optiplex 9010 No Post                                           |
-| 445 | Thinkpad X200 wifi issue                                        |
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-| 427 | x200: Two battery charging issues                               |
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-| 412 | x230 reboots on suspend                                         |
-| 393 | T500 restarts rather than waking up from suspend                |
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |

Documentation/releases/coreboot-4.20-relnotes.md

@@ -1,67 +0,0 @@
-Upcoming release - coreboot 4.20
-========================================================================
-
-The 4.20 release is planned for the 20th of April 2023.
-
-
-The 4.21 release is planned for around the 17th of July, 2023
-
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-* This document may also be edited at the google doc copy:
-  https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
-
-Significant or interesting changes
-----------------------------------
-
-### Add changes that need a full description here
-
-
-
-Additional coreboot changes
----------------------------
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-have so far failed.  The only user of this SoC ever was the Galileo
-board.
-
-Thus, to reduce the maintanence overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.19 to the 4.20 release
---------------------------------------------
-
-* To be filled in immediately before the release by the release team
-
-
-Significant Known and Open Issues
----------------------------------
-
-* To be filled in immediately before the release by the release team
-

Documentation/releases/coreboot-4.6-relnotes.md

@@ -55,15 +55,15 @@ is here: https://github.com/siro20/coreboot/tree/cbui/payloads/cbui
 
 ### UEFI support: A long road to go
 
-coreboot can be used with the edk2 UEFI implementation which
+coreboot can be used with the Tianocore EDK2 UEFI implementation which
 is open source and available at Github. Sadly it is not currently
 integrated into the coreboot build. This has several reasons:
 
-* edk2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
-* Incompatibilities with code inside the edk2 which has not been updated.
+* EDK2 only supports GCC 4.8 profile. coreboot is now running on GCC 6.3.0.
+* Incompatibilities with code inside the EDK2 which has not been updated.
 
 We started to make progress with the integration into our sources and
-the hope is that by the end of the summer, we finally support the edk2
+the hope is that by the end of the summer, we finally support the EDK2
 payload out-of-the- box. See the current patch state at
 http://review.coreboot.org/#/c/15057/
 

Documentation/releases/coreboot-4.7-relnotes.md

@@ -84,7 +84,7 @@ General changes
 
 * Integrate me_cleaner
 * Add flashconsole implementation
-* Build edk2 UEFI payload from upstream source
+* Build Tianocore UEFI payload from upstream source
 * Remove CMOS NVRAM configurable baud rates
 * A common mrc_cache driver to store romstage settings in SPI flash
 

Documentation/releases/coreboot-4.8.1-relnotes.md

@@ -71,7 +71,7 @@ detection
 Payloads
 --------
 * Bumped SeaBIOS to 1.11.1
-* Improved edk2 integration
+* Improved TianoCore integration
 
 Security
 --------

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.20 - April 2023](coreboot-4.20-relnotes.md)
+* [4.18 - Aug 2022](coreboot-4.18-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,10 +15,8 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.19 - January 2023](coreboot-4.19-relnotes.md)
-* [4.18 - October 2022](coreboot-4.18-relnotes.md)
 * [4.17 - May 2022](coreboot-4.17-relnotes.md)
-* [4.16 - February 2022](coreboot-4.16-relnotes.md)
+* [4.16 - Feb 2022](coreboot-4.16-relnotes.md)
 * [4.15 - November 2021](coreboot-4.15-relnotes.md)
 * [4.14 - May 2021](coreboot-4.14-relnotes.md)
 * [4.13 - November 2020](coreboot-4.13-relnotes.md)

Documentation/security/vboot/list_vboot.md

@@ -1,7 +1,6 @@
 # vboot-enabled devices
 
 ## AMD
-- Birman
 - Chausie
 - Majolica
 
@@ -36,6 +35,7 @@
 - Anahera4ES
 - Brask
 - Brya 0
+- Brya4ES
 - Felwinter
 - Gimble
 - Gimble4ES
@@ -46,8 +46,6 @@
 - Primus4ES
 - Redrix
 - Redrix4ES
-- Skolas
-- Skolas4ES
 - Taeko
 - Taeko4ES
 - Taniks
@@ -57,26 +55,12 @@
 - Crota
 - Moli
 - Kinox
-- Craask
-- Osiris
-- Mithrax
-- Kuldax
-- Joxer
-- Pujjo
-- Xivu
-- Gaelin4ADL
-- Yaviks
-- Lisbon
-- Zydron
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
 - Tomato
 - Kingler
-- Steelix
 - Krabby
-- Tentacruel
-- Magikarp
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -88,6 +72,7 @@
 - Terra (ASUS Chromebook C202SA/C300SA/C301SA)
 - Ultima (Lenovo Yoga 11e G3)
 - Wizpig
+- Daisy (Samsung Chromebook (2012))
 - Drallion
 - Eve (Google Pixelbook)
 - Fizz
@@ -95,7 +80,6 @@
 - Endeavour
 - Foster
 - Gale (Google WiFi)
-- Geralt
 - Asuka (Dell Chromebook 13 3380)
 - Caroline (Samsung Chromebook Pro)
 - Cave (Asus Chromebook Flip C302SA)
@@ -113,25 +97,34 @@
 - Nipperkin
 - Dewatt
 - Akemi (IdeaPad Flex 5/5i Chromebook)
+- Ambassador
+- Dooly
 - Dratini (HP Pro c640 Chromebook)
+- Duffy Legacy (32MB)
+- Duffy (ASUS Chromebox 4)
+- Faffy (ASUS Fanless Chromebox)
+- Genesis
 - Hatch
 - Helios (ASUS Chromebook Flip C436FA)
 - Helios_Diskswap
 - Jinlon (HP Elite c1030 Chromebook)
+- Kaisa Legacy (32MB)
+- Kaisa (Acer Chromebox CXI4)
 - Kindred (Acer Chromebook 712)
 - Kohaku (Samsung Galaxy Chromebook)
+- Moonbuggy
 - Mushu
 - Nightfury (Samsung Galaxy Chromebook 2)
+- Noibat (HP Chromebox G3)
 - Palkia
+- Puff
+- Scout
+- Wyvern (CTL Chromebox CBx2)
 - Herobrine
 - Herobrine_Rev0
 - Senor
 - Piglin
 - Hoglin
-- Villager
-- Evoker
-- Zoglin
-- Zombie
 - Guado (ASUS Chromebox CN62)
 - Jecht
 - Rikku (Acer Chromebox CXI2)
@@ -171,26 +164,14 @@
 - Elm (Acer Chromebook R13)
 - Hana (Lenovo N23 Yoga Chromebook)
 - Parrot (Acer C7/C710 Chromebook)
+- Peach Pit (Samsung Chromebook 2 11\")
 - Atlas (Google Pixelbook Go)
 - Poppy
 - Nami
 - Nautilus (Samsung Chromebook Plus V2, V2 LTE)
 - Nocturne (Google Pixel Slate)
-- Rammus
+- Rammus (Asus Chromebook C425, Flip C433, Flip C434)
 - Soraka (HP Chromebook x2)
-- Ambassador
-- Dooly
-- Duffy Legacy (32MB)
-- Duffy (ASUS Chromebox 4)
-- Faffy (ASUS Fanless Chromebox)
-- Genesis
-- Kaisa Legacy (32MB)
-- Kaisa (Acer Chromebox CXI4)
-- Moonbuggy
-- Noibat (HP Chromebox G3)
-- Puff
-- Scout
-- Wyvern (CTL Chromebox CBx2)
 - Banjo (Acer Chromebook 15 (CB3-531))
 - Candy (Dell Chromebook 11 3120)
 - Clapper (Lenovo N20 Chromebook)
@@ -212,13 +193,8 @@
 - Sand (Acer Chromebook 15 CB515-1HT/1H)
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
-- Rex 0
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
-- Skyrim
-- Winterhold
-- Morthal
-- Frostflow
 - Falco (HP Chromebook 14)
 - Leon (Toshiba Chromebook)
 - Peppy (Acer C720/C720P Chromebook)
@@ -246,25 +222,6 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Delbin (ASUS Chromebook Flip CX5)
-- Eldrid
-- Halvor
-- Lindar
-- Malefor
-- Terrador
-- Todor
-- Trondo
-- Volteer
-- Volteer2
-- Volteer2_Ti50
-- Voxel (Acer Chromebook Spin 713 (CP713-3W))
-- Elemi (HP Pro c640 G2 Chromebook)
-- Voema
-- Drobit (ASUS Chromebook CX9400)
-- Copano (ASUS Chromebook Flip CX5400)
-- Collis
-- Volet
-- Chronicler
 - Dalboz
 - Vilboz (Lenovo 100e/300e Gen3 AMD)
 - Ezkinil (Acer Chromebook Spin 514)
@@ -277,7 +234,6 @@
 - Gumboz (HP Chromebook x360 14a)
 
 ## HP
-- Z220 CMT Workstation
 - Z220 SFF Workstation
 
 ## Intel
@@ -288,7 +244,6 @@
 - Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
-- Raptorlake silicon with Alderlake-P RVP and Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
 - Coffeelake H SO-DIMM DDR4 RVP11
@@ -315,8 +270,6 @@
 - Whitetip Mountain 2 CRB
 
 ## Lenovo
-- ThinkPad T440p
-- ThinkPad W541
 - ThinkPad T400
 - ThinkPad T500
 - ThinkPad R400
@@ -328,6 +281,7 @@
 - ThinkPad T430
 - ThinkPad T430s
 - ThinkPad T431s
+- ThinkPad T440p
 - ThinkPad T520
 - ThinkPad W520
 - ThinkPad T530
@@ -345,9 +299,6 @@
 - ThinkPad X230s
 - ThinkPad X60 / X60s / X60t
 
-## MSI
-- PRO Z690-A WIFI DDR4
-
 ## OpenCellular
 - Elgon (GBCv2)
 
@@ -362,11 +313,6 @@
 - MC APL4
 - MC APL5
 - MC APL6
-- MC APL7
-
-## Star Labs
-- Star Labs Lite Mk III (N5000)
-- Star Labs Lite Mk IV (N5030)
 
 ## Supermicro
 - X11SSH-TF

Documentation/soc/amd/psp_integration.md

@@ -117,23 +117,14 @@ implementations currently use combo tables.
 +--------------+---------------+------------------+----------------------------+
 | Size         | 0x04          | 32               | Size of PSP entry in bytes |
 +--------------+---------------+------------------+----------------------------+
-| Location /   | 0x08          | 62               | Location: Physical Address |
+| Location /   | 0x08          | 64               | Location: Physical Address |
 | Value        |               |                  | of SPIROM location where   |
 |              |               |                  | corresponding PSP entry    |
 |              |               |                  | located.                   |
 |              |               |                  |                            |
-|              |               |                  | Value: 62-bit value for the|
+|              |               |                  | Value: 64-bit value for the|
 |              |               |                  | PSP Entry                  |
 +--------------+---------------+------------------+----------------------------+
-| Address Mode | 0x0F[7:6]     | 2                | 00: x86 Physical address   |
-|              |               |                  | 01: offset from start of   |
-|              |               |                  |     BIOS (flash offset)    |
-|              |               |                  | 02: offset from start of   |
-|              |               |                  |     directory header       |
-|              |               |                  | 03: offset from start of   |
-|              |               |                  |     partition              |
-+--------------+---------------+------------------+----------------------------+
-
 ```
 ### PSP Directory Table Types
 
@@ -181,10 +172,6 @@ implementations currently use combo tables.
 *   Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
     This is mandatory in order to support encrypted firmware.
 
-**0x22**: PSP Token Unlock data
-*   Used to support time-bound Secure Debug unlock during boot.  This entry may
-    be omitted if the Token Unlock debug feature is not required.
-
 **0x24**: Security policy binary
 *   A security policy is applied to restrict the untrusted access to security
     sensitive regions.
@@ -213,6 +200,10 @@ implementations currently use combo tables.
 **0x52**: PSP boot loader usermode OEM application
 *   Supported only in certain SKUs.
 
+**0x22**: PSP Token Unlock data
+*   Used to support time-bound Secure Debug unlock during boot.  This entry may
+    be omitted if the Token Unlock debug feature is not required.
+
 ### Firmware Version of Binaries
 
 Every firmware binary contains 256 bytes of a PSP Header, which includes
@@ -311,25 +302,15 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
 +--------------+---------------+------------------+----------------------------+
 | SubProgram   | 0x03[2:0]     | 3                | Specify the SubProgram     |
 +--------------+---------------+------------------+----------------------------+
-| RomId        | 0x03[4:3]     | 2                | Which SPI device the       |
-|              |               |                  | content is placed in       |
-+--------------+---------------+------------------+----------------------------+
-| Writeable    | 0x03[5]       | 1                | Region is writable or read |
-|              |               |                  | only                       |
-+--------------+---------------+------------------+----------------------------+
-| Reserved     | 0x03[7:6]     | 2                | Reserved - Set to zero     |
+| Reserved     | 0x03[7:3]     | 5                | Reserved - Set to zero     |
 +--------------+---------------+------------------+----------------------------+
 | Size         | 0x04          | 32               | Memory Region Size         |
 +--------------+---------------+------------------+----------------------------+
-| Source       | 0x08          | 62               | Physical Address of SPIROM |
+| Source       | 0x08          | 64               | Physical Address of SPIROM |
 | Address      |               |                  | location where the data for|
 |              |               |                  | the corresponding entry is |
 |              |               |                  | located                    |
 +--------------+---------------+------------------+----------------------------+
-| Entry Address| 0x0F[7:6]     | 2                | Same as Entry Address Mode |
-| Mode         |               |                  | in PSP directory table     |
-|              |               |                  | entry fields               |
-+--------------+---------------+------------------+----------------------------+
 | Destination  | 0x10          | 64               | Destination Address of     |
 | Address      |               |                  | memory location where the  |
 |              |               |                  | data for the corresponding |

Documentation/technotes/console.md

@@ -1,66 +0,0 @@
-# coreboot Console
-
-coreboot supports multiple ways to access its console.
-https://www.coreboot.org/Console_and_outputs
-
-
-## SMBus Console
-
-SMBus is a two-wire interface which is based on the principles of
-operation of I2C. SMBus, was first was designed to allow a battery to
-communicate with the charger, the system host, and/or other
-power-related components in the system.
-
-Enable the SMBus console with `CONSOLE_I2C_SMBUS` Kconfig. Set
-`CONSOLE_I2C_SMBUS_SLAVE_ADDRESS` and
-`CONSOLE_I2C_SMBUS_SLAVE_DATA_REGISTER` configuration values of the
-slave I2C device which you will use to capture I2C packets.
-
-Modern computer Random Access Memory (RAM) slot has SMBus in it
-according to the JEDEC standards. We can use a breakout-board to expose
-those SMBus pins. Some mainboard have SMBus pins in the PCIe slot as
-well.
-
-This feature has been tested on the following platforms:
-```eval_rst
-+------------------------------------+
-| Tested platforms                   |
-+====================================+
-| GA-H61M-S2PV + Intel Ivy Bridge    |
-+---------------------+---------------
-```
-
-A minimal DDR3 DIMM breakout board PCB design with only the
-SDA(Data line) and SCL(Clock line) pins of I2C/SMBus can be found
-[here](https://github.com/drac98/ram-breakout-board).
-See the PCB layout [here](https://archive.org/details/ddr3-dimm-F_Cu)
-
-NOTE:
-To capture the I2C packets, an I2C slave device is required. The easiest
-way to capture the log message is to use a I2C to UART converter chip
-with a UART to USB converter chip. The setup would be as follows.
-```text
-+---------+    +-------------+    +-------------+
-+   PC    +----+ UART to USB +----+ I2C to UART |
-+---------+    +-------------+    +-------------+
-                                              | |
-------------------------------------------------+--  System Management
-----------------------------------------------+----  Bus
-```
-
-Watch this [video](https://youtu.be/Q0dK41n9db8) to see how it is set
-up. A backup of the video is available
-[here](https://web.archive.org/web/20220916172605/https://www.youtube.com/watch?v=Q0dK41n9db8)
-
-If you are using any of the `SC16IS740/750/760` I2C to UART converter
-chip, you can enable the `SC16IS7XX_INIT` option to initialize the chip.
-
-If not we can use other I2C slave devices like an Arduino or a
-Beagleboard.
-* [Linux I2C Slave interface](https://web.archive.org/web/20220926173943/https://www.kernel.org/doc/html/latest/i2c/slave-interface.html)
-* [BeagleBone Black I2C Slave](https://web.archive.org/web/20220926171211/https://forum.beagleboard.org/t/beaglebone-black-and-arduino-uno-i2c-communication-using-c/29990/8)
-
-This feature was added as part of a GSoC 2022 project. Checkout the
-following blog posts for more details.
-* [coreboot Console via SMBus — Part I](https://medium.com/@husnifaiz/coreboot-console-via-smbus-introduction-38273691a8ac)
-* [coreboot Console via SMBus — Part II](https://medium.com/@husnifaiz/coreboot-console-via-smbus-part-ii-bc324fdd2f24)

Documentation/technotes/index.md

@@ -5,4 +5,3 @@
 * [Unit testing coreboot](2020-03-unit-testing-coreboot.md)
 * [Unit Test Code Coverage](2021-05-code-coverage.md)
 * [Address Sanitizer](asan.md)
-* [coreboot Consoles](console.md)

Documentation/tutorial/flashing_firmware/ext_standalone.md

@@ -19,45 +19,5 @@ It is possible to set the onboard flash on hold and use another flash chip.
 Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC
 low, and /HOLD of your replacement flash IC high.
 
-### SPI header
-Some boards feature a pin header which is connected to the SPI bus. This can
-also be used to connect a secondary flash chip.
-
-#### HP boards
-Many HP desktop mainboards have a 2x8 or 2x10 block of header pins which
-can be used to connect a second flash chip. One pin is connected to the
-onboard flash's /CS pin, and another is connected to the chipset's /CS
-pin. Normally a jumper cap is placed between these pins, allowing the
-chipset to access the onboard flash. To use this header, remove this
-jumper and connect all lines except /CS one-to-one with the
-corresponding pin on the header. The secondary flash chip's /CS line
-should be connected to the chipset /CS pin on the header. By doing this
-the secondary SPI flash, rather than the onboard flash, will respond to
-accesses from the chipset.
-
-![][hp_spi_header_pinout]
-
-![][hp_spi_header_mainboard]
-
-Note that on boards where this header is unpopulated, a jumper resistor
-will be populated nearby which serves the purpose of the jumper cap. One
-end should have continuity with the /CS pin on the flash, and the other
-end should have continuity with the chipset /CS pin on the unpopulated
-header. It may also be possible to find this resistor through visual
-inspection of the traces on the /CS pins. This resistor should be
-desoldered if you wish to solder a pin header to the board and connect a
-secondary flash, otherwise the onboard flash will always respond to
-accesses.
-
-#### Other boards
-Other boards may have similar headers, but will likely use a different
-pinout than the ones explicitly mentioned here. Usually such a header
-will be located near the onboard SPI flash. If schematics are available,
-the pinout for the header will likely be found in it, but it could also
-be determined using a multimeter in continuity mode to map out the
-connections between the SPI flash and the header.
-
 
 [EM100Pro]: https://www.dediprog.com/product/EM100Pro
-[hp_spi_header_pinout]: hp_spi_header.svg
-[hp_spi_header_mainboard]: hp_spi_header_mb.jpg

Documentation/tutorial/flashing_firmware/hp_spi_header.svg

@@ -1,109 +0,0 @@
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-       y="16.285427"
-       id="text738"><tspan
-         id="tspan736"
-         x="22.770041"
-         y="16.285427">DO</tspan></text>
-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
-       x="13.605446"
-       y="16.286804"
-       id="text742"><tspan
-         id="tspan740"
-         x="13.605446"
-         y="16.286804">DI</tspan></text>
-    <text
-       xml:space="preserve"
-       font-size="2.82222px"
-       style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal"
-       x="2.5204566"
-       y="6.1998558"
-       id="text746"><tspan
-         id="tspan744"
-         x="2.5204566"
-         y="6.1998558">/CS</tspan></text>
-    <text
-       xml:space="preserve"
-       font-size="2.5px"
-       style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal"
-       x="5.0321894"
-       y="14.500522"
-       id="text750"><tspan
-         id="tspan748"
-         x="5.0321894"
-         y="14.500522">/CS</tspan><tspan
-         x="5.0321894"
-         y="17.146358"
-         id="tspan752">chipset</tspan></text>
-  </g>
-</svg>

Documentation/tutorial/part3.md

@@ -23,10 +23,10 @@ though TDD has a different work flow of building tests first, followed
 by the code that satisfies them, the process of writing tests and adding
 them to the tree is the same.
 
-## Analysis of unit under test
-First of all, it is necessary to precisely establish what we want to
-test in a particular module. Usually this will be an externally exposed
-API, which can be used by other modules.
+## Analysis of unit under test First of all, it is necessary to
+precisely establish what we want to test in a particular module. Usually
+this will be an externally exposed API, which can be used by other
+modules.
 
 ```eval_rst
 .. admonition:: i2c-test example

Documentation/util/ifdtool/layout.md

@@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 +------------+------------------+-----------+-------------------------------------------+
 | 4          | Platform Data    | SI_PDR    |                                           |
 +------------+------------------+-----------+-------------------------------------------+
-| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this     |
+| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this    |
 |            |                  |           | region; EC firmware is stored in BIOS     |
 |            |                  |           | region of flash                           |
 +------------+------------------+-----------+-------------------------------------------+

LICENSES/BSD-2-Clause-Patent.txt

@@ -1,49 +0,0 @@
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
-  notice, this list of conditions and the following disclaimer.
-
-2. Redistributions in binary form must reproduce the above copyright
-  notice, this list of conditions and the following disclaimer in the
-  documentation and/or other materials provided with the distribution.
-
-Subject to the terms and conditions of this license, each copyright
-holder and contributor hereby grants to those receiving rights under
-this license a perpetual, worldwide, non-exclusive, no-charge,
-royalty-free, irrevocable (except for failure to satisfy the conditions
-of this license) patent license to make, have made, use, offer to sell,
-sell, import, and otherwise transfer this software, where such license
-applies only to those patent claims, already acquired or hereafter
-acquired, licensable by such copyright holder or contributor that are
-necessarily infringed by:
-
-(a) their Contribution(s) (the licensed copyrights of copyright holders
-   and non-copyrightable additions of contributors, in source or binary
-   form) alone;
-or
-(b) combination of their Contribution(s) with the work of authorship to
-   which such Contribution(s) was added by such copyright holder or
-   contributor, if, at the time the Contribution is added, such addition
-   causes such combination to be necessarily infringed. The patent
-   license shall not apply to any other combinations which include the
-   Contribution.
-
-Except as expressly stated above, no rights or licenses from any
-copyright holder or contributor is granted under this license, whether
-expressly, by implication, estoppel or otherwise.
-
-DISCLAIMER
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/BSD-2-Clause.txt

@@ -1,23 +0,0 @@
-Copyright (c) <year> <owner>.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/BSD-4-Clause-UC.txt

@@ -1,31 +0,0 @@
-Copyright [various years] The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:
-
-1. Redistributions of source code must retain the above copyright
-   notice, this list of conditions and the following disclaimer.
-2. Redistributions in binary form must reproduce the above copyright
-   notice, this list of conditions and the following disclaimer in the
-   documentation and/or other materials provided with the distribution.
-3. All advertising materials mentioning features or use of this software
-   must display the following acknowledgement: This product includes
-   software developed by the University of California, Berkeley and its
-   contributors.
-4. Neither the name of the University nor the names of its contributors
-   may be used to endorse or promote products derived from this software
-   without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ''AS IS'' AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
-THE POSSIBILITY OF SUCH DAMAGE.

LICENSES/CC-PDDC.txt

@@ -1,28 +0,0 @@
-The person or persons who have associated work with this document (the
-"Dedicator" or "Certifier") hereby either (a) certifies that, to the
-best of his knowledge, the work of authorship identified is in the
-public domain of the country from which the work is published, or (b)
-hereby dedicates whatever copyright the dedicators holds in the work of
-authorship identified below (the "Work") to the public domain. A
-certifier, moreover, dedicates any copyright interest he may have in the
-associated work, and for these purposes, is described as a "dedicator"
-below.
-
-A certifier has taken reasonable steps to verify the copyright status of
-this work. Certifier recognizes that his good faith efforts may not
-shield him from liability if in fact the work certified is not in the
-public domain.
-
-Dedicator makes this dedication for the benefit of the public at large
-and to the detriment of the Dedicator's heirs and successors. Dedicator
-intends this dedication to be an overt act of relinquishment in
-perpetuity of all present and future rights under copyright law, whether
-vested or contingent, in the Work. Dedicator understands that such
-relinquishment of all rights includes the relinquishment of all rights
-to enforce (by lawsuit or otherwise) those copyrights in the Work.
-
-Dedicator recognizes that, once placed in the public domain, the Work
-may be freely reproduced, distributed, transmitted, used, modified,
-built upon, or otherwise exploited by anyone for any purpose, commercial
-or non-commercial, and in any way, including by methods that have not
-yet been invented or conceived.

LICENSES/HPND-sell-variant.txt

@@ -1,18 +0,0 @@
-Permission to use, copy, modify, distribute, and sell this software and
-its documentation for any purpose is hereby granted without fee,
-provided that the above copyright notice appears in all copies, and that
-both that the copyright notice and this permission notice appear in
-supporting documentation, and that the name of <copyright holder> <or
-related entities> not be used in advertising or publicity pertaining to
-distribution of the software without specific, written prior permission
-. <copyright holder> makes no representations about the suitability of
-this software for any purpose. It is provided "as is" without express or
-implied warranty.
-
-<copyright holder> DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
-SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS . IN NO EVENT SHALL <copyright holder> BE LIABLE FOR ANY
-SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
-RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF
-CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSES/HPND.txt

@@ -1,20 +0,0 @@
-<copyright notice>
-
-Permission to use, copy, modify and distribute this software and its
-documentation for any purpose and without fee is hereby granted,
-provided that the above copyright notice appear in all copies, and that
-both that the copyright notice and this permission notice appear in
-supporting documentation , and that the name of <copyright holder> <or
-related entities> not be used in advertising or publicity pertaining to
-distribution of the software without specific, written prior permission.
-<copyright holder> makes no representations about the suitability of
-this software for any purpose. It is provided "as is" without express or
-implied warranty.
-
-<copyright holder> DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS
-SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND
-FITNESS . IN NO EVENT SHALL <copyright holder> BE LIABLE FOR ANY
-SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
-RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF
-CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
-CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

LICENSES/exceptions/GCC-exception-3.1.txt

@@ -1,74 +0,0 @@
-GCC RUNTIME LIBRARY EXCEPTION
-
-Version 3.1, 31 March 2009
-
-General information: http://www.gnu.org/licenses/gcc-exception.html
-
-Copyright (C) 2009 Free Software Foundation, Inc. <http://fsf.org/>
-
-Everyone is permitted to copy and distribute verbatim copies of this
-license document, but changing it is not allowed.
-
-This GCC Runtime Library Exception ("Exception") is an additional
-permission under section 7 of the GNU General Public License, version 3
-("GPLv3"). It applies to a given file (the "Runtime Library") that bears
-a notice placed by the copyright holder of the file stating that the
-file is governed by GPLv3 along with this Exception.
-
-When you use GCC to compile a program, GCC may combine portions of
-certain GCC header files and runtime libraries with the compiled
-program. The purpose of this Exception is to allow compilation of
-non-GPL (including proprietary) programs to use, in this way, the header
-files and runtime libraries covered by this Exception.
-
-0. Definitions.
-
-  A file is an "Independent Module" if it either requires the Runtime
-  Library for execution after a Compilation Process, or makes use of an
-  interface provided by the Runtime Library, but is not otherwise based
-  on the Runtime Library.
-
-  "GCC" means a version of the GNU Compiler Collection, with or without
-  modifications, governed by version 3 (or a specified later version) of
-  the GNU General Public License (GPL) with the option of using any
-  subsequent versions published by the FSF.
-
-  "GPL-compatible Software" is software whose conditions of propagation,
-  modification and use would permit combination with GCC in accord with
-  the license of GCC.
-
-  "Target Code" refers to output from any compiler for a real or virtual
-  target processor architecture, in executable form or suitable for
-  input to an assembler, loader, linker and/or execution phase.
-  Notwithstanding that, Target Code does not include data in any format
-  that is used as a compiler intermediate representation, or used for
-  producing a compiler intermediate representation.
-
-  The "Compilation Process" transforms code entirely represented in
-  non-intermediate languages designed for human-written code, and/or in
-  Java Virtual Machine byte code, into Target Code. Thus, for example,
-  use of source code generators and preprocessors need not be considered
-  part of the Compilation Process, since the Compilation Process can be
-  understood as starting with the output of the generators or
-  preprocessors.
-
-  A Compilation Process is "Eligible" if it is done using GCC, alone or
-  with other GPL-compatible software, or if it is done without using any
-  work based on GCC. For example, using non-GPL-compatible Software to
-  optimize any GCC intermediate representations would not qualify as an
-  Eligible Compilation Process.
-
-1. Grant of Additional Permission.
-
-   You have permission to propagate a work of Target Code formed by
-   combining the Runtime Library with Independent Modules, even if such
-   propagation would otherwise violate the terms of GPLv3, provided that
-   all Target Code was generated by Eligible Compilation Processes. You
-   may then convey such a combination under terms of your choice,
-   consistent with the licensing of the Independent Modules.
-
-2. No Weakening of GCC Copyleft.
-
-  The availability of this Exception does not imply any general
-  presumption that third-party software is unaffected by the copyleft
-  requirements of the license of GCC.

LICENSES/exceptions/Linux-syscall-note.txt

@@ -1,12 +0,0 @@
-NOTE! This copyright does *not* cover user programs that use kernel
-services by normal system calls - this is merely considered normal use
-of the kernel, and does *not* fall under the heading of "derived work".
-Also note that the GPL below is copyrighted by the Free Software
-Foundation, but the instance of code that it refers to (the Linux
-kernel) is copyrighted by me and others who actually wrote it.
-
-Also note that the only valid version of the GPL as far as the kernel is
-concerned is _this_ particular version of the license (ie v2, not v2.2
-or v3.x or whatever), unless explicitly otherwise stated.
-
-Linus Torvalds

MAINTAINERS

@@ -14,17 +14,27 @@ Please try to follow the guidelines below.  This will make things
 easier on the maintainers.  Not all of these guidelines matter for every
 trivial patch so apply some common sense.
 
+1.	Always _test_ your changes, however small, on at least 1 or
+	2 people, preferably many more.
 
-1.	Make sure your changes compile correctly in multiple configurations. In
-	particular check that changes work for various boards in the tree that
-	it affects:
+2.	Try to release a few ALPHA test versions to gerrit. Announce
+	them onto the coreboot mailing list and IRC channel and await
+	results. This is especially important on coreboot core changes,
+	but also for device drivers, because often that's the only way
+	you will find things like the fact revision 3 chipset needs
+	a magic fix you didn't know about, or some clown changed the
+	chips on a board and not its name.  (Don't laugh!)
 
-	Test with: `util/abuild/abuild -c $(nproc) -t vendor/boardname`
+3.	Make sure your changes compile correctly in multiple
+	configurations. In particular check that changes work for all
+	boards in the tree (use abuild!)
 
-2.	When you are happy with a change make it generally available for
+4.	When you are happy with a change make it generally available for
 	testing in gerrit and await feedback.
 
-3.	Be prepared to get your changes sent back with seemingly
+5.	Make your patch available through coreboot's gerrit code review
+	system, and add the relevant maintainer from this list as a code
+	reviewer. Be prepared to get your changes sent back with seemingly
 	silly requests about formatting and variable names.  These aren't
 	as silly as they seem. One job the maintainers do is to keep
 	things looking the same.  Sometimes this means that the clever
@@ -35,27 +45,36 @@ trivial patch so apply some common sense.
 	(util/lint/checkpatch.pl) to catch trival style violations.
 	See https://www.coreboot.org/Coding_Style for guidance here.
 
+	PLEASE add the maintainers that are generated by
+	util/scripts/get_maintainer.pl as reviewers.  The results returned
+	by the script will be best if you have git installed and are
+	making your changes in a branch derived from coreboot.org's latest
+	git tree.
+
+	PLEASE try to include any credit lines you want added with the
+	patch. It avoids people being missed off by mistake and makes
+	it easier to know who wants adding and who doesn't.
+
 	PLEASE document known bugs. If it doesn't work for everything
 	or does something very odd once a month document it.
 
-	ALWAYS remember that submissions are made under the terms
+	PLEASE remember that submissions must be made under the terms
 	of the OSDL certificate of contribution and should include a
 	Signed-off-by: line.  The current version of this "Developer's
 	Certificate of Origin" (DCO) is listed at
 	https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure.
 
-4.	Make sure you have the right to send any changes you make. If you
+6.	Make sure you have the right to send any changes you make. If you
 	do changes at work you may find your employer owns the patch
 	not you.
 
-5.	Happy hacking.
+7.	Happy hacking.
 
 Descriptions of section entries:
 
 	M: Maintainer: FullName <address@domain>
 	   Must be registered to Gerrit (https://review.coreboot.org/).
-	   Should have experience with upstream coreboot development and
-	   +2 rights.
+	   Should have experience with upstream coreboot development.
 	R: Designated reviewer: FullName <address@domain>
 	   These reviewers should be CCed on patches.
 	L: Mailing list that is relevant to this area
@@ -118,57 +137,15 @@ Maintainers List (try to look for most precise areas first)
 # Mainboards
 ################################################################################
 
-51NB MAINBOARDS
-S:	Orphan
-F:	src/mainboard/51nb/
-
-
-
-ACER MAINBOARDS
-S:	Orphan
-F:	src/mainboard/acer/
-
-
-
-ADLINK MAINBOARDS
-S:	Orphan
-F:	src/mainboard/adlink/
-
-
-
 AMD family 17h and 19h reference boards
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
-F:	src/mainboard/amd/bilby/
-F:	src/mainboard/amd/birman/
 F:	src/mainboard/amd/chausie/
 F:	src/mainboard/amd/majolica/
 F:	src/mainboard/amd/mandolin/
-F:	src/mainboard/amd/mayan/
-
-AMD reference boards outside of family 17h and 19h
-S:	Odd Fixes
-L:	amd_coreboot_org_changes@googlegroups.com
-F:	src/mainboard/amd/gardenia/
-F:	src/mainboard/amd/inagua/
-F:	src/mainboard/amd/olivehill/
-F:	src/mainboard/amd/pademelon/
-F:	src/mainboard/amd/parmer/
-F:	src/mainboard/amd/persimmon/
-F:	src/mainboard/amd/south_station/
-F:	src/mainboard/amd/thatcher/
-F:	src/mainboard/amd/union_station/
-
-
-
-AOPEN MAINBOARDS
-S:	Orphan
-F:	src/mainboard/aopen/
-
-
 
 APPLE MAINBOARDS
 M:	Evgeny Zinoviev <me@ch1p.io>
@@ -187,6 +164,11 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/asrock/g41c-gs/
 
+ASROCK H81M-HDS MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/asrock/h81m-hds/
+
 
 
 ASUS A88XM-E MAINBOARD
@@ -201,9 +183,15 @@ F:	src/mainboard/asus/am1i-a/
 
 ASUS H61 SERIES MAINBOARDS
 M:	Angel Pons <th3fanbus@gmail.com>
+M:	Tristan Corrick <tristan@corrick.kiwi>
 S:	Maintained
 F:	src/mainboard/asus/h61-series/
 
+ASUS MAXIMUS IV GENE-Z MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/asus/maximus_iv_gene-z/
+
 ASUS P5QC PRO MAINBOARD & VARIANTS
 M:	Angel Pons <th3fanbus@gmail.com>
 R:	Stefan Ott <coreboot@desire.ch>
@@ -223,30 +211,6 @@ F:	src/mainboard/asus/p8z77-series/
 
 
 
-BAP MAINBOARDS
-S:	Orphan
-F:	src/mainboard/bap/
-
-
-
-BIOSTAR MAINBOARDS
-S:	Orphan
-F:	src/mainboard/biostar/
-
-
-
-BOSTENTECH MAINBOARDS
-S:	Orphan
-F:	src/mainboard/bostentech/
-
-
-
-CAVIUM MAINBOARDS
-S:	Orphan
-F:	src/mainboard/cavium/
-
-
-
 CLEVO MAINBOARDS
 M:	Felix Singer <felixsinger@posteo.net>
 M:	Michael Niewöhner <foss@mniewoehner.de>
@@ -255,36 +219,6 @@ F:	src/mainboard/clevo/
 
 
 
-COMPULAB MAINBOARDS
-S:	Orphan
-F:	src/mainboard/compulab/
-
-
-
-DELL MAINBOARDS
-S:	Orphan
-F:	src/mainboard/dell/
-
-
-
-ELMEX MAINBOARDS
-S:	Orphan
-F:	src/mainboard/elmex/
-
-
-
-EMULATION MAINBOARDS
-S:	Orphan
-F:	src/mainboard/emulation/
-
-
-
-EXAMPLE MAINBOARDS
-S:	Orphan
-F:	src/mainboard/example/
-
-
-
 FACEBOOK FBG1701 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
 M:	Erik van den Bogaert <ebogaert@eltan.com>
@@ -299,54 +233,39 @@ F:	src/mainboard/facebook/monolith/
 
 
 
-FOXCONN MAINBOARDS
-S:	Orphan
-F:	src/mainboard/foxconn/
-
-
-
-GETAC MAINBOARDS
-S:	Orphan
-F:	src/mainboard/getac/
-
-
-
 GIGABYTE GA-D510UD MAINBOARD
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/gigabyte/ga-d510ud/
 
+GIGABYTE GA-G41M-ES2L MAINBOARD
+M:	Damien Zammit <damien@zamaudio.com>
+S:	Odd Fixes
+F:	src/mainboard/gigabyte/ga-g41m-es2l/
+
 GIGABYTE GA-H61M SERIES MAINBOARDS
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/gigabyte/ga-h61m-series/
 
 
-
-GIZMOSPHERE MAINBOARDS
-S:	Orphan
-F:	src/mainboard/gizmosphere/
-
-
-
-GOOGLE REX MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
-M:	Kapil Porwal <kapilporwal@google.com>
-S:	Maintained
-F:	src/mainboard/google/rex/
-
 GOOGLE BRYA MAINBOARDS
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/brya/
 
 GOOGLE HATCH MAINBOARDS
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/hatch/
 
+GOOGLE PANTHER MAINBOARD
+M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
+S:	Supported
+F:	src/mainboard/google/panther/
+
 GOOGLE VOLTEER MAINBOARDS
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 M:	Nick Vaccaro <nvaccaro@chromium.org>
 S:	Maintained
 F:	src/mainboard/google/volteer/
@@ -365,16 +284,6 @@ F:	src/mainboard/google/parrot/
 F:	src/mainboard/google/slippy/
 F:	src/mainboard/google/stout/
 
-GOOGLE AMD-BASED MAINBOARDS
-M:	Martin Roth <martin.roth@amd.corp-partner.google.com>
-M:	Jason Nien <jason.nien@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
-F:	src/mainboard/google/kahlee/
-F:	src/mainboard/google/zork/
-F:	src/mainboard/google/guybrush/
-F:	src/mainboard/google/skyrim/
-
 
 
 HP 280 G2 MAINBOARD
@@ -384,23 +293,23 @@ F:	src/mainboard/hp/280_g2/
 
 
 
-IBASE MAINBOARDS
-S:	Orphan
-F:	src/mainboard/ibase/
-
-
+INTEL D510MO MAINBOARD
+M:	Damien Zammit <damien@zamaudio.com>
+S:	Odd Fixes
+F:	src/mainboard/intel/d510mo/
 
 INTEL HARCUVAR_CRB MAINBOARD
 M:	Jeff Daly <jeffd@silicom-usa.com>
 M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
+M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
+M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
 S:	Maintained
 F:	src/mainboard/intel/harcuvar/
 
-
-
-JETWAY MAINBOARDS
-S:	Orphan
-F:	src/mainboard/jetway/
+INTEL STRAGO MAINBOARD
+M:	Hannah Williams <hannah.williams@intel.com>
+S:	Supported
+F:	/src/mainboard/intel/strago/
 
 
 
@@ -440,7 +349,6 @@ S:	Maintained
 F:	src/mainboard/lenovo/x201/
 
 
-
 LIBRETREND LT1000 MAINBOARD
 M:	Piotr Król <piotr.krol@3mdeb.com>
 M:	Michał Żygowski <michal.zygowski@3mdeb.com>
@@ -449,23 +357,11 @@ F:	src/mainboard/libretrend/lt1000/
 
 
 
-LIPPERT MAINBOARDS (acquired by Adlink)
-S:	Orphan
-F:	src/mainboard/lippert/
-
-
-
 MSI H81M-P33 MAINBOARD
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/msi/h81m-p33/
 
-MSI MS-7D25 MAINBOARDS
-M:	Michał Żygowski <michal.zygowski@3mdeb.com>
-M:	Michał Kopeć <michal.kopec@3mdeb.com>
-S:	Maintained
-F:	src/mainboard/msi/ms7d25/
-
 
 
 OCP DELTALAKE MAINBOARD
@@ -479,6 +375,7 @@ F:	src/mainboard/ocp/deltalake/
 
 OCP TIOGAPASS MAINBOARD
 M:	Jonathan Zhang <jonzhang@fb.com>
+M:	Reddy Chagam <anjaneya.chagam@intel.com>
 M:	Johnny Lin <Johnny_Lin@wiwynn.com>
 M:	Morgan Jang <Morgan_Jang@wiwynn.com>
 M:	Ryback Hung <<Ryback.Hung@quantatw.com>
@@ -504,12 +401,6 @@ F:	src/mainboard/pcengines/
 
 
 
-PINE64 MAINBOARDS
-S:	Orphan
-F:	src/mainboard/pine64/
-
-
-
 PORTWELL PQ-M107 MAINBOARD
 M:	Frans Hendriks <fhendriks@eltan.com>
 M:	Erik van den Bogaert <ebogaert@eltan.com>
@@ -542,24 +433,12 @@ F:	src/mainboard/prodrive/hermes/
 
 
 PURISM MAINBOARDS
-M:	Jonathon Hall <jonathon.hall@puri.sm>
+M:	Matt DeVillier <matt.devillier@puri.sm>
 S:	Supported
 F:	src/mainboard/purism/
 
 
 
-RAZER MAINBOARDS
-S:	Orphan
-F:	src/mainboard/razer/
-
-
-
-RODA MAINBOARDS
-S:	Orphan
-F:	src/mainboard/roda/
-
-
-
 SAMSUNG CHROMEOS MAINBOARDS
 M:	Matt DeVillier <MrChromebox@gmail.com>
 S:	Maintained
@@ -568,18 +447,6 @@ F:	src/mainboard/samsung/stumpy/
 
 
 
-SAPPHIRE MAINBOARDS
-S:	Orphan
-F:	src/mainboard/sapphire/
-
-
-
-SCALEWAY MAINBOARDS
-S:	Orphan
-F:	src/mainboard/scaleway/
-
-
-
 SIEMENS CHILI MAINBAORD
 M:	Felix Singer <felixsinger@posteo.net>
 M:	Nico Huber <nico.h@gmx.de>
@@ -594,12 +461,6 @@ F:	src/mainboard/siemens/mc_ehl/
 
 
 
-SIFIVE MAINBOARDS
-S:	Orphan
-F:	src/mainboard/sifive/
-
-
-
 STAR LABS MAINBOARDS
 M:	Sean Rhodes <sean@starlabs.systems>
 S:	Maintained
@@ -607,13 +468,6 @@ F:	src/mainboard/starlabs/
 
 
 
-SUPERMICRO X11-LGA1151-SERIES
-M:	Michael Niewöhner <foss@mniewoehner.de>
-S:	Maintained
-F:	src/mainboard/supermicro/x11-lga1151-series/
-
-
-
 SYSTEM76 MAINBOARDS
 M:	Jeremy Soller <jeremy@system76.com>
 M:	Tim Crawford <tcrawford@system76.com>
@@ -622,15 +476,15 @@ F:	src/mainboard/system76/
 
 
 
-TI MAINBOARDS
-S:	Orphan
-F:	src/mainboard/ti/
+SUPERMICRO X10SLM+-F MAINBOARD
+M:	Tristan Corrick <tristan@corrick.kiwi>
+S:	Maintained
+F:	src/mainboard/supermicro/x10slm-f/
 
-
-
-UP MAINBOARDS
-S:	Orphan
-F:	src/mainboard/up/
+SUPERMICRO X11-LGA1151-SERIES
+M:	Michael Niewöhner <foss@mniewoehner.de>
+S:	Maintained
+F:	src/mainboard/supermicro/x11-lga1151-series/
 
 ################################################################################
 # Architectures
@@ -666,7 +520,6 @@ F:	src/mainboard/sifive/
 F:	util/riscv/
 
 X86 ARCHITECTURE
-S:	MAINTAINED
 F:	src/arch/x86/
 F:	src/cpu/x86/
 F:	src/drivers/pc80/
@@ -678,10 +531,9 @@ F:	src/include/cpu/x86/
 ################################################################################
 
 CHROME EC
-M:	Boris Mittelberg <bmbm@google.com>
-M:	Caveh Jalali <caveh@chromium.org>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
-F:	src/ec/google/
+F:	src/ec/google/chromeec/
 
 LENOVO EC
 M:	Alexander Couzens <lynxis@fe80.eu>
@@ -699,19 +551,6 @@ M:	Tim Crawford <tcrawford@system76.com>
 S:	Maintained
 F:	src/ec/system76/
 
-ORPHANED ECS
-S:	Orphan
-F:	src/ec/51nb/
-F:	src/ec/acpi/
-F:	src/ec/apple/
-F:	src/ec/compal/
-F:	src/ec/hp/
-F:	src/ec/kontron/
-F:	src/ec/purism/
-F:	src/ec/quanta/
-F:	src/ec/roda/
-F:	src/ec/smsc/
-
 ################################################################################
 # Northbridges
 ################################################################################
@@ -722,6 +561,7 @@ S:	Maintained
 F:	src/northbridge/intel/haswell/
 
 INTEL PINEVIEW CHIPSET
+M:	Damien Zammit <damien@zamaudio.com>
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Odd Fixes
 F:	src/northbridge/intel/pineview/
@@ -732,6 +572,7 @@ S:	Maintained
 F:	src/northbridge/intel/sandybridge/
 
 INTEL X4X CHIPSET
+M:	Damien Zammit <damien@zamaudio.com>
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Odd Fixes
 F:	src/northbridge/intel/x4x/
@@ -741,8 +582,6 @@ F:	src/northbridge/intel/x4x/
 ################################################################################
 
 AMD SUPPORT
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Odd Fixes
 F:	src/vendorcode/amd/
 F:	src/cpu/amd/
 F:	src/northbridge/amd/
@@ -760,7 +599,9 @@ F:	src/drivers/intel/
 F:	src/include/cpu/intel/
 
 INTEL FSP 1.1
+M:	Lee Leahy <leroy.p.leahy@intel.com>
 M:	Huang Jin <huang.jin@intel.com>
+M:	York Yang <york.yang@intel.com>
 S:	Supported
 F:	src/drivers/intel/fsp1_1/
 
@@ -774,80 +615,63 @@ F:	src/drivers/intel/fsp2_0/
 ################################################################################
 
 AMD Cezanne
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/cezanne/
 F:	src/vendorcode/amd/fsp/cezanne/
 
 AMD common SoC code
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Maintained
 F:	src/soc/amd/common/
 
 AMD Picasso
-M:	Felix Held <felix-coreboot@felixheld.de>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Fred Reitberger <reitbergerfred@gmail.com>
-M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Maintained
-F:	src/soc/amd/picasso/
-F:	src/vendorcode/amd/fsp/picasso/
-
-AMD Mendocino
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
 M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
-F:	src/soc/amd/mendocino/
-F:	src/vendorcode/amd/fsp/mendocino/
+S:	Maintained
+F:	src/soc/amd/picasso/
+F:	src/vendorcode/amd/fsp/picasso/
 
-AMD Phoenix
+AMD Sabrina
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
+M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
-S:	Supported
-F:	src/soc/amd/phoenix/
-F:	src/vendorcode/amd/fsp/phoenix/
+S:	Maintained
+F:	src/soc/amd/sabrina/
+F:	src/vendorcode/amd/fsp/sabrina/
 
 AMD Stoneyridge
+M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
-L:	amd_coreboot_org_changes@googlegroups.com
 S:	Odd Fixes
 F:	src/soc/amd/stoneyridge/
 
-INTEL METEORLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
-M:	Kapil Porwal <kapilporwal@google.com>
-S:	Maintained
-F:	src/soc/intel/meteorlake/
-
 INTEL ALDERLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/soc/intel/alderlake/
 
 INTEL APOLLOLAKE_SOC
-M:	Sean Rhodes <sean@starlabs.systems>
-S:	Odd Fixes
+M:	Andrey Petrov <andrey.petrov@gmail.com>
+S:	Maintained
 F:	src/soc/intel/apollolake/
 
 INTEL BRASWELL SOC
@@ -861,6 +685,8 @@ F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
 INTEL DENVERTON-NS SOC
 M:	Jeff Daly <jeffd@silicom-usa.com>
 M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
+M:	Suresh Bellampalli <suresh.bellampalli@intel.com>
+M:	Mariusz Szafranski <mariuszx.szafranski@intel.com>
 S:	Maintained
 F:	src/soc/intel/denverton_ns/
 
@@ -871,13 +697,13 @@ S:	Maintained
 F:	src/soc/intel/elkhartlake/
 
 INTEL TIGERLAKE SOC
-M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <taruntuli@google.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Maintained
 F:	src/soc/intel/tigerlake/
 
 INTEL Xeon Sacalable Processor Family
 M:	Jonathan Zhang <jonzhang@fb.com>
+M:	Reddy Chagam <anjaneya.chagam@intel.com>
 M:	Johnny Lin <Johnny_Lin@wiwynn.com>
 M:	Tim Chu <Tim.Chu@quantatw.com>
 M:	Arthur Heymans <arthur@aheymans.xyz>
@@ -899,7 +725,7 @@ F:	src/soc/mediatek/mt8192/
 F:	src/vendorcode/mediatek/mt8192/
 
 ORPHANED ARM SOCS
-S:	Orphan
+S:	Orphaned
 F:	src/cpu/armltd/
 F:	src/soc/ti/
 F:	src/soc/qualcomm/
@@ -956,10 +782,6 @@ F:	util/xcompile/
 F:	util/genbuild_h/
 
 TOOLCHAIN
-M:	Martin Roth <gaumless@gmail.com>
-M:	Felix Singer <felixsinger@posteo.net>
-M:	Elyes Haouas <ehaouas@noos.fr>
-S:	Supported
 F:	util/crossgcc/
 
 DOCKER
@@ -1016,7 +838,7 @@ F:	src/drivers/aspeed/ast2050/
 
 ACPI
 M:	Lance Zhao <lance.zhao@gmail.com>
-M:	Tim Wawrzynczak <inforichland@gmail.com>
+M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Supported
 F:	src/acpi/
 F:	src/arch/x86/acpi/
@@ -1111,16 +933,6 @@ S:	Maintained
 F:	tests/
 F:	payloads/libpayload/tests/
 
-COREBOOT RELEASES
-M:	Felix Singer <felixsinger@posteo.net>
-M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Angel Pons <th3fanbus@gmail.com>
-M:	Martin Roth <gaumless@gmail.com>
-M:	Matt DeVillier <MrChromebox@gmail.com>
-S:	Maintained
-F:	Documentation/releases/
-F:	util/release/
-
 MISSING: TIMERS / DELAYS
 
 MISSING: TIMESTAMPS
@@ -1157,7 +969,7 @@ MISSING: SPI
 
 CODE OF CONDUCT
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
-M:	Ronald Minnich <rminnich@gmail.com>
+M:	Ronald Minnich <rminnich@coreboot.org>
 M:	Martin Roth <martin@coreboot.org>
 S:	Maintained
 F:	Documentation/community/code_of_conduct.md

Makefile

@@ -38,11 +38,6 @@ COREBOOT_EXPORTS += KCONFIG_DEPENDENCIES KCONFIG_SPLITCONFIG KCONFIG_TRISTATE
 COREBOOT_EXPORTS += KCONFIG_NEGATIVES KCONFIG_STRICT
 COREBOOT_EXPORTS += KCONFIG_AUTOADS KCONFIG_PACKAGE
 
-# Make does not offer a recursive wildcard function, so here's one:
-rwildcard=$(wildcard $1$2) $(foreach d,$(wildcard $1*),$(call rwildcard,$d/,$2))
-SYMLINK_LIST = $(call rwildcard,site-local/,symlink.txt)
-
-
 # directory containing the toplevel Makefile.inc
 TOPLEVEL := .
 
@@ -69,9 +64,6 @@ endif
 HOSTCFLAGS := -g
 HOSTCXXFLAGS := -g
 
-HOSTPKG_CONFIG ?= pkg-config
-COREBOOT_EXPORTS += HOSTPKG_CONFIG
-
 PREPROCESS_ONLY := -E -P -x assembler-with-cpp -undef -I .
 
 export $(COREBOOT_EXPORTS)
@@ -151,14 +143,13 @@ include $(TOPLEVEL)/payloads/Makefile.inc
 include $(TOPLEVEL)/util/testing/Makefile.inc
 -include $(TOPLEVEL)/site-local/Makefile.inc
 include $(TOPLEVEL)/tests/Makefile.inc
-printall real-all:
+real-all:
 	@echo "Error: Trying to build, but NOCOMPILE is set." >&2
 	@echo "  Please file a bug with the following information:"
 	@echo "- MAKECMDGOALS: $(MAKECMDGOALS)" >&2
 	@echo "- HAVE_DOTCONFIG: $(HAVE_DOTCONFIG)" >&2
 	@echo "- HAVE_KCONFIG_MAKEFILE_REAL: $(HAVE_KCONFIG_MAKEFILE_REAL)" >&2
 	@exit 1
-
 else
 
 ifneq ($(UNIT_TEST),1)
@@ -316,9 +307,6 @@ $(eval $(postinclude-hooks))
 $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
 
 # Build Kconfig .ads if necessary
-ifeq ($(CONFIG_ROMSTAGE_ADA),y)
-romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
-endif
 ifeq ($(CONFIG_RAMSTAGE_ADA),y)
 ramstage-srcs += $(obj)/ramstage/$(notdir $(KCONFIG_AUTOADS))
 endif
@@ -467,29 +455,6 @@ sphinx:
 sphinx-lint:
 	$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
 
-symlink:
-	@echo "Creating Symbolic Links.."; \
-	for link in $(SYMLINK_LIST); do \
-		SYMLINK=`cat $$link`; \
-		REALPATH=`realpath $$link`; \
-		if [ -L "$$SYMLINK" ]; then \
-			continue; \
-		elif [ ! -e "$$SYMLINK" ]; then \
-			echo -e "\tLINK $$SYMLINK -> $$(dirname $$REALPATH)"; \
-			ln -s $$(dirname $$REALPATH) $$SYMLINK; \
-		else \
-			echo -e "\tFAILED: $$SYMLINK exists"; \
-		fi \
-	done
-
-clean-symlink:
-	@echo "Deleting symbolic link";\
-	EXISTING_SYMLINKS=`find -L ./src -xtype l | grep -v 3rdparty`; \
-	for link in $$EXISTING_SYMLINKS; do \
-		echo -e "\tUNLINK $$link"; \
-		rm "$$link"; \
-	done
-
 clean-for-update:
 	rm -rf $(obj) .xcompile
 
@@ -517,4 +482,4 @@ distclean: clean clean-ctags clean-cscope distclean-payloads distclean-utils
 	rm -f abuild*.xml junit.xml* util/lint/junit.xml
 
 .PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean sphinx sphinx-lint
-.PHONY: ctags-project cscope-project clean-ctags symlink clean-symlink
+.PHONY: ctags-project cscope-project clean-ctags

Makefile.inc

@@ -80,7 +80,6 @@ PHONY+= clean-abuild coreboot check-style build_complete
 #######################################################################
 # root source directories of coreboot
 subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common
-subdirs-$(CONFIG_EC_ACPI) += src/ec/intel
 subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*)
 subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*))
 subdirs-y += $(wildcard src/northbridge/*/*)
@@ -94,7 +93,6 @@ subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
 subdirs-y += src/security
 subdirs-y += payloads payloads/external
-subdirs-$(CONFIG_SBOM) += src/sbom
 
 subdirs-y += site-local
 subdirs-y += util/checklist util/testing
@@ -154,7 +152,7 @@ int-gt=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(wor
 int-eq=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) = $(call _toint,$(word 2,$1))))
 int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + \( \( $$B - \( $$A % $$B \) \) % $$B \) )
 int-align-down=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A - \( $$A % $$B \) )
-file-size=$(strip $(shell wc -c "$1" | cut -f 1 -d ' '))
+file-size=$(strip $(shell cat $1 | wc -c))
 tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
 toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
 ws_to_under=$(shell echo '$1' | tr ' \t' '_')
@@ -266,9 +264,26 @@ endef
 # ResourceTemplate is the correct code.
 # As it's valid ASL, disable the warning.
 EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
+# IASL compiler check for usage of _CRS, _DIS, _PRS, and _SRS objects:
+#	1) If _PRS is present, must have _CRS and _SRS
+#	2) If _SRS is present, must have _PRS (_PRS requires _CRS and _SRS)
+#	3) If _DIS is present, must have _SRS (_SRS requires _PRS, _PRS requires _CRS and _SRS)
+#	4) If _SRS is present, probably should have a _DIS (Remark only)
+# A warning will be issued for each of these cases.
+# For existing ASL code, ignore this warnings
+IASL_MISSING_DEPENDENCY = 3141
 
 IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING)
 
+ifeq ($(CONFIG_IGNORE_IASL_MISSING_DEPENDENCY),y)
+	IASL_WARNINGS_LIST += $(IASL_MISSING_DEPENDENCY)
+build_complete::
+	printf "*** WARNING: The ASL code for this platform is incomplete.  Please fix it. ***\n"
+	printf "*** If _PRS is present, must have _CRS and _SRS ***\n"
+	printf "*** If _SRS is present, must have _PRS and _CRS ***\n"
+	printf "*** If _DIS is present, must have _SRS, _PRS and _CRS ***\n"
+endif
+
 IGNORED_IASL_WARNINGS = $(addprefix -vw , $(IASL_WARNINGS_LIST))
 
 define asl_template
@@ -306,20 +321,18 @@ cbfs-files-processor-nvramtool= \
 		mv $(2).tmp $(2))
 
 #######################################################################
-# Reduce a .config file by removing lines about default unset booleans
+# Reduce a .config file to its minimal representation
 # arg1: input
 # arg2: output
-define cbfs-files-processor-config
-	$(eval $(2): $(1) $(obj)/build.h; \
+define cbfs-files-processor-defconfig
+	$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
 		+printf "    CREATE     $(2) (from $(1))\n"; \
 		printf "# This image was built using coreboot " > $(2).tmp && \
 		grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
 		$(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \
 		cat $(2).tmp2 >> $(2).tmp && \
-		printf "# End of defconfig. Derivable values start here.\n" >> $(2).tmp && \
-		grep "^CONFIG" $(1) | grep -F -v -f $(2).tmp2 >> $(2).tmp && \
 		rm -f $(2).tmp2 && \
-		mv -f $(2).tmp $(2))
+		\mv -f $(2).tmp $(2))
 endef
 
 #######################################################################
@@ -372,12 +385,9 @@ cbfs-files-handler= \
 #######################################################################
 # a variety of flags for our build
 CBFS_COMPRESS_FLAG:=none
-ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZMA),y)
+ifeq ($(CONFIG_COMPRESS_RAMSTAGE),y)
 CBFS_COMPRESS_FLAG:=LZMA
 endif
-ifeq ($(CONFIG_COMPRESS_RAMSTAGE_LZ4),y)
-CBFS_COMPRESS_FLAG:=LZ4
-endif
 
 CBFS_PAYLOAD_COMPRESS_FLAG:=none
 ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y)
@@ -422,7 +432,7 @@ endif
 CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
-CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition
+CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla
 CFLAGS_common += -Wdangling-else
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
@@ -432,7 +442,7 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
 CFLAGS_common += -Wnull-dereference -Wreturn-type
-CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
+CFLAGS_common += -Wlogical-op -Wduplicated-cond
 # cf. commit f69a99db (coreboot: x86: enable gc-sections)
 CFLAGS_common += -Wno-unused-but-set-variable
 endif
@@ -589,7 +599,6 @@ BINCFG:=$(objutil)/bincfg/bincfg
 IFDTOOL:=$(objutil)/ifdtool/ifdtool
 
 AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool
-AMDFWREAD:=$(objutil)/amdfwtool/amdfwread
 
 APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
@@ -691,7 +700,7 @@ install-git-commit-clangfmt:
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD)
+tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER)
 
 ###########################################################################
 # Common recipes for all stages
@@ -1218,9 +1227,8 @@ vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
 vgaroms/seavgabios.bin-type := raw
 
 cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += config
-config-file := $(DOTCONFIG):config
+config-file := $(DOTCONFIG):defconfig
 config-type := raw
-config-compression := LZMA
 
 cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += revision
 revision-file := $(obj)/build.h

README.md

@@ -1,41 +1,21 @@
 coreboot README
 ===============
 
-coreboot is a Free Software project aimed at replacing the proprietary
-firmware (BIOS/UEFI) found in most computers. coreboot performs the
-required hardware initialization to configure the system, then passes
-control to a different executable, referred to in coreboot as the
-payload. Most often, the primary function of the payload is to boot the
-operating system (OS).
+coreboot is a Free Software project aimed at replacing the proprietary BIOS
+(firmware) found in most computers.  coreboot performs a little bit of
+hardware initialization and then executes additional boot logic, called a
+payload.
 
 With the separation of hardware initialization and later boot logic,
-coreboot is perfect for a wide variety of situations. It can be used
-for specialized applications that run directly in the firmware, running
-operating systems from flash, loading custom bootloaders, or
-implementing firmware standards, like PC BIOS services or UEFI. This
-flexibility allows coreboot systems to include only the features
-necessary in the target application, reducing the amount of code and
-flash space required.
+coreboot can scale from specialized applications that run directly
+firmware, run operating systems in flash, load custom
+bootloaders, or implement firmware standards, like PC BIOS services or
+UEFI. This allows for systems to only include the features necessary
+in the target application, reducing the amount of code and flash space
+required.
 
+coreboot was formerly known as LinuxBIOS.
 
-Source code
------------
-
-All source code for coreboot is stored in git. It is downloaded with
-the command:
-
-`git clone https://review.coreboot.org/coreboot.git`.
-
-Code reviews are done in [the project's Gerrit
-instance](https://review.coreboot.org/).
-
-The code may be browsed via [coreboot's Gitiles
-instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master).
-
-The coreboot project also maintains a
-[mirror](https://github.com/coreboot/coreboot) of the project on github.
-This is read-only, as coreboot does not accept github pull requests,
-but allows browsing and downloading the coreboot source.
 
 Payloads
 --------
@@ -43,156 +23,81 @@ Payloads
 After the basic initialization of the hardware has been performed, any
 desired "payload" can be started by coreboot.
 
-See <https://doc.coreboot.org/payloads.html> for a list of some of
-coreboot's supported payloads.
+See <https://www.coreboot.org/Payloads> for a list of supported payloads.
 
 
 Supported Hardware
 ------------------
 
-The coreboot project supports a wide range of architectures, chipsets,
-devices, and mainboards. While not all of these are documented, you can
-find some information in the [Architecture-specific
-documentation](https://doc.coreboot.org/arch/index.html) or the
-[SOC-specific documentation](https://doc.coreboot.org/soc/index.html).
+coreboot supports a wide range of chipsets, devices, and mainboards.
 
-For details about the specific mainboard devices that coreboot supports,
-please consult the [Mainboard-specific
-documentation](https://doc.coreboot.org/mainboard/index.html) or the
-[Board Status](https://coreboot.org/status/board-status.html) pages.
+For details please consult:
+
+ * <https://www.coreboot.org/Supported_Motherboards>
 
 
-Releases
---------
+Build Requirements
+------------------
 
-Releases are currently done by coreboot every quarter. The
-release archives contain the entire coreboot codebase from the time of
-the release, along with any external submodules. The submodules
-containing binaries are separated from the general release archives. All
-of the packages required to build the coreboot toolchains are also kept
-at coreboot.org in case the websites change, or those specific packages
-become unavailable in the future.
+ * make
+ * gcc / g++
+   Because Linux distribution compilers tend to use lots of patches. coreboot
+   does lots of "unusual" things in its build system, some of which break due
+   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
+   by generating broken object code.
+   Two options: use our toolchain (eg. make crosstools-i386) or enable the
+   `ANY_TOOLCHAIN` Kconfig option if you're feeling lucky (no support in this
+   case).
+ * iasl (for targets with ACPI support)
+ * pkg-config
+ * libssl-dev (openssl)
 
-All releases are available on the [coreboot
-download](https://coreboot.org/downloads.html) page.
+Optional:
 
-Please note that the coreboot releases are best considered as snapshots
-of the codebase, and do not currently guarantee any sort of extra
-stability.
+  * gdb (for better debugging facilities on some targets)
+ * ncurses (for `make menuconfig` and `make nconfig`)
+ * flex and bison (for regenerating parsers)
 
-Build Requirements and building coreboot
-----------------------------------------
 
-The coreboot build, associated utilities and payloads require many
-additional tools and packages to build. The actual coreboot binary is
-typically built using a coreboot-controlled toolchain to provide
-reproducibility across various platforms. It is also possible, though
-not recommended, to make it directly with your system toolchain.
-Operating systems and distributions come with an unknown variety of
-system tools and utilities installed. Because of this, it isn't
-reasonable to list all the required packages to do a build, but the
-documentation lists the requirements for a few different Linux
-distributions.
+Building coreboot
+-----------------
 
-To see the list of tools and libraries, along with a list of
-instructions to get started building coreboot, go to the [Starting from
-scratch](https://doc.coreboot.org/tutorial/part1.html) tutorial page.
+Please consult <https://www.coreboot.org/Build_HOWTO> for details.
 
-That same page goes through how to use QEMU to boot the build and see
-the output.
+
+Testing coreboot Without Modifying Your Hardware
+------------------------------------------------
+
+If you want to test coreboot without any risks before you really decide
+to use it on your hardware, you can use the QEMU system emulator to run
+coreboot virtually in QEMU.
+
+Please see <https://www.coreboot.org/QEMU> for details.
 
 
 Website and Mailing List
 ------------------------
 
-Further details on the project, as well as links to documentation and
-more can be found on the coreboot website:
+Further details on the project, a FAQ, many HOWTOs, news, development
+guidelines and more can be found on the coreboot website:
 
   <https://www.coreboot.org>
 
 You can contact us directly on the coreboot mailing list:
 
-  <https://doc.coreboot.org/community/forums.html>
+  <https://www.coreboot.org/Mailinglist>
 
 
-
-Copyrights and Licenses
+Copyright and License
 ---------------------
 
-
-### Uncopyrightable files
-
-There are many files in the coreboot tree that we feel are not
-copyrightable due to a lack of creative content.
-
-"In order to qualify for copyright protection in the United States, a
-work must satisfy the originality requirement, which has two parts. The
-work must have “at least a modicum” of creativity, and it must be the
-independent creation of its author."
-
-  <https://guides.lib.umich.edu/copyrightbasics/copyrightability>
-
-Similar terms apply to other locations.
-
-These uncopyrightable files include:
-
-- Empty files or files with only a comment explaining their existence.
-  These may be required to exist as part of the build process but are
-  not needed for the particular project.
-- Configuration files either in binary or text form. Examples would be
-  files such as .vbt files describing graphics configuration, spd files
-  as binary .spd or text \*spd\*.hex representing memory chip
-  configuration.
-- Machine-generated files containing version numbers, dates, hash
-  values or other "non-creative" content.
-
-As non-creative content, these files are in the public domain by
-default.  As such, the coreboot project excludes them from the project's
-general license even though they may be included in a final binary.
-
-If there are questions or concerns about this policy, please get in
-touch with the coreboot project via the mailing list.
-
-
-### Copyrights
-
 The copyright on coreboot is owned by quite a large number of individual
-developers and companies. A list of companies and individuals with known
-copyright claims is present at the top level of the coreboot source tree
-in the 'AUTHORS' file. Please check the git history of each of the
-source files for details.
+developers and companies. Please check the individual source files for details.
 
+coreboot is licensed under the terms of the GNU General Public License (GPL).
+Some files are licensed under the "GPL (version 2, or any later version)",
+and some files are licensed under the "GPL, version 2". For some parts, which
+were derived from other projects, other (GPL-compatible) licenses may apply.
+Please check the individual source files for details.
 
-### Licenses
-
-Because of the way coreboot began, using a significant amount of source
-code from the Linux kernel, it's licensed the same way as the Linux
-Kernel, with GNU General Public License (GPL) Version 2. Individual
-files are licensed under various licenses, though all are compatible
-with GPLv2. The resulting coreboot image is licensed under the GPL,
-version 2. All source files should have an SPDX license identifier at
-the top for clarification.
-
-Files under coreboot/Documentation/ are licensed under CC-BY 4.0 terms.
-As an exception, files under Documentation/ with a history older than
-2017-05-24 might be under different licenses.
-
-Files in the coreboot/src/commonlib/bsd directory are all licensed with
-the BSD-3-clause license.  Many are also dual-licensed GPL-2.0-only or
-GPL-2.0-or-later.  These files are intended to be shared with libpayload
-or other BSD licensed projects.
-
-The libpayload project contained in coreboot/payloads/libpayload may be
-licensed as BSD or GPL, depending on the code pulled in during the build
-process. All GPL source code should be excluded unless the Kconfig
-option to include it is set.
-
-
-The Software Freedom Conservancy
---------------------------------
-
-Since 2017, coreboot has been a member of [The Software Freedom
-Conservancy](https://sfconservancy.org/), a nonprofit organization
-devoted to ethical technology and driving initiatives to make technology
-more inclusive. The conservancy acts as coreboot's fiscal sponsor and
-legal advisor.
+This makes the resulting coreboot images licensed under the GPL, version 2.

configs/config.asrock_b85m_pro4.native_raminit

@@ -1,5 +0,0 @@
-# Configuration used to build-test native raminit
-CONFIG_VENDOR_ASROCK=y
-CONFIG_BOARD_ASROCK_B85M_PRO4=y
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_DEBUG_RAM_SETUP=y

configs/config.facebook_fbg1701.sbom

@@ -1,6 +0,0 @@
-CONFIG_INCLUDE_COREBOOT_SBOM=y
-CONFIG_INCLUDE_PAYLOAD_SBOM=y
-CONFIG_INCLUDE_ME_SBOM=y
-CONFIG_INCLUDE_MICROCODE_SBOM=y
-CONFIG_VENDOR_FACEBOOK=y
-CONFIG_BOARD_FACEBOOK_FBG1701=y