Makefile.inc: Drop spurious -t from cbfstool add-payload

The `-t` argument was never required for `add-payload` and results in
a warning now because the type was renamed.

TEST=Built with BUILD_TIMELESS=1 and compared binaries with and without
     this patch.

Change-Id: I6ccb70acc6e88a602b90c625040d4f05d8e3630a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

.checkpatch.conf

@@ -17,9 +17,6 @@
 --ignore CONFIG_DESCRIPTION
 --ignore MISSING_SPACE
 --ignore CORRUPTED_PATCH
---ignore SPDX_LICENSE_TAG
---ignore UNDOCUMENTED_DT_STRING
---ignore PRINTK_WITHOUT_KERN_LEVEL
 
 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file

.clang-format

@@ -1,21 +1,10 @@
-BasedOnStyle:					LLVM
-Language:					Cpp
-IndentWidth:					8
-UseTab:						Always
-BreakBeforeBraces:				Linux
-AllowShortIfStatementsOnASingleLine:		false
-IndentCaseLabels:				false
-SortIncludes:					false
-ContinuationIndentWidth:			8
-ColumnLimit:					0
-AlwaysBreakBeforeMultilineStrings:		true
-AllowShortLoopsOnASingleLine:			false
-AllowShortFunctionsOnASingleLine:		false
-AlignEscapedNewlinesLeft:			false
-AlignTrailingComments:				true
-AllowAllParametersOfDeclarationOnNextLine:	false
-AlignAfterOpenBracket:				true
-SpaceAfterCStyleCast:				false
-MaxEmptyLinesToKeep:				2
-BreakBeforeBinaryOperators:			NonAssignment
-BreakStringLiterals:				false
+BasedOnStyle:                              LLVM
+Language:                                  Cpp
+IndentWidth:                               8
+UseTab:                                    Always
+BreakBeforeBraces:                         Linux
+AllowShortIfStatementsOnASingleLine:       false
+IndentCaseLabels:                          false
+SortIncludes:                              false
+ContinuationIndentWidth:                   8
+ColumnLimit:                               80

.gitignore

@@ -16,7 +16,6 @@ payloads/coreinfo/lp.config*
 payloads/external/depthcharge/depthcharge/
 payloads/external/FILO/filo/
 payloads/external/GRUB2/grub2/
-payloads/external/LinuxBoot/linuxboot/
 payloads/external/SeaBIOS/seabios/
 payloads/external/tianocore/tianocore/
 payloads/external/tint/tint/
@@ -87,7 +86,6 @@ util/archive/archive
 util/bimgtool/bimgtool
 util/bincfg/bincfg
 util/board_status/board-status
-util/bucts/bucts
 util/cbfstool/cbfs-compression-tool
 util/cbfstool/cbfstool
 util/cbfstool/fmaptool
@@ -101,6 +99,7 @@ util/futility/futility
 util/genprof/genprof
 util/getpir/getpir
 util/ifdtool/ifdtool
+util/ifdfake/ifdfake
 util/intelmetool/intelmetool
 util/inteltool/.dependencies
 util/inteltool/inteltool
@@ -123,12 +122,16 @@ util/autoport/autoport
 util/kbc1126/kbc1126_ec_dump
 util/kbc1126/kbc1126_ec_insert
 
-Documentation/*.aux
-Documentation/*.idx
-Documentation/*.log
-Documentation/*.toc
-Documentation/*.out
-Documentation/*.pdf
+documentation/*.aux
+documentation/*.idx
+documentation/*.log
+documentation/*.toc
+documentation/*.out
+documentation/*.pdf
+documentation/cpukconfig.tex
+documentation/mainboardkconfig.tex
+documentation/skconfig.tex
+documentation/socketfkconfig.tex
 Documentation/_build
 
 doxygen/*

.gitmodules

@@ -21,8 +21,3 @@
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
 	url = ../libgfxinit.git
-[submodule "3rdparty/fsp"]
-	path = 3rdparty/fsp
-	url = ../fsp.git
-	update = none
-	ignore = dirty

Documentation/Intel/Board/Galileo_checklist.html

@@ -79,6 +79,8 @@
 <tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
 <tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
 <tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
 <tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
 <tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
 <tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>

Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md

@@ -0,0 +1,74 @@
+# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI
+
+## Introduction
+
+This documentation is intended to document the purpose for creating EFI service
+Interface inside coreboot space to perform CPU feature programming on Application
+Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs.
+
+Today coreboot is capable enough to handle multi-processor initialization on IA platforms.
+
+The multi-processor initialization code has to take care of lots of duties:
+
+1 Bringing all cores out of reset
+2 Load latest microcode on all cores
+3 Sync latest MTRR snapshot between BSP and APs
+4 Perform sets of CPU feature programming
+  * CPU Power & Thermal Management
+  * Overclocking
+  * Intel Trusted Execution Technology
+  * Intel Software Guard Extensions
+  * Intel Processor Trace etc.
+
+This above CPU feature programming lists are expected to grow with current and future
+CPU complexity and there might be some cases where certain feature programming mightbe
+closed source in nature.
+
+Platform code might need to compromise on those closed source nature of CPU programming
+if we don't plan to provide an alternate interface which can be used by coreboot to
+get-rid of such close source CPU programming.
+
+## Proposal
+
+As coreboot is doing CPU multi-processor initialization for IA platform before FSP-S
+initialization and having all possible information about cores in terms of maximum number
+of cores, APIC ids, stack size etc. It’s also possible for coreboot to extend its own
+support model and create a sets of APIs which later can be used by FSP to run CPU feature
+programming using coreboot published APIs.
+
+Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate
+PPI to perform certain API call, hence coreboot has to created MP services APIs known as
+EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.
+More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
+
+### coreboot to publish EFI_MP_SERVICES_PPI APIs
+| API                          | Description                                                      |
+|------------------------------|------------------------------------------------------------------|
+| PeiGetNumberOfProcessors     | Get the number of CPU's.                                         |
+| PeiGetProcessorInfo          | Get information on a specific CPU.                               |
+| PeiStartupAllAPs             | Activate all of the application processors.                      |
+| PeiStartupThisAP             | Activate a specific application processor.                       |
+| PeiSwitchBSP                 | Switch the boot strap processor.                                 |
+| PeiEnableDisableAP           | Enable or disable an application processor.                      |
+| PeiWhoAmI                    | Identify the currently executing processor.                      |
+|------------------------------|------------------------------------------------------------------|
+
+
+## Code Flow
+
+Here is proposed design flow with coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make
+use of the same to perform some CPU feature programming.
+
+** coreboot-FSP MP init flow **
+![alt text][coreboot_publish_mp_service_api]
+
+[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png "coreboot-fsp mp init flow"
+
+## Benefits
+1. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.
+With proposed model, coreboot will make use of SkipMpInit=0 which will allow to run all
+Silicon recommended CPU programming.
+2. CPU feature programming inside FSP will be more transparent than before as it’s using
+coreboot interfaces to execute those programming.
+3. coreboot will have more control over running those feature programming as API optimization
+handled by coreboot.

Documentation/Intel/NativeRaminit/Sandybridge.md

@@ -0,0 +1,135 @@
+# Sandy Bridge Raminit
+
+## Introduction
+
+This documentation is intended to document the closed source memory controller
+hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
+
+The memory initialization code has to take care of lots of duties:
+1. Selection of operating frequency
+* Selection of common timings
+* Applying frequency specific compensation values
+* Read training of all populated channels
+* Write training of all populated channels
+* Adjusting delay networks of address and command signals
+* DQS training of all populated channels
+* Programming memory map
+* Report DRAM configuration
+* Error handling
+
+## Definitions
+```eval_rst
++---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
++=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| timA    | IO phase: The phase delay of the IO signals                       | 1/64th DCK | [0-512)      |
++---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | Mhz        | 100, 133     |
++---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
++---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+```
+
+## (Inoffical) register documentation
+- [Sandy Bride - Register documentation](SandyBridge_registers.md)
+
+## Frequency selection
+- [Sandy Bride - Frequency selection](Sandybridge_freq.md)
+
+## Read training
+- [Sandy Bride - Read training](Sandybridge_read.md)
+
+### SMBIOS type 17
+The SMBIOS specification allows to report the memory configuration in use.
+On GNU/Linux you can run `# dmidecode -t 17` to view it.
+Example output of dmidecode:
+
+```
+Handle 0x0045, DMI type 17, 34 bytes
+    Memory Device
+	Array Handle: 0x0042
+	Error Information Handle: Not Provided
+	Total Width: 64 bits
+	Data Width: 64 bits
+	Size: 8192 MB
+	Form Factor: DIMM
+	Set: None
+	Locator: ChannelB-DIMM0
+	Bank Locator: BANK 2
+	Type: DDR3
+	Type Detail: Synchronous
+	Speed: 933 MHz
+	Manufacturer: 0420
+	Serial Number: 00000000
+	Asset Tag: 9876543210
+	Part Number: F3-1866C9-8GSR
+	Rank: 2
+	Configured Clock Speed: 933 MHz
+```
+The memory frequency printed by dmidecode is the active memory frequency. It's
+**not** the double datarate and it's **not** the one encoded maximum frequency
+in each DIMM's SPD.
+
+> **Note:** This feature is available since coreboot 4.4
+
+### MRC cache
+The name *MRC cache* might be missleading as in case of *Native ram init*
+there's no MRC, but for historical reasons it's still named *MRC cache*.
+The MRC cache is part of flash memory that is writeable by coreboot.
+At the end of the boot process coreboot will write the RAM training results to
+flash for future use, as RAM training is time intensive. Storing the results
+allows to boot faster on normal boot and allows to support S3 resume,
+as the RAM training results can't be stored in RAM (you need to configure
+the memory controller first to access RAM).
+
+The MRC cache needs to be invalidated in case the memory configuration has
+been changed. To detect a changed memory configuration the CRC16 of each DIMM
+is stored to MRC cache.
+> **Note:** This feature is available since coreboot 4.4
+
+### Error handling
+As of writing the only supported error handling is to disable the failing
+channel and restart the memory training sequence. It's very likely to succeed,
+as memory channels operate independent of each other.
+In case no DIMM could be initilized coreboot will halt. The screen will stay
+black until you power of your device. On some platforms there's additional
+feedback to indicate such an event.
+
+If you find `dmidecode -t 17` to report only half of the memory installed,
+it's likely that a fatal memory init failure had happened.
+It is assumed, that a working board with less physical memory, is much better,
+than a board that doesn't boot at all.
+
+> **Note:** This feature is available since coreboot 4.5
+
+Try to swap memory modules and or try to use a different vendor. If nothing
+helps you could have a look at capter [Debuggin] or report a ticket
+at [ticket.coreboot.org]. Please provide a full RAM init log,
+that has been captured using EHCI debug.
+
+To enable extensive RAM training logging enable the Kconfig option
+`DEBUG_RAM_SETUP`
+#### Lenovo Thinkpads
+Lenovo Thinkpads do have an additional feature to indicate that RAM init has
+failed and coreboot has died (it calls die() on fatal error, thus the name).
+The Kconfig options
+`H8_BEEP_ON_DEATH`
+`H8_FLASH_LEDS_ON_DEATH`
+enable blinking LEDs and enable a beep to indicate death.
+
+> **Note:** This feature is available since coreboot 4.7
+
+## Debugging
+It's recommended to use an external debugger, such as serial or EHCI debug
+dongle. In case of failing memory init the board might not boot at all,
+preventing you from using CBMEM.

Documentation/Intel/NativeRaminit/Sandybridge_freq.md

@@ -0,0 +1,165 @@
+# Frequency selection
+
+## Introduction
+This chapter explains the frequency selection done on Sandybride and Ivybridge.
+
+## Definitions
+```eval_rst
++---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
++=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | MHz        | 100, 133     |
++---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
++---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+```
+## SPD
+The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
+located on every DIMM is factory program with various timings. One of them
+specifies the maximum clock frequency the DIMM should be used with. The
+operating frequency is stores as fixed point value (tCK), rounded to the next
+smallest supported operating frequency. Some
+[SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
+contains additional and optional
+[XMP](https://de.wikipedia.org/wiki/Extreme_Memory_Profile "Extreme Memory Profile")
+data, that stores so called "performance" modes, that advertises higher clock
+frequencies.
+
+## XMP profiles
+At time of writing coreboot's raminit is able to parse XMP profile 1 and 2.
+Only **XMP profile 1** is being used in case it advertises:
+* 1.5V operating voltage
+* The channel's installed DIMM count doesn't exceed the XMP coded limit
+
+In case the XMP profile doesn't fullfill those limits, the regular SPD will be
+used.
+> **Note:** XMP Profiles are supported since coreboot 4.4.
+
+It is possible to ignore the max DIMM count limit set by XMP profiles.
+By activating Kconfig option `NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS` it is
+possible to install two DIMMs per channel, even if XMP tells you not to do.
+
+> **Note:** Ignoring XMP Profiles limit is supported since coreboot 4.7.
+
+## Soft fuses
+Every board manufacturer does program "soft" fuses to indicate the maximum
+DRAM frequency supported. However, those fuses don't set a limit in hardware
+and thus are called "soft" fuses, as it is possible to ignore them.
+
+> **Note:** Ignoring the fuses might cause system instability !
+
+On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
+read. coreboot reads those registers and honors the limit in case the Kconfig
+option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
+Power users that want to let their RAM run at DRAM's "stock" frequency need to
+enable the Kconfig symbol.
+
+It is possible to override the soft fuses limit by using a board-specific
+[devicetree](#devicetree) setting.
+
+> **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.
+
+## <a name="hard_fuses"></a> Hard fuses
+"Hard" fuses are programmed by Intel and limit the maximum frequency that can
+be used on a given CPU/board/chipset. At time of writing there's no register
+to read this limit, before trying to set a given DRAM frequency. The memory PLL
+won't lock, indicating that the chosen memory multiplier isn't available. In
+this case coreboot tries the next smaller memory multiplier until the PLL will
+lock.
+
+## <a name="devicetree"></a> Devicetree
+The devicetree register ```max_mem_clock_mhz``` overrides the "soft" fuses set
+by the board manufacturer.
+
+By using this register it's possible to force a minimum operating frequency.
+
+## Reference clock
+While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
+supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
+multiplier to select the DRAM frequency (SCK) by the following formula:
+
+ REFCK * MULT = 1 / DCK
+
+> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
+
+## Sandy Bride's supported frequencies
+```eval_rst
++------------+-----------+------------------+-------------------------+---------------+
+| SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
++============+===========+==================+=========================+===============+
+| 400        | DDR3-800  | 3                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 533        | DDR3-1066 | 4                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 666        | DDR3-1333 | 5                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 800        | DDR3-1600 | 6                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 933        | DDR3-1866 | 7                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 1066       | DDR3-2166 | 8                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+```
+
+## Ivybridge's supported frequencies
+```eval_rst
++------------+-----------+------------------+-------------------------+---------------+
+| SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
++============+===========+==================+=========================+===============+
+| 400        | DDR3-800  | 3                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 533        | DDR3-1066 | 4                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 666        | DDR3-1333 | 5                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 800        | DDR3-1600 | 6                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 933        | DDR3-1866 | 7                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 1066       | DDR3-2166 | 8                | 133 MHz                 |               |
++------------+-----------+------------------+-------------------------+---------------+
+| 700        | DDR3-1400 | 7                | 100 MHz                 | '1            |
++------------+-----------+------------------+-------------------------+---------------+
+| 800        | DDR3-1600 | 8                | 100 MHz                 | '1            |
++------------+-----------+------------------+-------------------------+---------------+
+| 900        | DDR3-1800 | 9                | 100 MHz                 | '1            |
++------------+-----------+------------------+-------------------------+---------------+
+| 1000       | DDR3-2000 | 10               | 100 MHz                 | '1            |
++------------+-----------+------------------+-------------------------+---------------+
+| 1100       | DDR3-2200 | 11               | 100 MHz                 | '1            |
++------------+-----------+------------------+-------------------------+---------------+
+| 1200       | DDR3-2400 | 12               | 100 MHz                 | '1            |
++------------+-----------+------------------+-------------------------+---------------+
+```
+> '1: since coreboot 4.6
+
+## Multiplier selection
+coreboot select the maximum frequency to operate at by the following formula:
+```
+if devicetree's max_mem_clock_mhz > 0:
+     freq_max := max_mem_clock_mhz
+else:
+     freq_max := soft_fuse_max_mhz
+
+for i in SPDs:
+     freq_max := MIN(freq_max, ddr_spd_max_mhz[i])
+```
+
+As you can see, by using DIMMs with different maximum DRAM frequencies, the
+slowest DIMMs' frequency will be selected, to prevent over-clocking it.
+
+The selected frequency gives the PLL multiplier to operate at. In case the PLL
+locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
+all DIMMs. At this point it's not possible to change the multiplier again,
+until the system has been powered off. In case the PLL doesn't lock, the next
+smaller multiplier will be used until a working multiplier will be found.

Documentation/Intel/NativeRaminit/Sandybridge_read.md

@@ -0,0 +1,153 @@
+# Read training
+
+## Introduction
+
+This chapter explains the read training sequence done on Sandy Bride and
+Ivy Bridge memory initialization.
+
+Read training is done to compensate the skew between DQS and SCK and to find
+the smallest supported roundtrip delay.
+
+Every board does have a vendor depended routing topology, and can be equip
+with any combination of DDR3 memory modules, that introduces different
+skew between the memory lanes. With DDR3 a "Fly-By" routing topology
+has been introduced, that makes the biggest part of DQS-SCK skew.
+The memory code measures the actual skew and actives delay gates,
+that will "compensate" the skew.
+
+When in read training the DRAM and the controller are placed in a special mode.
+On every read instruction the DRAM outputs a predefined pattern and the memory
+controller samples the DQS after a given delay. As the pattern is known, the
+actual delay of every lane can be measured.
+
+The values programmed in read training effect DRAM-to-MC transfers only !
+
+## Definitions
+```eval_rst
++---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
++=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| timA    | IO phase: The phase delay of the IO signals                       | 1/64th DCK | [0-512)      |
++---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | MHz        | 100, 133     |
++---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
++---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+| DQS     | Data Strobe signal used to sample all lane's DQ signals           |            |              |
++---------+-------------------------------------------------------------------+------------+--------------+
+```
+## Hardware
+The hardware does have delay logic blocks that can delay the DQ / DQS of a
+lane/rank by one or multiple clock cylces and it does have delay logic blocks
+that can delay the signal by a multiple of 1/64th DCK per lane.
+
+All delay values can be controlled via software by writing registers in the
+MCHBAR.
+
+## IO phase
+
+The IO phase can be adjusted in [0-512) * 1/64th DCK. Incrementing it by 64 is
+the same as Incrementing IO delay by 1.
+
+## IO delay
+Delays the DQ / DQS signal by one or multiple clock cycles.
+
+### Roundtrip time
+The roundtrip time is the time the memory controller waits for data arraving
+after a read has been issued. Due to clock-domain crossings, multiple
+delay instances and phase interpolators, the signal runtime to DRAM and back
+to memory controller defaults to 55 DCKs. The real roundtrip time has to be
+measured.
+
+After a read command has been issued, a counter counts down until zero has been
+reached and activates the input buffers.
+
+The following pictures shows the relationship between those three values.
+The picture was generated from 16 IO delay values times 64 timA values.
+The highest IO delay was set on the right-hand side, while the last block
+on the left-hand side has zero IO delay.
+
+#### roundtrip 55 DCKs
+![alt text][timA_lane0-3_rt55]
+
+[timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"
+
+#### roundtrip 54 DCKs
+![alt text][timA_lane0-3_rt54]
+
+[timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"
+
+
+#### roundtrip 53 DCKs
+![alt text][timA_lane0-3_rt53]
+
+[timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"
+
+As you can see the signal has some jitter as every sample was taken in a
+different loop iteration. The result register only contains a single bit per
+lane.
+
+## Algorithm
+### Steps
+The algorithm finds the roundtrip time, IO delay and IO phase. The IO phase
+will be adjusted to match the falling edge of the preamble of each lane.
+The roundtrip time is adjusted to an minimal value, that still includes the
+preamble.
+
+### Synchronize to data phase
+
+The first measurement done in read-leveling samples all DQS values for one
+phase [0-64) * 1/64th DCK. It then searches for the middle of the low data
+symbol and adjusts timA to the found phase and thus the following measurements
+will be aligned to the low data symbol.
+The code assumes that the initial roundtrip time causes the measurement to be
+in the alternating pattern data phase.
+
+### Finding the preamble
+After adjusting the IO phase to the middle of one data symbol the preamble will
+be located. Unlike the data phase, which is an alternating pattern (010101...),
+the preamble consists of two high data cycles.
+
+The code decrements the IO delay/RTT and samples the DQS signal with timA
+untouched. As it has been positioned in the middle of the data symbol, it'll
+read as either "low" or "high".
+
+If it's "low" we are still in the data phase.
+If it's "high" we have found the preamble.
+
+The roundtrip time and IO delay will be adjusted until all lanes are aligned.
+The resulting IO delay is visible in the picture below.
+
+** roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs **
+![alt text][timA_lane0-3_discover_420x]
+
+[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png "timA for lane0 - lane3, finding minimum roundtrip time"
+
+** Note: The sampled data has been shifted by timA. The preamble is now
+in phase. **
+
+## Fine adjustment
+
+As timA still points the middle of the data symbol an offset of 32 is added.
+It now points the falling edge of the preamble.
+The fine adjustment is to reduce errors introduced by jitter. The phase is
+adjusted from `timA - 25` to `timA + 25` and the DQS signal is sampled 100
+times. The fine adjustment finds the middle of each rising edge (it's actual
+the falling edge of the preamble) to get the final IO phase. You can see the
+result in the picture below.
+
+![alt text][timA_lane0-3_adjust_fine]
+
+[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png "timA for lane0 - lane3, fine adjustment"
+
+Lanes 0 - 2 will be adjusted by a phase of -10, while lane 3 is already correct.

Documentation/Intel/SoC/soc.html

@@ -234,6 +234,8 @@ Use the following steps to locate the FSP binary:
         <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
       </li>
       <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
+        specifically building
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
       </li>
     </ol>
   </li>
@@ -514,7 +516,7 @@ Use the following steps to debug the call to TempRamInit:
   a "struct pci_operations" that specifies a routine to set the subsystem
   IDs for the device.  The routine might look something like this:
 </p>
-<pre><code>static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
+<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
 	if (!vendor || !device) {
 		vendor = pci_read_config32(dev, PCI_VENDOR_ID);
@@ -536,7 +538,7 @@ Use the following steps to debug the call to TempRamInit:
   The memory map is built by the various PCI device drivers during the
   BS_DEV_RESOURCES state of ramstage.  The northcluster driver will typically
   specify the DRAM resources while the other drivers will typically specify
-  the IO resources.  These resources are hung off the struct device *data structure by
+  the IO resources.  These resources are hung off the device_t data structure by
   src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
 </p>
 <p>

Documentation/Intel/development.html

@@ -264,7 +264,7 @@
       <ul>
         <li>MemoryInit UPD values are correct</li>
         <li>MemoryInit returns 0 (success) and</li>
-        <li>The message "ERROR - coreboot's requirements not met by FSP binary!"
+        <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
           is not displayed
         </li>
       </ul>
@@ -324,7 +324,7 @@
       <ul>
         <li>MemoryInit UPD values are correct</li>
         <li>MemoryInit returns 0 (success) and</li>
-        <li>The message "ERROR - coreboot's requirements not met by FSP binary!"
+        <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
           is not displayed
         </li>
       </ul>
@@ -374,4 +374,4 @@
 <hr>
 <p>Modified: 4 March 2016</p>
   </body>
-</html>
+</html>

Documentation/Kconfig.tex

@@ -0,0 +1,480 @@
+\documentclass[10pt,letterpaper]{article}
+\usepackage[latin1]{inputenc}
+\usepackage{amsmath}
+\usepackage{amsfonts}
+\usepackage{amssymb}
+\author{Ron Minnich}
+\title{Kconfig usage in coreboot v2}
+\begin{document}
+\section{Introduction}
+This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
+\section{Kconfig variations}
+Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
+
+For variables set by the user, see src/console/Kconfig.
+
+For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent.
+
+Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
+
+\section{Makefile and Makefile.inc}
+There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
+
+Make is not recursive. There is only one make process.
+\subsection{subdirs usage}
+Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
+
+We define the common rules for which variation to use below.
+\subsection{object file specification}
+There are several different types of objects specified in the tree. They are:
+\begin{description}
+\item[obj]objects for the RAM part of the code
+\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
+\item[initobj]seperately-compiled code for the ROM section of coreboot
+\end{description}
+These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
+
+\section{Example: AMD serengeti cheetah}
+\subsection{mainboard/Kconfig}
+Defines Vendor variables. Currently defined variables are:
+Sources all Kconfig files in the vendor directories.
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/Makefile.inc}
+There is none at this time.
+\subsection{mainboard/$<$vendor$>$/Kconfig}
+We use the amd as a model. The only action currently taken is to source all Kconfig's in the
+subdirectories.
+\subsection{mainboard/$<$vendor$>$/Makefile.inc}
+We use amd as a model. There is currently no Makefile.inc at this level.
+\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig}
+The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines
+and rules in here determine everything about how a mainboard target is built.
+We will use serengeti\_cheetah as a model. It defines these variables.
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc}
+This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece.
+Note that this is the mainboard as of August, 2009, and it may change over time.
+\subsubsection{objects}
+We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional:
+\begin{verbatim}
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  ssdt4.o
+driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+\end{verbatim}
+\subsubsection{romcc legacy support}
+We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define
+crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the
+old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally.
+\begin{verbatim}
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+\end{verbatim}
+\subsubsection{POST\_EVALUATION}
+POST\_EVALUATION rules should be placed after this section:
+\begin{verbatim}
+ifdef POST_EVALUATION
+\end{verbatim}
+to ensure that the values of variables are correct.
+Here are the post-evaluation rules for this mainboard:
+\begin{verbatim}
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+  iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+  mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+  $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+  iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+  perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+  mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+  iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+  perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+  mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+  iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+  perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+  mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
+  $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
+  perl -e 's/\.rodata/.rom.data/g' -pi $@
+  perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+\end{verbatim}
+The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
+\subsubsection{devicetree.cb}
+Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
+properly, as it defines topology and chips that can be defined no other way.
+Let's go through the tree.
+\begin{verbatim}
+chip northbridge/amd/amdk8/root_complex
+  device cpu_cluster 0 on
+    chip cpu/amd/socket_F
+      device lapic 0 on end
+    end
+  end
+\end{verbatim}
+This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
+
+We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
+have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
+somewhere, since it runs memory.
+
+
+What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
+CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
+its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
+{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
+which connects to a {\it cpu/amd/socket\_F},
+which has a local apic, which is on.
+
+Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
+is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
+BIOSes) that the BSP be CPU 0; any CPU will do.
+\begin{verbatim}
+  device domain 0 on
+    chip northbridge/amd/amdk8
+      device pci 18.0 on #  northbridge
+        #  devices on link 0, link 0 == LDT 0
+\end{verbatim}
+Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
+Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
+\begin{verbatim}
+        chip southbridge/amd/amd8132
+          # the on/off keyword is mandatory
+          device pci 0.0 on end
+          device pci 0.1 on end
+          device pci 1.0 on end
+          device pci 1.1 on end
+        end
+\end{verbatim}
+This is the 8132, a bridge to a secondary PCI bus.
+\begin{verbatim}
+        chip southbridge/amd/amd8111
+          # this "device pci 0.0" is the parent the next one
+          # PCI bridge
+          device pci 0.0 on
+            device pci 0.0 on end
+            device pci 0.1 on end
+            device pci 0.2 off end
+            device pci 1.0 off end
+          end
+\end{verbatim}
+The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
+\begin{verbatim}
+          device pci 1.0 on
+            chip superio/winbond/w83627hf
+              device pnp 2e.0 off #  Floppy
+                 io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 off #  Parallel Port
+                 io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 2e.2 on #  Com1
+                 io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off #  Com2
+                 io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 on #  Keyboard
+                 io 0x60 = 0x60
+                 io 0x62 = 0x64
+                irq 0x70 = 1
+                irq 0x72 = 12
+              end
+              device pnp 2e.6 off #  CIR
+                io 0x60 = 0x100
+              end
+              device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                io 0x60 = 0x220
+                io 0x62 = 0x300
+                irq 0x70 = 9
+              end
+              device pnp 2e.8 off end #  GPIO2
+              device pnp 2e.9 off end #  GPIO3
+              device pnp 2e.a off end #  ACPI
+              device pnp 2e.b on #  HW Monitor
+                  io 0x60 = 0x290
+                irq 0x70 = 5
+              end
+            end
+          end
+\end{verbatim}
+The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
+2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
+\begin{verbatim}
+          device pci 1.1 on end
+          device pci 1.2 on end
+\end{verbatim}
+More devices. These statements set up placeholders in the device tree.
+\begin{verbatim}
+          device pci 1.3 on
+            chip drivers/i2c/i2cmux # pca9556 smbus mux
+              device i2c 18 on #0 pca9516 1
+                chip drivers/generic/generic #dimm 0-0-0
+                  device i2c 50 on end
+                end
+                chip drivers/generic/generic #dimm 0-0-1
+                  device i2c 51 on end
+                end
+                chip drivers/generic/generic #dimm 0-1-0
+                  device i2c 52 on end
+                end
+                chip drivers/generic/generic #dimm 0-1-1
+                  device i2c 53 on end
+                end
+              end
+              device i2c 18 on #1 pca9516 2
+                chip drivers/generic/generic #dimm 1-0-0
+                  device i2c 50 on end
+                end
+                chip drivers/generic/generic #dimm 1-0-1
+                  device i2c 51 on end
+                end
+                chip drivers/generic/generic #dimm 1-1-0
+                  device i2c 52 on end
+                end
+                chip drivers/generic/generic #dimm 1-1-1
+                  device i2c 53 on end
+                end
+                chip drivers/generic/generic #dimm 1-2-0
+                  device i2c 54 on end
+                end
+                chip drivers/generic/generic #dimm 1-2-1
+                  device i2c 55 on end
+                end
+                chip drivers/generic/generic #dimm 1-3-0
+                  device i2c 56 on end
+                end
+                chip drivers/generic/generic #dimm 1-3-1
+                  device i2c 57 on end
+                end
+              end
+            end
+          end # acpi
+\end{verbatim}
+These are the i2c devices.
+\begin{verbatim}
+          device pci 1.5 off end
+          device pci 1.6 off end
+\end{verbatim}
+More placeholders.
+\begin{verbatim}
+               register "ide0_enable" = "1"
+          register "ide1_enable" = "1"
+        end
+      end #  device pci 18.0
+
+\end{verbatim}
+These "register" commands set controls in the southbridge.
+\begin{verbatim}
+           device pci 18.0 on end
+      device pci 18.0 on end
+\end{verbatim}
+These are the other two hypertransport links.
+\begin{verbatim}
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+\end{verbatim}
+The 18.1 devices are, again, northbridge control for various k8 functions.
+\begin{verbatim}
+    end
+  \end{verbatim}
+That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
+\begin{verbatim}
+        chip northbridge/amd/amdk8
+      device pci 19.0 on #  northbridge
+        chip southbridge/amd/amd8151
+          # the on/off keyword is mandatory
+          device pci 0.0 on end
+          device pci 1.0 on end
+        end
+      end #  device pci 19.0
+
+      device pci 19.0 on end
+      device pci 19.0 on end
+      device pci 19.1 on end
+      device pci 19.2 on end
+      device pci 19.3 on end
+    end
+
+
+\end{verbatim}
+
+\subsection{cpu socket}
+The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
+the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
+of all defines and Makefile controls for building the CPU components of a board.
+
+\subsubsection{ cpu/Kconfig}
+Defines variables. Current variables are:
+\input{cpukconfig.tex}
+Sources all Kconfig files in the vendor directories.
+\subsubsection{ cpu/Makefile.inc}
+Unconditionally sources all Makefile.inc in the vendor directories.
+
+\subsection{cpu/$<$vendor$>$/Kconfig}
+The only action currently taken is to source all Kconfig's in the
+subdirectories.
+\subsection{cpu/$<$vendor$>$/Makefile.inc}
+{\em Conditionally} source the socket directories.
+Example:
+\begin{verbatim}
+subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
+\end{verbatim}
+.
+CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
+
+\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig}
+Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that
+the socket, as much as possible, should control the models, because the models may plug into many sockets.
+Socket\_F currently sets:
+\input{socketfkconfig.tex}
+
+It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced.
+
+\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig}
+CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
+if needed.
+\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc}
+The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional
+compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all}
+objects, because it is not possible to determine at build time what options may be needed for a given model CPU.
+This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
+
+\subsection{northbridge}
+\subsubsection{northbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs.
+\subsubsection{northbridge/Makefile.inc}
+No variables. unconditionally include all vendor Makefile.inc
+\subsubsection{northbridge/$<$vendor$>$/Kconfig}
+No variables. Source all chip directory Kconfigs.
+\subsubsection{northbridge/$<$vendor$>$/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
+is the name of the part, e.g.
+\begin{verbatim}
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
+\end{verbatim}
+.
+\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example
+of the variables defined for the K8.
+\begin{verbatim}
+config NORTHBRIDGE_AMD_AMDK8
+  bool
+  default n
+
+config AGP_APERTURE_SIZE
+  hex
+  default 0x4000000
+\end{verbatim}
+\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
+Typically very small set of rules, and very simple.
+Since this file is already conditionally included,
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD K8.
+Note that we can make a variable conditional on the ACPI tables.
+\begin{verbatim}
+driver-y += northbridge.o
+driver-y += misc_control.o
+obj-y +=  get_sblk_pci1234.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  amdk8_acpi.o
+\end{verbatim}
+
+\subsection{southbridge}
+\subsubsection{southbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs.
+\subsubsection{southbridge/Makefile.inc}
+No variables. {\em Unconditionally} include all vendor Makefile.inc
+\subsubsection{southbridge/$<$vendor$>$/Kconfig}
+No variables. Source all chip directory Kconfigs.
+\subsubsection{southbridge/$<$vendor$>$/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
+is the name of the part, e.g.
+\begin{verbatim}
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
+\end{verbatim}
+.
+\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example
+of the variables defined for the K8.
+\begin{verbatim}
+config SOUTHBRIDGE_AMD_AMD8111
+	bool
+	default n
+
+\end{verbatim}
+\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
+Typically very small set of rules, and very simple.
+Since this file is already conditionally included,
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD 8111.
+No conditionals in this one yet.
+\begin{verbatim}
+driver-y += amd8111.o
+driver-y += amd8111_usb.o
+driver-y += amd8111_lpc.o
+driver-y += amd8111_ide.o
+driver-y += amd8111_acpi.o
+driver-y += amd8111_usb2.o
+driver-y += amd8111_ac97.o
+driver-y += amd8111_nic.o
+driver-y += amd8111_pci.o
+driver-y += amd8111_smbus.o
+obj-y += amd8111_reset.o
+\end{verbatim}
+
+\subsubsection{vendor and part}
+\subsection{southbridge}
+\subsubsection{vendor and part}
+\subsection{superio}
+\subsection{drivers/i2c}
+This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed.
+To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have:
+\begin{verbatim}
+\end{verbatim}
+
+\subsubsection{vendor and part}
+
+\end{document}

Documentation/Lesson2.md

@@ -0,0 +1,281 @@
+# coreboot Lesson 2: Submitting a patch to coreboot.org
+
+## Part 1: Setting up an account at coreboot.org
+
+If you already have an account, skip to Part 2.
+
+Otherwise, go to <https://review.coreboot.org> in your preferred web browser.
+Select **Register** in the upper right corner.
+
+Select the appropriate sign-in. For example, if you have a Google account,
+select **Google OAuth2** (gerrit-oauth-provider plugin)".**Note:** Your
+username for the account will be the username of the account you used to
+sign-in with. (ex. your Google username).
+
+## Part 2a: Set up RSA Private/Public Key
+
+If you prefer to use an HTTP password instead, skip to Part 2b.
+
+For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
+<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh)>
+and follow the instructions there. Then, skip to Part 3.
+
+Additionally, that section of the Web site provides explanation on starting
+an ssh-agent, which may be particularly helpful for those who anticipate
+frequently uploading changes.
+
+If you instead prefer to have review.coreboot.org specific instructions,
+follow the steps below. Note that this particular section may have the
+most up-to-date instructions.
+
+If you do not have an RSA key set up on your account already (as is the case
+with a newly created account), follow the instructions below; otherwise,
+doing so could overwrite an existing key.
+
+In the upper right corner, select your name and click on **Settings**.
+Select **SSH Public Keys** on the left-hand side.
+
+In a terminal, run "ssh-keygen" and confirm the default path ".ssh/id_rsa".
+
+Make a passphrase -- remember this phrase. It will be needed whenever you use
+this RSA Public Key. **Note:** You might want to use a short password, or
+forego the password altogether as you will be using it very often.
+
+Open "id_rsa.pub", copy all contents and paste into the textbox under
+"Add SSH Public Key" in the https://review.coreboot.org webpage.
+
+## Part 2b: Setting up an HTTP Password
+
+Alternatively, instead of using SSH keys, you can use an HTTP password. To do so,
+after you select your name and click on **Settings** on the left-hand side, rather
+than selecting **SSH Public Keys**, select **HTTP Password**.
+
+Click **Generate Password**. This should fill the "Password" box with a password. Copy
+the password, and add the following to your $HOME/.netrc file:
+
+	machine review.coreboot.org login YourUserNameHere password YourPasswordHere
+
+where YourUserNameHere is your username, and YourPasswordHere is the password you
+just generated.
+
+## Part 3: Clone coreboot and configure it for submitting patches
+
+Go to the **Projects** tab in the upper left corner and select **List**.
+From the dropdown menu that appears, select "coreboot".
+
+If you are using SSH keys, select **ssh** from the tabs under "Project coreboot"
+and run the command that appears. This should prompt you for your id_rsa passphrase,
+if you previously set one.
+
+If you are using HTTP, instead, select **http** from the tabs under "Project coreboot"
+and run the command that appears
+
+After it finishes cloning, "cd coreboot" will take you into the local
+git repository. Run "make gitconfig" to set up the hooks and configurations.
+For example, you will be asked to run the following commands to set your
+username and email.
+
+	git config --global user.name "Your Name"
+	git config --global user.email "Your Email"
+
+## Part 4: Submit a commit
+
+An easy first commit to make is fixing existing checkpatch errors and warnings
+in the source files. To see errors that are already present, build the files in
+the repository by running 'make lint' in the coreboot directory. Alternatively,
+if you want to run 'make lint' on a specific directory, run:
+
+	for file in $(git ls-files | grep src/amd/quadcore); do \
+	util/lint/checkpatch.pl --file $file --terse; done
+
+where <filepath> is the filepath of the directory (ex. src/cpu/amd/car).
+
+Any changes made to files under the src directory are made locally,
+and can be submitted for review.
+
+Once you finish making your desired changes, use the command line to stage
+and submit your changes. An alternative and potentially easier way to stage
+and submit commits is to use git cola, a graphical user interface for git. For
+instructions on how to do so, skip to Part 4b.
+
+## Part 4a: Using the command line to stage and submit a commit
+
+To use the command line to stage a commit, run
+
+	git add <filename>
+
+where `filename` is the name of your file.
+
+To commit the change, run
+
+	git commit -s
+
+**Note:** The -s adds a signed-off-by line by the committer. Your commit should be
+signed off with your name and email (i.e. **Your Name** **<Your Email>**, based on
+what you set with git config earlier).
+
+Running git commit first checks for any errors and warnings using lint. If
+there are any, you must go back and fix them before submitting your commit.
+You can do so by making the necessary changes, and then staging your commit again.
+
+When there are no errors or warnings, your default text editor will open.
+This is where you will write your commit message.
+
+The first line of your commit message is your commit summary. This is a brief
+one-line description of what you changed in the files using the template
+below:
+
+<filepath>: Short description
+*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors*
+**Note:** It is good practice to use present tense in your descriptions
+and do not punctuate your summary.
+
+Then hit Enter. The next paragraph should be a more in-depth explanation of the
+changes you've made to the files. Again, it is good practice to use present
+tense.
+*ex.  Fix space prohibited between function name and open parenthesis,
+line over 80 characters, unnecessary braces for single statement blocks,
+space required before open brace errors and warnings.*
+
+When you have finished writing your commit message, save and exit the text
+editor. You have finished committing your change. If, after submitting your
+commit, you wish to make changes to it, running "git commit --amend" allows
+you to take back your commit and amend it.
+
+When you are done with your commit, run 'git push' to push your commit to
+coreboot.org. **Note:** To submit as a draft, use
+'git push origin HEAD:refs/drafts/master' Submitting as a draft means that
+your commit will be on coreboot.org, but is only visible to those you add
+as reviewers.
+
+## Part 4b: Using git cola to stage and submit a commit
+
+If git cola is not installed on your machine, see
+https://git-cola.github.io/downloads.html for download instructions.
+
+After making some edits to src files, rather than run "git add," run
+'git cola' from the command line. You should see all of the files
+edited under "Modified".
+
+In the textbox labeled "Commit summary" provide a brief one-line
+description of what you changed in the files according to the template
+below:
+
+<filepath>: Short description
+*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors*
+**Note:** It is good practice to use present tense in your descriptions
+and do not punctuate your short description.
+
+In the larger text box labeled 'Extended description...' provide a more
+in-depth explanation of the changes you've made to the files. Again, it
+is good practice to use present tense.
+*ex.  Fix space prohibited between function name and open parenthesis,
+line over 80 characters, unnecessary braces for single statement blocks,
+space required before open brace errors and warnings.*
+
+Then press Enter two times to move the cursor to below your description.
+To the left of the text boxes, there is an icon with an downward arrow.
+Press the arrow and select "Sign Off." Make sure that you are signing off
+with your name and email (i.e. **Your Name** **<Your Email>**, based on what
+you set with git config earlier).
+
+Now, review each of your changes and mark either individual changes or
+an entire file as Ready to Commit by marking it as 'Staged'. To do
+this, select one file from the 'Modified' list. If you only want to
+submit particular changes from each file, then highlight the red and
+green lines for your changes, right click and select 'Stage Selected
+Lines'. Alternatively, if an entire file is ready to be committed, just
+double click on the file under 'Modified' and it will be marked as
+Staged.
+
+Once the descriptions are done and all the edits you would like to
+commit have been staged, press 'Commit' on the right of the text
+boxes.
+
+If the commit fails due to persisting errors, a text box will appear
+showing the errors. You can correct these errors within 'git cola' by
+right-clicking on the file in which the error occurred and selecting
+'Launch Diff Tool'. Make necessary corrections, close the Diff Tool and
+'Stage' the corrected file again. It might be necessary to refresh
+'git cola' in order for the file to be shown under 'Modified' again.
+Note: Be sure to add any other changes that haven't already been
+explained in the extended description.
+
+When ready, select 'Commit' again. Once all errors have been satisfied
+and the commit succeeds, move to the command line and run 'git push'.
+**Note:** To submit as a draft, use 'git push origin HEAD:refs/drafts/master'
+Submitting as a draft means that your commit will be on coreboot.org, but is
+only visible to those you add as reviewers.
+
+## Part 5: Getting your commit reviewed
+
+Your commits can now be seen on review.coreboot.org if you select “My”
+and click on “Changes” and can be reviewed by others. Your code will
+first be reviewed by build bot (Jenkins), which will either give you a warning
+or verify a successful build; if so, your commit will receive a +1. Other
+users may also give your commit +1.  For a commit to be merged, it needs
+to receive a +2.**Note:** A +1 and a +1 does not make a +2. Only certain users
+can give a +2.
+
+## Part 6 (optional): bash-git-prompt
+
+To help make it easier to understand the state of the git repository
+without running 'git status' or 'git log', there is a way to make the
+command line show the status of the repository at every point. This
+is through bash-git-prompt.
+
+Instructions for installing this are found at:
+https://github.com/magicmonty/bash-git-prompt
+**Note:** Feel free to search for different versions of git prompt,
+as this one is specific to bash.
+
+Alternatively, follow the instructions below:
+Run the following two commands in the command line:
+
+    cd
+    git clone https://github.com/magicmonty/bash-git-prompt.git .bash-git-prompt --depth=1
+
+**Note:** cd will change your directory to your home directory, so the
+git clone command will be run there.
+
+Finally, open the ~/.bashrc file and append the following two lines:
+
+    GIT_PROMPT_ONLY_IN_REPO=1
+    source ~/.bash-git-prompt/gitprompt.sh
+
+Now, whenever you are in a git repository, it will continuously display
+its state.
+
+There also are additional configurations that you can change depending on your
+preferences. If you wish to do so, look at the "All configs for .bashrc" section
+on https://github.com/magicmonty/bash-git-prompt. Listed in that section are
+various lines that you can copy, uncomment and add to your .bashrc file to
+change the configurations. Example configurations include avoid fetching remote
+status, and supporting versions of Git older than 1.7.10.
+
+## Appendix: Miscellaneous Advice
+
+### Updating a commit after running git push:
+
+Suppose you would like to update a commit that has already been pushed to the
+remote repository. If the commit you wish to update is the most recent
+commit you have made, after making your desired changes, stage the files
+(either using git add or in git cola), and amend the commit. To do so,
+if you are using the command line, run "git commit --amend." If you are
+using git cola, click on the gear icon located on the upper left side under
+**Commit** and select **Amend Last Commit** in the drop down menu. Then, stage
+the files you have changed, commit the changes, and run git push to push the
+changes to the remote repository. Your change should be reflected in Gerrit as
+a new patch set.
+
+If, however, the commit you wish to update is not the most recent commit you
+have made, you will first need to checkout that commit. To do so, find the
+URL of the commit on <https://review.coreboot.org> and go to that page; if
+the commit is one that you previously pushed, it can be found by selecting
+**My** and then **Changes** in the upper left corner. To checkout this commit,
+in the upper right corner, click on **Download**, and copy the command listed
+next to checkout by clicking **Copy to clipboard**. Then, run the copied
+command in your coreboot repository. Now, the last commit should be the most
+recent commit to that patch; to update it, make your desired changes, stage
+the files, then amend and push the commit using the instructions in the above
+paragraph.

Documentation/Makefile

@@ -7,7 +7,7 @@ PDFLATEX=pdflatex -t a4
 
 FIGS=codeflow.pdf hypertransport.pdf
 
-all: corebootPortingGuide.pdf
+all: corebootPortingGuide.pdf Kconfig.pdf
 
 SVG2PDF=$(shell which svg2pdf)
 INKSCAPE=$(shell which inkscape)
@@ -39,6 +39,30 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
 	$(PDFLATEX) corebootBuildingGuide.tex
 
+Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
+	$(PDFLATEX) $<
+
+# quick, somebody! make me a macro!
+mainboardkconfig.tex: ../src/mainboard/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+cpukconfig.tex: ../src/cpu/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
 sphinx:
 	$(MAKE) -f Makefile.sphinx html
 
@@ -46,10 +70,7 @@ clean-sphinx:
 	$(MAKE) -f Makefile.sphinx clean
 
 clean: clean-sphinx
-	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
+	rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex
 
 distclean: clean
-	rm -f corebootPortingGuide.pdf
-
-livesphinx:
-	$(MAKE) -f Makefile.sphinx livehtml
+	rm -f corebootPortingGuide.pdf Kconfig.pdf

Documentation/Makefile.sphinx

@@ -2,11 +2,10 @@
 #
 
 # You can set these variables from the command line.
-SPHINXOPTS        =
-SPHINXBUILD       = sphinx-build
-SPHINXAUTOBUILD   = sphinx-autobuild
-PAPER             =
-BUILDDIR          = _build
+SPHINXOPTS    =
+SPHINXBUILD   = sphinx-build
+PAPER         =
+BUILDDIR      = _build
 
 # Internal variables.
 PAPEROPT_a4     = -D latex_paper_size=a4
@@ -47,7 +46,7 @@ help:
 
 .PHONY: clean
 clean:
-	rm -rf $(BUILDDIR)
+	rm -rf $(BUILDDIR)/*
 
 .PHONY: html
 html:
@@ -55,13 +54,6 @@ html:
 	@echo
 	@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
 
-.PHONY: livehtml
-livehtml:
-	@echo "Starting sphinx-autobuild. The HTML pages are in $(BUILDDIR)."
-	@echo "Press Ctrl-C to stop."
-	@echo
-	$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
-
 .PHONY: dirhtml
 dirhtml:
 	$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml

Documentation/RFC/config.tex

@@ -119,8 +119,8 @@ addaction ::= 'addaction' PATH ``ACTION''
 statement ::=
 		  option
 		| default
-		| cpu
-		| arch
+        	| cpu
+        	| arch
 		| northbridge
 		| southbridge
 		| superio

Documentation/arch/index.md

@@ -1,11 +0,0 @@
-# Architecture-specific documentation
-
-This section contains documentation about coreboot on specific CPU
-architectures.
-
-## RISC-V
-
-- [RISC-V documentation](riscv/index.md)
-
-## x86
-- [x86 documentation](x86/index.md)

Documentation/arch/riscv/index.md

@@ -1,46 +0,0 @@
-# RISC-V architecture documentation
-
-This section contains documentation about coreboot on RISC-V architecture.
-
-## Mode usage
-All stages run in M mode.
-
-Payloads have a choice of managing M mode activity: they can control
-everything or nothing.
-
-Payloads run from the romstage (i.e. rampayloads) are started in M mode.
-The payload must, for example, prepare and install its own SBI.
-
-Payloads run from the ramstage are started in S mode, and trap delegation
-will have been done. These payloads rely on the SBI and can not replace it.
-
-## Stage handoff protocol
-On entry to a stage or payload,
-* all harts are running.
-* A0 is the hart ID.
-* A1 is the pointer to the Flattened Device Tree (FDT).
-
-## Additional payload handoff requirements
-The location of cbmem should be placed in a node in the FDT.
-
-## Trap delegation
-Traps are delegated in the ramstage.
-
-## SMP within a stage
-At the beginning of each stage, all harts save 0 are spinning in a loop on
-a semaphore.  At the end of the stage harts 1..max are released by changing
-the semaphore.
-
-A possible way to do this is to have a pointer to a struct containing
-variables, e.g.
-
-```c
-struct blocker {
-	void (*fn)(); // never returns
-}
-```
-
-The hart blocks until fn is non-null, and then calls it.  If fn returns, we
-will panic if possible, but behavior is largely undefined.
-
-Only hart 0 runs through most of the code in each stage.

Documentation/arch/x86/index.md

@@ -1,42 +0,0 @@
-# x86 architecture documentation
-
-This section contains documentation about coreboot on x86 architecture.
-
-## State of x86_64 support
-At the moment there's no single board that supports x86_64 or to be exact
-`ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`.
-
-In order to add support for x86_64 the following assumptions are made:
-* The CPU supports long mode
-* All memory returned by malloc must be below 4GiB in physical memory
-* All code that is to be run must be below 4GiB in physical memory
-* The high dword of pointers is always zero
-* The reference implementation is qemu
-* The CPU supports 1GiB hugepages
-
-## Assuptions for ARCH_ROMSTAGE_X86_64 reference implementation
-* 0-4GiB are identity mapped using 1GiB huge-pages
-* Memory above 4GiB isn't accessible
-* pagetables reside in _pagetables
-* Romstage must install new pagetables in CBMEM after RAMINIT
-
-## Assuptions for ARCH_RAMSTAGE_X86_64 reference implementation
-* Romstage installed pagetables according to memory layout
-* Memory above 4GiB is accessible
-
-## Steps to add basic support for x86_64
-* Add x86_64 toolchain support - *DONE*
-* Fix compilation errors - *DONE*
-* Fix linker errors - *TODO*
-* Add x86_64 rmodule support - *ONGERRIT*
-* Add x86_64 exception handlers - *TODO*
-* Setup page tables for long mode - *TODO*
-* Add assembly code for long mode - *TODO*
-* Add assembly code to return to protected mode - *TODO*
-* Implement reference code for mainboard `emulation/qemu-q35` - *TODO*
-
-## Porting other boards
-* Fix compilation errors
-* Test how well CAR works with x86_64 and paging
-* Improve mode switches
-* Test libgfxinit / VGA Option ROMs / FSP

Documentation/cbfs.txt

@@ -174,7 +174,7 @@ with
 regards to the erase block sizes on the ROM - allowing one to replace a
 component at runtime without disturbing the others.
 
-'offset' is the offset of the first CBFS component (from the start of
+'offset' is the offset of the the first CBFS component (from the start of
 the ROM).  This is to allow for arbitrary space to be left at the beginning
 of the ROM for things like embedded controller firmware.
 
@@ -384,7 +384,7 @@ PAYLOAD_SEGMENT_BSS    0x20535342   The memory specified by the segment
 PAYLOAD_SEGMENT_PARAMS 0x41524150   The segment contains information for
                                      the payload
 PAYLOAD_SEGMENT_ENTRY  0x52544E45   The segment contains the entry point
-		  		    for the payload
+		       		    for the payload
 
 'compression' is the compression scheme for the segment.  Each segment can
 be independently compressed. There are three compression types defined by

Documentation/code_of_conduct.md

@@ -1,112 +0,0 @@
-# Code of Conduct
-
-This code of conduct outlines our rules and expectations for everybody
-participating in the coreboot community.
-
-## coreboot community etiquette
-
-We have a friendly and productive atmosphere on our mailing lists,
-development / code review tools, IRC chat rooms and when we meet in
-person.  Our principles evolve around the following:
-
-* It's not the user's fault if something goes wrong.
-* Attempt collaboration before conflict.
-* People who intentionally insult others (users, developers, corporations,
-  other projects, or the coreboot project itself) will be dealt with. See
-  policy below.
-* We are dealing with hardware with lots of undocumented pitfalls. It is quite
-  possible that you did everything right, but coreboot or its tools still
-  won't work for you.
-
-Refrain from insulting anyone or the group they belong to. Remember that
-people might be sensitive to other things than you are.
-
-Most of our community members are not native English speakers, thus
-misunderstandings can (and do) happen. Always assume that others are
-friendly and may have picked less-than-stellar wording by accident.
-
-If you have a grievance due to conduct in this community, we want to hear
-about it so we can handle the situation. Please contact our arbitration
-team directly: They will listen to you and react in a timely fashion.
-
-For transparency there is no alias or private mailing list address for
-you to reach out to, since we want to make sure that you know who will
-(and who won't) read your message.
-
-However since people might be on travel or otherwise be unavailable at
-times, consider reaching out to multiple persons.
-
-The team will treat your messages confidential as far as the law permits.
-For the purpose of knowing what law applies, the list provides the usual
-country of residence of each team member.
-
-## Unacceptable Behavior
-
-Unacceptable behaviors include: intimidating, harassing, abusive,
-discriminatory, derogatory or demeaning speech or actions by any
-participant in our community online, at all related events and in
-one-on-one communications carried out in the context of community
-business. Community event venues may be shared with members of the public;
-please be respectful to all patrons of these locations.
-
-Examples of behaviors we do not accept in our community:
-
-* harmful or prejudicial verbal or written comments related to gender,
-  sexual orientation, race, religion, disability;
-* inappropriate physical contact, and unwelcome sexual advances;
-* deliberate intimidation, stalking or following;
-* harassing photography or recording;
-* sustained disruption of talks or other events.
-
-Using this code of conduct aggressively against other people in the
-community might also be harassment. Be considerate when enforcing the code
-of conduct and always try to listen to both sides before passing judgment.
-
-## Consequences of Unacceptable Behavior
-
-Unacceptable behavior from any community member, including sponsors and
-those with decision-making authority, will not be tolerated.
-
-Anyone asked to stop unacceptable behavior is expected to comply
-immediately.
-
-If a community member engages in unacceptable behavior, the community
-organizers may take any action they deem appropriate, up to and including
-a temporary ban or permanent expulsion from the community without warning
-(and without refund in the case of a paid event). Community organizers
-can be part of the arbitration team, or organizers of events and online
-communities.
-
-## If You Witness or Are Subject to Unacceptable Behavior
-
-If you are subject to or witness unacceptable behavior, or have any other
-concerns, please notify someone from the arbitration team immediately.
-
-
-## Addressing Grievances
-
-If you feel you have been falsely or unfairly accused of violating this
-Code of Conduct, you should notify the arbitration team with a concise
-description of your grievance.
-
-## Scope
-
-We expect all community participants (contributors, paid or otherwise;
-sponsors; and other guests) to abide by this Code of Conduct in all
-community venues, online and in-person, as well as in all one-on-one
-communications pertaining to community business.
-
-## Contact info
-
-Our arbitration team consists of the following people
-* Stefan Reinauer <stefan.reinauer@coreboot.org> (USA)
-* Patrick Georgi <patrick@coreboot.org> (Germany)
-* Ronald Minnich <rminnich@coreboot.org> (USA)
-* Marc Jones <mjones@coreboot.org> (USA)
-
-## License and attribution
-
-This Code of Conduct is distributed under
-a [Creative Commons Attribution-ShareAlike
-license](http://creativecommons.org/licenses/by-sa/3.0/).  It is based
-on the [Citizen Code of Conduct](http://citizencodeofconduct.org/)

Documentation/codeflow.svg

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Documentation/conf.py

@@ -1,6 +1,4 @@
 # -*- coding: utf-8 -*-
-import subprocess
-from recommonmark.parser import CommonMarkParser
 
 # Add any paths that contain templates here, relative to this directory.
 templates_path = ['_templates']
@@ -13,17 +11,17 @@ master_doc = 'index'
 
 # General information about the project.
 project = u'coreboot'
-copyright = u'CC-by 4.0 the coreboot project'
+copyright = u'the coreboot project'
 author = u'the coreboot project'
 
 # The version info for the project you're documenting, acts as replacement for
 # |version| and |release|, also used in various other places throughout the
 # built documents.
 #
-# The full version, including alpha/beta/rc tags.
-release = subprocess.check_output(('git', 'describe')).decode("utf-8")
 # The short X.Y version.
-version = release.split("-")[0]
+version = u'4.7'
+# The full version, including alpha/beta/rc tags.
+release = u'4.7' # TODO: use 'git describe'
 
 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.
@@ -121,7 +119,7 @@ latex_documents = [
 #
 # latex_appendices = []
 
-# If false, will not define \strong, \code,	itleref, \crossref ... but only
+# It false, will not define \strong, \code, 	itleref, \crossref ... but only
 # \sphinxstrong, ..., \sphinxtitleref, ... To help avoid clash with user added
 # packages.
 #
@@ -157,14 +155,9 @@ texinfo_documents = [
      'Miscellaneous'),
 ]
 
-enable_auto_toc_tree = True
-
-class MyCommonMarkParser(CommonMarkParser):
-    # remove this hack once upsteam RecommonMark supports inline code
-    def visit_code(self, mdnode):
-        from docutils import nodes
-        n = nodes.literal(mdnode.literal, mdnode.literal)
-        self.current_node.append(n)
+source_parsers = {
+    '.md': 'recommonmark.parser.CommonMarkParser',
+}
 
 # Documents to append as an appendix to all manuals.
 #
@@ -182,14 +175,14 @@ class MyCommonMarkParser(CommonMarkParser):
 #
 # texinfo_no_detailmenu = False
 
+enable_auto_toc_tree = True
+
 
 def setup(app):
     from recommonmark.transform import AutoStructify
-    app.add_source_parser('.md', MyCommonMarkParser)
-
     app.add_config_value('recommonmark_config', {
         'enable_auto_toc_tree': True,
-        'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
+        'enable_auto_doc_ref': True,
         'enable_eval_rst': True,
         'url_resolver': lambda url: '/' + url
     }, True)

Documentation/flash_tutorial/ext_power.md

@@ -1,28 +0,0 @@
-# Flashing firmware externally supplying direct power
-
-**WARNING:** Never use a high current rated power supply, like PC ATX power
-             supply. It'll literally melt your PCB traces on short circuit.
-
-On some mainboards the flash IC Vcc pin is connected to a diode, which prevents
-powering the rest of the board.
-
-![][flash_ic_diode]
-
-Please have a look at the mainboard specific documentation for details.
-
-On those boards it's safe to use a programmer and supply power externally.
-
-**WARNING:** Verify that you apply the correct voltage!
-
-## USB programmer
-USB programmers are usually current limited by the host USB hub. On USB 2.0
-ports the limit is 500mA, which is sufficient to power the flash. Those are
-the best choice as they are stateless and have a fast power on reset cycle.
-
-## Single board computers (like BeagleBone Black / RPi)
-Be careful when connecting a flash chip, especially when using a Pomona
-test-clip. A short circuit or overcurrent (250mA) causes a brown-out reset,
-resulting in a reboot of the running operating system (and possible loss of
-remote shell).
-
-[flash_ic_diode]: flash_ic_diode.svg

Documentation/flash_tutorial/ext_standalone.md

@@ -1,23 +0,0 @@
-# Flashing firmware standalone
-
-If none of the other methods work, there are three possibilities:
-
-## Desolder
-You must remove or desolder the flash IC before you can flash it.
-It's recommended to solder a socket in place of the flash IC.
-
-When flashing the IC, always connect all input pins.
-If in doubt, pull /WP, /HOLD, /RESET and alike up towards Vcc.
-
-## SPI flash emulator
-If you are a developer, you might want to use an [EM100Pro] instead, which sets
-the onboard flash on hold, and allows to run custom firmware.
-It provides a very fast development cycle without actually writing to flash.
-
-## SPI flash overwrite
-It is possible to set the onboard flash on hold and use another flash chip.
-Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC
-low, and /HOLD of your replacement flash IC high.
-
-
-[EM100Pro]: https://www.dediprog.com/product/EM100Pro

Documentation/flash_tutorial/flash_ic_diode.svg

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Documentation/flash_tutorial/flash_ic_no_diode.svg

@@ -1,55 +0,0 @@
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-</svg>

Documentation/flash_tutorial/index.md

@@ -1,111 +0,0 @@
-# Flashing firmware tutorial
-
-Updating the firmware is possible using the **internal method**, where the updates
-happen from a running system, or using the **external method**, where the system
-is in a shut down state and an external programmer is attached to write into the
-flash IC.
-
-## Contents
-
-* [Flashing internaly](int_flashrom.md)
-* [Flashing firmware standalone](ext_standalone.md)
-* [Flashing firmware externally supplying direct power](ext_power.md)
-* [Flashing firmware externally without supplying direct power](no_ext_power.md)
-
-## General advice
-
-* It's recommended to only flash the BIOS region.
-* Always verify the firmware image.
-* If you flash externally and have transmission errors:
-  * Use short wires
-  * Reduce clock frequency
-  * Check power supply
-  * Make sure that there are no other bus masters (EC, ME, SoC, ...)
-
-## Internal method
-
-This method using [flashrom] is available on many platforms, as long as they
-aren't locked down.
-
-There are various protection schemes that make it impossible to modify or
-replace a firmware from a running system. coreboot allows to disable these
-mechanisms, making it possible to overwrite (or update) the firmware from a
-running system.
-
-Usually you must use the **external method** once to install a retrofitted
-coreboot and then you can use the **internal method** for future updates.
-
-There are multiple ways to update the firmware:
-* Using flashrom's *internal* programmer to directly write into the firmware
-  flash IC, running on the target machine itself
-* A proprietary software to update the firmware, running on the target machine
-  itself
-* A UEFI firmware update capsule
-
-More details on flashrom's
-* [internal programmer](int_flashrom.md)
-
-## External method
-
-External flashing is possible on many platforms, but requires disassembling
-the target hardware. You need to buy a flash programmer, that
-exposes the same interface as your flash IC (likely SPI).
-
-Please also have a look at the mainboard-specific documentation for details.
-
-After exposing the firmware flash IC, read the schematics and use one of the
-possible methods:
-
-* [Flashing firmware standalone](ext_standalone.md)
-* [Flashing firmware externally supplying direct power](ext_power.md)
-* [Flashing firmware externally without supplying direct power](no_ext_power.md)
-
-**WARNING:** Using the wrong method or accidentally using the wrong pinout might
-  permanently damage your hardware!
-
-**WARNING:** Do not rely on dots *painted* on flash ICs to orient the pins!
-Any dots painted on flash ICs may only indicate if they've been tested.  Dots
-that appear in datasheets to indicate pin 1 correspond to some kind of physical
-marker, such as a drilled hole, or one side being more flat than the other.
-
-## Using a layout file
-On platforms where the flash IC is shared with other components you might want
-to write only a part of the flash IC. On Intel for example there are IFD, ME and
-GBE which don't need to be updated to install coreboot.
-To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD
-untouched, you can use a layout file, which can be created with ifdtool and a backup
-of the original firmware.
-
-```bash
-ifdtool -f rom.layout backup.rom
-```
-
-and looks similar to:
-
-```
-00000000:00000fff fd
-00500000:00bfffff bios
-00003000:004fffff me
-00001000:00002fff gbe
-```
-
-By specifying *-l* and *-i* [flashrom] writes a single region:
-```bash
-flashrom -l rom.layout -i bios -w coreboot.rom -p <programmer>
-```
-
-## Using an IFD to determine the layout
-flashrom version 1.0 supports reading the layout from the IFD (first 4KiB of
-the ROM). You don't need to manually specify a layout it, but it only works
-under the following conditions:
-
-* Only available on Intel ICH7+
-* There's only one flash IC when flashing externally
-
-```bash
-flashrom --ifd -i bios -w coreboot.rom -p <programmer>
-```
-
-**TODO** explain FMAP regions, normal/fallback mechanism, flash lock mechanisms
-
-[flashrom]: https://www.flashrom.org/Flashrom

Documentation/flash_tutorial/int_flashrom.md

@@ -1,19 +0,0 @@
-# Flashing firmware internally
-
-**WARNING:** If you flash a broken firmware and have no recovery mechanism, you
-             must use the **external method** to flash a working firmware again.
-
-## Using flashrom
-This method does only work on Linux, if it isn't locked down.
-You may also need to boot with 'iomem=relaxed' in the kernel command
-line if CONFIG_IO_STRICT_DEVMEM is set.
-
-
-For more details please also check [flashrom's wiki].
-Use the programmer *internal* to flash *coreboot.rom* internally:
-
-```bash
-flashrom -p internal -w coreboot.rom
-```
-
-[flashrom's wiki]: https://www.flashrom.org/Flashrom

Documentation/flash_tutorial/no_ext_power.md

@@ -1,22 +0,0 @@
-# Flashing firmware externally supplying no power
-
-On some mainboards the flash IC's Vcc pin is connected to the internal
-power-rail, powering the entire board if the flash IC is powered externally.
-Likely it powers other chips which access the flash IC, preventing the external
-programmer from reading/writing the chip. It also violates the components'
-power sequence, bringing the ICs into an undefined state.
-
-![][flash_ic_no_diode]
-
-Please have a look at the mainboard specific documentation for details.
-
-On those boards it's recommended to use a programmer without supplying power
-externally.
-
-The key to read and write the flash IC is to put the machine into *S3* sleep-
-state or *S5* sleep-state *maybe* with Wake-On-LAN enabled.
-Another option that sometimes works is to keep the device in reset. This method requires
-knowledge of the board schematics and might require hardware modifications.
-Use a multimeter to make sure the flash IC is powered in those sleep states.
-
-[flash_ic_no_diode]: flash_ic_no_diode.svg

Documentation/gerrit_guidelines.md

@@ -13,8 +13,8 @@ here, please discuss it in the mailing list to get this document  updated.
 Don't just assume that it's okay, even if someone on IRC says it is.
 
 
-Summary
--------
+Summary:
+--------
 These are the expectations for committing, reviewing, and submitting code
 into coreboot git and gerrit. While breaking individual rules may not have
 immediate consequences, the coreboot leadership may act on repeated or
@@ -33,8 +33,8 @@ addresses.
 * Don’t submit patches that you know will break other platforms.
 
 
-More detail
------------
+More detail:
+------------
 * Don't violate the licenses. If you're submitting code that you didn't
 write yourself, make sure the license is compatible with the license of the
 project you're submitting the changes to. If you’re submitting code that
@@ -98,8 +98,8 @@ must at least provide a path that will allow other platforms to continue
 working.
 
 
-Recommendations for gerrit activity
------------------------------------
+Recommendations for gerrit activity:
+------------------------------------
 These guidelines are less strict than the ones listed above. These are more
 of the “good idea” variety. You are requested to follow the below
 guidelines, but there will probably be no actual consequences if they’re
@@ -150,8 +150,8 @@ together so people can easily see the connection at the top level of
 gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
-commits with the i915-kernel-x60 set, use the command:
-        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
+commits with the the i915-kernel-x60 set, use the command:
+        git push origin HEAD:refs/for/master/i915-kernel-x60
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
@@ -167,7 +167,7 @@ as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
 draft commits, so that only explicitly added reviewers will see them. These
 sorts of patches are frequently posted as ideas or RFCs for the community
 to look at. To push a draft, use the command:
-        git push origin HEAD:refs/for/master%private,wip
+        git push origin HEAD:refs/drafts/master
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a
@@ -251,8 +251,8 @@ The script 'util/gitconfig/rebase.sh' can be used to help automate this.
 Other tags such as 'Commit-Queue' can simply be removed.
 
 
-Expectations contributors should have
--------------------------------------
+Expectations contributors should have:
+--------------------------------------
 * Don't expect that people will review your patch unless you ask them to.
 Adding other people as reviewers is the easiest way. Asking for reviews for
 individual patches in the IRC channel, or by sending a direct request to an

Documentation/getting_started/index.md

@@ -1,8 +0,0 @@
-# Getting Started
-
-* [Build System](build_system.md)
-* [Submodules](submodules.md)
-* [Kconfig](kconfig.md)
-* [Gerrit Guidelines](gerrit_guidelines.md)
-* [Documentation License](license.md)
-* [Writing Documentation](writing_documentation.md)

Documentation/getting_started/license.md

@@ -1,164 +0,0 @@
-# coreboot documentation license
-
-Files under Documentation/ are licensed under CC-BY 4.0 terms, printed below.
-As an exception, files under Documentation/ with a history older than 2017-05-24
-might be under different licenses (but should be cleared up ASAP).
-
-## Attribution 4.0 International
-
-Creative Commons Corporation (“Creative Commons”) is not a law firm and does not provide legal services or legal advice. Distribution of Creative Commons public licenses does not create a lawyer-client or other relationship. Creative Commons makes its licenses and related information available on an “as-is” basis. Creative Commons gives no warranties regarding its licenses, any material licensed under their terms and conditions, or any related information. Creative Commons disclaims all liability for damages resulting from their use to the fullest extent possible.
-
-### Using Creative Commons Public Licenses
-
-Creative Commons public licenses provide a standard set of terms and conditions that creators and other rights holders may use to share original works of authorship and other material subject to copyright and certain other rights specified in the public license below. The following considerations are for informational purposes only, are not exhaustive, and do not form part of our licenses.
-
-* __Considerations for licensors:__ Our public licenses are intended for use by those authorized to give the public permission to use material in ways otherwise restricted by copyright and certain other rights. Our licenses are irrevocable. Licensors should read and understand the terms and conditions of the license they choose before applying it. Licensors should also secure all rights necessary before applying our licenses so that the public can reuse the material as expected. Licensors should clearly mark any material not subject to the license. This includes other CC-licensed material, or material used under an exception or limitation to copyright. [More considerations for licensors](http://wiki.creativecommons.org/Considerations_for_licensors_and_licensees#Considerations_for_licensors).
-
-* __Considerations for the public:__ By using one of our public licenses, a licensor grants the public permission to use the licensed material under specified terms and conditions. If the licensor’s permission is not necessary for any reason–for example, because of any applicable exception or limitation to copyright–then that use is not regulated by the license. Our licenses grant only permissions under copyright and certain other rights that a licensor has authority to grant. Use of the licensed material may still be restricted for other reasons, including because others have copyright or other rights in the material. A licensor may make special requests, such as asking that all changes be marked or described. Although not required by our licenses, you are encouraged to respect those requests where reasonable. [More considerations for the public](http://wiki.creativecommons.org/Considerations_for_licensors_and_licensees#Considerations_for_licensees).
-
-## Creative Commons Attribution 4.0 International Public License
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-By exercising the Licensed Rights (defined below), You accept and agree to be bound by the terms and conditions of this Creative Commons Attribution 4.0 International Public License ("Public License"). To the extent this Public License may be interpreted as a contract, You are granted the Licensed Rights in consideration of Your acceptance of these terms and conditions, and the Licensor grants You such rights in consideration of benefits the Licensor receives from making the Licensed Material available under these terms and conditions.
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-### Section 3 – License Conditions.
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-   3. If requested by the Licensor, You must remove any of the information required by Section 3(a)(1)(A) to the extent reasonably practicable.
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-   4. If You Share Adapted Material You produce, the Adapter's License You apply must not prevent recipients of the Adapted Material from complying with this Public License.
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-### Section 4 – Sui Generis Database Rights.
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-
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-For the avoidance of doubt, this Section 4 supplements and does not replace Your obligations under this Public License where the Licensed Rights include other Copyright and Similar Rights.
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-### Section 5 – Disclaimer of Warranties and Limitation of Liability.
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-b. __To the extent possible, in no event will the Licensor be liable to You on any legal theory (including, without limitation, negligence) or otherwise for any direct, special, indirect, incidental, consequential, punitive, exemplary, or other losses, costs, expenses, or damages arising out of this Public License or use of the Licensed Material, even if the Licensor has been advised of the possibility of such losses, costs, expenses, or damages. Where a limitation of liability is not allowed in full or in part, this limitation may not apply to You.__
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-

Documentation/getting_started/writing_documentation.md

@@ -1,110 +0,0 @@
-# coreboot documentation guidelines
-
-> Documentation is like sex: when it is good, it is very, very good;
-> and when it is bad, it is better than nothing.
-
-That said please always try to write documentation! One problem in the
-firmware development is the missing documentation. In this document
-you will get a brief introduction how to write, submit and publish
-documenation to coreboot.
-
-## Preparations
-
-coreboot uses [Sphinx] documentation tool. We prefer the markdown format
-over reStructuredText so only embedded ReST is supported. Checkout the
-[Markdown Guide] for more information.
-
-### Install Sphinx
-
-Please follow this official [guide] to install sphinx.
-You will also need python-recommonmark for sphinx to be able to handle
-markdown documenation.
-
-The recommended version is sphinx 1.7.7, sphinx_rtd_theme 0.4.1 and
-recommonmark 0.4.0.
-
-### Optional
-
-Install [shpinx-autobuild] for rebuilding markdown/rst sources on the fly!
-
-## Basic and simple rules
-
-The following rules should be followed in order to get it at least reviewed
-on [review.coreboot.org].
-
-Documentation:
-
-1.  Must be written in **markdown** with **embedded reStructuredText**
-    format.
-2.  Must be written in **English**.
-3.  Must be placed into **Documentation/** directory subfolder.
-4.  Should follow the same directory structure as **src/** when practical.
-5.  Must be referenced from within other markdown files
-6.  The commit must follow the [Gerrit Guidelines].
-7.  Must have all **lowercase filenames**.
-8.  Running text should have a visible width of about **72 chars**.
-9.  Should not **duplicate** documentation, but reference it instead.
-10.  Must not include the same picture in multiple markdown files.
-11.  Images should be kept small. They should be under 700px in width, as
-     the current theme doesn't allow bigger images.
-12.  Shouldn't cover implementation details; for details, the code is the
-     reference.
-
-## Referencing markdown documents
-
-Starting with Sphinx 1.6 recommonmark's *auto_doc_ref* feature is broken.
-To reference documents use the TOC tree or inline RST code.
-
-## Markdown and Tables
-
-Under Sphinx markdown tables are not supported. Therefore you can use following
-code block to write tables in reStructuredText and embed them into the markdown:
-
-    ```eval_rst
-    +------------+------------+-----------+
-    | Header 1   | Header 2   | Header 3  |
-    +============+============+===========+
-    | body row 1 | column 2   | column 3  |
-    +------------+------------+-----------+
-    | body row 2 | Cells may span columns.|
-    +------------+------------+-----------+
-    | body row 3 | Cells may  | - Cells   |
-    +------------+ span rows. | - contain |
-    | body row 4 |            | - blocks. |
-    +------------+------------+-----------+
-    ``` #just a code block is enough
-
-## TocTree
-
-To make sure that all documents are included into the final documentation, you
-must reference each document from at least one *toctree*. The *toctree* must
-only reference files in the same folder or in subfolders !
-To create a toctree, simply use a bullet list or numbered list with a single
-reference. References in regular text aren't considered as *toctree* .
-This feature is enabled by recommonmark's *enable_auto_toc_tree* .
-
-**Example toctree:**
-
-```
-* [Chapter 1](chapter1.md)
-* [Chapter 2](chapter2.md)
-* [Subchapter](sub/index.md)
-```
-
-```
-1. [Chapter 1](chapter1.md)
-2. [Chapter 2](chapter2.md)
-```
-
-If you do only reference the document, but do not include it in any toctree,
-you'll see the following warning:
-**WARNING: document isn't included in any toctree**
-
-[coreboot]: https://coreboot.org
-[Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation
-[shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild
-[guide]: http://www.sphinx-doc.org/en/stable/install.html
-[Sphinx]: http://www.sphinx-doc.org/en/master/
-[Markdown Guide]: https://www.markdownguide.org/
-[Gerrit Guidelines]: https://doc.coreboot.org/gerrit_guidelines.html
-[review.coreboot.org]: https://review.coreboot.org

Documentation/gfx/libgfxinit.md

@@ -76,11 +76,8 @@ know through which interface the EDID can be queried:
     select GFX_GMA_ANALOG_I2C_HDMI_D
 
 Beside Kconfig options, *libgfxinit* needs to know which ports are
-implemented on a board and should be probed for displays. The mapping
-between the physical ports and these entries depends on the hardware
-implementation and can be recovered by testing or studying the output
-of `intelvbttool` or `intel_vbt_decode`.
-Each board has to implement the package `GMA.Mainboard` with a list:
+implemented on a board and should be probed for displays. Each
+board has to implement the package `GMA.Mainboard` with a list:
 
     ports : HW.GFX.GMA.Display_Probing.Port_List;
 

Documentation/index.md

@@ -1,4 +1,5 @@
-# Welcome to the coreboot documentation
+Welcome to coreboot's documentation!
+====================================
 
 This is the developer documentation for [coreboot](https://coreboot.org).
 It is built from Markdown files in the
@@ -7,22 +8,14 @@ directory in the source code.
 
 Contents:
 
-* [Getting Started](getting_started/index.md)
-* [Rookie Guide](lessons/index.md)
-* [Code of Conduct](code_of_conduct.md)
+* [Lesson 2: Submitting a patch to coreboot.org](Lesson2.md)
+* [Gerrit Etiquette and Guidelines](gerrit_guidelines.md)
+* [coreboot's build system](build_system.md)
+* [Kconfig in coreboot](core/Kconfig.md)
+* [Use of git submodules in coreboot](submodules.md)
 * [Timestamps](timestamp.md)
-* [Intel IFD Binary Extraction](Binary_Extraction.md)
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
 * [ABI data consumption](abi-data-consumption.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
-* [Architecture-specific documentation](arch/index.md)
-* [Northbridge-specific documentation](northbridge/index.md)
-* [System on Chip-specific documentation](soc/index.md)
-* [Mainboard-specific documentation](mainboard/index.md)
-* [Payload-specific documentation](lib/payloads/index.md)
-* [SuperIO-specific documentation](superio/index.md)
-* [Vendorcode-specific documentation](vendorcode/index.md)
-* [Utilities](util.md)
-* [Release notes for past releases](releases/index.md)
-* [Flashing firmware tutorial](flash_tutorial/index.md)
+* [Sandy Bridge Raminit](Intel/NativeRaminit/Sandybridge.md)

Documentation/lessons/index.md

@@ -1,4 +0,0 @@
-# Rookie Guide
-
-* [Lesson 1: Starting from scratch](lesson1.md)
-* [Lesson 2: Submitting a patch to coreboot.org](lesson2.md)

Documentation/lessons/lesson1.md

@@ -1,168 +0,0 @@
-coreboot lesson 1 - Starting from scratch
-=========================================
-
-From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for
-a very basic build:
-
-Download, configure, and build coreboot
----------------------------------------
-
-### Step 1 - Install tools and libraries needed for coreboot
-    $ sudo apt-get install -y bison build-essential curl flex git gnat-5 libncurses5-dev m4 zlib1g-dev
-
-### Step 2 - Download coreboot source tree
-    $ git clone https://review.coreboot.org/coreboot
-    $ cd coreboot
-
-### Step 3 - Build the coreboot toolchain
-Please note that this can take a significant amount of time
-
-    $ make crossgcc-i386 CPUS=$(nproc)
-
-Also note that you can possibly use your system toolchain, but the results are
-not reproducible, and may have issues, so this is not recommended.  See step 5
-to use your system toolchain.
-
-### Step 4 - Build the payload - coreinfo
-    $ make -C payloads/coreinfo olddefconfig
-    $ make -C payloads/coreinfo
-
-### Step 5 - Configure the build
-
-##### Configure your mainboard
-    $ make menuconfig
-       select 'Mainboard' menu
-       Beside 'Mainboard vendor' should be '(Emulation)'
-       Beside 'Mainboard model' should be 'QEMU x86 i440fx/piix4'
-       select < Exit >
-These should be the default selections, so if anything else was set, run
-`make distclean` to remove your old config file and start over.
-
-##### Optionally use your system toolchain (Again, not recommended)
-       select 'General Setup' menu
-       select 'Allow building with any toolchain'
-       select < Exit >
-
-##### Select the payload
-       select 'Payload' menu
-       select 'Add a Payload'
-       choose 'An Elf executable payload'
-       select 'Payload path and filename'
-       enter 'payloads/coreinfo/build/coreinfo.elf'
-       select < Exit >
-       select < Exit >
-       select < Yes >
-
-##### check your configuration (optional step):
-
-    $ make savedefconfig
-    $ cat defconfig
-
-There should only be two lines (or 3 if you're using the system toolchain):
-
-    CONFIG_PAYLOAD_ELF=y
-    CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
-
-### Step 6 - build coreboot
-    $ make
-
-At the end of the build, you should see:
-
-    Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)
-
-This means your build was successful. The output from the build is in the build
-directory. build/coreboot.rom is the full rom file.
-
-Test the image using QEMU
--------------------------
-
-### Step 7 - Install QEMU
-    $ sudo apt-get install -y qemu
-
-### Step 8 - Run QEMU
-Start QEMU, and point it to the ROM you just built:
-
-    $ qemu-system-x86_64 -bios build/coreboot.rom -serial stdio
-
-You should see the serial output of coreboot in the original console window, and
-a new window will appear running the coreinfo payload.
-
-Summary
--------
-
-### Step 1 summary - Install tools and libraries needed for coreboot
-You installed the minimum additional requirements for ubuntu to download and
-build coreboot. Ubuntu already has most of the other tools that would be
-required installed by default.
-
-* `build-essential` is the basic tools for doing builds.  It comes pre-installed
-on some Ubuntu flavors, and not on others.
-* `git` is needed to download coreboot from the coreboot git repository.
-* `libncurses5-dev` is needed to build the menu for 'make menuconfig'
-* `m4, bison, curl, flex, gnat-5, zlib1g-dev` are needed to build the coreboot
-toolchain.
-
-If you started with a different distribution, you might need to install many
-other items which vary by distribution.
-
-### Step 2 summary - Download coreboot source tree
-This will download a 'read-only' copy of the coreboot tree. This just means
-that if you made changes to the coreboot tree, you couldn't immediately
-contribute them back to the community. To pull a copy of coreboot that would
-allow you to contribute back, you would first need to sign up for an account on
-gerrit.
-
-### Step 3 summary - Build the coreboot toolchain.
-This builds one of the coreboot cross-compiler toolchains for X86 platforms.
-Because of the variability of compilers and the other required tools between
-the various operating systems that coreboot can be built on, coreboot supplies
-and uses its own cross-compiler toolchain to build the binaries that end up as
-part of the coreboot ROM. The toolchain provided by the operating system (the
-'host toolchain') is used to build various tools that will run on the local
-system during the build process.
-
-### Step 4 summary - Build the payload
-To actually do anything useful with coreboot, you need to build a payload to
-include in the rom. The idea behind coreboot is that it does the minimum amount
-possible before passing control of the machine to a payload. There are various
-payloads such as grub or SeaBIOS that are typically used to boot the operating
-system. Instead, we used coreinfo, a small demonstration payload that allows the
-user to look at various things such as memory and the contents of coreboot's
-cbfs - the pieces that make up the coreboot rom.
-
-### Step 5 summary - Configure the build
-This step configures coreboot's build options using the menuconfig interface to
-Kconfig. Kconfig is the same configuration program used by the linux kernel. It
-allows you to enable, disable, and change various values to control the coreboot
-build process, including which mainboard(motherboard) to use, which toolchain to
-use, and how the runtime debug console should be presented and saved.
-Anytime you change mainboards in Kconfig, you should always run `make distclean`
-before running `make menuconfig`. Due to the way that Kconfig works, values will
-be kept from the previous mainboard if you skip the clean step. This leads to a
-hybrid configuration which may or may not work as expected.
-
-### Step 6 summary - Build coreboot
-You may notice that a number of other pieces are downloaded at the beginning of
-the build process. These are the git submodules used in various coreboot builds.
-By default, the _blobs_ submodule is not downloaded. This git submodule may be
-required for other builds for microcode or other binaries. To enable downloading
-this submodule, select the option "Allow use of binary-only repository" in the
-"General Setup" menu of Kconfig
-This attempts to build the coreboot rom. The rom file itself ends up in the
-build directory as 'coreboot.rom'. At the end of the build process, the build
-displayed the contents of the rom file.
-
-### Step 7 summary - Install QEMU
-QEMU is a processor emulator which we can use to show coreboot
-
-### Step 8 summary - Run QEMU
-Here's the command line broken down:
-* `qemu-system-x86_64`
-This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to
-ISA bridge.
-* `-bios build/coreboot.rom`
-Use the bios rom image that we just built. If this is left off, the standard
-SeaBIOS image that comes with QEMU is used.
-* `-serial stdio`
-Send the serial output to the console. This allows you to view the coreboot
-debug output.

Documentation/lessons/lesson2.md

@@ -1,291 +0,0 @@
-# coreboot Lesson 2: Submitting a patch to coreboot.org
-
-## Part 1: Setting up an account at coreboot.org
-
-If you already have an account, skip to Part 2.
-
-Otherwise, go to <https://review.coreboot.org> in your preferred web browser.
-Select **Register** in the upper right corner.
-
-Select the appropriate sign-in. For example, if you have a Google account,
-select **Google OAuth2** (gerrit-oauth-provider plugin)".**Note:** Your
-username for the account will be the username of the account you used to
-sign-in with. (ex. your Google username).
-
-## Part 2a: Set up RSA Private/Public Key
-
-If you prefer to use an HTTP password instead, skip to Part 2b.
-
-For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
-<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh)>
-and follow the instructions there. Then, skip to Part 3.
-
-Additionally, that section of the Web site provides explanation on starting
-an ssh-agent, which may be particularly helpful for those who anticipate
-frequently uploading changes.
-
-If you instead prefer to have review.coreboot.org specific instructions,
-follow the steps below. Note that this particular section may have the
-most up-to-date instructions.
-
-If you do not have an RSA key set up on your account already (as is the case
-with a newly created account), follow the instructions below; otherwise,
-doing so could overwrite an existing key.
-
-In the upper right corner, select your name and click on **Settings**.
-Select **SSH Public Keys** on the left-hand side.
-
-In a terminal, run "ssh-keygen" and confirm the default path ".ssh/id_rsa".
-
-Make a passphrase -- remember this phrase. It will be needed whenever you use
-this RSA Public Key. **Note:** You might want to use a short password, or
-forego the password altogether as you will be using it very often.
-
-Open "id_rsa.pub", copy all contents and paste into the textbox under
-"Add SSH Public Key" in the https://review.coreboot.org webpage.
-
-## Part 2b: Setting up an HTTP Password
-
-Alternatively, instead of using SSH keys, you can use an HTTP password. To do so,
-after you select your name and click on **Settings** on the left-hand side, rather
-than selecting **SSH Public Keys**, select **HTTP Password**.
-
-Click **Generate Password**. This should fill the "Password" box with a password. Copy
-the password, and add the following to your $HOME/.netrc file:
-
-	machine review.coreboot.org login YourUserNameHere password YourPasswordHere
-
-where YourUserNameHere is your username, and YourPasswordHere is the password you
-just generated.
-
-## Part 3: Clone coreboot and configure it for submitting patches
-
-On Gerrit, click on the **Browse** tab in the upper left corner and select
-**Repositories**.  From the listing, select the "coreboot" repo.  You may have
-to click the next page arrow at the bottom a few times to find it.
-
-If you are using SSH keys, select **ssh** from the tabs under "Project
-coreboot" and run the "clone with commit-msg hook" command that's provided.
-This should prompt you for your id_rsa passphrase, if you previously set one.
-
-If you are using HTTP, instead, select **http** from the tabs under "Project coreboot"
-and run the command that appears
-
-Now is a good time to configure your global git identity, if you haven't
-already.
-
-	git config --global user.name "Your Name"
-	git config --global user.email "Your Email"
-
-Finally, enter the local git repository and set up repository specific hooks
-and other configurations.
-
-	cd coreboot
-	make gitconfig
-
-## Part 4: Submit a commit
-
-An easy first commit to make is fixing existing checkpatch errors and warnings
-in the source files. To see errors that are already present, build the files in
-the repository by running 'make lint' in the coreboot directory. Alternatively,
-if you want to run 'make lint' on a specific directory, run:
-
-	for file in $(git ls-files | grep src/amd/quadcore); do \
-	util/lint/checkpatch.pl --file $file --terse; done
-
-where <filepath> is the filepath of the directory (ex. src/cpu/amd/car).
-
-Any changes made to files under the src directory are made locally,
-and can be submitted for review.
-
-Once you finish making your desired changes, use the command line to stage
-and submit your changes. An alternative and potentially easier way to stage
-and submit commits is to use git cola, a graphical user interface for git. For
-instructions on how to do so, skip to Part 4b.
-
-## Part 4a: Using the command line to stage and submit a commit
-
-To use the command line to stage a commit, run
-
-	git add <filename>
-
-where `filename` is the name of your file.
-
-To commit the change, run
-
-	git commit -s
-
-**Note:** The -s adds a signed-off-by line by the committer. Your commit should be
-signed off with your name and email (i.e. **Your Name** **<Your Email>**, based on
-what you set with git config earlier).
-
-Running git commit first checks for any errors and warnings using lint. If
-there are any, you must go back and fix them before submitting your commit.
-You can do so by making the necessary changes, and then staging your commit again.
-
-When there are no errors or warnings, your default text editor will open.
-This is where you will write your commit message.
-
-The first line of your commit message is your commit summary. This is a brief
-one-line description of what you changed in the files using the template
-below:
-
-<filepath>: Short description
-*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors*
-**Note:** It is good practice to use present tense in your descriptions
-and do not punctuate your summary.
-
-Then hit Enter. The next paragraph should be a more in-depth explanation of the
-changes you've made to the files. Again, it is good practice to use present
-tense.
-*ex.  Fix space prohibited between function name and open parenthesis,
-line over 80 characters, unnecessary braces for single statement blocks,
-space required before open brace errors and warnings.*
-
-When you have finished writing your commit message, save and exit the text
-editor. You have finished committing your change. If, after submitting your
-commit, you wish to make changes to it, running "git commit --amend" allows
-you to take back your commit and amend it.
-
-When you are done with your commit, run 'git push' to push your commit to
-coreboot.org. **Note:** To submit as a draft, use
-'git push origin HEAD:refs/drafts/master' Submitting as a draft means that
-your commit will be on coreboot.org, but is only visible to those you add
-as reviewers.
-
-This has been a quick primer on how to submit a change to Gerrit for review
-using git.  You may wish to review the [Gerrit code review workflow
-documentation](https://gerrit-review.googlesource.com/Documentation/intro-user.html#code-review),
-especially if you plan to work on multiple changes at the same time.
-
-## Part 4b: Using git cola to stage and submit a commit
-
-If git cola is not installed on your machine, see
-https://git-cola.github.io/downloads.html for download instructions.
-
-After making some edits to src files, rather than run "git add," run
-'git cola' from the command line. You should see all of the files
-edited under "Modified".
-
-In the textbox labeled "Commit summary" provide a brief one-line
-description of what you changed in the files according to the template
-below:
-
-<filepath>: Short description
-*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors*
-**Note:** It is good practice to use present tense in your descriptions
-and do not punctuate your short description.
-
-In the larger text box labeled 'Extended description...' provide a more
-in-depth explanation of the changes you've made to the files. Again, it
-is good practice to use present tense.
-*ex.  Fix space prohibited between function name and open parenthesis,
-line over 80 characters, unnecessary braces for single statement blocks,
-space required before open brace errors and warnings.*
-
-Then press Enter two times to move the cursor to below your description.
-To the left of the text boxes, there is an icon with an downward arrow.
-Press the arrow and select "Sign Off." Make sure that you are signing off
-with your name and email (i.e. **Your Name** **<Your Email>**, based on what
-you set with git config earlier).
-
-Now, review each of your changes and mark either individual changes or
-an entire file as Ready to Commit by marking it as 'Staged'. To do
-this, select one file from the 'Modified' list. If you only want to
-submit particular changes from each file, then highlight the red and
-green lines for your changes, right click and select 'Stage Selected
-Lines'. Alternatively, if an entire file is ready to be committed, just
-double click on the file under 'Modified' and it will be marked as
-Staged.
-
-Once the descriptions are done and all the edits you would like to
-commit have been staged, press 'Commit' on the right of the text
-boxes.
-
-If the commit fails due to persisting errors, a text box will appear
-showing the errors. You can correct these errors within 'git cola' by
-right-clicking on the file in which the error occurred and selecting
-'Launch Diff Tool'. Make necessary corrections, close the Diff Tool and
-'Stage' the corrected file again. It might be necessary to refresh
-'git cola' in order for the file to be shown under 'Modified' again.
-Note: Be sure to add any other changes that haven't already been
-explained in the extended description.
-
-When ready, select 'Commit' again. Once all errors have been satisfied
-and the commit succeeds, move to the command line and run 'git push'.
-**Note:** To submit as a draft, use 'git push origin HEAD:refs/drafts/master'
-Submitting as a draft means that your commit will be on coreboot.org, but is
-only visible to those you add as reviewers.
-
-## Part 5: Getting your commit reviewed
-
-Your commits can now be seen on review.coreboot.org if you select “Your”
-and click on “Changes” and can be reviewed by others. Your code will
-first be reviewed by build bot (Jenkins), which will either give you a warning
-or verify a successful build; if so, your commit will receive a +1. Other
-users may also give your commit +1.  For a commit to be merged, it needs
-to receive a +2.**Note:** A +1 and a +1 does not make a +2. Only certain users
-can give a +2.
-
-## Part 6 (optional): bash-git-prompt
-
-To help make it easier to understand the state of the git repository
-without running 'git status' or 'git log', there is a way to make the
-command line show the status of the repository at every point. This
-is through bash-git-prompt.
-
-Instructions for installing this are found at:
-https://github.com/magicmonty/bash-git-prompt
-**Note:** Feel free to search for different versions of git prompt,
-as this one is specific to bash.
-
-Alternatively, follow the instructions below:
-Run the following two commands in the command line:
-
-    cd
-    git clone https://github.com/magicmonty/bash-git-prompt.git .bash-git-prompt --depth=1
-
-**Note:** cd will change your directory to your home directory, so the
-git clone command will be run there.
-
-Finally, open the ~/.bashrc file and append the following two lines:
-
-    GIT_PROMPT_ONLY_IN_REPO=1
-    source ~/.bash-git-prompt/gitprompt.sh
-
-Now, whenever you are in a git repository, it will continuously display
-its state.
-
-There also are additional configurations that you can change depending on your
-preferences. If you wish to do so, look at the "All configs for .bashrc" section
-on https://github.com/magicmonty/bash-git-prompt. Listed in that section are
-various lines that you can copy, uncomment and add to your .bashrc file to
-change the configurations. Example configurations include avoid fetching remote
-status, and supporting versions of Git older than 1.7.10.
-
-## Appendix: Miscellaneous Advice
-
-### Updating a commit after running git push:
-
-Suppose you would like to update a commit that has already been pushed to the
-remote repository. If the commit you wish to update is the most recent
-commit you have made, after making your desired changes, stage the files
-(either using git add or in git cola), and amend the commit. To do so,
-if you are using the command line, run "git commit --amend." If you are
-using git cola, click on the gear icon located on the upper left side under
-**Commit** and select **Amend Last Commit** in the drop down menu. Then, stage
-the files you have changed, commit the changes, and run git push to push the
-changes to the remote repository. Your change should be reflected in Gerrit as
-a new patch set.
-
-If, however, the commit you wish to update is not the most recent commit you
-have made, you will first need to checkout that commit. To do so, find the
-URL of the commit on <https://review.coreboot.org> and go to that page; if
-the commit is one that you previously pushed, it can be found by selecting
-**My** and then **Changes** in the upper left corner. To checkout this commit,
-in the upper right corner, click on **Download**, and copy the command listed
-next to checkout by clicking **Copy to clipboard**. Then, run the copied
-command in your coreboot repository. Now, the last commit should be the most
-recent commit to that patch; to update it, make your desired changes, stage
-the files, then amend and push the commit using the instructions in the above
-paragraph.

Documentation/lib/payloads/fit.md

@@ -1,167 +0,0 @@
-# Flattened uImage Tree documentation
-
-[uImage.FIT] is the new format used for uImage payloads developed by
-[U-boot].
-
-## Supported architectures
-
-* aarch64
-
-## Supported FIT sections
-
-The FIT can contain multiple sections, each holding a unique
-kernel, initrd or config. Out of the sections one kernel and
-one initrd is chosen, depending on the matching config.
-
-The config is selected depending on the compat string.
-
-The section must be named in order to be found by the FIT parser:
-
-* kernel
-* fdt
-* ramdisk
-
-## Architecture specifics
-
-The FIT parser needs architecure support.
-### aarch64
-The source code can be found in `src/arch/arm64/fit_payload.c`.
-
-On aarch64 the kernel (a section named 'kernel') must be in **Image**
-format and it needs a devicetree (a section named 'fdt') to boot.
-The kernel will be placed close to "*DRAMSTART*".
-
-### Other
-Other architectures aren't supported.
-
-## Supported compression
-
-The FIT image has to be included uncompressed into the CBFS. The sections
-inside the FIT image can use different compression schemes.
-
-Supported compression algorithms:
-* LZMA
-* LZ4
-* none
-
-## Compat string
-
-The config entries contain a compatible string, that is used to find a
-matching config.
-
-The following mainboard specific funtions provide the BOARDID and SKUID:
-
-```c
-uint32_t board_id(void);
-```
-
-```c
-uint32_t sku_id(void);
-```
-
-By default the following compat strings are added:
-
-* *CONFIG_MAINBOARD_VENDOR*,*CONFIG_MAINBOARD_PART_NUMBER*
-* *CONFIG_MAINBOARD_VENDOR*,*CONFIG_MAINBOARD_PART_NUMBER*-rev*BOARDID*
-* *CONFIG_MAINBOARD_VENDOR*,*CONFIG_MAINBOARD_PART_NUMBER*-rev*BOARDID*-sku*SKUID*
-
-Example:
-
-```
-cavium,cn8100_sff_evb
-```
-
-If *board_id()* or *sku_id()* return invalid, the single comapt string isn't added.
-
-You can add custom compat strings by calling:
-
-```c
-fit_add_compat_string(const char *str);
-```
-
-If no matching compat string is found, the default config is chosen.
-
-## Building FIT image
-
-The FIT image has to be built by calling `mkimage`. You can use
-the following example configuration:
-
-```
-/*
- * Simple U-Boot uImage source file containing a single kernel and FDT blob
- */
-
-/dts-v1/;
-
-/ {
-	description = "Simple image with single Linux kernel and FDT blob";
-	#address-cells = <1>;
-
-	images {
-		kernel {
-			description = "Vanilla Linux kernel";
-			data = /incbin/("Image.lzma");
-			type = "kernel";
-			arch = "arm64";
-			os = "linux";
-			compression = "lzma";
-			load = <0x80000>;
-			entry = <0x80000>;
-			hash-1 {
-				algo = "crc32";
-			};
-		};
-		fdt-1 {
-			description = "Flattened Device Tree blob";
-			data = /incbin/("target.dtb");
-			type = "flat_dt";
-			arch = "arm64";
-			compression = "none";
-			hash-1 {
-				algo = "crc32";
-			};
-		};
-		ramdisk-1 {
-			description = "Compressed Initramfs";
-			data = /incbin/("initramfs.cpio.xz");
-			type = "ramdisk";
-			arch = "arm64";
-			os = "linux";
-			compression = "none";
-			load = <00000000>;
-			entry = <00000000>;
-			hash-1 {
-				algo = "sha1";
-			};
-		};
-	};
-
-	configurations {
-		default = "conf-1";
-		conf-1 {
-			description = "Boot Linux kernel with FDT blob";
-			kernel = "kernel";
-			fdt = "fdt-1";
-			ramdisk = "ramdisk-1";
-		};
-	};
-};
-```
-
-Save it as ITS file `config.its` along with the other files defined here:
-* target.dtb
-* initramfs.cpio.xz
-* Image.lzma
-
-Generate the `uImage` that will be included into the CBFS by calling
-
-```bash
-mkimage -f config.its uImage
-```
-
-The generated file includes a compressed initrd **initramfs.cpio.xz**, which
-will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**,
-which will be decompressed by the FIT loader and an uncompressed devicetree blob.
-
-[uImage.FIT]: https://raw.githubusercontent.com/u-boot/u-boot/master/doc/uImage.FIT/howto.txt
-[U-Boot]: https://www.denx.de/wiki/U-Boot

Documentation/lib/payloads/index.md

@@ -1,11 +0,0 @@
-# Payload-specific documentation
-
-This section contains documentation about coreboot on specific payloads.
-
-Payloads are run after coreboot has initialized the hardware.
-coreboot supports multiple payloads, depending on the architecture of the
-selected mainboard.
-
-## FIT
-
-- [uImage.FIT support](fit.md)

Documentation/mainboard/asrock/h81m-hds.md

@@ -1,146 +0,0 @@
-# ASRock H81M-HDS
-
-This page describes how to run coreboot on the [ASRock H81M-HDS].
-
-## Required proprietary blobs
-
-This board currently requires a proprietary blob in order to initialise
-the RAM and a few other components. The blob largely consists of Intel's
-Memory Reference Code (shortened to mrc), and is just under 200 KiB
-in size. It is also known as a system agent binary. Unfortunately,
-it is not currently possible to distribute this as part of coreboot.
-However, the mrc can be obtained from a Haswell Chromebook firmware
-image, and you might find one online. The mrc from a ChromeOS image can
-be extracted with the following command. If extracting from a "standard"
-coreboot image, omit `-r RO_SECTION`.
-
-```bash
-cbfstool coreboot.rom extract -f mrc.bin -n mrc.bin -r RO_SECTION
-```
-
-Now, place mrc.bin in the root of the coreboot directory.
-Alternatively, place it anywhere you want, and set `MRC_FILE` to its
-location when building coreboot.
-
-## Building coreboot
-
-A fully working image should be possible just by setting your MAC
-address and obtaining the Haswell mrc. You can set the basic config
-with the following commands. However, it is strongly advised to use
-`make menuconfig` afterwards (or instead), so that you can see all of
-the settings.
-
-```bash
-make distclean # Note: this will remove your current config, if it exists.
-touch .config
-./util/scripts/config --enable VENDOR_ASROCK
-./util/scripts/config --enable BOARD_ASROCK_H81M_HDS
-./util/scripts/config --enable HAVE_MRC
-./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" # Fill this in!
-make olddefconfig
-```
-
-If you don't plan on using coreboot's serial console to collect logs,
-you might want to disable it at this point (`./util/scripts/config
---disable CONSOLE_SERIAL`). It should reduce the boot time by several
-seconds. However, a more flexible method is to change the console log
-level from within an OS using `util/nvramtool`, or with the `nvramcui`
-payload.
-
-Now, run `make` to build the coreboot image.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. By default, only
-the BIOS region of the flash is writable. If you wish to change any
-other region, such as the Management Engine or firmware descriptor, then
-an external programmer is required (unless you find a clever way around
-the flash protection).
-
-The following command may be used to flash coreboot:
-
-```bash
-sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
-```
-
-The use of `--noverify-all` is required since the Management Engine
-region is not readable even by the host.
-
-### External programming
-
-The flash chip is a 4 MiB socketed DIP-8 chip. Specifically, it's a
-Winbond W25Q32FV, whose datasheet can be found [here][W25Q32FV].
-The chip is located to the bottom right-hand side of the board. For
-a precise location, refer to section 1.4 (Motherboard Layout) of the
-[board manual], where the chip is labelled "32Mb BIOS". Take note of
-the chip's orientation, remove it from its socket, and flash it with
-an external programmer. For reference, the notch in the chip should be
-facing towards the bottom of the board.
-
-## Known issues
-
-- PCIe graphics is non-functional. The PCIe 16x slot doesn't work
-  with other devices, either.
-
-- The VGA port doesn't work until the OS reinitialises the display.
-
-- There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
-  readings from the PECI agent, but the required driver doesn't exist
-  in coreboot. The `coretemp` driver can still be used for accurate CPU
-  temperature readings from an OS.
-
-## Untested
-
-- parallel port
-- PS/2 keyboard
-- EHCI debug
-- TPM
-- infrared module
-- chassis intrusion header
-- chassis speaker header
-
-## Working
-
-- USB
-- S3 suspend/resume
-- Gigabit Ethernet
-- integrated graphics
-- PCIe (but not the 16x slot, see [Known issues](#known-issues))
-- SATA
-- PS/2 mouse
-- serial port
-- hardware monitor (see [Known issues](#known-issues))
-- onboard audio
-- front panel audio
-- initialisation with Haswell mrc version 1.6.1 build 2
-- graphics init with libgfxinit (see [Known issues](#known-issues))
-- flashrom under the vendor firmware
-- flashrom under coreboot
-- Wake-on-LAN
-- Using `me_cleaner`
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel Haswell                                    |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel Lynx Point (H81)                           |
-+------------------+--------------------------------------------------+
-| CPU              | Intel Haswell (LGA1150)                          |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6776                                  |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-[ASRock H81M-HDS]: https://www.asrock.com/mb/Intel/H81M-HDS/
-[W25Q32FV]: https://www.winbond.com/resource-files/w25q32fv%20revi%2010202015.pdf
-[flashrom]: https://flashrom.org/Flashrom
-[Board manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H81M-HDS.pdf

Documentation/mainboard/asus/p8h61-m_lx.md

@@ -1,111 +0,0 @@
-# ASUS P8H61-M LX
-
-This page describes how to run coreboot on the [ASUS P8H61-M LX].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | yes        |
-+---------------------+------------+
-| Model               | W25Q32BV   |
-+---------------------+------------+
-| Size                | 4 MiB      |
-+---------------------+------------+
-| Package             | DIP-8      |
-+---------------------+------------+
-| Write protection    | no         |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. By default, only
-the BIOS region of the flash is writable. If you wish to change any
-other region (Management Engine or flash descriptor), then an external
-programmer is required.
-
-The following command may be used to flash coreboot:
-
-```
-$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
-```
-
-The use of `--noverify-all` is required since the Management Engine
-region is not readable even by the host.
-
-## Known issues
-
-- S3 suspend/resume does not work. This is the case for both coreboot
-  and the vendor firmware, tested with Linux 4.9, Linux 4.17, and
-  OpenBSD 6.3. Interestingly, it is possible to resume from S3 with
-  Linux, but _only_ if the resume is started immediately after the
-  suspend.
-
-- There is no automatic, OS-independent fan control. This is because
-  the super I/O hardware monitor can only obtain valid CPU temperature
-  readings from the PECI agent, whose complete initialisation is not
-  publicly documented. The `coretemp` driver can still be used for
-  accurate CPU temperature readings.
-
-## Untested
-
-- PCIe graphics
-- parallel port
-- PS/2 keyboard
-- EHCI debug
-- S/PDIF audio
-
-## Working
-
-- USB
-- Gigabit Ethernet
-- integrated graphics
-- PCIe
-- SATA
-- PS/2 mouse
-- serial port
-- hardware monitor (see [Known issues](#known-issues) for caveats)
-- onboard audio
-- front panel audio
-- native raminit (2 x 2GB, DDR3-1333)
-- native graphics init (libgfxinit)
-- flashrom under the vendor firmware
-- flashrom under coreboot
-- Wake-on-LAN
-- Using `me_cleaner` (add `-S --whitelist EFFS,FCRS` if not using
-  `me_cleaner` as part of the coreboot build process).
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6776                                  |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-- [Board manual]
-- [Flash chip datasheet][W25Q32BV]
-
-[ASUS P8H61-M LX]: https://www.asus.com/Motherboards/P8H61M_LX/
-[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
-[flashrom]: https://flashrom.org/Flashrom
-[Board manual]: http://dlcdnet.asus.com/pub/ASUS/mb/LGA1155/P8H61_M_LX/E6803_P8H61-M_LX.zip

Documentation/mainboard/cavium/cn8100_sff_evb.md

@@ -1,76 +0,0 @@
-# CN81xx Evaluation-board SFF
-
-## Specs
-
-* 3 mini PCIe slots
-* 4 SATA ports
-* one USB3.0 A connector
-* 20Pin JTAG
-* 4 Gigabit Ethernet
-* 2 SFP+ connectors
-* PCIe x4 slot
-* UART over USB
-* eMMC Flash or MicroSD card slot for on-board storage
-* 1 Slot with DDR-4 memory with ECC support
-* SPI flash
-* MMC and uSD-card
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+----------------+
-| Type                | Value          |
-+=====================+================+
-| Socketed flash      | no             |
-+---------------------+----------------+
-| Model               | Micron 25Q128A |
-+---------------------+----------------+
-| Size                | 8 MiB          |
-+---------------------+----------------+
-| In circuit flashing | no             |
-+---------------------+----------------+
-| Package             | SOIC-8         |
-+---------------------+----------------+
-| Write protection    | No             |
-+---------------------+----------------+
-| Dual BIOS feature   | No             |
-+---------------------+----------------+
-| Internal flashing   | ?              |
-+---------------------+----------------+
-```
-
-## Notes about the hardware
-
-1. Cavium connected *GPIO10* to a global reset line.
-   It's unclear which chips are connected, but at least the PHY and SATA chips
-   are connected.
-
-2. The 4 QLMs can be configured using DIP switches (SW1). That means only a
-   subset of of the available connectors is working at time.
-
-3. The boot source can be configure using DIP switches (SW1).
-
-4. The core and system clock frequency can be configured using DIP switches
-   (SW3 / SW2).
-
-5. The JTAG follows Cavium's own protocol. Support for it is missing in
-   OpenOCD. You have to use ARMs official hardware and software.
-
-## Technology
-
-```eval_rst
-+---------------+----------------------------------------+
-| SoC           | :doc:`../../soc/cavium/cn81xx/index`   |
-+---------------+----------------------------------------+
-| CPU           | Cavium ARMv8-Quadcore `CN81XX`_        |
-+---------------+----------------------------------------+
-
-.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
-
-```
-
-## Picture
-
-![][cn81xx_board]
-
-[cn81xx_board]: cavium_cn81xx_sff_evb.jpg

Documentation/mainboard/emulation/spike-riscv.md

@@ -1,23 +0,0 @@
-# Spike RISC-V emulator
-
-[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator.
-
-
-## Installation
-
-- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/>
-- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>,
-  which are necessary in order to have a serial console
-- Compile `riscv-fesvr` and then `riscv-isa-sim`
-
-
-## Building coreboot and running it in Spike
-
-- Configure coreboot and run `make` as usual
-- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to
-  convert coreboot to an ELF that Spike can load
-- Run `spike -m1024 build/coreboot.elf`
-
-
-[Spike]: https://github.com/riscv/riscv-isa-sim
-[RISC-V]: https://riscv.org/

Documentation/mainboard/foxconn/d41s.md

@@ -1,75 +0,0 @@
-# Foxconn D41S
-
-This page describes how to run coreboot on the [FOXCONN D41S] desktop from [FOXCONN].
-The D42S, D51S, D52S are compatible boards with the difference being the CPU.
-
-## Building coreboot
-
-The default options for this board should result in a fully working image:
-
-	# echo "CONFIG_VENDOR_FOXCONN=y" > .config
-	# echo "CONFIG_BOARD_FOXCONN_D41S=y" >> .config
-	# make olddefconfig && make
-
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+--------+
-| Type                | Value  |
-+=====================+========+
-| Socketed flash      | yes    |
-+---------------------+--------+
-| Model               | W25X80 |
-+---------------------+--------+
-| Size                | 1 MiB  |
-+---------------------+--------+
-| In circuit flashing | yes    |
-+---------------------+--------+
-| Package             | DIP-8  |
-+---------------------+--------+
-| Write protection    | No     |
-+---------------------+--------+
-| Dual BIOS feature   | No     |
-+---------------------+--------+
-| Internal flashing   | yes    |
-+---------------------+--------+
-```
-
-### Internal programming
-
-The SPI flash can be accessed using [flashrom].
-
-### External programming
-
-The easiest to flash externally is to simply extract the SPI flash from its socket.
-To do this gently take the SPI flash out of its socket and flash with your programmer.
-
-**NOTE: Don't forget to set the WP# AND HOLD# to 3V.**
-
-**NOTE2: Make sure to reinsert it in the right direction afterward**
-
-**Location and orientation of the SPI flash socket**
-![][d41s_flash]
-
-[d41s_flash]: d41s_flash.jpg
-
-## Technology
-
-```eval_rst
-+------------------+------------------+
-| Northbridge      | Intel Pinevew    |
-+------------------+------------------+
-| Southbridge      | Intel NM10       |
-+------------------+------------------+
-| CPU              | model_106cx      |
-+------------------+------------------+
-| SuperIO          | ITE IT8721F      |
-+------------------+------------------+
-| clockgen (CK505) | ICS 9LPRS525AGLF |
-+------------------+------------------+
-```
-
-[FOXCONN D41S]: http://www.foxconnchannel.com/ProductDetail.aspx?T=motherboard&U=en-us0000481
-[FOXCONN]: http://www.foxconnchannel.com
-[Flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/gigabyte/ga-h61m-s2pv.md

@@ -1,84 +0,0 @@
-# Gigabyte GA-H61M-S2PV
-
-This page describes how to run coreboot on the [Gigabyte GA-H61M-S2PV] desktop
-from [Gigabyte].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | No         |
-+---------------------+------------+
-| Model               | MX25L3206E |
-+---------------------+------------+
-| Size                | 4 MiB      |
-+---------------------+------------+
-| In circuit flashing | Yes        |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | No         |
-+---------------------+------------+
-| Dual BIOS feature   | Yes        |
-+---------------------+------------+
-| Internal flashing   | Yes        |
-+---------------------+------------+
-```
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. The DualBIOS backup flash
-chip is accessible as well using the `dualbiosindex` programmer parameter.
-Since the flash recovery mechanism works even with coreboot installed on the
-main flash chip (it still restores the vendor UEFI though), it is useful to
-leave the backup chip untouched.
-
-### Notes about the original firmware
-
-The original IFD defines the BIOS region as the whole flash chip. While this is
-not an issue if flashing a complete image, it confuses flashrom and trashes the
-flash chip's contents when using the --ifd option. However, this can be easily
-fixed by reading the IFD with flashrom, editing the correct values into it with
-ifdtool and then reflashing it.
-
-Create a layout.txt with the following contents:
-
-	00000000:00000fff fd
-	00180000:003fffff bios
-	00001000:0017ffff me
-
-After that, simply run:
-
-```bash
-sudo flashrom -p internal --ifd -i fd -r ifd.rom
-ifdtool -n layout.txt ifd.rom
-sudo flashrom -p internal --ifd -i fd -w ifd.rom.new
-```
-
-After flashing, power cycle the computer to ensure the new IFD is being used.
-If only a reboot is done, the old IFD layout is still seen by flashrom, even if
-the IFD on the flash chip is correctly defining the new region layout.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| SuperIO          | ITE IT8728F                                      |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel ME                                         |
-+------------------+--------------------------------------------------+
-```
-
-[Gigabyte GA-H61M-S2PV]: https://www.gigabyte.com/us/Motherboard/GA-H61M-S2PV-rev-10
-[Gigabyte]: https://www.gigabyte.com
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/google/dragonegg.md

@@ -1,40 +0,0 @@
-# Google Dragonegg (Chromebook)
-
-This page describes how to run coreboot on the google dragonegg board.
-
-Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details
-```eval_rst
-:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
-```
-
-## Building coreboot
-
-* Follow build instructions mentioned in Ice Lake document
-```eval_rst
-:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
-```
-
-* The default options for this board should result in a fully working image:
-```bash
-	# echo "CONFIG_VENDOR_GOOGLE=y" > .config
-	# echo "CONFIG_BOARD_GOOGLE_DRAGONEGG=y" >> .config
-	# make olddefconfig && make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-```

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -1,80 +0,0 @@
-# HP Compaq 8200 Elite SFF
-
-This page describes how to run coreboot on the [Compaq 8200 Elite SFF] desktop
-from [HP].
-
-## TODO
-
-The following things are still missing from this coreboot port:
-
-- Extended HWM reporting
-- Advanced LED control
-- Advanced power configuration in S3
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | MX25L6406E |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| In circuit flashing | yes        |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | No         |
-+---------------------+------------+
-| Dual BIOS feature   | No         |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-### Internal programming
-
-The SPI flash can be accessed using [flashrom].
-
-### External programming
-
-External programming with an SPI adapter and [flashrom] does work, but it powers the
-whole southbridge complex. You need to supply enough current through the programming adapter.
-
-If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
-as otherwise there's not enough space near the flash.
-
-**Position of SOIC-8 flash IC near 2nd DIMM holder**
-![][compaq_8200_flash1]
-
-[compaq_8200_flash1]: compaq_8200_sff_flash1.jpg
-
-**Closeup view of SOIC-8 flash IC**
-![][compaq_8200_flash2]
-
-[compaq_8200_flash2]: compaq_8200_sff_flash2.jpg
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| SuperIO          | :doc:`../../superio/nuvoton/npcd378`             |
-+------------------+--------------------------------------------------+
-| EC               |                                                  |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel ME                                         |
-+------------------+--------------------------------------------------+
-```
-
-[Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
-[HP]: https://www.hp.com/
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -1,68 +0,0 @@
-# Mainboard-specific documentation
-
-This section contains documentation about coreboot on specific mainboards.
-
-## ASUS
-
-- [P8H61-M LX](asus/p8h61-m_lx.md)
-
-## ASRock
-
-- [H81M-HDS](asrock/h81m-hds.md)
-
-## Cavium
-
-- [CN81XX EVB SFF](cavium/cn8100_sff_evb.md)
-
-## Emulation
-
-The boards in this section are not real mainboards, but emulators.
-
-- [Spike RISC-V emulator](emulation/spike-riscv.md)
-
-## Intel
-
-- [DG43GT](intel/dg43gt.md)
-- [IceLake RVP](intel/icelake_rvp.md)
-- [KBLRVP11](intel/kblrvp11.md)
-
-## Foxconn
-
-- [D41S](foxconn/d41s.md)
-
-## Gigabyte
-
-- [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
-
-## Google
-
-- [Dragonegg](google/dragonegg.md)
-
-## Open Cellular
-
-- [Elgon](opencellular/elgon.md)
-
-## HP
-
-- [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
-
-## Lenovo
-
-- [T4xx common](lenovo/t4xx_series.md)
-
-### Sandy Bridge series
-
-- [T420](lenovo/t420.md)
-- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md)
-
-### Ivy Bridge series
-
-- [T430](lenovo/t430.md)
-- [T530](lenovo/w530.md)
-- [W530](lenovo/w530.md)
-- [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md)
-- [T431s](lenovo/t431s.md)
-
-## SiFive
-
-- [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)

Documentation/mainboard/intel/dg43gt.md

@@ -1,99 +0,0 @@
-# Intel DG43GT
-
-This page describes how to run coreboot on the [Intel DG43GT] desktop.
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | W25X32     |
-+---------------------+------------+
-| Size                | 4 MiB      |
-+---------------------+------------+
-| In circuit flashing | NO!        |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | No         |
-+---------------------+------------+
-| Dual BIOS feature   | No         |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-### Internal programming
-
-The SPI flash can be accessed internally using [flashrom].
-Only the BIOS region can and needs to be written to.
-
-```bash
-     $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
-```
-
-### External programming
-
-ISP (in circuit programming) seems to be impossible on this board, which
-is a property it shares with many boards featuring the ICH10 southbridge.
-**Recovering from a bad flash will require desoldering the flash!**
-Desoldering the SPI flash can easily be done with a hot air station.
-Apply some flux around the SPI flash, set the hot air station to 350-400°C
-and after heating the chip up for a minute it should be possible to remove it.
-
-Having removed the flash chip, you can reprogram it externally then resolder
-it using a soldering iron.
-Another option would be to hook up a SPI flash (socket) to the SPI header,
-for easier flash removing in the future (if you expect to be hacking on this
-board). To do this you first need to solder the SPI header to the board.
-
-**NOTE: This header cannot be used for ISP either.**
-
-**NOTE2: Don't forget to connect the WP# and HOLD# pin on the SPI flash to 3.3V.**
-
-The layout of the header is:
-
-```
-                  +---+---+
-           GND <- | x | x | -> SPI_CLK
-                  +---+---+
-          3VSB <- | x | x | -> SPI_MISO
-                  +---+---+
-                  |   | x | -> SPI_MOSI
-                  +---+---+
-        SPI_CS# <-| x | x | -> SPI_CS# (again)
-                  +---+---+
-```
-
-**Picture of the board with the flash hooked on externally**
-![][dg43gt_full]
-
-**Close up picture of the SPI flash pads and recovery header**
-![][dg43gt_closeup]
-
-[dg43gt_full]: dg43gt_full.jpg
-[dg43gt_closeup]: dg43gt_closeup.jpg
-
-## Technology
-
-```eval_rst
-+------------------+---------------------------------------------------+
-| Northbridge      | Intel G43 (called x4x in coreboot code)           |
-+------------------+---------------------------------------------------+
-| Southbridge      | Intel ICH10 (called i82801jx in coreboot code)    |
-+------------------+---------------------------------------------------+
-| CPU (LGA775)     | model f4x, f6x, 6fx, 1067x (pentium 4, d, core 2) |
-+------------------+---------------------------------------------------+
-| SuperIO          | Winbond W83627DHG                                 |
-+------------------+---------------------------------------------------+
-| Coprocessor      | Intel ME (optionally enabled)                     |
-+------------------+---------------------------------------------------+
-| Clockgen (CK505) | SLG8XP549T                                        |
-+------------------+---------------------------------------------------+
-```
-
-[Intel DG43GT]: https://ark.intel.com/products/41036/Intel-Desktop-Board-DG43GT
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/intel/icelake_rvp.md

@@ -1,40 +0,0 @@
-# Intel Ice Lake RVP (Reference Validation Platform)
-
-This page describes how to run coreboot on the Intel icelake_rvp board.
-
-Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
-```eval_rst
-:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
-```
-
-## Building coreboot
-
-* Follow build instructions mentioned in Ice Lake document
-```eval_rst
-:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
-```
-
-* The default options for this board should result in a fully working image:
-```bash
-	# echo "CONFIG_VENDOR_INTEL=y" > .config
-	# echo "CONFIG_BOARD_INTEL_ICELAKE_RVPU=y" >> .config
-	# make olddefconfig && make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Size                | 32 MiB     |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-| External flashing   | yes        |
-+---------------------+------------+
-```

Documentation/mainboard/intel/kblrvp11.md

@@ -1,79 +0,0 @@
-# Intel Kaby lake RVP11
-
-## Specs
-
-* 1 SATA cable connect
-* 1 SATAe direct
-* 2 USB2.0 connector
-* 4 USB3.0 connector
-* 1 Gigabit Ethernet
-* 1 x4 PCIe slot
-* 1 x1 PCIe slot
-* 1 X16 PEG slot
-* UART debug DB9 connector
-* 4 DIMMS with DDR4 memory
-* SPI flash
-* Audio Jack
-* PS2 Keyboard and Mouse
-* Display: HDMI, DP, VGA
-
-## Target Audience
-
-* OEMs, internal only
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Vendor              | Winbond    |
-+---------------------+------------+
-| Model               | W25Q128FV  |
-+---------------------+------------+
-| Size                | 16 MiB     |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | No         |
-+---------------------+------------+
-| Dual BIOS feature   | No         |
-+---------------------+------------+
-```
-
-### Instruction to flash coreboot to SPI
-
-### Internal programming
-
-The SPI flash can be accessed internally using [flashrom].
-The following command is used to flash BIOS region.
-
-```bash
-$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
-```
-
-### External programming
-
-1. Dediprog SF600 with adapter B is used.
-2. Make sure power supply is disconnected from board.
-3. Connect Dediprog SF600 to header at J7H1.
-4. Ensure that "currently working on" is in "application memory chip 1"
-5. Go to "file" and select the .rom file (16 MB) to program chip1.
-6. Execute the batch operation to erase and program the chip.
-
-## Technology
-
-```eval_rst
-+------------------+---------------------------------------------------+
-| CPU              | Kaby lake H (i7-7820EQ)                          |
-+------------------+---------------------------------------------------+
-| PCH              | Skylake PCH-H (called SPT-H)                      |
-+------------------+---------------------------------------------------+
-| Coprocessor      | Intel ME                                          |
-+------------------+---------------------------------------------------+
-```
-
-[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/lenovo/flashlayout_xx20.svg

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-  </text>
-</svg>

Documentation/mainboard/lenovo/flashlayout_xx30.svg

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Documentation/mainboard/lenovo/t420.md

@@ -1,25 +0,0 @@
-# Lenovo T420
-
-## Flashing instructions
-The flash IC is located at the bottom center of the mainboard.  Sadly,
-access to the IC is blocked by the magnesum frame, so you need to disassemble
-the entire laptop and remove the mainboard.
-
-Below is a picture of IC on the mainboard, with the pinouts labeled.
-
-![t420_chip_location](t420_chip_location.jpg)
-
-The chip will either be a Macronix MX25L6404E (shown above) or a Winbond
-W25Q64CVSIG.  Do not rely on dots painted in the corner of the chip (such as
-the blue dot pictured) to orient the pins!
-
-For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and
-
-```eval_rst
-:doc:`../../flash_tutorial/ext_power`
-```
-
-Steps to access the flash IC are described here [T4xx series].
-
-[T4xx series]: t4xx_series.md
-[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md

Documentation/mainboard/lenovo/t430.md

@@ -1,15 +0,0 @@
-# Lenovo T430
-
-## Flashing instructions
-You have to disassemble the whole device, as the flash ICs are on the bottom
-of the mainboard.
-
-For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and
-```eval_rst
-:doc:`../../flash_tutorial/ext_power`
-```
-
-Steps to access the flash IC are described here [T4xx series].
-
-[T4xx series]: t4xx_series.md
-[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md

Documentation/mainboard/lenovo/t431s.md

@@ -1,42 +0,0 @@
-# Lenovo T431s
-
-## Disassembly Instructions
-
-You must remove the following parts before flipping the mainboard
-off the main frame:
-
-![t431s_bc_removed](t431s_bc_removed.jpg)
-
-* Base cover
-* Hard disk drive
-* Battery pack
-* Keyboard
-
-Its [Hardware Maintenance Manual](https://thinkpads.com/support/hmm/hmm_pdf/t431s_hmm_en_0c10894_02.pdf) could be used as a guidance of disassembly.
-
-![t431s_flash_chip](t431s_flash_chip.jpg)
-
-The WSON-8 flash chip (surrounded with red circle in the photo above)
-sits on the opposite side of the mainboard, under a piece of insulating
-tape. If solders between the chip and soldering pads fortunately
-overflows beside the chip as tiny tin balls attached to soldering pads,
-it will be possible to use a pomona 5250 clip to hold the chip, with
-its metal tips just attached to tin balls, thus connecting the chip to
-the programmer.
-
-![t431s_programming](t431s_programming.jpg)
-
-```eval_rst
-:doc:`../../flash_tutorial/ext_power`
-```
-
-Currently, detecting the model of soldered RAM at runtime and loading
-the corresponding SPD datum from CBFS is not implemented yet. You may
-have to dump the SPD data when running the vendor firmware with
-inteltool, and replace the content of the SPD hex with what is dumped.
-
-(the mechanism may be similar to that on x1_carbon_gen1 and s230u, but
-I do not know how to find gpio ports for that, and SPD data stored in
-vendor firmware.)
-
-[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md

Documentation/mainboard/lenovo/t4xx_series.md

@@ -1,34 +0,0 @@
-# Lenovo T4xx series disassembly instructions
-
-A skilled engineer takes around 40 minutes to disassemble, flash and reassemble
-the whole device.
-
-## Steps to access the flash IC
-
-* Unplug the main battery
-* Remove the harddisk, CDROM, ExpressCard, SIM-card, SDcard, SmartCard, ...
-* Open the bottom flap and remove the keyboard screw
-* Remove the keyboard
-* Remove the screen
-* Remove the top enclosure
-* Remove the CMOS battery
-* Remove the speakers
-* Remove WWAN and WIFI card
-* Remove the CPU fan
-* Unplug the power cable
-* Remove the bottom enclosure
-* Flip the mainboard and remove the main frame
-
-## Docking stations
-The following docking stations are supported by coreboot:
-* Type 2505
-  * VGA, Ethernet, Modem, PS2, 4 USB Ports
-  * Dock ID on pc87382 reads as: 2
-* Type 2504
-  * Serial, LPT, LEDs, Audio, DVI, VGA, Ethernet, Modem, PS2, 4 USB Ports
-  * Dock ID on pc87382 reads as: 1
-  * PNP IO address of SuperIO pc87384: 0x2e
-
-There's no hotplug support for LPT and Serial on Type 2504.
-
-The Dock ID reads as 7 if no dock is connected.

Documentation/mainboard/lenovo/w530.md

@@ -1,27 +0,0 @@
-# Lenovo W530 / T530
-
-## Flashing instructions
-You have to remove the keyboard and the palm rest to access one of the
-flash ICs. The second flash ICs is behind the case frame, but can be
-flashed by using a simple trick. Connect every pin of the first flash
-IC, but tie /CS to Vcc. Connect /CS of the second flash IC to the
-programmer.
-As all lines except /CS are shared between the flash ICs you can access
-both with an external programmer.
-
-For more details have a look at [T430 / T530 / X230 / T430s / W530 common] and
-```eval_rst
-:doc:`../../flash_tutorial/ext_power`
-```
-
-### After removing the keyboard and palm rest
-![][w530-1]
-
-[w530-1]: w530-1.jpg
-
-### Closeup view of the flash ICs
-![][w530-2]
-
-[w530-2]: w530-2.jpg
-
-[T430 / T530 / X230 / T430s / W530 common]: xx30_series.md

Documentation/mainboard/lenovo/xx20_series.md

@@ -1,48 +0,0 @@
-# Lenovo Sandy Bridge series
-
-## Flashing coreboot
-```eval_rst
-+---------------------+--------------------+
-| Type                | Value              |
-+=====================+====================+
-| Socketed flash      | no                 |
-+---------------------+--------------------+
-| Size                | 8 MiB              |
-+---------------------+--------------------+
-| In circuit flashing | Yes                |
-+---------------------+--------------------+
-| Package             | SOIC-8             |
-+---------------------+--------------------+
-| Write protection    | No                 |
-+---------------------+--------------------+
-| Dual BIOS feature   | No                 |
-+---------------------+--------------------+
-| Internal flashing   | Yes                |
-+---------------------+--------------------+
-```
-
-## Installation instructions
-* Update the EC firmware, as there's no support for EC updates in coreboot.
-* Do **NOT** accidently swap pins or power on the board while a SPI flasher
-  is connected. It will destroy your device.
-* It's recommended to only flash the BIOS region. In that case you don't
-  need to extract blobs from vendor firmware.
-  If you want to flash the whole chip, you need blobs when building
-  coreboot.
-* The shipped *Flash layout* allocates 3MiB to the BIOS region, which is the space
-  usable by coreboot.
-* ROM chip size should be set to 8MiB.
-
-```eval_rst
-Please also have a look at :doc:`../../flash_tutorial/index`.
-```
-
-## Flash layout
-There's one 8MiB flash which contains IFD, GBE, ME and BIOS regions.
-On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
-region. The update is then written into the EC once.
-
-![][fl]
-
-[fl]: flashlayout_xx20.svg
-

Documentation/mainboard/lenovo/xx30_series.md

@@ -1,76 +0,0 @@
-# Lenovo Ivy Bridge series
-
-## Flashing coreboot
-```eval_rst
-+---------------------+--------------------------------+
-| Type                | Value                          |
-+=====================+================================+
-| Socketed flash      | no                             |
-+---------------------+--------------------------------+
-| Size                | 8 MiB + 4MiB                   |
-+---------------------+--------------------------------+
-| In circuit flashing | Yes                            |
-+---------------------+--------------------------------+
-| Package             | SOIC-8                         |
-+---------------------+--------------------------------+
-| Write protection    | No                             |
-+---------------------+--------------------------------+
-| Dual BIOS feature   | No                             |
-+---------------------+--------------------------------+
-| Internal flashing   | Yes                            |
-+---------------------+--------------------------------+
-```
-
-## Installation instructions
-* Update the EC firmware, as there's no support for EC updates in coreboot.
-* Do **NOT** accidently swap pins or power on the board while a SPI flasher
-  is connected. It will permanently brick your device.
-* It's recommended to only flash the BIOS region. In that case you don't
-  need to extract blobs from vendor firmware.
-  If you want to flash the whole chip, you need blobs when building
-  coreboot.
-* The *Flash layout* shows that by default 7MiB of space are available for
-  the use with coreboot.
-* In that case you only want to use a part of the BIOS region that must not
-  exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
-* ROM chip size should be set to 12MiB.
-
-```eval_rst
-Please also have a look at :doc:`../../flash_tutorial/index`.
-```
-
-## Splitting the coreboot.rom
-
-To split the coreboot.rom into two images (one for the 8MiB and one for the
-4 MiB flash IC), run the following commands:
-
-```bash
-dd of=top.rom bs=1M if=build/coreboot.rom skip=8
-dd of=bottom.rom bs=1M if=build/coreboot.rom count=8
-```
-
-That gives one ROM for each flash IC, where *top.rom* is the upper part of the
-flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part
-of the flash image, that resides on the 8 MiB flash.
-
-## Dumping a full ROM
-
-If you flash externally you need to read both flash chips to get two images
-(one for the 8MiB and one for the 4 MiB flash IC), and then run the following
-command to concatenate the files:
-
-```bash
-cat bottom.rom top.rom > firmware.rom
-```
-
-## Flash layout
-There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and
-BIOS region. These two flash ICs appear as a single 12MiB when flashing
-internally.
-On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
-region. The update is then written into the EC once.
-
-![][fl]
-
-[fl]: flashlayout_xx30.svg
-

Documentation/mainboard/opencellular/elgon.md

@@ -1,84 +0,0 @@
-# Elgon
-
-This page describes how to run coreboot on the [Elgon] compute board
-from [OpenCellular].
-
-## TODO
-
-* Add hard reset control
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | W25Q128    |
-+---------------------+------------+
-| Size                | 16 MiB     |
-+---------------------+------------+
-| In circuit flashing | yes        |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | No         |
-+---------------------+------------+
-| Dual BIOS feature   | No         |
-+---------------------+------------+
-| Internal flashing   | yes        |
-+---------------------+------------+
-```
-
-### Internal programming
-
-The SPI flash can be accessed using [flashrom].
-
-### External programming
-
-The EVT board does have a pinheader to flash the SOIC-8 in circuit.
-Directly connecting a Pomona test-clip on the flash is also possible.
-
-**Total board view of EVT**
-
-![][elgon1]
-
-[elgon1]: elgon1.jpg
-
-**Closeup view of SOIC-8 flash IC and USB serial connector of EVT (marked blue)**
-
-![][elgon2]
-
-[elgon2]: elgon2.jpg
-
-
-**SPI header (marked blue)**
-
-![][elgon_conn_j9_pcb]
-
-[elgon_conn_j9_pcb]: elgon_conn_j9_pcb.jpg
-
-**SPI header pinout**
-
-Dediprog compatible pinout.
-
-![][elgon_conn_j9]
-
-[elgon_conn_j9]: elgon_conn_j9.png
-
-## Technology
-
-```eval_rst
-+---------------+----------------------------------------+
-| SoC           | :doc:`../../soc/cavium/cn81xx/index`   |
-+---------------+----------------------------------------+
-| CPU           | Cavium ARMv8-Quadcore `CN81XX`_        |
-+---------------+----------------------------------------+
-
-.. _CN81XX: https://www.cavium.com/product-octeon-tx-cn80xx-81xx.html
-```
-
-[Elgon]: https://github.com/Telecominfraproject/OpenCellular
-[OpenCellular]: https://code.fb.com/connectivity/introducing-opencellular-an-open-source-wireless-access-platform/
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/sifive/hifive-unleashed.md

@@ -11,14 +11,15 @@ For general setup instructions, please refer to the [Getting Started Guide].
 
 The following things are still missing from this coreboot port:
 
-- Support running romstage from flash (fix stack) to support boot mode 1
+- Trampoline in the MBR block to support boot mode 1
+- SiFive UART driver
 - CBMEM support
 - FU540 clock configuration
 - FU540 RAM init
 - Placing the ramstage in DRAM
 - Starting the U54 cores
 - FU540 PIN configuration and GPIO access macros
-- Provide serial number to payload (e.g. in device tree)
+- FU540 OTP driver and serial number read-out
 - Support for booting Linux on RISC-V
 
 
@@ -96,8 +97,8 @@ console in certain situations.
 
 [HiFive Unleashed]: https://www.crowdsupply.com/sifive/hifive-unleashed
 [SiFive]: https://www.sifive.com/
-[Getting Started Guide]: https://sifive.cdn.prismic.io/sifive%2Ffa3a584a-a02f-4fda-b758-a2def05f49f9_hifive-unleashed-getting-started-guide-v1p1.pdf
+[Getting Started Guide]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-getting-started-guide/
 [RISC-V fork of OpenOCD]: https://github.com/riscv/riscv-openocd
 [OpenOCD script]: https://github.com/sifive/freedom-u-sdk/blob/057a47f657fa33e2c60df7f183884a68e90381cc/bsp/env/freedom-u500-unleashed/openocd.cfg
 [flashrom]: https://flashrom.org/Flashrom
-[schematics]: https://sifive.cdn.prismic.io/sifive%2Ff7173056-bf37-4407-87cb-d5ab76abf61a_hifive-unleashed-a00-schematics.pdf
+[schematics]: https://www.sifive.com/documentation/boards/hifive-unleashed/hifive-unleashed-schematics/

Documentation/northbridge/index.md

@@ -1,7 +0,0 @@
-# Northbridge-specific documentation
-
-This section contains documentation about coreboot on specific northbridges.
-
-## Vendor
-
-- [Intel](intel/index.md)

Documentation/northbridge/intel/index.md

@@ -1,7 +0,0 @@
-# Intel Northbridge-specific documentation
-
-This section contains documentation about coreboot on specific Intel Northbridges.
-
-## Platforms
-
-- [Sandy Bridge](sandybridge/index.md)

Documentation/northbridge/intel/sandybridge/index.md

@@ -1,8 +0,0 @@
-# Intel Sandy Bridge-specific documentation
-
-This section contains documentation about coreboot on specific Intel "Sandy Bridge" northbridge.
-
-## Topics
-
-- [Native Ram Initialization](nri.md)
-- [RAM initialization feature matrix](nri_features.md)