Makefile.inc: Drop spurious -t from cbfstool add-payload

The `-t` argument was never required for `add-payload` and results in a warning now because the type was renamed. TEST=Built with BUILD_TIMELESS=1 and compared binaries with and without this patch. Change-Id: I6ccb70acc6e88a602b90c625040d4f05d8e3630a Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Revert "cbfs/payload type: Fix build warning and whitespace in name"
2018-05-16 19:00:17 +00:00 · 2018-05-16 19:00:09 +00:00
25803 changed files with 2110408 additions and 1842699 deletions
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
--ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS
@ -18,12 +17,6 @@
 --ignore CONFIG_DESCRIPTION
 --ignore MISSING_SPACE
 --ignore CORRUPTED_PATCH
--ignore SPDX_LICENSE_TAG
--ignore UNDOCUMENTED_DT_STRING
--ignore PRINTK_WITHOUT_KERN_LEVEL
--ignore ASSIGN_IN_IF
--ignore UNNECESSARY_ELSE
--ignore GERRIT_CHANGE_ID

 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file
@ -34,8 +27,5 @@
 # some commits unnecessarily.
 --ignore EXECUTE_PERMISSIONS

-# Exclude vendorcode directories that don't follow coreboot's coding style.
--exclude src/vendorcode/amd
--exclude src/vendorcode/cavium
--exclude src/vendorcode/intel
--exclude src/vendorcode/mediatek
+# Exclude the vendorcode directory
+--exclude src/vendorcode
--- a/.clang-format
+++ b/.clang-format
@ -1,21 +1,10 @@
-BasedOnStyle:					LLVM
-Language:					Cpp
-IndentWidth:					8
-UseTab:						Always
-BreakBeforeBraces:				Linux
-AllowShortIfStatementsOnASingleLine:		false
-IndentCaseLabels:				false
-SortIncludes:					false
-ContinuationIndentWidth:			8
-ColumnLimit:					96
-AlwaysBreakBeforeMultilineStrings:		true
-AllowShortLoopsOnASingleLine:			false
-AllowShortFunctionsOnASingleLine:		false
-AlignEscapedNewlinesLeft:			false
-AlignTrailingComments:				true
-AllowAllParametersOfDeclarationOnNextLine:	false
-AlignAfterOpenBracket:				true
-SpaceAfterCStyleCast:				false
-MaxEmptyLinesToKeep:				2
-BreakBeforeBinaryOperators:			NonAssignment
-BreakStringLiterals:				false
+BasedOnStyle:                              LLVM
+Language:                                  Cpp
+IndentWidth:                               8
+UseTab:                                    Always
+BreakBeforeBraces:                         Linux
+AllowShortIfStatementsOnASingleLine:       false
+IndentCaseLabels:                          false
+SortIncludes:                              false
+ContinuationIndentWidth:                   8
+ColumnLimit:                               80
--- a/.editorconfig
+++ b/.editorconfig
@ -1,11 +0,0 @@
-# EditorConfig: https://EditorConfig.org
-
-root = true
-
-[*]
-indent_style = tab
-tab_width = 8
-charset = utf-8
-insert_final_newline = true
-end_of_line = lf
-trim_trailing_whitespace = true
--- a/.gitignore
+++ b/.gitignore
@ -1,3 +1,6 @@
+payloads/libpayload/install/
+payloads/nvramcui/build
+payloads/nvramcui/libpayload
 junit.xml
 abuild*.xml
 .config
@ -8,38 +11,127 @@ defconfig
 .ccwrap
 build/
 coreboot-builds/
-coreboot-builds*/
-
+payloads/coreinfo/lpbuild/
+payloads/coreinfo/lp.config*
+payloads/external/depthcharge/depthcharge/
+payloads/external/FILO/filo/
+payloads/external/GRUB2/grub2/
+payloads/external/SeaBIOS/seabios/
+payloads/external/tianocore/tianocore/
+payloads/external/tint/tint/
+payloads/external/U-Boot/u-boot/
+payloads/external/Memtest86Plus/memtest86plus/
+payloads/external/iPXE/ipxe/
+util/crossgcc/acpica-unix-*/
+util/crossgcc/binutils-*/
+util/crossgcc/build-*BINUTILS/
+util/crossgcc/build-*EXPAT/
+util/crossgcc/build-*GCC/
+util/crossgcc/build-*GDB/
+util/crossgcc/build-*GMP/
+util/crossgcc/build-*LIBELF/
+util/crossgcc/build-*MPC/
+util/crossgcc/build-*MPFR/
+util/crossgcc/build-*PYTHON/
+util/crossgcc/build-*LVM/
+util/crossgcc/build-*IASL/
+util/crossgcc/expat-*/
+util/crossgcc/gcc-*/
+util/crossgcc/gdb-*/
+util/crossgcc/gmp-*/
+util/crossgcc/libelf-*/
+util/crossgcc/mingwrt-*/
+util/crossgcc/mpc-*/
+util/crossgcc/mpfr-*/
+util/crossgcc/Python-*/
+util/crossgcc/*.src/
+util/crossgcc/tarballs/
+util/crossgcc/w32api-*/
+util/crossgcc/xgcc/
+util/crossgcc/xgcc-*/
+util/crossgcc/xgcc
 site-local

 *.\#
-*.a
 *.bin
 *.debug
-!Kconfig.debug
 *.elf
-*.fd
 *.o
-*.o.d
 *.out
 *.pyc
 *.sw[po]
 /*.rom
-.test
-.dependencies
+coreboot-builds*/

 # Development friendly files
 tags
 .clang_complete
-.cache
-compile_commands.json
-.vscode/

 # Cross-compile toolkits
 xgcc/
 tarballs/

-# editor backup files, temporary files, IDE project files
+#
+# KDE editors create lots of backup files whenever
+# a file is edited, so just ignore them
 *~
 *.kate-swp
+# Ignore Kdevelop project file
 *.kdev4
+
+util/*/.dependencies
+util/*/.test
+util/amdfwtool/amdfwtool
+util/archive/archive
+util/bimgtool/bimgtool
+util/bincfg/bincfg
+util/board_status/board-status
+util/cbfstool/cbfs-compression-tool
+util/cbfstool/cbfstool
+util/cbfstool/fmaptool
+util/cbfstool/ifwitool
+util/cbfstool/rmodtool
+util/cbmem/.dependencies
+util/cbmem/cbmem
+util/dumpmmcr/dumpmmcr
+util/ectool/ectool
+util/futility/futility
+util/genprof/genprof
+util/getpir/getpir
+util/ifdtool/ifdtool
+util/ifdfake/ifdfake
+util/intelmetool/intelmetool
+util/inteltool/.dependencies
+util/inteltool/inteltool
+util/intelvbttool/intelvbttool
+util/k8resdump/k8resdump
+util/lbtdump/lbtdump
+util/mptable/mptable
+util/msrtool/Makefile
+util/msrtool/Makefile.deps
+util/msrtool/msrtool
+util/nvramtool/.dependencies
+util/nvramtool/nvramtool
+util/optionlist/Options.wiki
+util/romcc/build
+util/runfw/googlesnow
+util/superiotool/superiotool
+util/vgabios/testbios
+util/viatool/viatool
+util/autoport/autoport
+util/kbc1126/kbc1126_ec_dump
+util/kbc1126/kbc1126_ec_insert
+
+documentation/*.aux
+documentation/*.idx
+documentation/*.log
+documentation/*.toc
+documentation/*.out
+documentation/*.pdf
+documentation/cpukconfig.tex
+documentation/mainboardkconfig.tex
+documentation/skconfig.tex
+documentation/socketfkconfig.tex
+Documentation/_build
+
+doxygen/*
--- a/.gitmodules
+++ b/.gitmodules
@ -9,7 +9,6 @@
 [submodule "vboot"]
 	path = 3rdparty/vboot
 	url = ../vboot.git
-	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
 	url = ../arm-trusted-firmware.git
@ -22,46 +21,3 @@
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
 	url = ../libgfxinit.git
-[submodule "3rdparty/fsp"]
-	path = 3rdparty/fsp
-	url = ../fsp.git
-	update = none
-	ignore = dirty
-[submodule "opensbi"]
-	path = 3rdparty/opensbi
-	url = ../opensbi.git
-[submodule "intel-microcode"]
-	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
-	update = none
-	ignore = dirty
-	branch = main
-[submodule "3rdparty/ffs"]
-	path = 3rdparty/ffs
-	url = ../ffs.git
-[submodule "3rdparty/amd_blobs"]
-	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
-	update = none
-	ignore = dirty
-[submodule "3rdparty/cmocka"]
-	path = 3rdparty/cmocka
-	url = ../cmocka.git
-	update = none
-	branch = stable-1.1
-[submodule "3rdparty/qc_blobs"]
-	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
-	update = none
-	ignore = dirty
-[submodule "3rdparty/intel-sec-tools"]
-	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
-[submodule "3rdparty/stm"]
-	path = 3rdparty/stm
-	url = ../STM
-	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = ../goswid
-	branch = trunk
--- a/.mailmap
+++ b/.mailmap
@ -1,425 +0,0 @@
-# Map author and committer names and email addresses to canonical real names and
-# email addresses. https://git-scm.com/docs/gitmailmap
-#
-# Note that this is only needed in the case where someone has contributed
-# with multiple different email addresses or Names.
-#
-# Forms: Proper Name <commit@email.xx>
-#        Proper Name <proper@email.xx> <commit@email.xx>
-#        Proper Name <proper@email.xx> Commit Name <commit@email.xx>
-
-
-Aamir Bohra <aamirbohra@gmail.com> <aamir.bohra@intel.com>
-Aaron Durbin <adurbin@chromium.org>
-Aaron Durbin <adurbin@chromium.org> <adurbin@adurbin.bld.corp.google.com>
-Aaron Durbin <adurbin@chromium.org> <adurbin@google.com>
-Abhay Kumar <abhay.kumar@intel.com>
-Abhinav Hardikar <realdevmaster64@gmail.com> devmaster64 <devmaster64@gmail.com>
-Alex Levin <levinale@google.com> <levinale@chromium.org>
-Alex Miao <alex.miao@mediatek.corp-partner.google.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> <alexandrux.gagniuc@intel.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> mrnuke <mrnuke@nukelap.gtech>
-Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
-Amol N Sukerkar <amol.n.sukerkar@intel.com>
-Andrea Barberio <barberio@fb.com> <insomniac@slackware.it>
-Andrey Petrov <anpetrov@fb.com> <andrey.petrov@intel.com>
-Andrey Pronin <apronin@chromium.org> <apronin@google.com>
-Andriy Gapon <avg@FreeBSD.org> <avg@icyb.net.ua>
-Anil Kumar <anil.kumar.k@intel.com> <anil.kumar.k@intel.corp-partner.google.com>
-Anish K. Patel <anishp@win-ent.com>
-Anton Kochkov <anton.kochkov@gmail.com> <a.kochkov@securitycode.ru>
-Antonello Dettori <dev@dettori.io> <dettori.an@gmail.com>
-Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
-Arne Georg Gleditsch <arne.gleditsch@numascale.com> <arne.gleditsch@numscale.com>
-Asami Doi <d0iasm.pub@gmail.com> <doiasami1219@gmail.com>
-Ashwin Kumar <ashk@codeaurora.org>
-Axel Holewa <mono@posteo.de> Mono <mono-for-coreboot@donderklumpen.de>
-Axel Holewa <mono@posteo.de> Mono <mono@posteo.de>
-Bao Zheng <fishbaozi@gmail.com>
-Bao Zheng <fishbaozi@gmail.com> <Zheng Bao zheng.bao@amd.com>
-Bao Zheng <fishbaozi@gmail.com> <zheng.bao@amd.com>
-Bayi Cheng <bayi.cheng@mediatek.com>
-Ben Zhang <benzh@google.com> <benzh@chromium.org>
-Bernhard M. Wiedermann <corebootbmw@lsmod.de>
-Bill Xie <persmule@hardenedlinux.org> <persmule@gmail.com>
-Bill Xie <persmule@hardenedlinux.org> Bill XIE <persmule@hardenedlinux.org>
-Bingxun Shi <bingxunshi@gmail.com>
-Bingxun Shi <bingxunshi@gmail.com> <bxshi@msik.com.cn>
-Brandon Breitenstein <brandon.breitenstein@intel.com> <brandon.breitenstein@intel.corp-partner.google.com>
-Bruce Griffith <bruce.griffith@se-eng.com> <Bruce.Griffith@se-eng.com>
-Bryant Ou <Bryant.Ou.Q@gmail.com>
-Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> <Carl-Daniel Hailfinger>
-Casper Chang<casper_chang@wistron.corp-partner.google.com> <casper.chang@bitland.corp-partner.google.com>
-Caveh Jalali <caveh@chromium.org> <caveh@google.com>
-Caveh Jalali <caveh@chromium.org> caveh jalali <caveh@chromium.org>
-Charles Marslett <charles@scarlettechnologies.com> <charles.marslett@silverbackltd.com>
-Chee Soon Lew <chee.soon.lew@intel.com>
-Cheng-Yi Chiang <cychiang@chromium.org> <cychiang@google.com>
-Chris Ching <chris@ching.codes> <chingcodes@chromium.org>
-Chris Ching <chris@ching.codes> <chingcodes@google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> <chriswang@ami.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris Wang <chris.wang@amd-corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> chris wang <chris.wang@amd.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris.Wang <chris.wang@amd.corp-partner.google.com>
-Chris Zhou <chris_zhou@compal.corp-partner.google.com>
-Christian Ruppert <idl0r@qasl.de> <idl0r@gentoo.org>
-Chun-Jie Chen <chun-jie.chen@mediatek.corp-partner.google.com>
-Clay Daniels Jr <clay.daniels.jr@gmail.com>
-Cole Nelson<colex.nelson@intel.com>
-Corey Osgood <corey.osgod@gmail.com> <corey_osgood@verizon.net>
-Corey Osgood <corey.osgod@gmail.com> <corey.osgood@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
-Da Lao <dalao@tutanota.com> dalao <dalao@tutanota.com>
-Daisuke Nojiri <dnojiri@chromium.org> dnojiri <dnojiri@chromium.org>
-Dan Elkouby <streetwalkermc@gmail.com> <streetwalrus@codewalr.us>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@chromium.org>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@google.com>
-Dave Parker <dparker@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <david.hendricks@gmail.com>
-David Hendricks <davidhendricks@gmail.com> <dhendricks@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@google.com>
-David Hendricks <davidhendricks@gmail.com> David W. Hendricks <dwh@lanl.gov>
-David Wu <david_wu@quantatw.com> <david_wu@quanta.corp-partner.google.com>
-David Wu <david_wu@quantatw.com> david <david_wu@quantatw.com>
-Dawei Chien <dawei.chien@mediatek.com>
-Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> <GNUtoo@no-log.org>
-Derek Huang <derek.huang@intel.com> <derek.huang@intel.corp-partner.google.com>
-Dmitry Ponamorev <dponamorev@gmail.com>
-Douglas Anderson <dianders@chromium.org>
-Duncan Laurie <dlaurie@chromium.org> <dlaurie@google.com>
-Ed Swierk <eswierk@aristanetworks.com> <eswierk@arastra.com>
-Edward O'Callaghan <quasisec@google.com> <edward.ocallaghan@koparo.com>
-Edward O'Callaghan <quasisec@google.com> <eocallaghan@alterapraxis.com>
-Edward O'Callaghan <quasisec@google.com> <funfunctor@folklore1984.net>
-Edward O'Callaghan <quasisec@google.com> <quasisec@chromium.org>
-Eric Biederman <ebiederm@xmission.com> <ebiederman@lnxi.com>
-Eric Biederman <ebiederm@xmission.com> Eric W. Biederman <ebiederm@xmission.com>
-Eugene Myers <edmyers@tycho.nsa.gov> <cedarhouse@comcast.net>
-Evgeny Zinoviev <me@ch1p.io> <me@ch1p.com>
-Felix Durairaj <felixx.durairaj@intel.com>
-Felix Held <felix-coreboot@felixheld.de> <felix-github@felixheld.de>
-Felix Held <felix-coreboot@felixheld.de> <felix.held@amd.corp-partner.google.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@9elements.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@secunet.com>
-Felix Singer <felixsinger@posteo.net> <migy@darmstadt.ccc.de>
-Francois Toguo Fotso <francois.toguo.fotso@intel.com> Francois Toguo <francois.toguo.fotso@intel.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Vibrans <efdesign98@gmail.com> efdesign98 <efdesign98@gmail.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@amd.com>
-Frank Vibrans <efdesign98@gmail.com> frank vibrans <frank.vibrans@scarletltd.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@se-eng.com>
-Frank Vibrans <efdesign98@gmail.com> Frank.Vibrans <frank.vibrans@amd.com>
-Furquan Shaikh <furquan@chromium.org> <furquan@google.com>
-G. Pangao <gtk_pangao@mediatek.com> <gtk_pangao@mediatek.corp-partner.google.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@chromium.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@google.com>
-Gaggery Tsai <gaggery.tsai@intel.com>
-Georg Wicherski <gwicherski@gmail.com> <gw@oxff.net>
-Gomathi Kumar <gomathi.kumar@intel.com>
-Greg V <greg@unrelenting.technology>
-Greg Watson <gwatson@lanl.gov> <jarrah@users.sourceforge.net>
-Hannah Williams <hannah.williams@dell.com> <hannah.williams@intel.com>
-Hao Chou <hao_chou@pegatron.corp-partner.google.com>
-Haridhar Kalvala <haridhar.kalvala@intel.com> haridhar <haridhar.kalvala@intel.com>
-Harsha Priya <harshapriya.n@intel.com>
-Harsha Priya <harshapriya.n@intel.com> <harhapriya.n@intel.com>
-Harshit Sharma <harshitsharmajs@gmail.com> harshit <harshitsharmajs@gmail.com>
-Henry C Chen <henryc.chen@mediatek.com> henryc.chen <henryc.chen@mediatek.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> <himanshusah@hcl.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
-Hsuan Ting Chen <roccochen@chromium.org> Hsuan-ting Chen <roccochen@google.com>
-Huang Lin <hl@rock-chips.com>
-Huayang Duan <huayang.duan@mediatek.com>
-Huki Huang <huki.huang@intel.com>
-Idwer Vollering <vidwer@gmail.com> <idwer_v@hotmail.com>
-Igor Bagnucki <bagnucki02@gmail.com> <igor.bagnucki@3mdeb.com>
-Indrek Kruusa <indrek.kruusa@artecdesign.ee>  <Indrek Kruusa>
-Ivy Jian <ivy_jian@compal.com> <ivy_jian@compal.corp-partner.google.com>
-Jacob Laska <jlaska91@gmail.com> <jlaska@xes-inc.com>
-Jakub Czapiga <jacz@semihalf.com>
-Jason Wang <Qingpei.Wang@amd.com> Jason WangQingpei.wang <Jason WangQingpei.wang@amd.com>
-JasonX Z Chen <jasonx.z.chen@intel.com>
-Jens Kühnel <coreboot@jens.kuehnel.org> Jens Kuehnel <coreboot@jens.kuehnel.org>
-Jens Rottmann <JRottmann@LiPPERTembedded.de> <JRottmann@LiPPERTEmbedded.de>
-Jeremy Compostella  <jeremy.compostella@intel.com> <jeremy.compostella@gmail.com>
-Jeremy Soller <jackpot51@gmail.com> <jeremy@system76.com>
-Jiaxin Yu <jiaxin.yu@mediatek.com>
-Jiazi Yang <Tomato_Yang@asus.com>
-Jim Lai <jim.lai@intel.com>
-Jingle Hsu <jingle_hsu@wiwynn.com>
-Jinkun Hong <jinkun.hong@rock-chips.com>
-Joe Moore <awokd@danwin1210.me>
-Joe Pillow <joseph.a.pillow@gmail.com>
-Johanna Schander <coreboot@mimoja.de>
-John Zhao <john.zhao@intel.com>
-Jonathan Kollasch <jakllsch@kollasch.net>
-Jordan Crouse <jordan@cosmicpenguin.net>  <Jordan Crouse>
-Jordan Crouse <jordan@cosmicpenguin.net> <jordan.crouse@amd.com>
-Josef Kellermann <Joseph.Kellermann@heitec.de> <seppk@arcor.de>
-Josef Kellermann <Joseph.Kellermann@heitec.de> Josef Kellermannseppk <Josef Kellermannseppk@arcor.de>
-Joseph Smith <joe@settoplinux.org> <joe@settoplinux.org Acked-by: Joseph Smith joe@settoplinux.org>
-Joseph Smith <joe@settoplinux.org> <joe@smittys.pointclark.net>
-Juergen Beisert <juergen@kreuzholzen.de> <juergen127@kreuzholzen.de>
-Julian Schroeder <julianmarcusschroeder@gmail.com> <julian.schroeder@amd.com>
-Julien Viard de Galbert <julien@vdg.name> <jviarddegalbert@online.net>
-Justin Wu <amersel@runbox.me>
-Kaiyen Chang <kaiyen.chang@intel.com> <kaiyen.chang@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane.chen@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> Kane Chenffd <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> kane_chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
-Karthikeyan Ramasubramanian <kramasub@google.com> <kramasub@chromium.org>
-Katie Roberts-Hoffman <katierh@chromium.org>  <katierh@google.com>
-Kerry She <kerry.she@amd.com> <Kerry.she@amd.com>
-Kerry Sheh <shekairui@gmail.com>
-Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quanta.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quantatw.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <Kevin.Chiu@quantatw.com>
-Kevin Paul Herbert <kph@platinasystems.com> <kevin@trippers.org>
-Kevin Paul Herbert <kph@platinasystems.com> <kph@meraki.net>
-Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
-Konstantin Aladyshev <aladyshev22@gmail.com> <aladyshev@nicevt.ru>
-Kyösti Mälkki <kyosti.malkki@gmail.com>
-Kyösti Mälkki <kyosti.malkki@gmail.com> <kyosti.malkki@3mdeb.com>
-Lean Sheng Tan <sheng.tan@9elements.com> <lean.sheng.tan@intel.com>
-Lee Leahy <lpleahyjr@gmail.com> <leroy.p.leahy@intel.com>
-Li Cheng Sooi <li.cheng.sooi@intel.com>
-Lijian Zhao <lijian.zhao@intel.com>
-Lin Huang <hl@rock-chips.com>
-Maciej Matuszczyk <maccraft123mc@gmail.com>
-Maggie Li <maggie.li@amd.com> <Maggie.li@amd.com>
-Manideep Kurumella <mkurumel@qualcomm.corp-partner.google.com> <mkurumel@codeaurora.org>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@scarletltd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@se-eng.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@yahoo.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcjones@sysproconsulting.com>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones(marc.jones <Marc Jones(marc.jones@amd.com)>
-Marcello Sylvester Bauer <sylv@sylv.io>
-Marcello Sylvester Bauer <sylv@sylv.io> <info@marcellobauer.com>
-Marcello Sylvester Bauer <sylv@sylv.io> <sylvblck@sylv.io>
-Marco Chen <marcochen@google.com> <marcochen@chromium.org>
-Mariusz Szafrański <mariuszx.szafranski@intel.com> Mariusz Szafranski <mariuszx.szafranski@intel.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@amd.corp-partner.google.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@scarletltd.com>
-Mart Raudsepp <leio@gentoo.org> <mart.raudsepp@artecdesign.ee>
-Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
-Martin Roth <gaumless@gmail.com> <martin.roth@se-eng.com>
-Martin Roth <gaumless@gmail.com> <martin@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinr@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinroth@chromium.org>
-Martin Roth <gaumless@gmail.com> <martinroth@google.com>
-Martin Roth <gaumless@gmail.com> Martin Roth <martin@se-eng.com>
-Marx Wang <marx.wang@intel.com>
-Mathias Krause <minipli@googlemail.com> <mathias.krause@secunet.com>
-Mathias Krause <minipli@googlemail.com> <Mathias.Krause@secunet.com>
-Mats Erik Andersson <mats.andersson@gisladisker.org> <mats.andersson@gisladisker.se>
-Matt DeVillier <matt.devillier@gmail.com> <matt.devillier@puri.sm>
-Matt Papageorge <matthewpapa07@gmail.com> <matt.papageorge@amd.corp-partner.google.com>
-Matt Ziegelbaum <ziegs@google.com> <ziegs@chromium.org>
-Maulik V Vaghela <maulik.v.vaghela@intel.com>
-Maulik V Vaghela <maulik.v.vaghela@intel.com> <maulik.v.vaghela@intel.corp-partner.google.com>
-Max Blau <tripleshiftone@gmail.com> Bluemax <1403092+BlueMax@users.noreply.github.com>
-Maxim Polyakov <max.senia.poliak@gmail.com> <m.poliakov@yahoo.com>
-Mengqi Zhang <Mengqi.Zhang@mediatek.com> mengqi.zhang <mengqi.zhang@mediatek.com>
-Michael Niewöhner <foss@mniewoehner.de> <michael.niewoehner@8com.de>
-Michael Xie <Michael.Xie@amd.com> <Michael Xie Michael.Xie@amd.com>
-Michele Guerini Rocco <rnhmjoj@inventati.org>
-Mike Banon <mikebdp2@gmail.com> <mike.banon@3mdeb.com>
-Mike Hsieh <Mike_Hsieh@wistron.com> <mike_hsieh@wistron.corp-partner.google.com>
-Mike Loptien <loptienm@gmail.com> <mike.loptien@se-eng.com>
-Mondrian Nuessle <nuessle@uni-hd.de>
-Mondrian Nuessle <nuessle@uni-hd.de> <nuessle@uni-mannheim.de>
-Motiejus Jakštys <desired.mta@gmail.com>
-Myles Watson <mylesgw@gmail.com>  <myles@pel.cs.byu.edu>
-Nancy Lin <nancy.lin@mediatek.com>
-Naresh Solanki <naresh.solanki@intel.com>
-Naresh Solanki <naresh.solanki@intel.com> <Naresh.Solanki@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Neil Chen <neilc@nvidia.com> <neilc%nvidia.com@gtempaccount.com>
-Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
-Nick Vaccaro <nvaccaro@google.com> <nvaccaro@chromium.org>
-Nicky Sielicki <nlsielicki@wisc.edu>
-Nico Huber <nico.h@gmx.de> <nico.huber@secunet.com>
-Nicolas Boichat <drinkcat@chromium.org> <drinkcat@google.com>
-Nicolas Reinecke <nr@das-labor.org>
-Nils Jacobs <njacobs8@adsltotaal.nl> <njacobs8@hetnet.nl>
-Nina Wu <nina-cm.wu@mediatek.com> <nina-cm.wu@mediatek.corp-partner.google.com>
-Oskar Enoksson <enok@lysator.liu.se>
-Oskar Enoksson <enok@lysator.liu.se> <oskeno@foi.se>
-Pablo Moyano <42.pablo.ms@gmail.com> p4block <p4block@users.noreply.github.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick.Georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi.software>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@chromium.org>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@google.com>
-Patrick Rudolph  <siro@das-labor.org> <patrick.rudolph@9elements.com>
-Paul Fagerburg <pfagerburg@chromium.org> <pfagerburg@google.com>
-Paul Kocialkowski <contact@paulk.fr>
-Paul Ma <magf@bitland.com.cn> <magf@bitland.corp-partner.google.com>
-Paul Ma <magf@bitland.com.cn> Magf - <magf@bitland.corp-partner.google.com>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@mailbox.org>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@users.sourceforge.net>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Philip Chen <philipchen@google.com>
-Philip Chen <philipchen@google.com> <philipchen@chromium.org>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <philipp.deppenwiese@9elements.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <zaolin@das-labor.org>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> <piotr.kleins@gmail.com>
-Piotr Szymaniak <szarpaj@grubelek.pl>
-Po Xu <jg_poxu@mediatek.com>
-Po Xu <jg_poxu@mediatek.com> <jg_poxu@mediatek.corp-partner.google.com>
-Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
-Preetham Chandrian <preetham.chandrian@intel.com>
-Puthikorn Voravootivat <puthik@chromium.org> <puthik@google.com>
-QingPei Wang <wangqingpei@gmail.com>
-Quan Tran <qeed.quan@gmail.com>
-Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
-Raul Rangel <rrangel@chromium.org>
-Ravi Kumar Bokka <rbokka@codeaurora.org>
-Ravindra <ravindra@intel.com>
-Ravindra <ravindra@intel.com> Ravindra N <ravindra@intel.corp-partner.google.com>
-Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
-Raymond Chung <raymondchung@ami.corp-partner.google.com>
-Raymond Danks <raymonddanks@gmail.com> <ray.danks@se-eng.com>
-Reka Norman <rekanorman@google.com> <rekanorman@chromium.org>
-Ren Kuo <ren.kuo@quantatw.com>
-Ren Kuo <ren.kuo@quantatw.com> <ren.kuo@quanta.corp-partner.google.com>
-Rex-BC Chen <rex-bc.chen@mediatek.com> <rex-bc.chen@mediatek.corp-partner.google.com>
-Ricardo Ribalda <ribalda@chromium.org> <ricardo.ribalda@gmail.com>
-Richard Spiegel <richard.spiegel@silverbackltd.com> <richard.spiegel@amd.corp-partner.google.com>
-Rishavnath Satapathy <rishavnath.satapathy@intel.com>
-Ritul Guru <ritul.bits@gmail.com>
-Rizwan Qureshi <rizwan.qureshi@intel.com> <rizwan.qureshi@intel.corp-partner.google.com>
-Robbie Zhang <robbie.zhang@intel.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com> = <robert.chen@quanta.corp-partner.google.com>
-Roger Pau Monne <roger.pau@citrix.com>
-Roman Kononov <kononov@dls.net> <kononov195-lbl@yahoo.com>
-Ron Minnich <rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> <Ron Minnich>
-Ron Minnich <rminnich@gmail.com> <Ronald G. Minnich rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <minnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@chromium.org>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@lanl.gov>
-Ron Minnich <rminnich@gmail.com> ronald g. minnich <ronald g. minnich>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <Ronald G. Minnich>
-Ronak Kanabar <ronak.kanabar@intel.com>
-Rudolf Marek <r.marek@assembler.cz> <r.marek@asssembler.cz>
-Ryan Chuang <ryan.chuang@mediatek.com> <ryan.chuang@mediatek.corp-partner.google.com>
-Santhosh Janardhana Hassan <sahassan@google.com>
-Scott Chao <scott_chao@wistron.corp-partner.google.com> <scott.chao@bitland.corp-partner.google.com>
-Scott Duplichan <scott@notabs.org> <sc...@notabs.org>
-Scott Tsai <AT>
-Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
-Selma Bensaid <selma.bensaid@intel.com>
-Seunghwan Kim <sh_.kim@samsung.com>
-Seunghwan Kim <sh_.kim@samsung.com> <sh_.kim@samsung.corp-partner.google.com>
-Seunghwan Kim <sh_.kim@samsung.com> sh.kim <sh_.kim@samsung.corp-partner.google.com>
-Shawn Chang <citypw@gmail.com>
-Shawn Nematbakhsh <shawnn@google.com> <shawnn@chromium.org>
-Shelley Chen <shchen@google.com> <shchen@chromium.org>
-Sheng-Liang Pan <Sheng-Liang.Pan@quantatw.com> <sheng-liang.pan@quanta.corp-partner.google.com>
-Shreesh Chhabbi <shreesh.chhabbi@intel.com> <shreesh.chhabbi@intel.corp-partner.google.com>
-Shunqian Zheng <zhengsq@rock-chips.com>
-Siyuan Wang <wangsiyuanbuaa@gmail.com>
-Sowmya <v.sowmya@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com> <sridhar.siricilla@intel.corp-partner.google.com>
-Srinidhi Kaushik <srinidhi.n.kaushik@intel.com>
-Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
-Stefan Ott <stefan@ott.net> <coreboot@desire.ch>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@chromium.org>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@google.com>
-Stefan Reinauer <stepan@coreboot.org> <Stefan Reinauerstepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stefan.reinauer@coreboot.org>
-Stefan Reinauer <stepan@coreboot.org> <stepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stepan@openbios.org>
-Stephan Guilloux <stephan.guilloux@free.fr> <mailto:stephan.guilloux@free.fr>
-Subrata Banik <subratabanik@google.com> <subi.banik@gmail.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Sudheer Kumar Amrabadi <samrab@codeaurora.org>
-Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
-Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
-Susendra Selvaraj <susendra.selvaraj@intel.com>
-Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
-T Michael Turney <mturney@codeaurora.org> mturney mturney <quic_mturney@quicinc.com>
-T Michael Turney <mturney@codeaurora.org> T Michael Turney <quic_mturney@quicinc.com>
-T.H. Lin <T.H_Lin@quantatw.com> <t.h_lin@quanta.corp-partner.google.com>
-T.H. Lin <T.H_Lin@quantatw.com> T.H.Lin <T.H_Lin@quantatw.com>
-Taniya Das <quic_tdas@quicinc.com> <tdas@codeaurora.org>
-Tao Xia <xiatao5@huaqin.corp-partner.google.com>
-Thejaswani Putta  <thejaswani.putta@intel.com> <thejaswani.putta@intel.corp-partner.google.com>
-Thejaswani Putta <thejaswani.putta@intel.com>
-Thejaswani Putta <thejaswani.putta@intel.com> Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
-Thomas Heijligen <thomas.heijligen@secunet.com> <src@posteo.de>
-Tim Chen <Tim-Chen@quantatw.com> <tim-chen@quanta.corp-partner.google.com>
-Tim Chu <Tim.Chu@quantatw.com>
-Tim Wawrzynczak <twawrzynczak@chromium.org> <twawrzynczak@google.com>
-Timothy Pearson <tpearson@raptorengineering.com> <tpearson@raptorengineeringinc.com>
-Tinghan Shen <tinghan.shen@mediatek.com>
-Tobias Diedrich <ranma+coreboot@tdiedrich.de> <ranma+openocd@tdiedrich.de>
-Tracy Wu <tracy.wu@intel.com> <tracy.wu@intel.corp-partner.google.com>
-Tristan Corrick <tristan@corrick.kiwi> <tristancorrick86@gmail.com>
-Tyler Wang <tyler.wang@quanta.corp-partner.google.com> <Tyler.Wang@quanta.corp-partner.google.com>
-Usha P <usha.p@intel.com> <usha.p@intel.corp-partner.google.com>
-V Sujith Kumar Reddy <vsujithk@codeaurora.org>
-Vadim Bendebury <vbendeb@chromium.org> <vbendeb@google.com>
-Vaibhav Shankar <vaibhav.shankar@intel.com>
-Van Chen <van_chen@compal.corp-partner.google.com>
-Varshit Pandya <varshit.b.pandya@intel.com>
-Varshit Pandya <varshit.b.pandya@intel.com> Varshit B Pandya <varshit.b.pandya@intel.com>
-Varun Joshi <varun.joshi@intel.com> <varun.joshi@intel.corp-partner.google.com>
-Vincent Lim <vincent.lim@amd.com>  <Vincent Lim vincent.lim@amd.com>
-Vladimir Serbinenko <phcoder@gmail.com>
-Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> <Wayne3_Wang@pegatron.corp-partner.google.com>
-William Wu <wulf@rock-chips.com>
-Wim Vervoorn <wvervoorn@eltan.com>
-Wisley Chen <wisley.chen@quantatw.com>
-Wisley Chen <wisley.chen@quantatw.com> <wisley.chen@quanta.corp-partner.google.com>
-Xi Chen <xixi.chen@mediatek.com> <xixi.chen@mediatek.corp-partner.google.com>
-Xiang Wang <merle@hardenedlinux.org> <wxjstz@126.com>
-Xingyu Wu <wuxy@bitland.corp-partner.google.com>
-Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
-Yang A Fang <yang.a.fang@intel.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu at amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu@amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai@kernel.org>
-Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
-Yongqiang Niu <yongqiang.niu@mediatek.com>
-Youness Alaoui <snifikino@gmail.com> <kakaroto@kakaroto.homelinux.net>
-Youness Alaoui <snifikino@gmail.com> <youness.alaoui@puri.sm>
-Yu-Hsuan Hsu <yuhsuan@google.com>
-Yu-Hsuan Hsu <yuhsuan@google.com> <yuhsuan@chromium.org>
-Yu-Ping Wu <yupingso@google.com> <yupingso@chromium.org>
-Yuanlidingm <yuanliding@huaqin.corp-partner.google.com>
-Yuchen Huang <yuchen.huang@mediatek.com> <yuchen.huang@mediatek.corp-partner.google.com>
-Yuji Sasaki <sasakiy@chromium.org> <sasakiy@google.com>
-Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
-Zhi Li <lizhi7@huaqin.corp-partner.google.com>
-Zhongze Hu <frankhu@chromium.org> <frankhu@google.com>
-Zhuo-Hao Lee <zhuo-hao.lee@intel.com>
-Zhuohao Lee <zhuohao@chromium.org> <zhuohao@google.com>
--- a/3rdparty/amd_blobs
+++ b/3rdparty/amd_blobs
--- a/3rdparty/arm-trusted-firmware
+++ b/3rdparty/arm-trusted-firmware
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
--- a/3rdparty/chromeec
+++ b/3rdparty/chromeec
--- a/3rdparty/cmocka
+++ b/3rdparty/cmocka
--- a/3rdparty/ffs
+++ b/3rdparty/ffs
--- a/3rdparty/fsp
+++ b/3rdparty/fsp
--- a/3rdparty/intel-microcode
+++ b/3rdparty/intel-microcode
--- a/3rdparty/intel-sec-tools
+++ b/3rdparty/intel-sec-tools
--- a/3rdparty/libgfxinit
+++ b/3rdparty/libgfxinit
--- a/3rdparty/libhwbase
+++ b/3rdparty/libhwbase
--- a/3rdparty/opensbi
+++ b/3rdparty/opensbi
--- a/3rdparty/qc_blobs
+++ b/3rdparty/qc_blobs
--- a/3rdparty/stm
+++ b/3rdparty/stm
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
--- a/247
+++ b/247
@ -1,247 +0,0 @@
-# This is the list of coreboot authors for copyright purposes.
-#
-# This does not necessarily list everyone who has contributed code, since in
-# some cases, their employer may be the copyright holder.  To see the full list
-# of contributors, and their email addresses, see the revision history in source
-# control.
-# Run the below commands in the coreboot repo for additional information.
-# To see a list of contributors: git log --pretty=format:%an | sort | uniq
-# For patches adding or removing a name: git log -i -S "NAME" --source --all
-
-3mdeb Embedded Systems Consulting
-9elements Agency GmbH
-Abhinav Hardikar
-Advanced Computing Lab, LANL
-Advanced Micro Devices, Inc.
-AdaCore
-AG Electronics Ltd.
-Alex Thiessen
-Alex Züpke
-Alexander Couzens
-Alexandru Gagniuc
-Analog Devices Inc.
-Analogix Semiconductor
-Andre Heider
-Andriy Gapon
-Andy Fleming
-Angel Pons
-Anton Kochkov
-ARM Limited and Contributors
-Arthur Heymans
-Asami Doi
-ASPEED Technology Inc.
-Atheros Corporation
-Atmel Corporation
-BAP - Bruhnspace Advanced Projects
-Bill Xie
-Bitland Tech Inc.
-Boris Barbulovski
-Carl-Daniel Hailfinger
-Cavium Inc.
-Christoph Grenz
-Code Aurora Forum
-coresystems GmbH
-Corey Osgood
-Curt Brune
-Custom Ideas
-Damien Zammit
-Dave Airlie
-David Brownell
-David Greenman
-David Hendricks
-David Mosberger-Tang
-David Mueller
-David S. Peterson
-Denis 'GNUtoo' Carikli
-Denis Dowling
-DENX Software Engineering
-Derek Waldner
-Digital Design Corporation
-DMP Electronics Inc.
-Donghwa Lee
-Drew Eckhardt
-Dynon Avionics
-Edward O'Callaghan
-Egbert Eich
-ELSOFT AG
-Eltan B.V
-Elyes Haouas
-Eric Biederman
-Eswar Nallusamy
-Evgeny Zinoviev
-Fabian Kunkel
-Fabrice Bellard
-Facebook, Inc.
-Felix Held
-Felix Singer
-Frederic Potter
-Free Software Foundation, Inc.
-Freescale Semiconductor, Inc.
-Gary Jennejohn
-George Trudeau
-Gerald Van Baren
-Gerd Hoffmann
-Gergely Kiss
-Google LLC
-Greg Watson
-Guennadi Liakhovetski
-Hal Martin
-HardenedLinux
-Hewlett-Packard Development Company, L.P.
-Hewlett Packard Enterprise Development LP
-Huaqin Telecom Inc.
-IBM Corporation
-Idwer Vollering
-Igor Pavlov
-Imagination Technologies
-Infineon Technologies
-InKi Dae
-Intel Corporation
-Iru Cai
-Isaku Yamahata
-Ivan Vatlin
-James Ye
-Jason Zhao
-Joe Pillow
-Johanna Schander
-Jonas 'Sortie' Termansen
-Jonathan A. Kollasch
-Jonathan Neuschäfer
-Jordan Crouse
-Jörg Mische
-Joseph Smith
-Keith Hui
-Keith Packard
-Kevin Cody-Little
-Kevin O'Connor
-Kontron Europe GmbH
-Kshitij
-Kyösti Mälkki
-Leah Rowe
-Lei Wen
-Li-Ta Lo
-Libra Li
-Libretrend LDA
-Linaro Limited
-Linus Torvalds
-Linux Networx, Inc.
-LiPPERT ADLINK Technology GmbH
-Lubomir Rintel
-Luc Verhaegen
-Maciej Matuszczyk
-Marc Bertens
-Marc Jones
-Marek Vasut
-Marius Gröger
-Martin Mares
-Martin Renters
-Martin Roth
-Marvell International Ltd.
-Marvell Semiconductor Inc.
-Matt DeVillier
-Maxim Polyakov
-MediaTek Inc.
-Michael Brunner
-Michael Schroeder
-Michael Niewöhner
-Mika Westerberg
-Mondrian Nuessle
-MontaVista Software, Inc.
-Myles Watson
-Network Appliance Inc.
-Nicholas Sielicki
-Nick Barker
-Nico Huber
-Nico Rikken
-Nicola Corna
-Nils Jacobs
-Nir Tzachar
-Nokia Corporation
-NVIDIA Corporation
-Olivier Langlois
-Ollie Lo
-Omar Pakker
-Online SAS
-Orion Technologies, LLC
-Patrick Georgi
-Patrick Rudolph
-Pattrick Hueper
-Paulo Alcantara
-Pavel Sayekat
-PC Engines GmbH
-Per Odlund
-Peter Korsgaard
-Peter Stuge
-Philipp Degler
-Philipp Deppenwiese
-Philipp Hug
-Protectli
-Purism SPC
-Qualcomm Technologies
-Raptor Engineering, LLC
-Red Hat, Inc
-Reinhard Meyer
-Renze Nicolai
-Richard Spiegel
-Richard Woodruff
-Rob Landley
-Robert Reeves
-Robinson P. Tryon
-Rockchip, Inc.
-Romain Lievin
-Roman Zippel
-Ronald G. Minnich
-Rudolf Marek
-Russell King
-Ruud Schramp
-Sage Electronic Engineering, LLC
-Sam Ravnborg
-Samsung Electronics
-Samuel Holland
-SciTech Software, Inc.
-Sebastian Grzywna
-secunet Security Networks AG
-Sencore Inc
-Sergej Ivanov
-Siemens AG
-SiFive, Inc
-Silicon Integrated System Corporation
-Silverback Ltd.
-Stefan Reinauer
-Stefan Tauner
-Steve Magnani
-Steve Shenton
-ST Microelectronics
-SUSE LINUX AG
-Sven Schnelle
-Syed Mohammed Khasim
-System76
-Texas Instruments
-The Android Open Source Project
-The ChromiumOS Authors
-The Linux Foundation
-The Regents of the University of California
-Thomas Winischhofer
-Timothy Pearson
-Tobias Diedrich
-Tristan Corrick
-Tungsten Graphics, Inc.
-Tyan Computer Corp.
-ucRobotics Inc.
-University of Heidelberg
-Uwe Hermann
-VIA Technologies, Inc
-Vikram Narayanan
-Vipin Kumar
-Vladimir Serbinenko
-Vlado Cibic
-Wang Qing Pei
-Ward Vandewege
-Wilbert Duijvenvoorde
-Win Enterprises
-Wiwynn Corp.
-Wolfgang Denk
-YADRO
-Yann Collet
-Yinghai Lu
-Zachary Yedidia
--- a/Documentation/.gitignore
+++ b/Documentation/.gitignore
@ -1,7 +0,0 @@
-*.aux
-*.idx
-*.log
-*.toc
-*.out
-*.pdf
-_build
--- a/Documentation/.mdl_style.rb
+++ b/Documentation/.mdl_style.rb
@ -1,9 +0,0 @@
-# See one of the following URLs for explanations of all the rules
-# https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-# https://web.archive.org/web/20220424164542/https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-
-all
-exclude_rule 'no-multiple-blanks'
-exclude_rule 'blanks-around-headers'
-exclude_rule 'blanks-around-lists'
-rule 'line-length', :line_length => 72
--- a/Documentation/util/ifdtool/binary_extraction.md
+++ b/Documentation/util/ifdtool/binary_extraction.md
--- a/Documentation/Doxyfile.coreboot
+++ b/Documentation/Doxyfile.coreboot
--- a/Documentation/Doxyfile.coreboot_simple
+++ b/Documentation/Doxyfile.coreboot_simple
@ -0,0 +1,258 @@
+# Doxyfile 1.8.8
+DOXYFILE_ENCODING      = UTF-8
+PROJECT_NAME           = coreboot
+PROJECT_NUMBER         =
+PROJECT_BRIEF          = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
+PROJECT_LOGO           = Documentation/coreboot_logo.png
+OUTPUT_DIRECTORY       = doxygen
+CREATE_SUBDIRS         = YES
+ALLOW_UNICODE_NAMES    = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       =
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = YES
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+QT_AUTOBRIEF           = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                =
+TCL_SUBST              =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+OPTIMIZE_FOR_FORTRAN   = NO
+OPTIMIZE_OUTPUT_VHDL   = NO
+EXTENSION_MAPPING      =
+MARKDOWN_SUPPORT       = YES
+AUTOLINK_SUPPORT       = YES
+BUILTIN_STL_SUPPORT    = NO
+CPP_CLI_SUPPORT        = NO
+SIP_SUPPORT            = NO
+IDL_PROPERTY_SUPPORT   = YES
+DISTRIBUTE_GROUP_DOC   = NO
+SUBGROUPING            = YES
+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS  = NO
+TYPEDEF_HIDES_STRUCT   = NO
+LOOKUP_CACHE_SIZE      = 0
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = NO
+EXTRACT_PACKAGE        = NO
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+EXTRACT_ANON_NSPACES   = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = YES
+HIDE_SCOPE_NAMES       = NO
+SHOW_INCLUDE_FILES     = YES
+SHOW_GROUPED_MEMB_INC  = NO
+FORCE_LOCAL_INCLUDES   = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES       = NO
+SORT_BY_SCOPE_NAME     = NO
+STRICT_PROTO_MATCHING  = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_FILES             = YES
+SHOW_NAMESPACES        = YES
+FILE_VERSION_FILTER    =
+LAYOUT_FILE            =
+CITE_BIB_FILES         =
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           =
+INPUT                  = src
+INPUT_ENCODING         = UTF-8
+FILE_PATTERNS          =
+RECURSIVE              = YES
+EXCLUDE                = src/vendorcode
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXCLUDE_SYMBOLS        =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       =
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+FILTER_SOURCE_PATTERNS =
+USE_MDFILE_AS_MAINPAGE =
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = NO
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+REFERENCES_LINK_SOURCE = YES
+SOURCE_TOOLTIPS        = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = YES
+ALPHABETICAL_INDEX     = YES
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_EXTRA_STYLESHEET  =
+HTML_EXTRA_FILES       =
+HTML_COLORSTYLE_HUE    = 220
+HTML_COLORSTYLE_SAT    = 100
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+HTML_DYNAMIC_SECTIONS  = NO
+HTML_INDEX_NUM_ENTRIES = 100
+GENERATE_DOCSET        = NO
+DOCSET_FEEDNAME        = "Doxygen documentation"
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+DOCSET_PUBLISHER_NAME  = Publisher
+GENERATE_HTMLHELP      = NO
+CHM_FILE               =
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+MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
+MATHJAX_EXTENSIONS     =
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+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
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+GENERATE_XML           = NO
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+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
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+PERLMOD_MAKEVAR_PREFIX =
+ENABLE_PREPROCESSING   = YES
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+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           =
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             = __attribute__(x)=
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+EXTERNAL_PAGES         = YES
+PERL_PATH              = /usr/bin/perl
+CLASS_DIAGRAMS         = YES
+MSCGEN_PATH            =
+DIA_PATH               =
+HIDE_UNDOC_RELATIONS   = NO
+HAVE_DOT               = NO
+DOT_NUM_THREADS        = 0
+DOT_FONTNAME           = Helvetica
+DOT_FONTSIZE           = 10
+DOT_FONTPATH           =
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = YES
+UML_LIMIT_NUM_FIELDS   = 10
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = YES
+CALLER_GRAPH           = YES
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+INTERACTIVE_SVG        = NO
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DIAFILE_DIRS           =
+PLANTUML_JAR_PATH      =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = YES
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES
--- a/Documentation/Intel/Board/Galileo_checklist.html
+++ b/Documentation/Intel/Board/Galileo_checklist.html
@ -0,0 +1,162 @@
+<html>
+<head>
+<title>Galileo Implementation Status</title>
+</title>
+<body>
+<h1>Galileo Implementation Status<br>2016/07/08 06:51:34 PDT</h1>
+<table>
+  <tr><td colspan=2><b>Legend</b></td></tr>
+  <tr><td bgcolor="#ffc0c0">Red</td><td>Required - To-be-implemented</td></tr>
+  <tr><td bgcolor="#ffffc0">Yellow</td><td>Optional</td></tr>
+  <tr><td bgcolor="#c0ffc0">Green</td><td>Implemented</td></tr>
+</table>
+<table>
+  <tr valign="top">
+    <td>
+<table border=1>
+<tr><th colspan=2>bootblock: 100% Done</th></tr>
+<tr><th>Type</th><th>Routine</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_c_entry</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_main_with_timestamp</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_early_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_mainboard_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_pre_c_entry</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_protected_mode_entry</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>bootblock_soc_early_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>bootblock_soc_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>uart_init</td></tr>
+</table>
+    </td>
+    <td width=5>&nbsp;</td>
+    <td>
+<table border=1>
+<tr><th colspan=2>romstage: 67% Done</th></tr>
+<tr><th>Type</th><th>Routine</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_post_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_pre_console_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>car_stage_entry</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>fill_power_state</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_fill_spd_data</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>mainboard_romstage_entry</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_save_dimm_info</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>migrate_power_state</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_get_current_with_version</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_stash_data_with_version</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>print_fsp_info</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>raminit</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>ramstage_cache_invalid</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>romstage_common</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>set_max_freq</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>setup_stack_and_mtrrs</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_memory_init_params</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>timestamp_get</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vboot_platform_prepare_reboot</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>verstage_mainboard_init</td></tr>
+</table>
+    </td>
+    <td width=5>&nbsp;</td>
+    <td>
+<table border=1>
+<tr><th colspan=2>ramstage: 60% Done</th></tr>
+<tr><th>Type</th><th>Routine</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>fw_cfg_acpi_tables</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_silicon_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_suspend_resume</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>northbridge_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>nvm_mmio_to_flash_offset</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_bios_version</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_silicon_init_params</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_get</td></tr>
+<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_tick_freq_mhz</td></tr>
+<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>wifi_regulatory_domain</td></tr>
+<tr bgcolor=#ffffc0><td>Optional</td><td>write_smp_table</td></tr>
+</table>
+    </td>
+    <td width=5>&nbsp;</td>
+  </tr>
+</table>
+</body>
+</html>
--- a/Documentation/Intel/Board/board.html
+++ b/Documentation/Intel/Board/board.html
@ -0,0 +1,239 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Board</title>
+  </head>
+  <body>
+
+<h1>x86 Board Development</h1>
+<p>
+  Board development requires System-on-a-Chip (SoC) support.
+  The combined steps are listed
+  <a target="_blank" href="../development.html">here</a>.
+  The development steps for the board are listed below:
+</p>
+<ol>
+  <li><a href="#RequiredFiles">Required Files</a></li>
+  <li>Enable <a href="#SerialOutput">Serial Output</a></li>
+  <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
+  <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
+  <li><a href="#AcpiTables">ACPI Tables</a></li>
+</ol>
+
+
+<hr>
+<h2><a name="RequiredFiles">Required Files</a></h2>
+<p>
+  Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
+</p>
+
+<p>
+  The following files are required to build a new board:
+</p>
+<ol>
+  <li>Kconfig.name - Defines the Kconfig value for the board</li>
+  <li>Kconfig
+    <ol type="A">
+      <li>Selects the SoC for the board and specifies the SPI flash size
+        <ol type="I">
+          <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
+          <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
+        </ol>
+      </li>
+      <li>Declare the Kconfig values for:
+        <ol type="I">
+          <li>MAINBOARD_DIR</li>
+          <li>MAINBOARD_PART_NUMBER</li>
+          <li>MAINBOARD_VENDOR</li>
+        </ol>
+      </li>
+    </ol>
+  </li>
+  <li>devicetree.cb - Enable root bridge and serial port
+    <ol type="A">
+      <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
+        this path is used by the generated static.c to include the chip.h
+        header file
+      </li>
+    </ol>
+  </li>
+  <li>romstage.c
+    <ol type="A">
+      <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
+    </ol>
+  </li>
+  <li>Configure coreboot build:
+    <ol type="A">
+      <li>Set LOCALVERSION</li>
+      <li>Select vendor for the board</li>
+      <li>Select the board</li>
+      <li>CBFS_SIZE = 0x00100000</li>
+      <li>Set the CPU_MICROCODE_CBFS_LEN</li>
+      <li>Set the CPU_MICROCODE_CBFS_LOC</li>
+      <li>Set the FSP_IMAGE_ID_STRING</li>
+      <li>Set the FSP_LOC</li>
+      <li>No payload</li>
+      <li>Choose the default value for all other options</li>
+    </ol>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="SerialOutput">Enable Serial Output</a></h2>
+<p>
+  Use the following steps to enable serial output:
+</p>
+<ol>
+  <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
+    file:
+    <ol type="A">
+      <li>Power on and enable the UART controller</li>
+      <li>Connect the UART receive and transmit data lines to the
+        appropriate SoC pins
+      </li>
+    </ol>
+  </li>
+  <li>Add Makefile.inc
+    <ol type="A">
+      <li>Add com_init.c to romstage</li>
+    </ol>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="SpdData">Memory Timing Data</a></h2>
+<p>
+  Memory timing data is located in the flash.  This data is in the format of
+  <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
+  (SPD) data.
+  Use the following steps to load the SPD data:
+</p>
+<ol>
+  <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
+    display of the SPD data being passed to MemoryInit
+  </li>
+  <li>Create an "spd" subdirectory</li>
+  <li>Create an spd/spd.c file for the SPD implementation
+    <ol type="A">
+      <li>Implement the mainboard_fill_spd_data routine
+        <ol type="i">
+          <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
+          <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
+          <li>Set the DIMM channel configuration</li>
+        </ol>
+      </li>
+    </ol>
+  </li>
+  <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
+  <li>Create spd/Makefile.inc
+    <ol type="A">
+      <li>Add spd.c to romstage</li>
+      <li>Add the .spd.hex file to SPD_SOURCES</li>
+    </ol>
+  </li>
+  <li>Edit Makefile.inc to add the spd subdirectory</li>
+  <li>Edit romstage.c
+    <ol type="A">
+      <li>Call mainboard_fill_spd_data</li>
+      <li>Add mainboard_memory_init_params to copy the SPD and DRAM
+        configuration data from the pei_data structure into the UPDs
+        for MemoryInit
+      </li>
+    </ol>
+  </li>
+  <li>Edit devicetree.cb
+    <ol type="A">
+      <li>Include the UPD parameters for MemoryInit except for:
+        <ul>
+          <li>Address of SPD data</li>
+          <li>DRAM configuration set above</li>
+        </ul>
+      </li>
+    </ol>
+  </li>
+  <li>A working FSP
+    <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
+    routine is required to complete debugging</li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x34:
+        - Just after entering
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
+      </li>
+      <li>0x36:
+        - Just before displaying the
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
+        for FSP MemoryInit
+      </li>
+      <li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
+        - Just before calling FSP
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
+      </li>
+      <li>0x37:
+        - Just after returning from FSP
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
+      </li>
+    </ol>
+  </li>
+  <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
+</ol>
+
+
+
+<hr>
+<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2>
+<p>
+  Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
+  of the devices in the system.  Edit the devicetree.cb file:
+</p>
+<ol>
+  <li>Edit the devicetree.cb file:
+    <ol type="A">
+      <li>Add an entry for a PCI device.function and turn it off.  The entry
+        should look similar to:
+<pre><code>device pci 14.0 off end</code></pre>
+      </li>
+      <li>Turn on the devices for:
+        <ul>
+          <li>Memory Controller</li>
+          <li>Debug serial device</li>
+        </ul>
+      </li>
+    </ol>
+  </li>
+  <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
+</ol>
+
+
+
+<hr>
+<h2><a name="AcpiTables">ACPI Tables</a></h2>
+<ol>
+  <li>Edit Kconfig
+    <ol type="A">
+      <li>Add "select HAVE_ACPI_TABLES"</li>
+    </ol>
+  </li>
+  <li>Add the acpi_tables.c module:
+    <ol type="A">
+      <li>Include soc/acpi.h</li>
+      <li>Add the acpi_create_fadt routine
+        <ol type="I">
+          <li>fill in the ACPI header</li>
+          <li>Call the acpi_fill_in_fadt routine</li>
+        </ol>
+      </li>
+    </ol>
+  </li>
+  <li>Add the dsdt.asl module:
+  </li>
+</ol>
+
+
+
+<hr>
+<p>Modified: 20 February 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/Board/galileo.html
+++ b/Documentation/Intel/Board/galileo.html
@ -0,0 +1,114 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Galileo</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; Galileo Development Board</h1>
+<table>
+  <tr>
+    <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td>
+    <td>
+      The Intel&reg; Galileo Gen 2 mainboard code was developed along with the Intel&reg;
+      <a target="_blank" href="../SoC/quark.html">Quark&trade;</a> SoC:
+      <ul>
+        <li><a target="_blank" href="../development.html">Overall</a> development</li>
+        <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li>
+        <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
+        <li><a target="_blank" href="board.html">Board</a> support</li>
+        <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li>
+      </ul>
+    </td>
+  </tr>
+</table>
+
+
+
+<hr>
+<h2>Galileo Board Documentation</h2>
+<ul>
+  <li>Common Components
+    <ul>
+      <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li>
+      <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li>
+      <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li>
+      <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li>
+      <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li>
+      <li>SoC: Intel&reg; Quark&trade; <a target="_blank" href="../SoC/quark.html">X-1000</a></li>
+      <li>Serial EEPROM (1 KiB): ON Semiconductor&reg; <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li>
+      <li>SPI Flash (8 MiB): Winbond&trade; <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li>
+      <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li>
+      <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li>
+      <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li>
+    </ul>
+  </li>
+  <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li>
+</ul>
+
+<h3>Galileo Gen 2 Board Documentation</h3>
+<ul>
+  <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li>
+  <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li>
+  <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li>
+  <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li>
+  <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li>
+  <li>Components
+    <ul>
+      <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li>
+      <li>I2C 16-channel, 12-bit PWM: NXP Semiconductors <a target="_blank" href="http://cache.nxp.com/documents/data_sheet/PCA9685.pdf">PCA9685</a></li>
+      <li>I2C I/O Ports: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf">PCAL9535A</a></li>
+      <li>Octal Buffer/Driver: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf">SN74LV541AT</a></li>
+      <li>Quadruple Bus Buffer: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf">SN74LV125A</a></li>
+      <li>Quadruple Bus Buffer with 3-State Outputs: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf">SN74LVC126A</a></li>
+      <li>Serial EEPROM (1 KiB): ON Semiconductor&reg; <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li>
+      <li>Single 2-input multiplexer: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf">74LVC1G157</a></li>
+      <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li>
+    </ul>
+  </li>
+</ul>
+
+<h3>Galileo Gen 1 Board Documentation</h3>
+<ul>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galileo-g1-datasheet.pdf">Datasheet</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g1-schematic.pdf">Schematic</a></li>
+  <li>Components
+    <ul>
+      <li>A/D: Analog Devices <a target="_blank" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1.pdf">AD7298</a></li>
+      <li>Analog Switch, 2 channel: Texas Instruments <a target="_blank" href="http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li>
+      <li>EEPROM & GPIO: Cypress <a target="_blank" href="http://www.cypress.com/file/37971/download">CY8C9540A</a></li>
+      <li>Power Distribution Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps2044b.pdf">TPS2051BDBVR</a></li>
+      <li>RS232 Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/max3232.pdf">MAX3232</a></li>
+      <li>Voltage-Level Translator: Texas Instruments<a target="_blank" href="http://www.ti.com/lit/ds/symlink/txs0108e.pdf">TXS0108E</a></li>
+    </ul>
+  </li>
+</ul>
+
+
+
+<hr>
+<h2>Debug Tools</h2>
+<ul>
+  <li>Flash Programmer:
+    <ul>
+      <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li>
+    </ul>
+  </li>
+  <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li>
+  <li>JTAG Debugger:
+    <ul>
+      <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li>
+      <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li>
+    </ul>
+  </li>
+  <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li>
+  <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li>
+</ul>
+
+
+<hr>
+<p>Modified: 29 February 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md
+++ b/Documentation/Intel/MultiProcessorInit/MultiProcessorInit.md
@ -0,0 +1,74 @@
+# Intel Common Code Block Publishing EFI_MP_SERVICES_PPI
+
+## Introduction
+
+This documentation is intended to document the purpose for creating EFI service
+Interface inside coreboot space to perform CPU feature programming on Application
+Processors for Intel 9th Gen (Cannon Lake) and beyond CPUs.
+
+Today coreboot is capable enough to handle multi-processor initialization on IA platforms.
+
+The multi-processor initialization code has to take care of lots of duties:
+
+1 Bringing all cores out of reset
+2 Load latest microcode on all cores
+3 Sync latest MTRR snapshot between BSP and APs
+4 Perform sets of CPU feature programming
+  * CPU Power & Thermal Management
+  * Overclocking
+  * Intel Trusted Execution Technology
+  * Intel Software Guard Extensions
+  * Intel Processor Trace etc.
+
+This above CPU feature programming lists are expected to grow with current and future
+CPU complexity and there might be some cases where certain feature programming mightbe
+closed source in nature.
+
+Platform code might need to compromise on those closed source nature of CPU programming
+if we don't plan to provide an alternate interface which can be used by coreboot to
+get-rid of such close source CPU programming.
+
+## Proposal
+
+As coreboot is doing CPU multi-processor initialization for IA platform before FSP-S
+initialization and having all possible information about cores in terms of maximum number
+of cores, APIC ids, stack size etc. It’s also possible for coreboot to extend its own
+support model and create a sets of APIs which later can be used by FSP to run CPU feature
+programming using coreboot published APIs.
+
+Due to the fact that FSP is using EFI infrastructure and need to relying on install/locate
+PPI to perform certain API call, hence coreboot has to created MP services APIs known as
+EFI_MP_SERVICES_PPI as per PI specification volume 1, section 8.3.9.
+More details here: http://www.uefi.org/sites/default/files/resources/PI_Spec_1_6.pdf
+
+### coreboot to publish EFI_MP_SERVICES_PPI APIs
+| API                          | Description                                                      |
+|------------------------------|------------------------------------------------------------------|
+| PeiGetNumberOfProcessors     | Get the number of CPU's.                                         |
+| PeiGetProcessorInfo          | Get information on a specific CPU.                               |
+| PeiStartupAllAPs             | Activate all of the application processors.                      |
+| PeiStartupThisAP             | Activate a specific application processor.                       |
+| PeiSwitchBSP                 | Switch the boot strap processor.                                 |
+| PeiEnableDisableAP           | Enable or disable an application processor.                      |
+| PeiWhoAmI                    | Identify the currently executing processor.                      |
+|------------------------------|------------------------------------------------------------------|
+
+
+## Code Flow
+
+Here is proposed design flow with coreboot has implemented EFI_MP_SERVICES_PPI API and FSP will make
+use of the same to perform some CPU feature programming.
+
+** coreboot-FSP MP init flow **
+![alt text][coreboot_publish_mp_service_api]
+
+[coreboot_publish_mp_service_api]: coreboot_publish_mp_service_api.png "coreboot-fsp mp init flow"
+
+## Benefits
+1. coreboot was using SkipMpInit=1 which will skip entire FSP CPU feature programming.
+With proposed model, coreboot will make use of SkipMpInit=0 which will allow to run all
+Silicon recommended CPU programming.
+2. CPU feature programming inside FSP will be more transparent than before as it’s using
+coreboot interfaces to execute those programming.
+3. coreboot will have more control over running those feature programming as API optimization
+handled by coreboot.
--- a/Documentation/Intel/MultiProcessorInit/coreboot_publish_mp_service_api.png
+++ b/Documentation/Intel/MultiProcessorInit/coreboot_publish_mp_service_api.png
--- a/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
+++ b/Documentation/Intel/NativeRaminit/SandyBridge_registers.md
--- a/Documentation/Intel/NativeRaminit/Sandybridge.md
+++ b/Documentation/Intel/NativeRaminit/Sandybridge.md
@ -0,0 +1,135 @@
+# Sandy Bridge Raminit
+
+## Introduction
+
+This documentation is intended to document the closed source memory controller
+hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs.
+
+The memory initialization code has to take care of lots of duties:
+1. Selection of operating frequency
+* Selection of common timings
+* Applying frequency specific compensation values
+* Read training of all populated channels
+* Write training of all populated channels
+* Adjusting delay networks of address and command signals
+* DQS training of all populated channels
+* Programming memory map
+* Report DRAM configuration
+* Error handling
+
+## Definitions
+```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
+=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| timA    | IO phase: The phase delay of the IO signals                       | 1/64th DCK | [0-512)      |
+---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | Mhz        | 100, 133     |
+---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
+---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+```
+
+## (Inoffical) register documentation
+- [Sandy Bride - Register documentation](SandyBridge_registers.md)
+
+## Frequency selection
+- [Sandy Bride - Frequency selection](Sandybridge_freq.md)
+
+## Read training
+- [Sandy Bride - Read training](Sandybridge_read.md)
+
+### SMBIOS type 17
+The SMBIOS specification allows to report the memory configuration in use.
+On GNU/Linux you can run `# dmidecode -t 17` to view it.
+Example output of dmidecode:
+
+```
+Handle 0x0045, DMI type 17, 34 bytes
+    Memory Device
+	Array Handle: 0x0042
+	Error Information Handle: Not Provided
+	Total Width: 64 bits
+	Data Width: 64 bits
+	Size: 8192 MB
+	Form Factor: DIMM
+	Set: None
+	Locator: ChannelB-DIMM0
+	Bank Locator: BANK 2
+	Type: DDR3
+	Type Detail: Synchronous
+	Speed: 933 MHz
+	Manufacturer: 0420
+	Serial Number: 00000000
+	Asset Tag: 9876543210
+	Part Number: F3-1866C9-8GSR
+	Rank: 2
+	Configured Clock Speed: 933 MHz
+```
+The memory frequency printed by dmidecode is the active memory frequency. It's
+**not** the double datarate and it's **not** the one encoded maximum frequency
+in each DIMM's SPD.
+
+> **Note:** This feature is available since coreboot 4.4
+
+### MRC cache
+The name *MRC cache* might be missleading as in case of *Native ram init*
+there's no MRC, but for historical reasons it's still named *MRC cache*.
+The MRC cache is part of flash memory that is writeable by coreboot.
+At the end of the boot process coreboot will write the RAM training results to
+flash for future use, as RAM training is time intensive. Storing the results
+allows to boot faster on normal boot and allows to support S3 resume,
+as the RAM training results can't be stored in RAM (you need to configure
+the memory controller first to access RAM).
+
+The MRC cache needs to be invalidated in case the memory configuration has
+been changed. To detect a changed memory configuration the CRC16 of each DIMM
+is stored to MRC cache.
+> **Note:** This feature is available since coreboot 4.4
+
+### Error handling
+As of writing the only supported error handling is to disable the failing
+channel and restart the memory training sequence. It's very likely to succeed,
+as memory channels operate independent of each other.
+In case no DIMM could be initilized coreboot will halt. The screen will stay
+black until you power of your device. On some platforms there's additional
+feedback to indicate such an event.
+
+If you find `dmidecode -t 17` to report only half of the memory installed,
+it's likely that a fatal memory init failure had happened.
+It is assumed, that a working board with less physical memory, is much better,
+than a board that doesn't boot at all.
+
+> **Note:** This feature is available since coreboot 4.5
+
+Try to swap memory modules and or try to use a different vendor. If nothing
+helps you could have a look at capter [Debuggin] or report a ticket
+at [ticket.coreboot.org]. Please provide a full RAM init log,
+that has been captured using EHCI debug.
+
+To enable extensive RAM training logging enable the Kconfig option
+`DEBUG_RAM_SETUP`
+#### Lenovo Thinkpads
+Lenovo Thinkpads do have an additional feature to indicate that RAM init has
+failed and coreboot has died (it calls die() on fatal error, thus the name).
+The Kconfig options
+`H8_BEEP_ON_DEATH`
+`H8_FLASH_LEDS_ON_DEATH`
+enable blinking LEDs and enable a beep to indicate death.
+
+> **Note:** This feature is available since coreboot 4.7
+
+## Debugging
+It's recommended to use an external debugger, such as serial or EHCI debug
+dongle. In case of failing memory init the board might not boot at all,
+preventing you from using CBMEM.
--- a/Documentation/Intel/NativeRaminit/Sandybridge_freq.md
+++ b/Documentation/Intel/NativeRaminit/Sandybridge_freq.md
@ -0,0 +1,165 @@
+# Frequency selection
+
+## Introduction
+This chapter explains the frequency selection done on Sandybride and Ivybridge.
+
+## Definitions
+```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
+=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | MHz        | 100, 133     |
+---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
+---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+```
+## SPD
+The [SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
+located on every DIMM is factory program with various timings. One of them
+specifies the maximum clock frequency the DIMM should be used with. The
+operating frequency is stores as fixed point value (tCK), rounded to the next
+smallest supported operating frequency. Some
+[SPD](https://de.wikipedia.org/wiki/Serial_Presence_Detect "Serial Presence Detect")
+contains additional and optional
+[XMP](https://de.wikipedia.org/wiki/Extreme_Memory_Profile "Extreme Memory Profile")
+data, that stores so called "performance" modes, that advertises higher clock
+frequencies.
+
+## XMP profiles
+At time of writing coreboot's raminit is able to parse XMP profile 1 and 2.
+Only **XMP profile 1** is being used in case it advertises:
+* 1.5V operating voltage
+* The channel's installed DIMM count doesn't exceed the XMP coded limit
+
+In case the XMP profile doesn't fullfill those limits, the regular SPD will be
+used.
+> **Note:** XMP Profiles are supported since coreboot 4.4.
+
+It is possible to ignore the max DIMM count limit set by XMP profiles.
+By activating Kconfig option `NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS` it is
+possible to install two DIMMs per channel, even if XMP tells you not to do.
+
+> **Note:** Ignoring XMP Profiles limit is supported since coreboot 4.7.
+
+## Soft fuses
+Every board manufacturer does program "soft" fuses to indicate the maximum
+DRAM frequency supported. However, those fuses don't set a limit in hardware
+and thus are called "soft" fuses, as it is possible to ignore them.
+
+> **Note:** Ignoring the fuses might cause system instability !
+
+On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being
+read. coreboot reads those registers and honors the limit in case the Kconfig
+option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set.
+Power users that want to let their RAM run at DRAM's "stock" frequency need to
+enable the Kconfig symbol.
+
+It is possible to override the soft fuses limit by using a board-specific
+[devicetree](#devicetree) setting.
+
+> **Note:** Ignoring max mem freq. fuses is supported since coreboot 4.7.
+
+## <a name="hard_fuses"></a> Hard fuses
+"Hard" fuses are programmed by Intel and limit the maximum frequency that can
+be used on a given CPU/board/chipset. At time of writing there's no register
+to read this limit, before trying to set a given DRAM frequency. The memory PLL
+won't lock, indicating that the chosen memory multiplier isn't available. In
+this case coreboot tries the next smaller memory multiplier until the PLL will
+lock.
+
+## <a name="devicetree"></a> Devicetree
+The devicetree register ```max_mem_clock_mhz``` overrides the "soft" fuses set
+by the board manufacturer.
+
+By using this register it's possible to force a minimum operating frequency.
+
+## Reference clock
+While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also
+supports 100 MHz reference clock. The reference clock is multiplied by the DRAM
+multiplier to select the DRAM frequency (SCK) by the following formula:
+
+ REFCK * MULT = 1 / DCK
+
+> **Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
+
+## Sandy Bride's supported frequencies
+```eval_rst
+------------+-----------+------------------+-------------------------+---------------+
+| SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
+============+===========+==================+=========================+===============+
+| 400        | DDR3-800  | 3                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 533        | DDR3-1066 | 4                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 666        | DDR3-1333 | 5                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 800        | DDR3-1600 | 6                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 933        | DDR3-1866 | 7                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 1066       | DDR3-2166 | 8                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+```
+
+## Ivybridge's supported frequencies
+```eval_rst
+------------+-----------+------------------+-------------------------+---------------+
+| SCK [Mhz]  | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment       |
+============+===========+==================+=========================+===============+
+| 400        | DDR3-800  | 3                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 533        | DDR3-1066 | 4                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 666        | DDR3-1333 | 5                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 800        | DDR3-1600 | 6                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 933        | DDR3-1866 | 7                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 1066       | DDR3-2166 | 8                | 133 MHz                 |               |
+------------+-----------+------------------+-------------------------+---------------+
+| 700        | DDR3-1400 | 7                | 100 MHz                 | '1            |
+------------+-----------+------------------+-------------------------+---------------+
+| 800        | DDR3-1600 | 8                | 100 MHz                 | '1            |
+------------+-----------+------------------+-------------------------+---------------+
+| 900        | DDR3-1800 | 9                | 100 MHz                 | '1            |
+------------+-----------+------------------+-------------------------+---------------+
+| 1000       | DDR3-2000 | 10               | 100 MHz                 | '1            |
+------------+-----------+------------------+-------------------------+---------------+
+| 1100       | DDR3-2200 | 11               | 100 MHz                 | '1            |
+------------+-----------+------------------+-------------------------+---------------+
+| 1200       | DDR3-2400 | 12               | 100 MHz                 | '1            |
+------------+-----------+------------------+-------------------------+---------------+
+```
+> '1: since coreboot 4.6
+
+## Multiplier selection
+coreboot select the maximum frequency to operate at by the following formula:
+```
+if devicetree's max_mem_clock_mhz > 0:
+     freq_max := max_mem_clock_mhz
+else:
+     freq_max := soft_fuse_max_mhz
+
+for i in SPDs:
+     freq_max := MIN(freq_max, ddr_spd_max_mhz[i])
+```
+
+As you can see, by using DIMMs with different maximum DRAM frequencies, the
+slowest DIMMs' frequency will be selected, to prevent over-clocking it.
+
+The selected frequency gives the PLL multiplier to operate at. In case the PLL
+locks (see Take me to [Hard fuses](#hard_fuses)) the frequency will be used for
+all DIMMs. At this point it's not possible to change the multiplier again,
+until the system has been powered off. In case the PLL doesn't lock, the next
+smaller multiplier will be used until a working multiplier will be found.
--- a/Documentation/Intel/NativeRaminit/Sandybridge_read.md
+++ b/Documentation/Intel/NativeRaminit/Sandybridge_read.md
@ -0,0 +1,153 @@
+# Read training
+
+## Introduction
+
+This chapter explains the read training sequence done on Sandy Bride and
+Ivy Bridge memory initialization.
+
+Read training is done to compensate the skew between DQS and SCK and to find
+the smallest supported roundtrip delay.
+
+Every board does have a vendor depended routing topology, and can be equip
+with any combination of DDR3 memory modules, that introduces different
+skew between the memory lanes. With DDR3 a "Fly-By" routing topology
+has been introduced, that makes the biggest part of DQS-SCK skew.
+The memory code measures the actual skew and actives delay gates,
+that will "compensate" the skew.
+
+When in read training the DRAM and the controller are placed in a special mode.
+On every read instruction the DRAM outputs a predefined pattern and the memory
+controller samples the DQS after a given delay. As the pattern is known, the
+actual delay of every lane can be measured.
+
+The values programmed in read training effect DRAM-to-MC transfers only !
+
+## Definitions
+```eval_rst
+---------+-------------------------------------------------------------------+------------+--------------+
+| Symbol  | Description                                                       | Units      | Valid region |
+=========+===================================================================+============+==============+
+| SCK     | DRAM system clock cycle time                                      | s          |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| tCK     | DRAM system clock cycle time                                      | 1/256th ns |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| DCK     | Data clock cycle time: The time between two SCK clock edges       | s          |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| timA    | IO phase: The phase delay of the IO signals                       | 1/64th DCK | [0-512)      |
+---------+-------------------------------------------------------------------+------------+--------------+
+| SPD     | Manufacturer set memory timings located on an EEPROM on every DIMM| bytes      |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| REFCK   | Reference clock, either 100 or 133                                | MHz        | 100, 133     |
+---------+-------------------------------------------------------------------+------------+--------------+
+| MULT    | DRAM PLL multiplier                                               |            | [3-12]       |
+---------+-------------------------------------------------------------------+------------+--------------+
+| XMP     | Extreme Memory Profiles                                           |            |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+| DQS     | Data Strobe signal used to sample all lane's DQ signals           |            |              |
+---------+-------------------------------------------------------------------+------------+--------------+
+```
+## Hardware
+The hardware does have delay logic blocks that can delay the DQ / DQS of a
+lane/rank by one or multiple clock cylces and it does have delay logic blocks
+that can delay the signal by a multiple of 1/64th DCK per lane.
+
+All delay values can be controlled via software by writing registers in the
+MCHBAR.
+
+## IO phase
+
+The IO phase can be adjusted in [0-512) * 1/64th DCK. Incrementing it by 64 is
+the same as Incrementing IO delay by 1.
+
+## IO delay
+Delays the DQ / DQS signal by one or multiple clock cycles.
+
+### Roundtrip time
+The roundtrip time is the time the memory controller waits for data arraving
+after a read has been issued. Due to clock-domain crossings, multiple
+delay instances and phase interpolators, the signal runtime to DRAM and back
+to memory controller defaults to 55 DCKs. The real roundtrip time has to be
+measured.
+
+After a read command has been issued, a counter counts down until zero has been
+reached and activates the input buffers.
+
+The following pictures shows the relationship between those three values.
+The picture was generated from 16 IO delay values times 64 timA values.
+The highest IO delay was set on the right-hand side, while the last block
+on the left-hand side has zero IO delay.
+
+#### roundtrip 55 DCKs
+![alt text][timA_lane0-3_rt55]
+
+[timA_lane0-3_rt55]: timA_lane0-3_rt55.png "timA for lane0 - lane3, roundtrip 55"
+
+#### roundtrip 54 DCKs
+![alt text][timA_lane0-3_rt54]
+
+[timA_lane0-3_rt54]: timA_lane0-3_rt54.png "timA for lane0 - lane3, roundtrip 54"
+
+
+#### roundtrip 53 DCKs
+![alt text][timA_lane0-3_rt53]
+
+[timA_lane0-3_rt53]: timA_lane0-3_rt53.png "timA for lane0 - lane3, roundtrip 53"
+
+As you can see the signal has some jitter as every sample was taken in a
+different loop iteration. The result register only contains a single bit per
+lane.
+
+## Algorithm
+### Steps
+The algorithm finds the roundtrip time, IO delay and IO phase. The IO phase
+will be adjusted to match the falling edge of the preamble of each lane.
+The roundtrip time is adjusted to an minimal value, that still includes the
+preamble.
+
+### Synchronize to data phase
+
+The first measurement done in read-leveling samples all DQS values for one
+phase [0-64) * 1/64th DCK. It then searches for the middle of the low data
+symbol and adjusts timA to the found phase and thus the following measurements
+will be aligned to the low data symbol.
+The code assumes that the initial roundtrip time causes the measurement to be
+in the alternating pattern data phase.
+
+### Finding the preamble
+After adjusting the IO phase to the middle of one data symbol the preamble will
+be located. Unlike the data phase, which is an alternating pattern (010101...),
+the preamble consists of two high data cycles.
+
+The code decrements the IO delay/RTT and samples the DQS signal with timA
+untouched. As it has been positioned in the middle of the data symbol, it'll
+read as either "low" or "high".
+
+If it's "low" we are still in the data phase.
+If it's "high" we have found the preamble.
+
+The roundtrip time and IO delay will be adjusted until all lanes are aligned.
+The resulting IO delay is visible in the picture below.
+
+** roundtrip time: 49 DCKs, IO delay (at blue point): 6 DCKs **
+![alt text][timA_lane0-3_discover_420x]
+
+[timA_lane0-3_discover_420x]: timA_lane0-3_discover_420x.png "timA for lane0 - lane3, finding minimum roundtrip time"
+
+** Note: The sampled data has been shifted by timA. The preamble is now
+in phase. **
+
+## Fine adjustment
+
+As timA still points the middle of the data symbol an offset of 32 is added.
+It now points the falling edge of the preamble.
+The fine adjustment is to reduce errors introduced by jitter. The phase is
+adjusted from `timA - 25` to `timA + 25` and the DQS signal is sampled 100
+times. The fine adjustment finds the middle of each rising edge (it's actual
+the falling edge of the preamble) to get the final IO phase. You can see the
+result in the picture below.
+
+![alt text][timA_lane0-3_adjust_fine]
+
+[timA_lane0-3_adjust_fine]: timA_lane0-3_adjust_fine.png "timA for lane0 - lane3, fine adjustment"
+
+Lanes 0 - 2 will be adjusted by a phase of -10, while lane 3 is already correct.
--- a/Documentation/northbridge/intel/sandybridge/timA_lane0-3_adjust_fine.png
+++ b/Documentation/northbridge/intel/sandybridge/timA_lane0-3_adjust_fine.png
--- a/Documentation/northbridge/intel/sandybridge/timA_lane0-3_discover_420x.png
+++ b/Documentation/northbridge/intel/sandybridge/timA_lane0-3_discover_420x.png
--- a/Documentation/northbridge/intel/sandybridge/timA_lane0-3_rt53.png
+++ b/Documentation/northbridge/intel/sandybridge/timA_lane0-3_rt53.png
--- a/Documentation/northbridge/intel/sandybridge/timA_lane0-3_rt54.png
+++ b/Documentation/northbridge/intel/sandybridge/timA_lane0-3_rt54.png
--- a/Documentation/northbridge/intel/sandybridge/timA_lane0-3_rt55.png
+++ b/Documentation/northbridge/intel/sandybridge/timA_lane0-3_rt55.png
--- a/Documentation/Intel/SoC/quark.html
+++ b/Documentation/Intel/SoC/quark.html
@ -0,0 +1,220 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Quark&trade; SoC</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; Quark&trade; SoC</h1>
+<table>
+  <tr>
+    <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td>
+    <td>
+      The Quark&trade; SoC code was developed using the
+      <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a>
+      board:
+      <ul>
+        <li><a target="_blank" href="../development.html">Overall</a> development</li>
+        <li><a target="_blank" href="soc.html">SoC</a> support</li>
+        <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
+        <li><a target="_blank" href="../Board/board.html">Board</a> support</li>
+        <li><a target="_blank" href="#QuarkFsp">Quark&trade; FSP</a></li>
+        <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li>
+      </ul>
+    </td>
+  </tr>
+</table>
+
+
+
+<hr>
+<h2>Quark&trade; Documentation</h2>
+<ul>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>:
+    <ul>
+      <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a>
+        - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>:
+        <ul>
+          <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li>
+          <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li>
+          <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li>
+        </ul>
+      </li>
+    </ul>
+  </li>
+  <li><a target="_blank" href="../index.html#Documentation">More documentation</a></li>
+</ul>
+
+
+
+<hr>
+<h2><a name="CorebootPayloadPkg">Quark&trade; EDK2 CorebootPayloadPkg</a></h2>
+<p>
+Build Instructions:
+</p>
+<ol>
+  <li>Set up <a href="#BuildEnvironment">build environment</a></li>
+  <li>Linux (assumes GCC48):
+<pre><code>build  -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc  -a IA32  \
+    -t GCC48  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  \
+    -DDEBUG_PRINT_ERROR_LEVEL=0x80000042  -DSHELL_TYPE=BUILD_SHELL  \
+    -DMAX_LOGICAL_PROCESSORS=1
+ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd
+</code></pre>
+  </li>
+  <li>Windows (assumes Visual Studio 2015):
+<pre><code>build  -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc  -a IA32  -t VS2015x86  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042  -DSHELL_TYPE=BUILD_SHELL  -DMAX_LOGICAL_PROCESSORS=1
+dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd
+</code></pre>
+  </li>
+  <li>In the .config for coreboot, set the following Kconfig values:
+    <ul>
+      <li>CONFIG_PAYLOAD_ELF=y</li>
+      <li>CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"</li>
+    </ul>
+  </li>
+  <li>Build coreboot</li>
+  <li>Copy the image build/coreboot.rom into flash</li>
+</ol>
+
+
+
+<hr>
+<h2><a name="BuildEnvironment">Quark&trade; EDK2 Build Environment</a></h2>
+<p>
+  Use the following steps to setup a build environment:
+</p>
+<ol>
+  <li>Get the EDK2 sources:
+    <ol type="A">
+      <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li>
+      <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li>
+      <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li>
+    </ol>
+  </li>
+  <li>Set up a build window:
+    <ul>
+      <li>Linux:
+<pre><code>export WORKSPACE=$PWD
+export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi"
+cd edk2
+export WORKSPACE=$PWD
+. edksetup.sh
+</code></pre>
+      </li>
+      <li>Windows:
+<pre><code>set WORKSPACE=%CD%
+set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+cd edk2
+edksetup.bat
+</code></pre>
+      </li>
+    </ul>
+  </li>
+</ol>
+
+
+
+<hr>
+<h2><a name="QuarkFsp">Quark&trade; FSP</a></h2>
+<p>
+Getting the Quark FSP source:
+</p>
+<ol>
+  <li>Set up an EDK-II <a href="#BuildEnvironment">Build Environment</a></li>
+  <li>cd edk2</li>
+  <li>mkdir QuarkFspPkg</li>
+  <li>cd QuarkFspPkg</li>
+  <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li>
+</ol>
+
+<h3>Building QuarkFspPkg</h3>
+<p>
+There are two versions of FSP: FSP 1.1 and FSP 2.0.  There are also two
+different implementations of FSP, one using subroutines without SEC and
+PEI core and the original implementation which relies on SEC and PEI core.
+Finally there are two different build x86 types release (r32) and debug (d32).
+</p>
+<p>Note that the subroutine implementations are a <b>work in progress</b>.</p>
+<p>
+Build commands shown building debug FSP:
+</p>
+<ul>
+  <li>Linux:
+    <ul>
+      <li>QuarkFspPkg/BuildFsp1_1.sh  -d32</li>
+      <li>QuarkFspPkg/BuildFsp1_1Pei.sh  -d32</li>
+      <li>QuarkFspPkg/BuildFsp2_0.sh  -d32</li>
+      <li>QuarkFspPkg/BuildFsp2_0Pei.sh  -d32</li>
+    </ul>
+  <li>Windows:
+    <ul>
+      <li>QuarkFspPkg/BuildFsp1_1.bat  -d32</li>
+      <li>Windows: QuarkFspPkg/BuildFsp2_0.bat  -d32</li>
+    </ul>
+  </li>
+</ul>
+
+<h3>Copying FSP files into coreboot Source Tree</h3>
+<p>
+There are some helper scripts to copy the FSP output into the coreboot
+source tree.  The parameters to these scripts are:
+</p>
+<ol>
+  <li>EDK2 tree root</li>
+  <li>coreboot tree root</li>
+  <li>Build type: DEBUG or RELEASE</li>
+</ol>
+<p>
+Script files:
+</p>
+<ul>
+  <li>Linux:
+    <ul>
+      <li>QuarkFspPkg/coreboot_fsp1_1.sh</li>
+      <li>QuarkFspPkg/coreboot_fsp1_1Pei.sh</li>
+      <li>QuarkFspPkg/coreboot_fsp2_0.sh</li>
+      <li>QuarkFspPkg/coreboot_fsp2_0Pei.sh</li>
+    </ul>
+</ul>
+
+
+<hr>
+<h2>Quark&trade; EDK2 BIOS</h2>
+<p>
+Build Instructions:
+</p>
+<ol>
+  <li>Set up <a href="#BuildEnvironment">build environment</a></li>
+  <li>Build the image:
+    <ul>
+      <li>Linux:
+<pre><code>build -p QuarkPlatformPkg/Quark.dsc  -a IA32  -t GCC48  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+ls Build/Quark/DEBUG_GCC48/FV/Quark.fd
+</code></pre>
+      </li>
+      <li>Windows:
+<pre><code>build -p QuarkPlatformPkg/Quark.dsc  -a IA32  -t VS2012x86  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd
+</code></pre>
+  </li>
+    </ul>
+  </li>
+</ol>
+
+<p>
+Documentation:
+</p>
+<ul>
+  <li><a target="_blank" href="https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg">EDK II firmware for Intel&reg; Quark&trade; SoC X1000 based platforms</a></li>
+  <li>Intel&reg; Quark&trade; SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li>
+</ul>
+
+
+
+<hr>
+<p>Modified: 17 May 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/SoC/soc.html
+++ b/Documentation/Intel/SoC/soc.html
@ -0,0 +1,733 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>SoC</title>
+  </head>
+  <body>
+
+<h1>x86 System on a Chip (SoC) Development</h1>
+<p>
+  SoC development is best done in parallel with development for a specific
+  board.  The combined steps are listed
+  <a target="_blank" href="../development.html">here</a>.
+  The development steps for the SoC are listed below:
+</p>
+<ol>
+  <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
+  <li>SoC <a href="#RequiredFiles">Required Files</a></li>
+  <li><a href="#Descriptor">Start Booting</a></li>
+  <li><a href="#EarlyDebug">Early Debug</a></li>
+  <li><a href="#Bootblock">Bootblock</a></li>
+  <li><a href="#TempRamInit">TempRamInit</a></li>
+  <li><a href="#Romstage">Romstage</a>
+    <ol type="A">
+      <li>Enable <a href="#SerialOutput">Serial Output"</a></li>
+      <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
+      <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
+      <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li>
+    </ol>
+  </li>
+  <li><a href="#Ramstage">Ramstage</a>
+    <ol type="A">
+      <li><a href="#DeviceTree">Start Device Tree Processing</a></li>
+      <li>Set up the <a href="#MemoryMap">Memory Map"</a></li>
+    </ol>
+  </li>
+  <li><a href="#AcpiTables">ACPI Tables</a></li>
+  <li><a href="#LegacyHardware">Legacy Hardware</a></li>
+</ol>
+
+
+<hr>
+<h2><a name="RequiredFiles">Required Files</a></h2>
+<p>
+  Create the directory as src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;.
+</p>
+
+<p>
+  The following files are required to build a new SoC:
+</p>
+<ul>
+  <li>Include files
+    <ul>
+      <li>include/soc/pei_data.h</li>
+      <li>include/soc/pm.h</li>
+    </ul>
+  </li>
+  <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
+    chains for the various stages:
+    <ul>
+      <li>select ARCH_BOOTBLOCK_&lt;Tool Chain&gt;</li>
+      <li>select ARCH_RAMSTAGE_&lt;Tool Chain&gt;</li>
+      <li>select ARCH_ROMSTAGE_&lt;Tool Chain&gt;</li>
+      <li>select ARCH_VERSTAGE_&lt;Tool Chain&gt;</li>
+    </ul>
+  </li>
+  <li>Makefile.inc - Specify the include paths</li>
+  <li>memmap.c - Top of usable RAM</li>
+</ul>
+
+
+<hr>
+<h2><a name="Descriptor">Start Booting</a></h2>
+<p>
+  Some SoC parts require additional firmware components in the flash.
+  This section describes how to add those pieces.
+</p>
+
+<h3>Intel Firmware Descriptor</h3>
+<p>
+  The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
+  The following command overwrites the base of the flash image with the Intel
+  Firmware Descriptor:
+</p>
+<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
+
+
+<h3><a name="MEB">Management Engine Binary</a></h3>
+<p>
+  Some SoC parts contain and require that the Management Engine (ME) be running
+  before it is possible to bring the x86 processor out of reset.  A binary file
+  containing the management engine code must be added to the firmware using the
+  ifdtool.  The following commands add this binary blob:
+</p>
+<pre><code>util/ifdtool/ifdtool -i ME:me.bin  build/coreboot.rom
+mv build/coreboot.rom.new build/coreboot.rom
+</code></pre>
+
+
+<h3><a name="EarlyDebug">Early Debug</a></h3>
+<p>
+  Early debugging between the reset vector and the time the serial port is enabled
+  is most easily done by writing values to port 0x80.
+</p>
+
+
+<h3>Success</h3>
+<p>
+  When the reset vector is successfully invoked, port 0x80 will output the following value:
+</p>
+<ul>
+  <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+    - Bootblock successfully executed the
+    <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+    and entered the 16-bit code at
+    <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+  </li>
+</ul>
+
+
+<hr>
+<h2><a name="Bootblock">Bootblock</a></h2>
+<p>
+  Implement the bootblock using the following steps:
+</p>
+<ol>
+  <li>Create the directory as src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock</li>
+  <li>Add the timestamp.inc file which initializes the floating point registers and saves
+    the initial timestamp.
+  </li>
+  <li>Add the bootblock.c file which:
+    <ol type="A">
+      <li>Enables memory-mapped PCI config access</li>
+      <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
+      <li>Enable ROM caching</li>
+    </ol>
+  </li>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Kconfig file
+    <ol type="A">
+      <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
+      <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
+    </ol>
+  </li>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Makefile.inc file
+    <ol type="A">
+      <li>Add the bootblock subdirectory</li>
+    </ol>
+  </li>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/memmap.c file
+    <ol type="A">
+      <li>Add the fsp/memmap.h include file</li>
+      <li>Add the mmap_region_granularity routine</li>
+    </ol>
+  </li>
+  <li>Add the necessary .h files to define the necessary values and structures</li>
+  <li>When successful port 0x80 will output the following values:
+    <ol type="A">
+      <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+        - Bootblock successfully executed the
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+        and entered the 16-bit code at
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+      </li>
+      <li>0x10: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
+        - Bootblock executing in
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
+      </li>
+      <li>0x10 - Verstage/romstage reached 32-bit mode</li>
+    </ol>
+  </li>
+</ol>
+
+<p>
+  <b>Build Note:</b> The following files are included into the default bootblock image:
+</p>
+<ul>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
+    added by   <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
+    and includes the following files:
+    <ul>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
+      <li>The code in
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
+        includes src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock/timestamp.inc using the
+        CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
+      </li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
+      <li>The code in
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
+        invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
+        <ul>
+          <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
+          <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
+          <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
+            src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock/bootblock.c
+          </li>
+        </ul>
+      </li>
+    </ul>
+  </li>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
+    added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
+  </li>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
+    added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
+  </li>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
+    added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
+  </li>
+</ul>
+
+
+<hr>
+<h2><a name="TempRamInit">TempRamInit</a></h2>
+<p>
+  Enable the call to TempRamInit in two stages:
+</p>
+<ol>
+  <li>Finding the FSP binary in the read-only CBFS region</li>
+  <li>Call TempRamInit</li>
+</ol>
+
+
+<h3>Find FSP Binary</h3>
+<p>
+Use the following steps to locate the FSP binary:
+</p>
+<ol>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Kconfig file
+    <ol type="A">
+      <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
+      </li>
+      <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
+        specifically building
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/common/util.c">util.c</a>
+      </li>
+    </ol>
+  </li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+        - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+      </li>
+      <li>Alternating 0xba and 0x01 - The FSP image was not found</li>
+    </ol>
+  </li>
+  <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li>
+  <li>Set the following Kconfig values:
+    <ul>
+      <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li>
+      <li>CONFIG_FSP_IMAGE_ID_STRING</li>
+    </ul>
+  </li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+        - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+      </li>
+      <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li>
+    </ol>
+  </li>
+</ol>
+
+
+<h3>Calling TempRamInit</h3>
+<p>
+Use the following steps to debug the call to TempRamInit:
+</p>
+<ol>
+  <li>Add the CPU microcode update file
+    <ol type="A">
+      <li>Add the microcode file with the following command
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b &lt;base address&gt; -f cpu_microcode_blob.bin</code></pre>
+      </li>
+      <li>Set the Kconfig values
+        <ul>
+          <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li>
+          <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li>
+        </ul>
+      </li>
+    </ol>
+  </li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+        - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+      </li>
+      <li>0x2A - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a>
+        which is the start of the verstage code which may be part of romstage
+      </li>
+    </ol>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="Romstage">Romstage</a></h2>
+
+<h3><a name="SerialOutput">Serial Output</a></h3>
+<p>
+  The following steps add the serial output support for romstage:
+</p>
+<ol>
+  <li>Create the romstage subdirectory</li>
+  <li>Add romstage/romstage.c
+    <ol type="A">
+      <li>Program the necessary base addresses</li>
+      <li>Disable the TCO</li>
+    </ol>
+  </li>
+  <li>Add romstage/Makefile.inc
+    <ol type="A">
+      <li>Add romstage.c to romstage</li>
+    </ol>
+  </li>
+  <li>Add gpio configuration support if necessary</li>
+  <li>Add the necessary .h files to support the build</li>
+  <li>Update Makefile.inc
+    <ol type="A">
+      <li>Add the romstage subdirectory</li>
+      <li>Add the gpio configuration support file to romstage</li>
+    </ol>
+  </li>
+  <li>Set the necessary Kconfig values to enable serial output:
+    <ul>
+      <li>CONFIG_DRIVERS_UART_&lt;driver&gt;=y</li>
+      <li>CONFIG_CONSOLE_SERIAL=y</li>
+      <li>CONFIG_UART_FOR_CONSOLE=&lt;port&gt;</li>
+      <li>CONFIG_CONSOLE_SERIAL_115200=y</li>
+    </ul>
+  </li>
+</ol>
+
+
+<h3><a name="PreviousSleepState">Determine Previous Sleep State</a></h3>
+<p>
+  The following steps implement the code to get the previous sleep state:
+</p>
+<ol>
+  <li>Implement the fill_power_state routine which determines the previous sleep state</li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x32:
+        - Just after entering
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a>
+      </li>
+      <li>0x33 - Just after calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a>
+      </li>
+      <li>0x34:
+        - Just after entering
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
+      </li>
+    </ol>
+</ol>
+
+
+<h3><a name="MemoryInit">MemoryInit Support</a></h3>
+<p>
+  The following steps implement the code to support the FSP MemoryInit call:
+</p>
+<ol>
+  <li>Add the chip.h header file to define the UPD values which get passed
+    to MemoryInit.  Skip the values containing SPD addresses and DRAM
+    configuration data which is determined by the board.
+    <p>
+      <b>Build Note</b>: The src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/devicetree.cb
+      file specifies the default values for these parameters.  The build
+      process creates the static.c module which contains the config data
+      structure containing these values.
+    </p>
+  </li>
+  <li>Edit romstage/romstage.c
+    <ol type="A">
+      <li>Implement the romstage/romstage.c/soc_memory_init_params routine to
+        copy the values from the config structure into the UPD structure
+      </li>
+      <li>Implement the soc_display_memory_init_params routine to display
+        the updated UPD parameters by calling fsp_display_upd_value
+      </li>
+    </ol>
+  </li>
+</ol>
+
+
+<h3><a name="DisableShadowRom">Disable Shadow ROM</a></h3>
+<p>
+  A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff.
+  This shadow needs to be disabled to allow RAM to properly respond to
+  this address range.
+</p>
+<ol>
+  <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li>
+</ol>
+
+
+<hr>
+<h2><a name="Ramstage">Ramstage</a></h2>
+
+<h3><a name="DeviceTree">Start Device Tree Processing</a></h3>
+<p>
+  The src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/devicetree.cb file drives the
+  execution during ramstage.  This file is processed by the util/sconfig utility
+  to generate build/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/static.c.  The various
+  state routines in
+  src/lib/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a>
+  call dev_* routines which use the tables in static.c to locate operation tables
+  associated with the various chips and devices.  After location the operation
+  tables, the state routines call one or more functions depending upon the
+  state of the state machine.
+</p>
+
+<h4><a name="ChipOperations">Chip Operations</a></h4>
+<p>
+  Kick-starting the ramstage state machine requires creating the operation table
+  for the chip listed in devicetree.cb:
+</p>
+<ol>
+  <li>Edit src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/chip.c:
+    <ol type="A">
+      <li>
+        This chip's operation table has the name
+        soc_&lt;SoC Vendor&gt;_&lt;SoC Family&gt;_ops which is derived from the
+        chip path specified in the devicetree.cb file.
+      </li>
+      <li>Use the CHIP_NAME macro to specify the name for the chip</li>
+      <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li>
+    </ol>
+  </li>
+  <li>Edit src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/Makefile.inc and add chip.c to ramstage</li>
+</ol>
+
+<h4>Domain Operations</h4>
+<p>
+  coreboot uses the domain operation table to initiate operations on all of the
+  devices in the domain.  By default coreboot enables all PCI devices which it
+  finds.  Listing a device in devicetree.cb gives the board vendor control over
+  the device state.  Non-PCI devices may also be listed under PCI device such as
+  the LPC bus or SMbus devices.
+</p>
+<ol>
+  <li>Edit src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/chip.c:
+    <ol type="A">
+      <li>
+        The domain operation table is typically placed in
+        src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/chip.c.
+        The table typically looks like the following:
+<pre><code>static struct device_operations pci_domain_ops = {
+	.read_resources	= pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.scan_bus	= pci_domain_scan_bus,
+};
+</code></pre>
+      </li>
+      <li>
+        Create a .enable_dev entry in the chip operations table which points to a
+        routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN.
+<pre><code>	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	}
+</code></pre>
+      </li>
+      <li>
+        During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+        for the PCI devices on the bus.
+      </li>
+    </ol>
+  </li>
+  <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li>
+  <li>
+    Debug the result until the PCI vendor and device IDs are displayed
+    during the BS_DEV_ENUMERATE state.
+  </li>
+</ol>
+
+
+<h3><a name="DeviceDrivers">PCI Device Drivers</a></h3>
+<p>
+  PCI device drivers consist of a ".c" file which contains a "pci_driver" data
+  structure at the end of the file with the attribute tag "__pci_driver".  This
+  attribute tag places an entry into a link time table listing the various
+  coreboot device drivers.
+</p>
+<p>
+  Specify the following fields in the table:
+</p>
+<ol>
+  <li>.vendor - PCI vendor ID value of the device</li>
+  <li>.device - PCI device ID value of the device or<br>
+  .devices - Address of a zero terminated array of PCI device IDs
+  </li>
+  <li>.ops - Operations table for the device.  This is the address
+    of a "static struct device_operations" data structure specifying
+    the routines to execute during the different states and sub-states
+    of ramstage's processing.
+  </li>
+  <li>Turn on the device in mainboard/&lt;Vendor&gt;/&lt;Board&gt;/devicetree.cb</li>
+  <li>
+    Debug until the device is on and properly configured in coreboot and
+    usable by the payload
+  </li>
+</ol>
+
+<h4><a name="SubsystemIds">Subsystem IDs</a></h4>
+<p>
+  PCI subsystem IDs are assigned during the BS_DEV_ENABLE state.  The device
+  driver may use the common mechanism to assign subsystem IDs by adding
+  the ".ops_pci" to the pci_driver data structure.  This field points to
+  a "struct pci_operations" that specifies a routine to set the subsystem
+  IDs for the device.  The routine might look something like this:
+</p>
+<pre><code>static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		vendor = pci_read_config32(dev, PCI_VENDOR_ID);
+		device = vendor >> 16;
+	}
+	printk(BIOS_SPEW,
+		"PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n",
+		0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn),
+		vendor & 0xffff, device);
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+			((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+</code></pre>
+
+
+
+<h3>Set up the <a name="MemoryMap">Memory Map</a></h3>
+<p>
+  The memory map is built by the various PCI device drivers during the
+  BS_DEV_RESOURCES state of ramstage.  The northcluster driver will typically
+  specify the DRAM resources while the other drivers will typically specify
+  the IO resources.  These resources are hung off the device_t data structure by
+  src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
+</p>
+<p>
+  During the BS_WRITE_TABLES state, coreboot collects these resources and
+  places them into a data structure identified by LB_MEM_TABLE.
+</p>
+<p>
+  Edit the device driver file:
+</p>
+<ol>
+  <li>
+    Implement a read_resources routine which calls macros defined in
+    src/include/device/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a>
+    like:
+    <ul>
+      <li>ram_resource</li>
+      <li>reserved_ram_resource</li>
+      <li>bad_ram_resource</li>
+      <li>uma_resource</li>
+      <li>mmio_resource</li>
+    </ul>
+  </li>
+</ol>
+
+<p>
+  Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state.
+</p>
+
+
+
+<hr>
+<h2><a name="AcpiTables">ACPI Tables</a></h2>
+<p>
+  One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
+</p>
+
+<h3>FADT</h3>
+<p>
+  The EDK2 module
+  CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l450">CbParseLib.c</a>
+  requires that the FADT contains the values in the table below.
+  These values are placed into a HOB identified by
+  <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootModulePkg.dec#l36">gUefiAcpiBoardInfoGuid</a>
+  by routine
+  CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei/CbSupportPei.c#l364">CbPeiEntryPoint</a>.
+</p>
+<table border="1">
+  <tr bgcolor="#c0ffc0">
+    <td>coreboot Field</td>
+    <td>EDK2 Field</td>
+    <td>gUefiAcpiBoardInfoGuid</td>
+    <td>Use</li>
+    <td>
+      <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a>
+      Section
+    </td>
+  </tr>
+  <tr>
+    <td>gpe0_blk<br>gpe0_blk_len</td>
+    <td>Gpe0Blk<br>Gpe0BlkLen</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l477">PmGpeEnBase</a>
+    </td>
+    <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l129">Shutdown</a></td>
+    <td>4.8.4.1</td>
+  </tr>
+  <tr>
+    <td>pm1a_cnt_blk</td>
+    <td>Pm1aCntBlk</td>
+    <td>PmCtrlRegBase</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l139">Shutdown</a><br>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l40">Suspend</a>
+    </td>
+    <td>4.8.3.2.1</td>
+  </tr>
+  <tr>
+    <td>pm1a_evt_blk</td>
+    <td>Pm1aEvtBlk</td>
+    <td>PmEvtBase</td>
+    <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l134">Shutdown</a></td>
+    <td>4.8.3.1.1</td>
+  </tr>
+  <tr>
+    <td>pm_tmr_blk</td>
+    <td>PmTmrBlk</td>
+    <td>PmTimerRegBase</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c#l55">Timer</a>
+    </td>
+    <td>4.8.3.3</td>
+  </tr>
+  <tr>
+    <td>reset_reg.</td>
+    <td>ResetReg.Address</td>
+    <td>ResetRegAddress</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a>
+      and
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a>
+      resets
+    </td>
+    <td>4.3.3.6</td>
+  </tr>
+  <tr>
+    <td>reset_value</td>
+    <td>ResetValue</td>
+    <td>ResetValue</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a>
+      and
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a>
+      resets
+    </td>
+    <td>4.8.3.6</td>
+  </tr>
+</table>
+<p>
+  The EDK2 data structure is defined in
+  MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a>
+  The coreboot data structure is defined in
+  src/arch/x86/include/arch/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/acpi.h;hb=HEAD#l237">acpi.h</a>
+</p>
+
+<ol>
+  <li>
+    Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a>
+    in the board's Kconfig file
+  </li>
+  <li>Create a acpi.c module:
+    <ol type="A">
+      <li>Add the acpi_fill_in_fadt routine and initialize the values above</li>
+    </ol>
+  </li>
+</ol>
+
+
+
+<hr>
+<h2><a name="LegacyHardware">Legacy Hardware</a></h2>
+<p>
+  One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
+</p>
+
+<table border="1">
+  <tr bgcolor="c0ffc0">
+    <th>Peripheral</th>
+    <th>Use</th>
+    <th>8259 Interrupt Vector</th>
+    <th>IDT Base Offset</th>
+    <th>Interrupt Handler</th>
+  </tr>
+  <tr>
+    <td>
+      <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a>
+      Programmable Interval Timer
+    </td>
+    <td>
+      EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a>
+    </td>
+    <td>0</td>
+    <td>0x340</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a>
+    </td>
+  </tr>
+  <tr>
+    <td>
+      <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a>
+      Programmable Interrupt Controller
+    </td>
+    <td>
+      EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a>
+    </td>
+    <td>
+      Master interrupts: 0, 2 - 7<br>
+      Slave interrupts: 8 - 15<br>
+      Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15
+    </td>
+    <td>
+      Master: 0x340, 0x350 - 0x378<br>
+      Slave: 0x380 - 0x3b8<br>
+      Interrupt descriptors are 8 bytes each
+    </td>
+    <td>&nbsp;</td>
+  </tr>
+</table>
+
+<hr>
+<p>Modified: 4 March 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/development.html
+++ b/Documentation/Intel/development.html
@ -0,0 +1,377 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Development</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; x86 coreboot/FSP Development Process</h1>
+<p>
+  The x86 development process for coreboot is broken into the following components:
+</p>
+<ul>
+  <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li>
+  <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li>
+  <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li>
+</ul>
+<p>
+  The development process has two main phases:
+</p>
+<ol>
+  <li>Minimal coreboot; This phase is single threaded</li>
+  <li>Adding coreboot features</li>
+</ol>
+
+<h2>Minimal coreboot</h2>
+<p>
+  The combined steps below describe how to bring up a minimal coreboot for a
+  system-on-a-chip (SoC) and a development board:
+</p>
+<table>
+  <tr bgcolor="#ffffc0">
+    <td>The initial coreboot steps are single threaded!
+      The initial minimal FSP development is also single threaded.
+      Progress can speed up by adding more developers after the minimal coreboot/FSP
+      implementation reaches the payload.
+    </td>
+  </tr>
+</table>
+<ol>
+  <li>Get the necessary tools:
+    <ul>
+      <li>Linux: Use your package manager to install m4 bison flex and the libcurses development
+        package.
+        <ul>
+          <li>Ubuntu or other Linux distribution that use apt, run:
+<pre><code>sudo apt-get install m4 bison flex libncurses5-dev
+</code></pre>
+          </li>
+        </ul>
+      </li>
+    </ul>
+  </li>
+  <li>Build the cross tools for i386:
+    <ul>
+      <li>Linux:
+<pre><code>make crossgcc-i386</code></pre>
+        To use multiple processors for the toolchain build (which takes a long time), use:
+<pre><code>make crossgcc-i386 CPUS=N</code></pre>
+        where N is the number of cores to use for the build.
+      </li>
+    </ul>
+  </li>
+  <li>Get something to build:
+    <ol type="A">
+      <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
+      <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li>
+      <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li>
+    </ol>
+  </li>
+  <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
+  <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
+  <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
+  <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
+  <li>Enable the serial port
+    <ol type="A">
+      <li>Power on, enable and configure GPIOs for the
+        <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
+      </li>
+      <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
+        support to romstage
+      </li>
+    </ol>
+  </li>
+  <li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
+  <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li>
+  <li>Enable DRAM:
+    <ol type="A">
+      <li>Implement the SoC
+        <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a>
+        Support
+      </li>
+      <li>Implement the board support to read the
+        <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a>
+      </li>
+    </ol>
+  </li>
+  <li>Disable the
+    <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
+  </li>
+  <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li>
+  <li>
+    Implement the .init routine for the
+    <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
+    structure which calls FSP SiliconInit
+  </li>
+  <li>
+    Start ramstage's
+    <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
+    to display the PCI vendor and device IDs
+  </li>
+  <li>
+    Disable the
+    <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
+  </li>
+  <li>
+    Implement the
+    <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
+  </li>
+  <li>coreboot should now attempt to load the payload</li>
+</ol>
+
+
+
+<h2>Add coreboot Features</h2>
+<p>
+  Most of the coreboot development gets done in this phase.  Implementation tasks in this
+  phase are easily done in parallel.
+</p>
+<ul>
+  <li>Payload and OS Features:
+    <ul>
+      <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
+      <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
+    </ul>
+  </li>
+</ul>
+
+
+
+<hr>
+<table border="1">
+  <tr bgcolor="#c0ffc0">
+    <th colspan=3><h1>Features</h1></th>
+  </tr>
+  <tr bgcolor="#c0ffc0">
+    <th>SoC</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>8254 Programmable Interval Timer</td>
+    <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
+    <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
+  </tr>
+  <tr>
+    <td>8259 Programmable Interrupt Controller</td>
+    <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
+    <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
+  </tr>
+  <tr>
+    <td>Cache-as-RAM</td>
+    <td>
+      <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
+      FSP binary:
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br>
+      Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
+      called from
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br>
+      Disable: FSP 1.1 TempRamExit called from
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
+    </td>
+    <td>FindFSP: POST code 0x90
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+      is displayed<br>
+      Enable: POST code
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
+      is displayed<br>
+      Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
+    </td>
+  </tr>
+  <tr>
+    <td>Memory Map</td>
+    <td>
+      Implement a device driver for the
+      <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
+    </td>
+    <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
+  </tr>
+  <tr>
+    <td>MTRRs</td>
+    <td>
+      Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br>
+      Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a>
+    </td>
+    <td>Set: Post code 0x91
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>)
+      is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
+      Load: Post code 0x3C is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br>
+      and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td>
+  </tr>
+  <tr>
+    <td>PCI Device Support</td>
+    <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
+    <td>The device is detected by coreboot and usable by the payload</td>
+  </tr>
+  <tr>
+    <td>Ramstage state machine</td>
+    <td>
+      Implement the chip and domain operations to start the
+      <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
+      processing
+    </td>
+    <td>
+      During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+      for the PCI devices on the bus.
+    </td>
+  </tr>
+  <tr>
+    <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
+    <td>
+      Disable: src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
+    </td>
+    <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
+  </tr>
+
+
+  <tr bgcolor="#c0ffc0">
+    <th>Board</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>Device Tree</td>
+    <td>
+      <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
+      the device tree processing<br>
+      <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
+      Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
+    <td>
+      List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
+      Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
+      Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
+    </td>
+  </tr>
+  <tr>
+    <td>DRAM</td>
+    <td>
+      Load SPD data: src/soc/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
+      UPD Setup:
+      <ul>
+        <li>src/soc&lt;Vendor&gt;//&lt;Chip Family&gt;/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li>
+        <li>src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li>
+      </ul>
+      FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a>
+    </td>
+    <td>Select the following Kconfig values
+      <ul>
+        <li>DISPLAY_HOBS</li>
+        <li>DISPLAY_UPD_DATA</li>
+      </ul>
+      Testing successful if:
+      <ul>
+        <li>MemoryInit UPD values are correct</li>
+        <li>MemoryInit returns 0 (success) and</li>
+        <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
+          is not displayed
+        </li>
+      </ul>
+    </td>
+  </tr>
+  <tr>
+    <td>Serial Port</td>
+    <td>
+      SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
+      Enable: src/soc/mainboard/&lt;Board&gt;/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
+    </td>
+    <td>Debug serial output works</td>
+  </tr>
+
+
+  <tr bgcolor="#c0ffc0">
+    <th>Payload</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>ACPI Tables</td>
+    <td>
+      SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
+    </td>
+    <td>Verified by payload or OS</td>
+  </tr>
+
+
+  <tr bgcolor="#c0ffc0">
+    <th>FSP</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>TempRamInit</td>
+    <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
+    <td>FSP binary found: POST code 0x90
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+      is displayed<br>
+      TempRamInit successful: POST code
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
+      is displayed<br>
+    </td>
+  </tr>
+  <tr>
+    <td>MemoryInit</td>
+    <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br>
+      <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br>
+    </td>
+    <td>Select the following Kconfig values
+      <ul>
+        <li>DISPLAY_HOBS</li>
+        <li>DISPLAY_UPD_DATA</li>
+      </ul>
+      Testing successful if:
+      <ul>
+        <li>MemoryInit UPD values are correct</li>
+        <li>MemoryInit returns 0 (success) and</li>
+        <li>The the message "ERROR - coreboot's requirements not met by FSP binary!"
+          is not displayed
+        </li>
+      </ul>
+    </td>
+  </tr>
+  <tr>
+    <td>TempRamExit</td>
+    <td>src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
+    <td>Post code 0x91
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
+      is displayed before calling TempRamExit by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
+      CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
+      Post code 0x39 is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
+    </td>
+  </tr>
+  <tr>
+    <td>SiliconInit</td>
+    <td>
+      Implement the .init routine for the
+      <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
+    </td>
+    <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
+  </tr>
+  <tr>
+    <td>FspNotify</td>
+    <td>
+      The code which calls FspNotify is located in
+      src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
+      The fsp_notify_boot_state_callback routine is called three times as specified
+      by the BOOT_STATE_INIT_ENTRY macros below the routine.
+    </td>
+    <td>
+      The FspNotify routines are called during:
+      <ul>
+        <li>BS_DEV_RESOURCES - on exit</li>
+        <li>BS_PAYLOAD_LOAD - on exit</li>
+        <li>BS_OS_RESUME - on entry (S3 resume)</li>
+      </ul>
+    </td>
+  </tr>
+</table>
+
+
+
+<hr>
+<p>Modified: 4 March 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/fsp1_1.html
+++ b/Documentation/Intel/fsp1_1.html
@ -0,0 +1,79 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>FSP 1.1</title>
+  </head>
+  <body>
+
+<h1>FSP 1.1</h1>
+
+<h2>x86 FSP 1.1 Integration</h2>
+<p>
+  Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC)
+  and board support.  The combined steps are listed
+  <a target="_blank" href="development.html">here</a>.
+  The development steps for FSP are listed below:
+</p>
+<ol>
+  <li><a href="#RequiredFiles">Required Files</a></li>
+  <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
+  <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
+</ol>
+
+<p>
+  FSP Documentation:
+</p>
+<ul>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
+</ul>
+
+<hr>
+<h2><a name="RequiredFiles">Required Files</a></h2>
+<h3><a name="corebootRequiredFiles">coreboot Required Files</a></h3>
+<ol>
+  <li>Create the following directories if they do not already exist:
+    <ul>
+      <li>src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;</li>
+      <li>3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;</li>
+    </ul>
+  </li>
+  <li>
+    The following files may need to be copied from the FSP build or release into the
+    directories above if they are not present or are out of date:
+    <ul>
+      <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;/FspUpdVpd.h</li>
+      <li>FSP.bin: 3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;/fsp.bin</li>
+    </ul>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h2>
+<p>
+  Add the FSP binary to the coreboot flash image using the following command:
+</p>
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b &lt;base address&gt; -f fsp.bin</code></pre>
+<p>
+  This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
+  FSP code for TempRamInit may be executed in place.
+</p>
+
+
+<hr>
+<h2><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h2>
+<p>
+  Set the following Kconfig values:
+</p>
+<ul>
+  <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
+  <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
+  <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
+  <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
+</ul>
+
+
+<hr>
+<p>Modified: 17 May 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/index.html
+++ b/Documentation/Intel/index.html
@ -0,0 +1,129 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Intel&reg; x86</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; x86</h1>
+
+<h2>Intel&reg; x86 Boards</h2>
+<ul>
+  <li><a target="_blank" href="Board/galileo.html">Galileo</a></li>
+  <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li>
+</ul>
+
+<h2>Intel&reg; x86 SoCs</h2>
+<ul>
+  <li><a target="_blank" href="SoC/quark.html">Quark&trade;</a></li>
+</ul>
+
+
+
+<hr>
+<h2>x86 coreboot Development</h2>
+<ul>
+  <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li>
+  <li><a target="_blank" href="development.html">Overall</a> development</li>
+  <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration
+  </li>
+  <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li>
+  <li><a target="_blank" href="Board/board.html">Board</a> support</li>
+  <li><a target="_blank" href="vboot.html">Verified Boot (vboot)</a> support</li>
+</ul>
+
+
+
+<hr>
+<h2>Payload Development</h2>
+<ul>
+  <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>
+    <ul>
+      <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li>
+      <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li>
+      <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li>
+      <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li>
+    </ul>
+  </li>
+</ul>
+
+
+
+<hr>
+<h2><a name="Documentation">Documentation</a></h2>
+<ul>
+  <li>Intel&reg; 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li>
+  <li><a target="_blank" href="http://www.uefi.org/specifications">UEFI Specifications</a></li>
+</ul>
+
+<h3><a name="Edk2Documentation">EDK-II Documentation</a></h3>
+<ul>
+  <li>Build <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_1_26.pdf">V1.26</a></li>
+  <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf">V2.1</a></li>
+  <li>DEC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1_25.pdf">V1.25</a></li>
+  <li>DSC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1_26.pdf">V1.26</a></li>
+  <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer's-Guide">Driver Writer's Guide</a></li>
+  <li>Expression Syntax <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/ExpressionSyntax_1.1.pdf">V1.1</a></li>
+  <li>FDF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1_26.pdf">V1.26</a></li>
+  <li>INF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1_25.pdf">V1.25</a></li>
+  <li>PCD <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/PCD_Infrastructure.pdf">PCD</a>V0.55</li>
+  <li>UNI <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/UNI_File_Spec_v1_2_Errata_A.pdf">V1.2 Errata A</a></li>
+  <li>VRF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf">V1.9</a></li>
+</ul>
+
+<h3><a name="FspDocumentation">FSP Documentation</a></h3>
+<ul>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf">V2.0</a></li>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf">V1.0</a></li>
+</ul>
+
+<h3><a name="FeatureDocumentation">Feature Documentation</a></h3>
+<table border="1">
+  <tr bgcolor="#c0ffc0"><th>Feature/Specification</th><th>Linux View/Test</th><th>EDK-II View/Test</th></tr>
+  <tr>
+    <td><a target="_blank" href="https://en.wikipedia.org/wiki/E820">e820</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/dmesg.1.html">dmesg</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.uefi.org/specifications">ACPI</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/precise/man1/acpidump.1.html">acpidump</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="https://en.wikipedia.org/wiki/Extended_Display_Identification_Data">EDID</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/get-edid.1.html">get-edid | parse-edid</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I2C</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/get-edid.1.html">i2cdetect</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.intel.com/design/archives/processors/pro/docs/242016.htm">Multiprocessor</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/lscpu.1.html">lscpu</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="https://pcisig.com/specifications">PCI</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man8/lspci.8.html">lspci</a></td>
+    <td><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI_Shell_Spec_2_0.pdf">pci</a></td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf">SMBIOS</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man8/dmidecode.8.html">dmidecode</a></td>
+    <td><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI_Shell_Spec_2_0.pdf">smbiosview</a></td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.usb.org/developers/docs/">USB</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/xenial/man8/lsusb.8.html">lsusb</a></td>
+    <td>&nbsp;</td>
+  </tr>
+</table>
+
+<hr>
+<p>Modified: 18 June 2016</p>
+  </body>
+</html>
--- a/Documentation/Intel/vboot.html
+++ b/Documentation/Intel/vboot.html
@ -0,0 +1,402 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>vboot - Verified Boot Support</title>
+  </head>
+  <body>
+
+<h1>vboot - Verified Boot Support</h1>
+
+<p>
+Google's verified boot support consists of:
+</p>
+<ul>
+  <li>A root of trust</li>
+  <li>Special firmware layout</li>
+  <li>Firmware verification</li>
+  <li>Firmware measurements</li>
+  <li>A firmware update mechanism</li>
+  <li>Specific build flags</li>
+  <li>Signing the coreboot image</li>
+</ul>
+
+Google's vboot verifies the firmware and places measurements
+within the TPM.
+
+<hr>
+<h2>Root of Trust</h2>
+<p>
+When using vboot, the root-of-trust is basically the read-only portion of the
+SPI flash.  The following items factor into the trust equation:
+</p>
+<ul>
+  <li>The GCC compiler must reliably translate the code into machine code
+      without inserting any additional code (virus, backdoor, etc.)
+  </li>
+  <li>The CPU must reliably execute the reset sequence and instructions as
+      documented by the CPU manufacturer.
+  </li>
+  <li>The SPI flash must provide only the code programmed into it to the CPU
+      without providing any alternative reset vector or code sequence.
+  </li>
+  <li>The SPI flash must honor the write-protect input and protect the
+      specified portion of the SPI flash from all erase and write accesses.
+  </li>
+</ul>
+
+<p>
+The firmware is typically protected using the write-protect pin on the SPI
+flash part and setting some of the write-protect bits in the status register
+during manufacturing.  The protected area is platform specific and for x86
+platforms is typically 1/4th of the SPI flash
+part size.  Because this portion of the SPI flash is hardware write protected,
+it is not possible to update this portion of the SPI flash in the field,
+without altering the system to eliminate the ground connection to the SPI flash
+write-protect pin.  Without hardware modifications, this portion of the SPI
+flash maintains the manufactured state during the system's lifetime.
+</p>
+
+<hr>
+<h2>Firmware Layout</h2>
+<p>
+Several sections are added to the firmware layout to support vboot:
+</p>
+<ul>
+  <li>Read-only section</li>
+  <li>Google Binary Blob (GBB) area</li>
+  <li>Read/write section A</li>
+  <li>Read/write section B</li>
+</ul>
+<p>
+The following sections describe the various portions of the flash layout.
+</p>
+
+<h3>Read-Only Section</h3>
+<p>
+The read-only section contains a coreboot file system (CBFS) that contains all
+of the boot firmware necessary to perform recovery for the system. This
+firmware is typically protected using the write-protect pin on the SPI flash
+part and setting some of the write-protect bits in the status register during
+manufacturing.  The protected area is typically 1/4th of the SPI flash part
+size and must cover the entire read-only section which consists of:
+</p>
+<ul>
+  <li>Vital Product Data (VPD) area</li>
+  <li>Firmware ID area</li>
+  <li>Google Binary Blob (GBB) area</li>
+  <li>coreboot file system containing read-only recovery firmware</li>
+</ul>
+
+<h3>Google Binary Blob (GBB) Area</h3>
+<p>
+The GBB area is part of the read-only section.  This area contains a 4096 or
+8192 bit public root RSA key that is used to verify the VBLOCK area to obtain
+the firmware signing key.
+</p>
+
+<h3>Recovery Firmware</h3>
+<p>
+The recovery firmware is contained within a coreboot file system and consists
+of:
+</p>
+<ul>
+  <li>reset vector</li>
+  <li>bootblock</li>
+  <li>verstage</li>
+  <li>romstage</li>
+  <li>postcar</li>
+  <li>ramstage</li>
+  <li>payload</li>
+  <li>flash map file</li>
+  <li>config file</li>
+  <li>processor specific files:
+    <ul>
+      <li>Microcode</li>
+      <li>fspm.bin</li>
+      <li>fsps.bin</li>
+    </ul>
+  </li>
+</ul>
+
+<p>
+The recovery firmware is written during manufacturing and typically contains
+code to write the storage device (eMMC device or hard disk).  The recovery
+image is usually contained on a socketed device such as a USB flash drive or
+an SD card.  Depending upon the payload firmware doing the recovery, it may
+be possible for the user to interact with the system to specify the recovery
+image path.  Part of the recovery is also to write the A and B areas of the
+SPI flash device to boot the system.
+</p>
+
+
+<h3>Read/Write Section</h3>
+
+<p>
+The read/write sections contain an area which contains the firmware signing
+key and signature and an area containing a coreboot file system with a subset
+of the firmware.  The firmware files in FW_MAIN_A and FW_MAIN_B are:
+</p>
+<ul>
+  <li>romstage</li>
+  <li>postcar</li>
+  <li>ramstage</li>
+  <li>payload</li>
+  <li>config file</li>
+  <li>processor specific files:
+    <ul>
+      <li>Microcode</li>
+      <li>fspm.bin</li>
+      <li>fsps.bin</li>
+    </ul>
+  </li>
+</ul>
+
+<p>
+The firmware subset enables most issues to be fixed in the field with firmware
+updates.  The firmware files handle memory and most of silicon initialization.
+These files also produce the tables which get passed to the operating system.
+</p>
+
+<hr>
+<h2>Firmware Updates</h2>
+<p>
+The read/write sections exist in one of three states:
+</p>
+<ul>
+  <li>Invalid</li>
+  <li>Ready to boot</li>
+  <li>Successfully booted</li>
+</ul>
+
+<table border="1">
+<tr bgcolor="#ffc0c0">
+<td>
+Where is this state information written?
+<br/>CMOS?
+<br/>RW_NVRAM?
+<br/>RW_FWID_*
+</td>
+</tr>
+</table>
+
+<p>
+Firmware updates are handled by the operating system by writing any read/write
+section that is not in the "successfully booted" state.  Upon the next reboot,
+vboot determines the section to boot.  If it finds one in the "ready to boot"
+state then it attempts to boot using that section.  If the boot fails then
+vboot marks the section as invalid and attempts to fall back to a read/write
+section in the "successfully booted" state.  If vboot is not able to find a
+section in the "successfully booted" state then vboot enters recovery mode.
+</p>
+
+<p>
+Only the operating system is able to transition a section from the "ready to
+boot" state to the "successfully booted" state.  The transition is typically
+done after the operating system has been running for a while indicating
+that successful boot was possible and the operating system is stable.
+</p>
+
+<p>
+Note that as long as the SPI write protection is in place then the system is
+always recoverable.  If the flash update fails then the system will continue
+to boot using the previous read/write area.  The same is true if coreboot
+passes control to the payload or the operating system and then the boot fails.
+In the worst case, the SPI flash gets totally corrupted in which case vboot
+fails the signature checks and enters recovery mode.  There are no times where
+the SPI flash is exposed and the reset vector or part of the recovery firmware
+gets corrupted.
+</p>
+
+<hr>
+<h2>Build Flags</h2>
+<p>
+The following Kconfig values need to be selected to enable vboot:
+</p>
+<ul>
+  <li>COLLECT_TIMESTAMPS</li>
+  <li>VBOOT</li>
+</ul>
+
+<p>
+The starting stage needs to be specified by selecting either
+VBOOT_STARTS_IN_BOOTBLOCK or VBOOT_STARTS_IN_ROMSTAGE.
+</p>
+
+<p>
+If vboot starts in bootblock then vboot may be built as a separate stage by
+selecting VBOOT_SEPARATE_VERSTAGE.  Additionally, if static RAM is too small
+to fit both verstage and romstage then selecting VBOOT_RETURN_FROM_VERSTAGE
+enables bootblock to reuse the RAM occupied by verstage for romstage.
+</p>
+
+<p>
+Non-volatile flash is needed for vboot operation.  This flash area may be in
+CMOS, the EC, or in a read/write area of the SPI flash device.  Select one of
+the following:
+</p>
+<ul>
+  <li>VBOOT_VBNV_CMOS</li>
+  <li>VBOOT_VBNV_EC</li>
+  <li>VBOOT_VBNV_FLASH</li>
+</ul>
+<p>
+More non-volatile storage features may be found in src/vboot/Kconfig.
+</p>
+
+<p>
+A TPM is also required for vboot operation.  TPMs are available in
+drivers/i2c/tpm and drivers/pc80/tpm.
+</p>
+
+<p>
+In addition to adding the coreboot files into the read-only region, enabling
+vboot causes the build script to add the read/write files into coreboot file
+systems in FW_MAIN_A and FW_MAIN_B.
+</p>
+
+<hr>
+<h2>Signing the coreboot Image</h2>
+<p>
+The following command script is an example of how to sign the coreboot image file.
+This script is used on the Intel Galileo board and creates the GBB area and
+inserts it into the coreboot image.  It also updates the VBLOCK areas with the
+firmware signing key and the signature for the FW_MAIN firmware.  More details
+are available in 3rdparty/vboot/README.
+</p>
+
+<pre><code>#!/bin/sh
+#
+#  The necessary tools were built and installed using the following commands:
+#
+#        pushd 3rdparty/vboot
+#        make
+#        sudo make install
+#        popd
+#
+#  The keys were made using the following command
+#
+#        3rdparty/vboot/scripts/keygeneration/create_new_keys.sh  \
+#                --4k --4k-root --output $PWD/keys
+#
+#
+#  The "magic" numbers below are derived from the GBB section in
+#  src/mainboard/intel/galileo/vboot.fmd.
+#
+#  GBB Header Size:     0x80
+#  GBB Offset:      0x611000, 4KiB block number: 1553 (0x611)
+#  GBB Length:       0x7f000, 4KiB blocks:        127  (0x7f)
+#  COREBOOT Offset: 0x690000, 4KiB block number: 1680 (0x690)
+#  COREBOOT Length: 0x170000, 4KiB blocks:        368 (0x170)
+#
+#  0x7f000 (GBB Length) = 0x80 + 0x100 + 0x1000 + 0x7ce80 + 0x1000
+#
+#  Create the GBB area blob
+#  Parameters: hwid_size,rootkey_size,bmpfv_size,recoverykey_size
+#
+gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
+
+#
+#  Copy from the start of the flash to the GBB region into the signed flash
+#  image.
+#
+#  1553 * 4096 = 0x611 * 0x1000 = 0x611000, size of area before GBB
+#
+dd  conv=fdatasync  ibs=4096  obs=4096  count=1553  \
+    if=build/coreboot.rom  of=build/coreboot.signed.rom
+
+#
+#  Append the empty GBB area to the coreboot.rom image.
+#
+#  1553 * 4096 = 0x611 * 0x1000 = 0x611000, offset to GBB
+#
+dd  conv=fdatasync  obs=4096  obs=4096  seek=1553  if=gbb.blob  \
+    of=build/coreboot.signed.rom
+
+#
+#  Append the rest of the read-only region into the signed flash image.
+#
+#  1680 * 4096 = 0x690 * 0x1000 = 0x690000, offset to COREBOOT area
+#   368 * 4096 = 0x170 * 0x1000 = 0x170000, length of COREBOOT area
+#
+dd  conv=fdatasync  ibs=4096  obs=4096  skip=1680  seek=1680  count=368  \
+    if=build/coreboot.rom  of=build/coreboot.signed.rom
+
+#
+#  Insert the HWID and public root and recovery RSA keys into the GBB area.
+#
+gbb_utility                          \
+   --set --hwid='Galileo'            \
+   -r $PWD/keys/recovery_key.vbpubk  \
+   -k $PWD/keys/root_key.vbpubk      \
+   build/coreboot.signed.rom
+
+#
+#  Sign the read/write firmware areas with the private signing key and update
+#  the VBLOCK_A and VBLOCK_B regions.
+#
+3rdparty/vboot/scripts/image_signing/sign_firmware.sh  \
+   build/coreboot.signed.rom                           \
+   $PWD/keys                                           \
+   build/coreboot.signed.rom
+</code></pre>
+
+<hr>
+<h2>Boot Flow</h2>
+<p>
+The reset vector exist in the read-only area and points to the bootblock entry
+point.  The only copy of the bootblock exists in the read-only area of the SPI
+flash.  Verstage may be part of the bootblock or a separate stage.  If separate
+then the bootblock loads verstage from the read-only area and transfers control
+to it.
+</p>
+
+<p>
+Upon first boot, verstage attempts to verify the read/write section A.  It gets
+the public root key from the GBB area and uses that to verify the VBLOCK area
+in read-write section A.  If the VBLOCK area is valid then it extracts the
+firmware signing key (1024-8192 bits) and uses that to verify the FW_MAIN_A
+area of read/write section A.  If the verification is successful then verstage
+instructs coreboot to use the coreboot file system in read/write section A for
+the contents of the remaining boot firmware (romstage, postcar, ramstage and
+the payload).
+</p>
+
+<p>
+If verification fails for the read/write area and the other read/write area is
+not valid vboot falls back to the read-only area to boot into system recovery.
+</p>
+
+<hr>
+<h2>Chromebook Special Features</h2>
+<p>
+Google's Chromebooks have some special features:
+</p>
+<ul>
+  <li>Developer mode</li>
+  <li>Write-protect screw</li>
+</ul>
+
+<h3>Developer Mode</h3>
+<p>
+Developer mode allows the user to use coreboot to boot another operating system.
+This may be a another (beta) version of Chrome OS, or another flavor of
+GNU/Linux.  Use of developer mode does not void the system warranty.  Upon
+entry into developer mode, all locally saved data on the system is lost.
+This prevents someone from entering developer mode to subvert the system
+security to access files on the local system or cloud.
+</p>
+
+<h3>Write Protect Screw</h3>
+<p>
+Chromebooks have a write-protect screw which provides the ground to the
+write-protect pin of the SPI flash.  Google specifically did this to allow
+the manufacturing line and advanced developers to re-write the entire SPI flash
+part.  Once the screw is removed, any firmware may be placed on the device.
+However, accessing this screw requires opening the case and voids the system
+warranty!
+</p>
+
+<hr>
+<p>Modified: 2 May 2017</p>
+  </body>
+</html>
--- a/Documentation/Kconfig.tex
+++ b/Documentation/Kconfig.tex
@ -0,0 +1,480 @@
+\documentclass[10pt,letterpaper]{article}
+\usepackage[latin1]{inputenc}
+\usepackage{amsmath}
+\usepackage{amsfonts}
+\usepackage{amssymb}
+\author{Ron Minnich}
+\title{Kconfig usage in coreboot v2}
+\begin{document}
+\section{Introduction}
+This document describes how to use Kconfig in v2. We describe our usage of Kconfig files, Makefile.inc files, when and where to use them, how to use them, and, interestingly, when and where not to use them.
+\section{Kconfig variations}
+Most Kconfig files set variables, which can be set as part of the Kconfig dialog. Not all Kconfig variables are set by the user, however; some are too dangerous. These are merely enabled by the mainboard.
+
+For variables set by the user, see src/console/Kconfig.
+
+For variables not set by the user, see src/mainboard/amd/serengeti\_cheetah/Kconfig. Users should never set such variables as the cache as RAM base. These are highly mainboard dependent.
+
+Kconfig files use the source command to include subdirectories. In most cases, save for limited cases described below, subdirectories have Kconfig files. They are always sourced unconditionally.
+
+\section{Makefile and Makefile.inc}
+There is only one Makefile, at the top level. All other makefiles are included as Makefile.inc. All the next-level Makefile.inc files are selected in the top level Makefile. Directories that are platform-independent are in BUILD-y; platform-dependent (e.g. Makefile.inc's that depend on architecture) are included in PLATFORM-y.
+
+Make is not recursive. There is only one make process.
+\subsection{subdirs usage}
+Further includes of Makefile.inc, if needed, are done via subdirs-y commands. As in Linux, the subdirs can be conditional or unconditional. Conditional includes are done via subdirs-\$(CONFIG\_VARIABLE) usage; unconditional are done via subdirs-y.
+
+We define the common rules for which variation to use below.
+\subsection{object file specification}
+There are several different types of objects specified in the tree. They are:
+\begin{description}
+\item[obj]objects for the RAM part of the code
+\item[driver]drivers for the RAM part. Drivers are not represented in the device tree but do have a driver struct attached in the driver section.
+\item[initobj]seperately-compiled code for the ROM section of coreboot
+\end{description}
+These items are specified via the -y syntax as well. Conditional object inclusion is done via the -\$(CONFIG\_VARIABLE) syntax.
+
+\section{Example: AMD serengeti cheetah}
+\subsection{mainboard/Kconfig}
+Defines Vendor variables. Currently defined variables are:
+Sources all Kconfig files in the vendor directories.
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/Makefile.inc}
+There is none at this time.
+\subsection{mainboard/$<$vendor$>$/Kconfig}
+We use the amd as a model. The only action currently taken is to source all Kconfig's in the
+subdirectories.
+\subsection{mainboard/$<$vendor$>$/Makefile.inc}
+We use amd as a model. There is currently no Makefile.inc at this level.
+\subsection{mainboard/$<$vendor$>$/$<$board$>$/Kconfig}
+The mainboard Kconfig and Makefile.inc are designed to be the heart of the build. The defines
+and rules in here determine everything about how a mainboard target is built.
+We will use serengeti\_cheetah as a model. It defines these variables.
+\input{ mainboardkconfig.tex}
+\subsection{mainboard/$<$vendor$>$/$<$board$>$/Makefile.inc}
+This is a fairly complex Makefile.inc. Because this is such a critical component, we are going to excerpt and take it piece by piece.
+Note that this is the mainboard as of August, 2009, and it may change over time.
+\subsubsection{objects}
+We define objects in the first part. The mainbard itself is a driver and included unconditionally. Other objects are conditional:
+\begin{verbatim}
+driver-y +=  mainboard.o
+
+#needed by irq_tables and mptable and acpi_tables
+obj-y += get_bus_conf.o
+obj-$(CONFIG_HAVE_MP_TABLE) += mptable.o
+obj-$(CONFIG_HAVE_PIRQ_TABLE) += irq_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  dsdt.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  acpi_tables.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  fadt.o
+
+#./ssdt.o is in northbridge/amd/amdk8/Config.lb
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt2.o
+obj-$(CONFIG_ACPI_SSDTX_NUM) +=  ssdt3.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  ssdt4.o
+driver-y += ../../../drivers/i2c/i2cmux/i2cmux.o
+
+# This is part of the conversion to init-obj and away from included code.
+
+initobj-y += crt0.o
+\end{verbatim}
+\subsubsection{romcc legacy support}
+We hope to move away from romcc soon, but for now, if one is using romcc, the Makefile.inc must define
+crt0 include files (assembly code for startup, usually); and several ldscripts. These are taken directly from the
+old Config.lb. Note that these use the -y syntax and can use the ability to be included conditionally.
+\begin{verbatim}
+crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc
+crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc
+crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc
+crt0-y += ../../../../src/arch/i386/lib/id.inc
+crt0-y += ../../../../src/cpu/amd/car/cache_as_ram.inc
+crt0-y += auto.inc
+
+ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb
+ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds
+ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds
+ldscript-y += ../../../../src/arch/i386/lib/id.lds
+ldscript-y += ../../../../src/arch/i386/lib/failover.lds
+
+\end{verbatim}
+\subsubsection{POST\_EVALUATION}
+POST\_EVALUATION rules should be placed after this section:
+\begin{verbatim}
+ifdef POST_EVALUATION
+\end{verbatim}
+to ensure that the values of variables are correct.
+Here are the post-evaluation rules for this mainboard:
+\begin{verbatim}
+$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+  iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.asl
+  mv dsdt.hex $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c
+  $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $< -o $@
+
+$(obj)/ssdt2.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci2.asl
+  iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl
+  perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex
+  mv pci2.hex ssdt2.c
+
+$(obj)/ssdt3.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci3.asl"
+  iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/
+  perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex
+  mv pci3.hex ssdt3.c
+
+$(obj)/ssdt4.c: $(src)/mainboard/$(MAINBOARDDIR)/dx/pci4.asl"
+  iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl
+  perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex
+  mv pci4.hex ssdt4.c
+
+$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/rom.c $(obj)/option_table.h
+  $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/rom.c -o $@
+  perl -e 's/\.rodata/.rom.data/g' -pi $@
+  perl -e 's/\.text/.section .rom.text/g' -pi $@
+
+\end{verbatim}
+The last rule is for romcc, and, again, we hope to eliminate romcc usage and this rule soon. The first set of rules concern ACPI tables.
+\subsubsection{devicetree.cb}
+Most of the old Config.lb is gone, but one piece remains: the device tree specification. This tree is still required to build a mainboard
+properly, as it defines topology and chips that can be defined no other way.
+Let's go through the tree.
+\begin{verbatim}
+chip northbridge/amd/amdk8/root_complex
+  device cpu_cluster 0 on
+    chip cpu/amd/socket_F
+      device lapic 0 on end
+    end
+  end
+\end{verbatim}
+This topology is always somewhat confusing to newcomers, and even to coreboot veterans.
+
+We root the tree at the pci-e {\it root complex}. There is always the question of how and where to root the tree. Over the years we
+have found that the one part that never goes away is the root complex. CPU sockets may be empty or full; but there is always a northbridge
+somewhere, since it runs memory.
+
+
+What is the APIC? Northbridges always have an Advanced Programmable Interrupt Controller, and that {\it APIC cluster} is a topological connection to the
+CPU socket. So the tree is rooted at the northbridge, which has a link to a CPU cluster, and then the CPU. The CPU contains
+its own APIC, and will define any parameters needed. In this case, we have a northbridge of type
+{\it northbridge/amd/amdk8/root\_complex}, with its own cpu\_cluster device which we turn on,
+which connects to a {\it cpu/amd/socket\_F},
+which has a local apic, which is on.
+
+Note that we do not enumerate all CPUs, even on this SMP mainboard. The reason is they may not all be there. The CPU we define here
+is the so-called Boot Strap Processor, or BSP; the other CPUs will come along later, as the are discovered. We do not require (unlike many
+BIOSes) that the BSP be CPU 0; any CPU will do.
+\begin{verbatim}
+  device domain 0 on
+    chip northbridge/amd/amdk8
+      device pci 18.0 on #  northbridge
+        #  devices on link 0, link 0 == LDT 0
+\end{verbatim}
+Here begins the pci domain, which usually starts with 0. Then there is the northbridge, which bridges to the PCI bus. On
+Opterons, certain CPU control registers are managed in PCI config space in device 18.0 (BSP), 19.0 (AP), and up.
+\begin{verbatim}
+        chip southbridge/amd/amd8132
+          # the on/off keyword is mandatory
+          device pci 0.0 on end
+          device pci 0.1 on end
+          device pci 1.0 on end
+          device pci 1.1 on end
+        end
+\end{verbatim}
+This is the 8132, a bridge to a secondary PCI bus.
+\begin{verbatim}
+        chip southbridge/amd/amd8111
+          # this "device pci 0.0" is the parent the next one
+          # PCI bridge
+          device pci 0.0 on
+            device pci 0.0 on end
+            device pci 0.1 on end
+            device pci 0.2 off end
+            device pci 1.0 off end
+          end
+\end{verbatim}
+The 8111 is a bridge to other busses and to the legacy ISA devices such as superio.
+\begin{verbatim}
+          device pci 1.0 on
+            chip superio/winbond/w83627hf
+              device pnp 2e.0 off #  Floppy
+                 io 0x60 = 0x3f0
+                irq 0x70 = 6
+                drq 0x74 = 2
+              end
+              device pnp 2e.1 off #  Parallel Port
+                 io 0x60 = 0x378
+                irq 0x70 = 7
+              end
+              device pnp 2e.2 on #  Com1
+                 io 0x60 = 0x3f8
+                irq 0x70 = 4
+              end
+              device pnp 2e.3 off #  Com2
+                 io 0x60 = 0x2f8
+                irq 0x70 = 3
+              end
+              device pnp 2e.5 on #  Keyboard
+                 io 0x60 = 0x60
+                 io 0x62 = 0x64
+                irq 0x70 = 1
+                irq 0x72 = 12
+              end
+              device pnp 2e.6 off #  CIR
+                io 0x60 = 0x100
+              end
+              device pnp 2e.7 off #  GAME_MIDI_GIPO1
+                io 0x60 = 0x220
+                io 0x62 = 0x300
+                irq 0x70 = 9
+              end
+              device pnp 2e.8 off end #  GPIO2
+              device pnp 2e.9 off end #  GPIO3
+              device pnp 2e.a off end #  ACPI
+              device pnp 2e.b on #  HW Monitor
+                  io 0x60 = 0x290
+                irq 0x70 = 5
+              end
+            end
+          end
+\end{verbatim}
+The pnp refers to the many Plug N Play devices on a superio. 2e refers to the base I/O address of the superio, and the number following the
+2e (i.e. 2e.1) is the Logical Device Number, or LDN. Each LDN has a common configuration (base, irq, etc.) and these are set by the statements under the LDN.
+\begin{verbatim}
+          device pci 1.1 on end
+          device pci 1.2 on end
+\end{verbatim}
+More devices. These statements set up placeholders in the device tree.
+\begin{verbatim}
+          device pci 1.3 on
+            chip drivers/i2c/i2cmux # pca9556 smbus mux
+              device i2c 18 on #0 pca9516 1
+                chip drivers/generic/generic #dimm 0-0-0
+                  device i2c 50 on end
+                end
+                chip drivers/generic/generic #dimm 0-0-1
+                  device i2c 51 on end
+                end
+                chip drivers/generic/generic #dimm 0-1-0
+                  device i2c 52 on end
+                end
+                chip drivers/generic/generic #dimm 0-1-1
+                  device i2c 53 on end
+                end
+              end
+              device i2c 18 on #1 pca9516 2
+                chip drivers/generic/generic #dimm 1-0-0
+                  device i2c 50 on end
+                end
+                chip drivers/generic/generic #dimm 1-0-1
+                  device i2c 51 on end
+                end
+                chip drivers/generic/generic #dimm 1-1-0
+                  device i2c 52 on end
+                end
+                chip drivers/generic/generic #dimm 1-1-1
+                  device i2c 53 on end
+                end
+                chip drivers/generic/generic #dimm 1-2-0
+                  device i2c 54 on end
+                end
+                chip drivers/generic/generic #dimm 1-2-1
+                  device i2c 55 on end
+                end
+                chip drivers/generic/generic #dimm 1-3-0
+                  device i2c 56 on end
+                end
+                chip drivers/generic/generic #dimm 1-3-1
+                  device i2c 57 on end
+                end
+              end
+            end
+          end # acpi
+\end{verbatim}
+These are the i2c devices.
+\begin{verbatim}
+          device pci 1.5 off end
+          device pci 1.6 off end
+\end{verbatim}
+More placeholders.
+\begin{verbatim}
+               register "ide0_enable" = "1"
+          register "ide1_enable" = "1"
+        end
+      end #  device pci 18.0
+
+\end{verbatim}
+These "register" commands set controls in the southbridge.
+\begin{verbatim}
+           device pci 18.0 on end
+      device pci 18.0 on end
+\end{verbatim}
+These are the other two hypertransport links.
+\begin{verbatim}
+      device pci 18.1 on end
+      device pci 18.2 on end
+      device pci 18.3 on end
+\end{verbatim}
+The 18.1 devices are, again, northbridge control for various k8 functions.
+\begin{verbatim}
+    end
+  \end{verbatim}
+That's it for the BSP I/O and HT busses. Now we begin the AP busses. Not much here.
+\begin{verbatim}
+        chip northbridge/amd/amdk8
+      device pci 19.0 on #  northbridge
+        chip southbridge/amd/amd8151
+          # the on/off keyword is mandatory
+          device pci 0.0 on end
+          device pci 1.0 on end
+        end
+      end #  device pci 19.0
+
+      device pci 19.0 on end
+      device pci 19.0 on end
+      device pci 19.1 on end
+      device pci 19.2 on end
+      device pci 19.3 on end
+    end
+
+
+\end{verbatim}
+
+\subsection{cpu socket}
+The CPU socket is the key link from mainboard to its CPUs. Since many models of CPU can go in a socket, the mainboard mentions only
+the socket, and the socket, in turn, references the various model CPUs which can be plugged into it. The socket is thus the focus
+of all defines and Makefile controls for building the CPU components of a board.
+
+\subsubsection{ cpu/Kconfig}
+Defines variables. Current variables are:
+\input{cpukconfig.tex}
+Sources all Kconfig files in the vendor directories.
+\subsubsection{ cpu/Makefile.inc}
+Unconditionally sources all Makefile.inc in the vendor directories.
+
+\subsection{cpu/$<$vendor$>$/Kconfig}
+The only action currently taken is to source all Kconfig's in the
+subdirectories.
+\subsection{cpu/$<$vendor$>$/Makefile.inc}
+{\em Conditionally} source the socket directories.
+Example:
+\begin{verbatim}
+subdirs-$(CONFIG_CPU_AMD_SOCKET_F) += socket_F
+\end{verbatim}
+.
+CONFIG\_CPU\_AMD\_SOCKET\_F is set in a mainboard file.
+
+\subsection{cpu/$<$vendor$>$/$<$socket$>$/Kconfig}
+Set variables that relate to this {\em socket}, and {\em any models that plug into this socket}. Note that
+the socket, as much as possible, should control the models, because the models may plug into many sockets.
+Socket\_F currently sets:
+\input{socketfkconfig.tex}
+
+It sources only those Kconfigs that relate to this particular socket, i.e. not all possible models are sourced.
+
+\subsection{cpu/$<$vendor$>$/$<$model$>$/Kconfig}
+CPU Model Kconfigs only set variables, We do not expect that they will source any other Kconfig. The socket Kconfig should do that
+if needed.
+\subsection{cpu/$<$vendor$>$/$<$model$>$/Makefile.inc}
+The Makefile.inc {\em unconditionally} specifies drivers and objects to be included in the build. There is no conditional
+compilation at this point. IF a socket is included, it includes the models. If a model is included, it should include {em all}
+objects, because it is not possible to determine at build time what options may be needed for a given model CPU.
+This Makefile.inc includes no other Makefile.inc files; any inclusion should be done in the socket Makefile.inc.
+
+\subsection{northbridge}
+\subsubsection{northbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs.
+\subsubsection{northbridge/Makefile.inc}
+No variables. unconditionally include all vendor Makefile.inc
+\subsubsection{northbridge/$<$vendor$>$/Kconfig}
+No variables. Source all chip directory Kconfigs.
+\subsubsection{northbridge/$<$vendor$>$/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
+is the name of the part, e.g.
+\begin{verbatim}
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
+\end{verbatim}
+.
+\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example
+of the variables defined for the K8.
+\begin{verbatim}
+config NORTHBRIDGE_AMD_AMDK8
+  bool
+  default n
+
+config AGP_APERTURE_SIZE
+  hex
+  default 0x4000000
+\end{verbatim}
+\subsubsection{northbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
+Typically very small set of rules, and very simple.
+Since this file is already conditionally included,
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD K8.
+Note that we can make a variable conditional on the ACPI tables.
+\begin{verbatim}
+driver-y += northbridge.o
+driver-y += misc_control.o
+obj-y +=  get_sblk_pci1234.o
+obj-$(CONFIG_HAVE_ACPI_TABLES) +=  amdk8_acpi.o
+\end{verbatim}
+
+\subsection{southbridge}
+\subsubsection{southbridge/Kconfig}
+No variables. Source all vendor directory Kconfigs.
+\subsubsection{southbridge/Makefile.inc}
+No variables. {\em Unconditionally} include all vendor Makefile.inc
+\subsubsection{southbridge/$<$vendor$>$/Kconfig}
+No variables. Source all chip directory Kconfigs.
+\subsubsection{southbridge/$<$vendor$>$/Makefile.inc}
+No variables. {\em Conditionally} include all chipset Makefile.inc. The variable
+is the name of the part, e.g.
+\begin{verbatim}
+subdirs-$(CONFIG_SOUTHBRIDGE_AMD_AMD8111) += amd8111
+\end{verbatim}
+.
+\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Kconfig}
+Typically a small number of variables. One defines the part name. Here is an example
+of the variables defined for the K8.
+\begin{verbatim}
+config SOUTHBRIDGE_AMD_AMD8111
+	bool
+	default n
+
+\end{verbatim}
+\subsubsection{southbridge/$<$vendor$>$/$<$chip$>$/Makefile.inc}
+Typically very small set of rules, and very simple.
+Since this file is already conditionally included,
+we don't need to test for the chipset CONFIG variable. We
+can therefore test other variables (which is part of the reason
+we set up conditional inclusion of this file, instead
+of unconditionally including it). Here is an example from AMD 8111.
+No conditionals in this one yet.
+\begin{verbatim}
+driver-y += amd8111.o
+driver-y += amd8111_usb.o
+driver-y += amd8111_lpc.o
+driver-y += amd8111_ide.o
+driver-y += amd8111_acpi.o
+driver-y += amd8111_usb2.o
+driver-y += amd8111_ac97.o
+driver-y += amd8111_nic.o
+driver-y += amd8111_pci.o
+driver-y += amd8111_smbus.o
+obj-y += amd8111_reset.o
+\end{verbatim}
+
+\subsubsection{vendor and part}
+\subsection{southbridge}
+\subsubsection{vendor and part}
+\subsection{superio}
+\subsection{drivers/i2c}
+This is a rather special case. There are no Kconfig files or Makefile.inc files here. They are not needed.
+To compile in one of these files, name the .o directory. E.g. in serengeti\_cheetah we have:
+\begin{verbatim}
+\end{verbatim}
+
+\subsubsection{vendor and part}
+
+\end{document}
--- a/Documentation/Lesson2.md
+++ b/Documentation/Lesson2.md
@ -0,0 +1,281 @@
+# coreboot Lesson 2: Submitting a patch to coreboot.org
+
+## Part 1: Setting up an account at coreboot.org
+
+If you already have an account, skip to Part 2.
+
+Otherwise, go to <https://review.coreboot.org> in your preferred web browser.
+Select **Register** in the upper right corner.
+
+Select the appropriate sign-in. For example, if you have a Google account,
+select **Google OAuth2** (gerrit-oauth-provider plugin)".**Note:** Your
+username for the account will be the username of the account you used to
+sign-in with. (ex. your Google username).
+
+## Part 2a: Set up RSA Private/Public Key
+
+If you prefer to use an HTTP password instead, skip to Part 2b.
+
+For the most up-to-date instructions on how to set up SSH keys with Gerrit go to
+<https://gerrit-documentation.storage.googleapis.com/Documentation/2.14.2/user-upload.html#configure_ssh)>
+and follow the instructions there. Then, skip to Part 3.
+
+Additionally, that section of the Web site provides explanation on starting
+an ssh-agent, which may be particularly helpful for those who anticipate
+frequently uploading changes.
+
+If you instead prefer to have review.coreboot.org specific instructions,
+follow the steps below. Note that this particular section may have the
+most up-to-date instructions.
+
+If you do not have an RSA key set up on your account already (as is the case
+with a newly created account), follow the instructions below; otherwise,
+doing so could overwrite an existing key.
+
+In the upper right corner, select your name and click on **Settings**.
+Select **SSH Public Keys** on the left-hand side.
+
+In a terminal, run "ssh-keygen" and confirm the default path ".ssh/id_rsa".
+
+Make a passphrase -- remember this phrase. It will be needed whenever you use
+this RSA Public Key. **Note:** You might want to use a short password, or
+forego the password altogether as you will be using it very often.
+
+Open "id_rsa.pub", copy all contents and paste into the textbox under
+"Add SSH Public Key" in the https://review.coreboot.org webpage.
+
+## Part 2b: Setting up an HTTP Password
+
+Alternatively, instead of using SSH keys, you can use an HTTP password. To do so,
+after you select your name and click on **Settings** on the left-hand side, rather
+than selecting **SSH Public Keys**, select **HTTP Password**.
+
+Click **Generate Password**. This should fill the "Password" box with a password. Copy
+the password, and add the following to your $HOME/.netrc file:
+
+	machine review.coreboot.org login YourUserNameHere password YourPasswordHere
+
+where YourUserNameHere is your username, and YourPasswordHere is the password you
+just generated.
+
+## Part 3: Clone coreboot and configure it for submitting patches
+
+Go to the **Projects** tab in the upper left corner and select **List**.
+From the dropdown menu that appears, select "coreboot".
+
+If you are using SSH keys, select **ssh** from the tabs under "Project coreboot"
+and run the command that appears. This should prompt you for your id_rsa passphrase,
+if you previously set one.
+
+If you are using HTTP, instead, select **http** from the tabs under "Project coreboot"
+and run the command that appears
+
+After it finishes cloning, "cd coreboot" will take you into the local
+git repository. Run "make gitconfig" to set up the hooks and configurations.
+For example, you will be asked to run the following commands to set your
+username and email.
+
+	git config --global user.name "Your Name"
+	git config --global user.email "Your Email"
+
+## Part 4: Submit a commit
+
+An easy first commit to make is fixing existing checkpatch errors and warnings
+in the source files. To see errors that are already present, build the files in
+the repository by running 'make lint' in the coreboot directory. Alternatively,
+if you want to run 'make lint' on a specific directory, run:
+
+	for file in $(git ls-files | grep src/amd/quadcore); do \
+	util/lint/checkpatch.pl --file $file --terse; done
+
+where <filepath> is the filepath of the directory (ex. src/cpu/amd/car).
+
+Any changes made to files under the src directory are made locally,
+and can be submitted for review.
+
+Once you finish making your desired changes, use the command line to stage
+and submit your changes. An alternative and potentially easier way to stage
+and submit commits is to use git cola, a graphical user interface for git. For
+instructions on how to do so, skip to Part 4b.
+
+## Part 4a: Using the command line to stage and submit a commit
+
+To use the command line to stage a commit, run
+
+	git add <filename>
+
+where `filename` is the name of your file.
+
+To commit the change, run
+
+	git commit -s
+
+**Note:** The -s adds a signed-off-by line by the committer. Your commit should be
+signed off with your name and email (i.e. **Your Name** **<Your Email>**, based on
+what you set with git config earlier).
+
+Running git commit first checks for any errors and warnings using lint. If
+there are any, you must go back and fix them before submitting your commit.
+You can do so by making the necessary changes, and then staging your commit again.
+
+When there are no errors or warnings, your default text editor will open.
+This is where you will write your commit message.
+
+The first line of your commit message is your commit summary. This is a brief
+one-line description of what you changed in the files using the template
+below:
+
+<filepath>: Short description
+*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors*
+**Note:** It is good practice to use present tense in your descriptions
+and do not punctuate your summary.
+
+Then hit Enter. The next paragraph should be a more in-depth explanation of the
+changes you've made to the files. Again, it is good practice to use present
+tense.
+*ex.  Fix space prohibited between function name and open parenthesis,
+line over 80 characters, unnecessary braces for single statement blocks,
+space required before open brace errors and warnings.*
+
+When you have finished writing your commit message, save and exit the text
+editor. You have finished committing your change. If, after submitting your
+commit, you wish to make changes to it, running "git commit --amend" allows
+you to take back your commit and amend it.
+
+When you are done with your commit, run 'git push' to push your commit to
+coreboot.org. **Note:** To submit as a draft, use
+'git push origin HEAD:refs/drafts/master' Submitting as a draft means that
+your commit will be on coreboot.org, but is only visible to those you add
+as reviewers.
+
+## Part 4b: Using git cola to stage and submit a commit
+
+If git cola is not installed on your machine, see
+https://git-cola.github.io/downloads.html for download instructions.
+
+After making some edits to src files, rather than run "git add," run
+'git cola' from the command line. You should see all of the files
+edited under "Modified".
+
+In the textbox labeled "Commit summary" provide a brief one-line
+description of what you changed in the files according to the template
+below:
+
+<filepath>: Short description
+*ex. cpu/amd/pi/00630F01: Fix checkpatch warnings and errors*
+**Note:** It is good practice to use present tense in your descriptions
+and do not punctuate your short description.
+
+In the larger text box labeled 'Extended description...' provide a more
+in-depth explanation of the changes you've made to the files. Again, it
+is good practice to use present tense.
+*ex.  Fix space prohibited between function name and open parenthesis,
+line over 80 characters, unnecessary braces for single statement blocks,
+space required before open brace errors and warnings.*
+
+Then press Enter two times to move the cursor to below your description.
+To the left of the text boxes, there is an icon with an downward arrow.
+Press the arrow and select "Sign Off." Make sure that you are signing off
+with your name and email (i.e. **Your Name** **<Your Email>**, based on what
+you set with git config earlier).
+
+Now, review each of your changes and mark either individual changes or
+an entire file as Ready to Commit by marking it as 'Staged'. To do
+this, select one file from the 'Modified' list. If you only want to
+submit particular changes from each file, then highlight the red and
+green lines for your changes, right click and select 'Stage Selected
+Lines'. Alternatively, if an entire file is ready to be committed, just
+double click on the file under 'Modified' and it will be marked as
+Staged.
+
+Once the descriptions are done and all the edits you would like to
+commit have been staged, press 'Commit' on the right of the text
+boxes.
+
+If the commit fails due to persisting errors, a text box will appear
+showing the errors. You can correct these errors within 'git cola' by
+right-clicking on the file in which the error occurred and selecting
+'Launch Diff Tool'. Make necessary corrections, close the Diff Tool and
+'Stage' the corrected file again. It might be necessary to refresh
+'git cola' in order for the file to be shown under 'Modified' again.
+Note: Be sure to add any other changes that haven't already been
+explained in the extended description.
+
+When ready, select 'Commit' again. Once all errors have been satisfied
+and the commit succeeds, move to the command line and run 'git push'.
+**Note:** To submit as a draft, use 'git push origin HEAD:refs/drafts/master'
+Submitting as a draft means that your commit will be on coreboot.org, but is
+only visible to those you add as reviewers.
+
+## Part 5: Getting your commit reviewed
+
+Your commits can now be seen on review.coreboot.org if you select “My”
+and click on “Changes” and can be reviewed by others. Your code will
+first be reviewed by build bot (Jenkins), which will either give you a warning
+or verify a successful build; if so, your commit will receive a +1. Other
+users may also give your commit +1.  For a commit to be merged, it needs
+to receive a +2.**Note:** A +1 and a +1 does not make a +2. Only certain users
+can give a +2.
+
+## Part 6 (optional): bash-git-prompt
+
+To help make it easier to understand the state of the git repository
+without running 'git status' or 'git log', there is a way to make the
+command line show the status of the repository at every point. This
+is through bash-git-prompt.
+
+Instructions for installing this are found at:
+https://github.com/magicmonty/bash-git-prompt
+**Note:** Feel free to search for different versions of git prompt,
+as this one is specific to bash.
+
+Alternatively, follow the instructions below:
+Run the following two commands in the command line:
+
+    cd
+    git clone https://github.com/magicmonty/bash-git-prompt.git .bash-git-prompt --depth=1
+
+**Note:** cd will change your directory to your home directory, so the
+git clone command will be run there.
+
+Finally, open the ~/.bashrc file and append the following two lines:
+
+    GIT_PROMPT_ONLY_IN_REPO=1
+    source ~/.bash-git-prompt/gitprompt.sh
+
+Now, whenever you are in a git repository, it will continuously display
+its state.
+
+There also are additional configurations that you can change depending on your
+preferences. If you wish to do so, look at the "All configs for .bashrc" section
+on https://github.com/magicmonty/bash-git-prompt. Listed in that section are
+various lines that you can copy, uncomment and add to your .bashrc file to
+change the configurations. Example configurations include avoid fetching remote
+status, and supporting versions of Git older than 1.7.10.
+
+## Appendix: Miscellaneous Advice
+
+### Updating a commit after running git push:
+
+Suppose you would like to update a commit that has already been pushed to the
+remote repository. If the commit you wish to update is the most recent
+commit you have made, after making your desired changes, stage the files
+(either using git add or in git cola), and amend the commit. To do so,
+if you are using the command line, run "git commit --amend." If you are
+using git cola, click on the gear icon located on the upper left side under
+**Commit** and select **Amend Last Commit** in the drop down menu. Then, stage
+the files you have changed, commit the changes, and run git push to push the
+changes to the remote repository. Your change should be reflected in Gerrit as
+a new patch set.
+
+If, however, the commit you wish to update is not the most recent commit you
+have made, you will first need to checkout that commit. To do so, find the
+URL of the commit on <https://review.coreboot.org> and go to that page; if
+the commit is one that you previously pushed, it can be found by selecting
+**My** and then **Changes** in the upper left corner. To checkout this commit,
+in the upper right corner, click on **Download**, and copy the command listed
+next to checkout by clicking **Copy to clipboard**. Then, run the copied
+command in your coreboot repository. Now, the last commit should be the most
+recent commit to that patch; to update it, make your desired changes, stage
+the files, then amend and push the commit using the instructions in the above
+paragraph.
--- a/Documentation/Makefile
+++ b/Documentation/Makefile
@ -1,19 +1,17 @@
-## SPDX-License-Identifier: GPL-2.0-only
 #
 # Makefile for coreboot paper.
 # hacked together by Stefan Reinauer <stepan@openbios.org>
 #

-PDFLATEX  = pdflatex -t a4
-BUILDDIR ?= _build
+PDFLATEX=pdflatex -t a4

 FIGS=codeflow.pdf hypertransport.pdf

-all: sphinx corebootPortingGuide.pdf
+all: corebootPortingGuide.pdf Kconfig.pdf

-SVG2PDF=$(shell command -v svg2pdf)
-INKSCAPE=$(shell command -v inkscape)
-CONVERT=$(shell command -v convert)
+SVG2PDF=$(shell which svg2pdf)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)

 codeflow.pdf: codeflow.svg
 ifneq ($(strip $(SVG2PDF)),)
@ -33,9 +31,6 @@ else ifneq ($(strip $(CONVERT)),)
 	convert $< $@
 endif

-$(BUILDDIR):
-	mkdir -p $(BUILDDIR)
-
 corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 	# 2 times to make sure we have a current toc.
 	$(PDFLATEX) corebootBuildingGuide.tex
@ -44,37 +39,38 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
 	$(PDFLATEX) corebootBuildingGuide.tex

-sphinx: $(BUILDDIR)
-	$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)"
+Kconfig.pdf: Kconfig.tex mainboardkconfig.tex cpukconfig.tex socketfkconfig.tex
+	$(PDFLATEX) $<
+
+# quick, somebody! make me a macro!
+mainboardkconfig.tex: ../src/mainboard/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+skconfig.tex: ../src/mainboard/amd/serengeti_cheetah/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+cpukconfig.tex: ../src/cpu/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+socketfkconfig.tex: ../src/cpu/amd/socket_F/Kconfig
+	cat beginverbatim.tex  > $@
+	grep '^config' $< | awk '{print $2}'  >>$@
+	cat endverbatim.tex  >> $@
+
+sphinx:
+	$(MAKE) -f Makefile.sphinx html

 clean-sphinx:
-	$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx clean

 clean: clean-sphinx
-	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
+	rm -f *.aux *.idx *.log *.toc *.out $(FIGS) mainboardkconfig.tex skconfig.tex cpukconfig.tex socketfkconfig.tex

 distclean: clean
-	rm -f corebootPortingGuide.pdf
-
-livesphinx: $(BUILDDIR)
-	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)" BUILDDIR="$(BUILDDIR)"
-
-test:
-	@echo "Test for logging purposes - Failing tests will not fail the build"
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
-
-help:
-	@echo "all            - Builds coreboot porting guide PDF (outdated)"
-	@echo "sphinx         - Builds html documentation in _build directory"
-	@echo "clean          - Cleans intermediate files"
-	@echo "clean-sphinx   - Removes sphinx output files"
-	@echo "distclean      - Removes PDF files as well"
-	@echo "test           - Runs documentation tests"
-	@echo
-	@echo "  Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
-	@echo
-	@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
-
-.phony: help livesphinx sphinx test
-.phony: distclean clean clean-sphinx
+	rm -f corebootPortingGuide.pdf Kconfig.pdf
--- a/Documentation/Makefile.sphinx
+++ b/Documentation/Makefile.sphinx
@ -1,13 +1,11 @@
-## SPDX-License-Identifier: GPL-2.0-only
 # Makefile for Sphinx documentation
 #

 # You can set these variables from the command line.
-SPHINXOPTS        ?=
-SPHINXBUILD       = sphinx-build
-SPHINXAUTOBUILD   = sphinx-autobuild
-PAPER             =
-BUILDDIR          = _build
+SPHINXOPTS    =
+SPHINXBUILD   = sphinx-build
+PAPER         =
+BUILDDIR      = _build

 # Internal variables.
 PAPEROPT_a4     = -D latex_paper_size=a4
@ -48,7 +46,7 @@ help:

 .PHONY: clean
 clean:
-	rm -rf $(BUILDDIR)
+	rm -rf $(BUILDDIR)/*

 .PHONY: html
 html:
@ -56,13 +54,6 @@ html:
 	@echo
 	@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."

-.PHONY: livehtml
-livehtml:
-	@echo "Starting sphinx-autobuild. The HTML pages are in $(BUILDDIR)."
-	@echo "Press Ctrl-C to stop."
-	@echo
-	$(SPHINXAUTOBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)
-
 .PHONY: dirhtml
 dirhtml:
 	$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
--- a/Documentation/POSTCODES
+++ b/Documentation/POSTCODES
@ -16,12 +16,6 @@ This is an (incomplete) list of POST codes emitted by coreboot v4.
 0x66 Devices have been enumerated
 0x88 Devices have been configured
 0x89 Devices have been enabled
-0xe0 Boot media (e.g. SPI ROM) is corrupt
-0xe1 Resource stored within CBFS is corrupt
-0xe2 Vendor binary (e.g. FSP) generated a fatal error
-0xe3 RAM could not be initialized
-0xe4 Critical hardware component could not initialize
-0xe5 Video subsystem failed to initialize
 0xf8 Entry into elf boot
 0xf3 Jumping to payload

--- a/Documentation/RFC/chip.tex
+++ b/Documentation/RFC/chip.tex
@ -7,7 +7,7 @@ change.

 \section{Scope}
 This document defines how LinuxBIOS programmers can specify chips that
-are used, specified, and initialized. The current scope is for superio
+are used, specified, and initalized. The current scope is for superio
 chips, but the architecture should allow for specification of other chips such
 as southbridges. Multiple chips of same or different type are supported.

--- a/Documentation/RFC/config.tex
+++ b/Documentation/RFC/config.tex
@ -0,0 +1,290 @@
+		New config language for LinuxBIOS
+
+\begin{abstract}
+We describe the new configuration language for LinuxBIOS.
+\end{abstract}
+
+\section{Scope}
+This document defines the new configuration language for LinuxBIOS.
+
+\section{Goals}
+The goals of the new language are these:
+\begin{itemize}
+\item Simplified Makefiles so people can see what is set
+\item Move from the regular-expression-based language to something
+a bit more comprehensible and flexible
+\item make the specification easier for people to use and understand
+\item allow unique register-set-specifiers for each chip
+\item allow generic register-set-specifiers for each chip
+\item generate static initialization code, as needed, for the
+specifiers.
+\end{itemize}
+
+\section{Language}
+Here is the new language. It is very similar to the old one, differing
+in only a few respects. It borrows heavily from Greg Watson's suggestions.
+
+I am presenting it in a pseudo-BNF in the hopes it will be easier. Things
+in '' are keywords; things in ``'' are strings in the actual text.
+\begin{verbatim}
+#exprs are composed of factor or factor + factor etc.
+expr ::= factor ( ``+'' factor | ``-'' factor | )*
+#factors are term or term * term or term / term or ...
+factor ::=  term ( ``*'' term | ``/'' term | ... )*
+#
+unary-op ::= ``!'' ID
+# term is a number, hexnumber, ID, unary-op, or a full-blown expression
+term ::= NUM | XNUM | ID | unary-op | ``(`` expr ``)''
+
+# Option command. Can be an expression or quote-string.
+# Options are used in the config tool itself (in expressions and 'if')
+# and are also passed to the C compiler when building linuxbios.
+# It is an error to have two option commands in a file.
+# It is an error to have an option command after the ID has been used
+#   in an expression (i.e. 'set after used' is an error)
+option ::= 'option' ID '=' (``value'' | term)
+
+# Default command. The ID is set to this value if no option command
+# is scanned.
+# Multiple defaults for an ID will produce warning, but not errors.
+# It is OK to scan a default command after use of an ID.
+# Options always over-ride defaults.
+default ::= 'default' ID '=' (``value'' | term)
+
+# the mainboard, southbridge, northbridge commands
+# cause sourcing of Config.lb files as in the old config tool
+# as parts are sourced, a device tree is built. The structure
+# of the tree is determined by the structure of the components
+# as they are specified. To attach a superio to a southbridge, for
+# example, one would do this:
+# southbridge acer/5432
+#   superio nsc/123
+#   end
+# end
+# the tool generates static initializers for this hierarchy.
+
+# add C code to the current component (motherboard, etc. )
+# to initialise the component-INDEPENDENT structure members
+init ::= 'init' ``CODE''
+
+# add C code to the current component (motherboard, etc. )
+# to initialise the component-DEPENDENT structure members
+register ::= 'register' ``CODE''
+
+
+# mainboard command
+# statements in this block will set variables controlling the mainboard,
+# and will also place components (northbridge etc.) in the device tree
+# under this mainboard
+mainboard ::= 'mainboard' PATH (statements)* 'end'
+
+# standard linuxbios commands
+southbridge ::= 'southbridge' PATH (statemnts)* 'end'
+northbridge ::= 'northbridge' PATH (statemnts)* 'end'
+superio ::= 'superio PATH (statemnts)* 'end'
+cpu ::= 'cpu' PATH (statemnts)* 'end'
+arch ::= 'arch' PATH (statemnts)* 'end'
+
+# files for building linuxbios
+# include a file in crt0.S
+mainboardinit ::= 'mainboardinit' PATH
+
+# object file
+object ::= 'object' PATH
+# driver objects are just built into the image in a different way
+driver ::= 'driver' PATH
+
+# Use the Config.lb file in the PATH
+dir ::= 'dir' PATH
+
+# add a file to the set of ldscript files
+ldscript ::= 'ldscript' PATH
+
+# dependencies or actions for the makerule command
+dep ::= 'dep' ``dependency-string''
+act ::= 'act' ``actions''
+depsacts ::= (dep | act)*
+# set up a makerule
+#
+makerule ::= 'makerule' PATH depsacts
+
+#defines for use in makefiles only
+# note usable in the config tool, not passed to cc
+makedefine ::= 'makedefine' ``RAWTEXT''
+
+# add an action to an existing make rule
+addaction ::= 'addaction' PATH ``ACTION''
+
+# statements
+statement ::=
+		  option
+		| default
+        	| cpu
+        	| arch
+		| northbridge
+		| southbridge
+		| superio
+		| object
+		| driver
+		| mainboardinit
+		| makerule
+		| makedefine
+		| addaction
+		| init
+		| register
+		| iif
+		| dir
+		| ldscript
+
+statements ::= (statement)*
+
+# target directory specification
+target ::= 'target' PATH
+
+# and the whole thing
+board ::= target (option)* mainboard
+
+\end{verbatim}
+
+\subsubsection{Command definitions}
+\subsubsubsection{option}
+\subsubsubsection{default}
+\subsubsubsection{cpu}
+\subsubsubsection{arch}
+\subsubsubsection{northbridge}
+\subsubsubsection{southbridge}
+\subsubsubsection{superio}
+\subsubsubsection{object}
+\subsubsubsection{driver}
+\subsubsubsection{mainboardinit}
+\subsubsubsection{makerule}
+\subsubsubsection{makedefine}
+\subsubsubsection{addaction}
+\subsubsubsection{init}
+\subsubsubsection{register}
+\subsubsubsection{iif}
+\subsubsubsection{dir}
+\subsubsubsection{ldscript}
+
+
+A sample file:
+
+\begin{verbatim}
+target x
+
+# over-ride the default ROM size in the mainboard file
+option CONFIG_ROM_SIZE=1024*1024
+mainboard amd/solo
+end
+
+\end{verbatim}
+
+Sample mainboard file
+\begin{verbatim}
+#
+###
+### Set all of the defaults for an x86 architecture
+###
+arch i386 end
+cpu k8 end
+#
+option CONFIG_DEBUG=1
+default CONFIG_USE_FALLBACK_IMAGE=1
+option A=(1+2)
+option B=0xa
+#
+###
+### Build our 16 bit and 32 bit linuxBIOS entry code
+###
+mainboardinit cpu/i386/entry16.inc
+mainboardinit cpu/i386/entry32.inc
+ldscript cpu/i386/entry16.lds
+ldscript cpu/i386/entry32.lds
+#
+###
+### Build our reset vector (This is where linuxBIOS is entered)
+###
+if CONFIG_USE_FALLBACK_IMAGE
+	mainboardinit cpu/i386/reset16.inc
+	ldscript cpu/i386/reset16.lds
+else
+	mainboardinit cpu/i386/reset32.inc
+	ldscript cpu/i386/reset32.lds
+end
+.
+.
+.
+if CONFIG_USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
+#
+###
+### Romcc output
+###
+#makerule ./failover.E dep "$(CONFIG_MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c > ./failever.E"
+#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
+#mainboardinit ./failover.inc
+makerule ./auto.E dep "$(CONFIG_MAINBOARD)/auto.c" act "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c > ./auto.E"
+makerule ./auto.inc dep "./romcc ./auto.E" act "./romcc -O ./auto.E > auto.inc"
+mainboardinit ./auto.inc
+#
+###
+### Include the secondary Configuration files
+###
+northbridge amd/amdk8
+end
+southbridge amd/amd8111
+end
+#mainboardinit arch/i386/smp/secondary.inc
+superio nsc/pc87360
+	register "com1={1} com2={0} floppy=1 lpt=1 keyboard=1"
+end
+dir /pc80
+##dir /src/superio/winbond/w83627hf
+cpu p5 end
+cpu p6 end
+cpu k7 end
+cpu k8 end
+#
+###
+### Build the objects we have code for in this directory.
+###
+##object mainboard.o
+driver mainboard.o
+object static_devices.o
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+### Location of the DIMM EEPROMS on the SMBUS
+### This is fixed into a narrow range by the DIMM package standard.
+###
+option SMBUS_MEM_DEVICE_START=(0xa << 3)
+option SMBUS_MEM_DEVICE_END=(SMBUS_MEM_DEVICE_START +1)
+option SMBUS_MEM_DEVICE_INC=1
+#
+### The linuxBIOS bootloader.
+###
+option CONFIG_PAYLOAD_SIZE            = (CONFIG_ROM_SECTION_SIZE - CONFIG_ROM_IMAGE_SIZE)
+option CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
+#
+
+\end{verbatim}
+
+I've found the output of the new tool to be easier to
+handle. Makefile.settings looks like this, for example:
+\begin{verbatim}
+TOP:=/home/rminnich/src/yapps2/freebios2
+TARGET_DIR:=x
+export CONFIG_MAINBOARD:=/home/rminnich/src/yapps2/freebios2/src/mainboard/amd/solo
+export CONFIG_ARCH:=i386
+export CONFIG_RAMBASE:=0x4000
+export CONFIG_ROM_IMAGE_SIZE:=65535
+export CONFIG_PAYLOAD_SIZE:=131073
+export CONFIG_MAX_CPUS:=1
+export CONFIG_HEAP_SIZE:=8192
+export CONFIG_STACK_SIZE:=8192
+export CONFIG_MEMORY_HOLE:=0
+export COREBOOT_VERSION:=1.1.0
+export CC:=$(CONFIG_CROSS_COMPILE)gcc
+
+\end{verbatim}
+
+In other words, instead of expressions, we see the values. It's easier to
+deal with.
--- a/Documentation/RFC/intel-gpio-cleanup.md
+++ b/Documentation/RFC/intel-gpio-cleanup.md
@ -1,98 +0,0 @@
-# Background
-
-CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
-done") introduced a workaround in coreboot for `soc/intel/cannonlake`
-platforms to save and restore GPIO configuration performed by
-mainboard across call to FSP Silicon Init (FSP-S). This workaround was
-required because FSP-S was configuring GPIOs differently than
-mainboard resulting in boot and runtime issues because of
-misconfigured GPIOs. This issue was observed on `google/hatch`
-mainboard and was raised with Intel to get the FSP behavior
-fixed. Until the fix in FSP was available, this workaround was used to
-ensure that the mainboards can operate correctly and were not impacted
-by the GPIO misconfiguration in FSP-S.
-
-The issues observed on `google/hatch` mainboard were fixed by adding
-(if required) and initializing appropriate FSP UPDs. This UPD
-initialization ensured that FSP did not configure any GPIOs
-differently than the mainboard configuration. Fixes included:
- * CB:31375 ("soc/intel/cannonlake: Configure serial debug uart")
- * CB:31520 ("soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports")
- * CB:32176 ("mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip select")
- * CB:34900 ("soc/intel/cnl: Add provision to configure SD controller write protect pin")
-
-With the above changes merged, it was verified on `google/hatch`
-mainboard that the workaround for GPIO reconfiguration was not
-needed. However, at the time, we missed dropping the workaround in
-'soc/intel/cannonlake`. Currently, this workaround is used by the
-following mainboards:
- * `google/drallion`
- * `google/sarien`
- * `purism/librem_cnl`
- * `system76/lemp9`
-
-As verified on `google/hatch`, FSP v1263 included all UPD additions
-that were required for addressing this issue.
-
-# Proposal
-
-* The workaround can be safely dropped from `soc/intel/cannonlake`
-  only after the above mainboards have verified that FSP-S does not
-  configure any pads differently than the mainboard in coreboot. Since
-  the fix included initialization of FSP UPDs correctly, the above
-  mainboards can use the following diff to check what pads change
-  after FSP-S has run:
-
-```
-diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
-index 28e78fb366..0cce41b316 100644
--- a/src/soc/intel/common/block/gpio/gpio.c
-+++ b/src/soc/intel/common/block/gpio/gpio.c
-@@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
-                /* Patch GPIO settings for SoC specifically */
-                soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
-
-               if (CONFIG(DEBUG_GPIO))
-+               if (soc_pad_conf != pad_conf)
-                        printk(BIOS_DEBUG,
-                       "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
-                       " : 0x%08x]\n",
-+                       "%d: gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
-+                       " : 0x%08x]\n", cfg->pad,
-                        comm->port, relative_pad_in_comm(comm, cfg->pad), i,
-                        pad_conf,/* old value */
-                        cfg->pad_config[i],/* value passed from gpio table */
-```
-
-Depending upon the pads that are misconfigured by FSP-S, these
-mainboards will have to set UPDs appropriately. Once this is verified
-by the above mainboards, the workaround implemented in CB:31250 can be
-dropped.
-
-* The fix implemented in FSP/coreboot for `soc/intel/cannonlake`
-  platforms is not really the right long term solution for the
-  problem. Ideally, FSP should not be touching any GPIO configuration
-  and letting coreboot configure the pads as per mainboard
-  design. This recommendation was accepted and implemented by Intel
-  starting with Jasper Lake and Tiger Lake platforms using a single
-  UPD `GpioOverride` that coreboot can set so that FSP does not change
-  any GPIO configuration. However, this implementation is not
-  backported to any older platforms. Given the issues that we have
-  observed across different platforms, the second proposal is to:
-
-  - Add a Kconfig `CHECK_GPIO_CONFIG_CHANGES` that enables checks
-    in coreboot to stash GPIO pad configuration before various calls
-    to FSP and compares the configuration on return from FSP.
-  - This will have to be implemented as part of
-    drivers/intel/fsp/fsp2_0/ to check for the above config selection
-    and make callbacks `gpio_snapshot()` and `gpio_verify_snapshot()`
-    to identify and print information about pads that have changed
-    configuration after calls to FSP.
-  - This config can be kept disabled by default and mainboard
-    developers can enable them as and when required for debug.
-  - This will be helpful not just for the `soc/intel/cannonlake`
-    platforms that want to get rid of the above workaround, but also
-    for all future platforms using FSP to identify and catch any GPIO
-    misconfigurations that might slip in to any platforms (in case the
-    `GpioOverride` UPD is not honored by any code path within FSP).
-
--- a/Documentation/lib/abi-data-consumption.md
+++ b/Documentation/lib/abi-data-consumption.md
@ -8,9 +8,8 @@ listed as consumable is subject to change without notice.
 ## Background and Usage

 coreboot passes information to downstream users using coreboot tables. These
-table definitions can be found in
-`./src/commonlib/include/commonlib/coreboot_tables.h` and
-`./payloads/libpayload/include/coreboot_tables.h` respectively within coreboot
+table definitions can be found in src/include/boot/coreboot_tables.h and
+payloads/libpayload/include/coreboot_tables.h respectively within coreboot
 and libpayload. One of the most vital and important pieces of information
 found within these tables is the memory map of the system indicating
 available and reserved memory.
--- a/Documentation/acpi/gpio.md
+++ b/Documentation/acpi/gpio.md
@ -73,17 +73,17 @@ calling the platform specific acpigen_soc_{set,clear}_tx_gpio
 functions internally. Thus, all the ACPI AML calling conventions for
 the platform functions apply to these helper functions as well.

-3. Get Rx GPIO
-   int acpigen_get_rx_gpio(struct acpi_gpio gpio)
-
-This function takes as input, an struct acpi_gpio type and outputs
-AML code to read the *logical* value of a gpio (after taking its
-polarity into consideration), into the Local0 variable. It calls
-the platform specific acpigen_soc_read_rx_gpio() to actually read
-the raw Rx gpio value.
-
 ## Implementation Details

+ACPI library in coreboot will provide weak definitions for all the
+above functions with error messages indicating that these functions
+are being used. This allows drivers to conditionally make use of GPIOs
+based on device-tree entries or any other config option. It is
+recommended that the SoC code in coreboot should provide
+implementations of all the above functions generating ACPI AML code
+irrespective of them being used in any driver. This allows mainboards
+to use any drivers and take advantage of this common infrastructure.
+
 Platforms are restricted to using Local5, Local6 and Local7 variables
 only in implementations of the above functions. Any AML methods called
 by the above functions do not have any such restrictions on use of
@ -150,6 +150,7 @@ for the GPIO.
 	 */
 	acpigen_write_if_and(Local5, TX_BIT);
 	acpigen_write_store_args(ONE_OP, LOCAL0_OP);
+	acpigen_pop_len();
 	acpigen_write_else();
 	acpigen_write_store_args(ZERO_OP, LOCAL0_OP);
 	acpigen_pop_len();
--- a/Documentation/acpi/index.md
+++ b/Documentation/acpi/index.md
@ -1,22 +0,0 @@
-# ACPI-specific documentation
-
-This section contains documentation about coreboot on ACPI. coreboot dropped
-backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and
-upwards.
-
-
- [SSDT UID generation](uid.md)
-
-## GPIO
-
- [GPIO toggling in ACPI AML](gpio.md)
-
-## Windows-specific ACPI documentation
-
- [Windows-specific documentation](windows.md)
-
-##  ACPI specification - Useful links
-
- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
--- a/Documentation/acpi/uid.md
+++ b/Documentation/acpi/uid.md
@ -1,14 +0,0 @@
-# ACPI SSDT \_UID generation
-
-According to the ACPI spec:
-
-> The _UID must be unique across all devices with either a common _HID or _CID.
-
-
-When generating SSDTs in coreboot the independent drivers don't know
-which \_UID is already in use for a specific \_HID or \_CID. To generate
-unique \_UIDs the ACPI device's path is hashed and used as ID. As every ACPI
-device has a different path, the hash will be also different for every device.
-
-Windows 10 verifies all devices with the same \_HID or \_CID and makes
-sure that no \_UID is duplicated. If it is it'll BSOD.
--- a/Documentation/acpi/windows.md
+++ b/Documentation/acpi/windows.md
@ -1,9 +0,0 @@
-# Testing ACPI changes under Windows
-
-When testing ACPI changes in coreboot against Windows 8 or newer, beware that
-during a normal boot after a clean shutdown, Windows will use the fast startup
-mechanism which results in it not evaluating the changed ACPI code but instead
-using some cached version which won't include the changes that were supposed to
-be tested. In order for Windows to actually use the new ACPI tables, either
-disable the fast startup or just tell Windows to do a reboot which will make it
-read and use the ACPI tables in memory instead of an outdated cached version.
--- a/Documentation/acronyms.md
+++ b/Documentation/acronyms.md
--- a/Documentation/arch/index.md
+++ b/Documentation/arch/index.md
@ -1,11 +0,0 @@
-# Architecture-specific documentation
-
-This section contains documentation about coreboot on specific CPU
-architectures.
-
-## RISC-V
-
- [RISC-V documentation](riscv/index.md)
-
-## x86
- [x86 documentation](x86/index.md)
--- a/Documentation/arch/riscv/index.md
+++ b/Documentation/arch/riscv/index.md
@ -1,64 +0,0 @@
-# RISC-V architecture documentation
-
-This section contains documentation about coreboot on RISC-V architecture.
-
-## Mode usage
-All stages run in M mode.
-
-Payloads have a choice of managing M mode activity: they can control
-everything or nothing.
-
-Payloads run from the romstage (i.e. rampayloads) are started in M mode.
-The payload must, for example, prepare and install its own SBI.
-
-Payloads run from the ramstage are started in S mode, and trap delegation
-will have been done. These payloads rely on the SBI and can not replace it.
-
-## Stage handoff protocol
-On entry to a stage or payload (including SELF payloads),
-* all harts are running.
-* A0 is the hart ID.
-* A1 is the pointer to the Flattened Device Tree (FDT).
-* A2 contains the additional program calling argument:
-  - cbmem_top for ramstage
-  - the address of the payload for opensbi
-
-## Additional payload handoff requirements
-The location of cbmem should be placed in a node in the FDT.
-
-## OpenSBI
-In case the payload doesn't install it's own SBI, like the [RISCV-PK] does,
-[OpenSBI] can be used instead.
-It's loaded into RAM after coreboot has finished loading the payload.
-coreboot then will jump to OpenSBI providing a pointer to the real payload,
-which OpenSBI will jump to once the SBI is installed.
-
-Besides providing SBI it also sets protected memory regions and provides
-a platform independent console.
-
-The OpenSBI code is always run in M mode.
-
-## Trap delegation
-Traps are delegated to the payload.
-
-## SMP within a stage
-At the beginning of each stage, all harts save 0 are spinning in a loop on
-a semaphore.  At the end of the stage harts 1..max are released by changing
-the semaphore.
-
-A possible way to do this is to have a pointer to a struct containing
-variables, e.g.
-
-```c
-struct blocker {
-	void (*fn)(); // never returns
-}
-```
-
-The hart blocks until fn is non-null, and then calls it.  If fn returns, we
-will panic if possible, but behavior is largely undefined.
-
-Only hart 0 runs through most of the code in each stage.
-
-[RISCV-PK]: https://github.com/riscv/riscv-pk
-[OpenSBI]: https://github.com/riscv/opensbi
--- a/Documentation/arch/x86/index.md
+++ b/Documentation/arch/x86/index.md
@ -1,95 +0,0 @@
-# x86 architecture documentation
-
-This section contains documentation about coreboot on x86 architecture.
-
-* [x86 PAE support](pae.md)
-
-## State of x86_64 support
-At the moment there's only experimental x86_64 support.
-The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support
-*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*.
-
-In order to add support for x86_64 the following assumptions were made:
-* The CPU supports long mode
-* All memory returned by malloc must be below 4GiB in physical memory
-* All code that is to be run must be below 4GiB in physical memory
-* The high dword of pointers is always zero
-* The reference implementation is qemu
-* The CPU supports 1GiB hugepages
-* x86 payloads are loaded below 4GiB in physical memory and are jumped
-  to in *protected mode*
-
-## Assumptions for all stages using the reference implementation
-* 0-4GiB are identity mapped using 2MiB-pages as WB
-* Memory above 4GiB isn't accessible
-* page tables reside in memory mapped ROM
-* A stage can install new page tables in RAM
-
-## Page tables
-A `pagetables` cbfs file is generated based on an assembly file.
-
-To generate the static page tables it must know the physical address where to
-place the file.
-
-The page tables contains the following structure:
-* PML4E pointing to PDPE
-* PDPE with *$n* entries each pointing to PDE
-* *$n* PDEs with 512 entries each
-
-At the moment *$n* is 4, which results in identity mapping the lower 4 GiB.
-
-## Basic x86_64 support
-Basic support for x86_64 has been implemented for QEMU mainboard target.
-
-## Reference implementation
-The reference implementation is
-* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md)
-* [QEMU Q35](../../mainboard/emulation/qemu-q35.md)
-
-## TODO
-* Identity map memory above 4GiB in ramstage
-
-## Future work
-
-1. Fine grained page tables for SMM:
-   * Must not have execute and write permissions for the same page.
-   * Must allow only that TSEG pages can be marked executable
-   * Must reside in SMRAM
-2. Support 64bit PCI BARs above 4GiB
-3. Place and run code above 4GiB
-
-## Porting other boards
-* Fix compilation errors
-* Test how well CAR works with x86_64 and paging
-* Improve mode switches
-* Test libgfxinit / VGA Option ROMs / FSP
-
-## Known bugs on real hardware
-
-According to Intel x86_64 mode hasn't been validated in CAR environments.
-Until now it could be verified on various Intel platforms and no issues have
-been found.
-
-## Known bugs on KVM enabled qemu
-
-The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues
-when using KVM mode on some machines. The workaround is to *not* place
-page-tables in ROM, as done in
-[CB:49228](https://review.coreboot.org/c/coreboot/+/49228).
-
-Here's a list of known issues:
-
-* After entering long mode, the FPU doesn't work anymore, including accessing
-  MMX registers. It works fine before entering long mode. It works fine when
-  switching back to protected mode. Other registers, like SSE registers, are
-  working fine.
-* Reading from virtual memory, when the page tables are stored in ROM, causes
-  the MMU to abort the "page table walking" mechanism when the lower address
-  bits of the virtual address to be translated have a specific pattern.
-  Instead of loading the correct physical page, the one containing the
-  page tables in ROM will be loaded and used, which breaks code and data as
-  the page table doesn't contain the expected data. This in turn leads to
-  undefined behaviour whenever the 'wrong' address is being read.
-* Disabling paging in compatibility mode crashes the CPU.
-* Returning from long mode to compatibility mode crashes the CPU.
-* Entering long mode crashes on AMD host platforms.
--- a/Documentation/arch/x86/pae.md
+++ b/Documentation/arch/x86/pae.md
@ -1,15 +0,0 @@
-# x86_32 PAE documentation
-
-Due to missing x86_64 support it's required to use PAE enabled x86_32 code.
-The corresponding functions can be found in ``src/cpu/x86/pae/``.
-
-## Memory clearing helper functions
-
-To clear all DRAM on request of the
-[Security API](../../security/memory_clearing.md), a helper function can be used
-called `memset_pae`.
-The function has additional requirements in contrast to `memset`, and has more
-overhead as it uses virtual memory to access memory above 4GiB.
-Memory is cleared in 2MiB chunks, which might take a while.
-
-Make sure to enable caches through MTRRs, otherwise `memset_pae` will be slow!
--- a/Documentation/getting_started/build_system.md
+++ b/Documentation/getting_started/build_system.md
@ -62,23 +62,6 @@ supported options are:

 `position` and `align` are mutually exclusive.

-### Adding Makefile fragments
-
-You can use the `add_intermediate` helper to add new post-processing steps for
-the final `coreboot.rom` image. For example you can add new files to CBFS by
-adding something like this to `site-local/Makefile.inc`
-
-```
-$(call add_intermediate, add_mrc_data)
-	$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
-```
-
-Note that the second line must start with a tab, not spaces.
-
-```eval_rst
-See also :doc:`../tutorial/managing_local_additions`.
-```
-
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a
 need to extend the specification of files to provide more precise control
--- a/Documentation/cbfs.txt
+++ b/Documentation/cbfs.txt
@ -174,7 +174,7 @@ with
 regards to the erase block sizes on the ROM - allowing one to replace a
 component at runtime without disturbing the others.

-'offset' is the offset of the first CBFS component (from the start of
+'offset' is the offset of the the first CBFS component (from the start of
 the ROM).  This is to allow for arbitrary space to be left at the beginning
 of the ROM for things like embedded controller firmware.

@ -384,7 +384,7 @@ PAYLOAD_SEGMENT_BSS    0x20535342   The memory specified by the segment
 PAYLOAD_SEGMENT_PARAMS 0x41524150   The segment contains information for
                                     the payload
 PAYLOAD_SEGMENT_ENTRY  0x52544E45   The segment contains the entry point
-		  		    for the payload
+		       		    for the payload

 'compression' is the compression scheme for the segment.  Each segment can
 be independently compressed. There are three compression types defined by
--- a/Documentation/codeflow.svg
+++ b/Documentation/codeflow.svg
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--- a/Documentation/community/code_of_conduct.md
+++ b/Documentation/community/code_of_conduct.md
@ -1,129 +0,0 @@
-# Code of Conduct
-
-This code of conduct outlines our rules and expectations for everybody
-participating in the coreboot community.
-
-## coreboot community etiquette
-
-We have a friendly and productive atmosphere on our mailing lists,
-development / code review tools, IRC chat rooms and when we meet in
-person.  Our principles evolve around the following:
-
-* It's not the user's fault if something goes wrong.
-* Attempt collaboration before conflict.
-* People who intentionally insult others (users, developers, corporations,
-  other projects, or the coreboot project itself) will be dealt with. See
-  policy below.
-* We are dealing with hardware with lots of undocumented pitfalls. It is quite
-  possible that you did everything right, but coreboot or its tools still
-  won't work for you.
-
-Refrain from insulting anyone or the group they belong to. Remember that
-people might be sensitive to other things than you are.
-
-Most of our community members are not native English speakers, thus
-misunderstandings can (and do) happen. Assume that others are friendly
-and may have picked less-than-stellar wording by accident as long as
-you possibly can.
-
-## Reporting Issues
-
-If you have a grievance due to conduct in this community, we're sorry
-that you have had a bad experience, and we want to hear about it so
-we can resolve the situation.
-
-Please contact members of our arbitration team (listed below) promptly
-and directly, in person (if available) or by email: They will listen
-to you and react in a timely fashion.
-
-If you feel uncomfortable, please don't wait it out, ask for help,
-so we can work on setting things right.
-
-For transparency there is no alias or private mailing list address for
-you to reach out to, since we want to make sure that you know who will
-and who won't read your message.
-
-However since people might be on travel or otherwise be unavailable
-at times, please reach out to multiple persons at once, especially
-when using email.
-
-The team will treat your messages confidential as far as the law permits.
-For the purpose of knowing what law applies, the list provides the usual
-country of residence of each team member.
-
-## Unacceptable Behavior
-
-Unacceptable behaviors include: intimidating, harassing, abusive,
-discriminatory, derogatory or demeaning speech or actions by any
-participant in our community online, at all related events and in
-one-on-one communications carried out in the context of community
-business. Community event venues may be shared with members of the public;
-please be respectful to all patrons of these locations.
-
-Examples of behaviors we do not accept in our community:
-
-* harmful or prejudicial verbal or written comments related to gender,
-  sexual orientation, race, religion, disability;
-* inappropriate physical contact, and unwelcome sexual advances;
-* deliberate intimidation, stalking or following;
-* harassing photography or recording;
-* sustained disruption of talks or other events.
-
-Using this code of conduct aggressively against other people in the
-community might also be harassment. Be considerate when enforcing the code
-of conduct and always try to listen to both sides before passing judgment.
-
-## Consequences of Unacceptable Behavior
-
-Unacceptable behavior from any community member, including sponsors and
-those with decision-making authority, will not be tolerated.
-
-Anyone asked to stop unacceptable behavior is expected to comply
-immediately.
-
-If a community member engages in unacceptable behavior, the community
-organizers may take any action they deem appropriate, up to and including
-a temporary ban or permanent expulsion from the community without warning
-(and without refund in the case of a paid event).
-
-Community organizers can be members of the arbitration team, or organizers
-of events and online communities.
-
-## Addressing Grievances
-
-If you feel you have been falsely or unfairly accused of violating this
-Code of Conduct, you should notify the arbitration team with a concise
-description of your grievance.
-
-## Legal action
-
-Threatening or starting legal action against the project, sibling
-projects hosted on coreboot.org infrastructure, project or infrastructure
-maintainers leads to an immediate ban from coreboot.org and related
-systems.
-
-The ban can be reconsidered, but it's the default action because the
-people who pour lots of time and money into the projects aren't interested
-in seeing their resources used against them.
-
-## Scope
-
-We expect all community participants (contributors, paid or otherwise;
-sponsors; and other guests) to abide by this Code of Conduct in all
-community venues, online and in-person, as well as in all one-on-one
-communications pertaining to community business.
-
-## Contact info
-
-Our arbitration team consists of the following people
-* Stefan Reinauer <stefan.reinauer@coreboot.org> (USA)
-* Patrick Georgi <patrick@coreboot.org> (Germany)
-* Ronald Minnich <rminnich@coreboot.org> (USA)
-* Martin Roth <martin@coreboot.org> (USA)
-
-## License and attribution
-
-This Code of Conduct is distributed under
-a [Creative Commons Attribution-ShareAlike
-license](http://creativecommons.org/licenses/by-sa/3.0/).  It is based
-on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofconduct.org/)
--- a/Documentation/community/conferences.md
+++ b/Documentation/community/conferences.md
@ -1,70 +0,0 @@
-# Conferences
-The coreboot community is present at a number of conferences over the year,
-usually at [FOSDEM](https://fosdem.org), [OSFC](https://osfc.io), and the
-[Chaos Communication Congress](https://events.ccc.de/congress/).
-
-The kind of presence differs, but there's usually a booth or other kind of
-gathering where everybody is welcome to say hello and to learn more about
-coreboot.
-
-Depending on the nature of the conference, coreboot developers might bring
-their development kit with them and conduct development sessions.
-
-## Talks
-
-[Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_facebook/)  by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebook.mp4)) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03)
-
-[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/congress/2018/wiki/index.php/Main_Page)
-([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27)
-
-[coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018
-
-[A tale of reusability in coreboot](https://www.youtube.com/watch?v=p2bnEYKBDpI) by Furquan Shaikh at OSFC 2018
-
-[How to enable AMD IOMMU in coreboot](https://www.youtube.com/watch?v=5JoEuh9qXx0) by Piotr Król at OSFC 2018
-
-[ARM Trusted Firmware for coreboot developers](https://www.youtube.com/watch?v=UC35q4OJg3k) by Julius Werner at OSFC 2018
-
-[Google Secure Microcontroller and Case Closed Debugging](https://www.youtube.com/watch?v=gC-lbMNmIsg) by Vadim Bendebury at OSFC 2018
-
-[coreboot rompayload](https://www.youtube.com/watch?v=ukSh1n7wjSA) by Ron Minnich at OSFC 2018
-
-[Run upstream coreboot on an ARM Chromebook](https://www.youtube.com/watch?v=N7_9okzPeHo) by Paul Menzel at ECC 2017
-
-[DDR3 memory initialization basics on Intel Sandybrige platforms](https://www.youtube.com/watch?v=h-Lkkg03Erk) by Patrick Rudolph at ECC 2017
-
-[Let's move SMM out of firmware and into the kernel](https://www.youtube.com/watch?v=6GEaw4msq6g) by Ron Minnich at ECC 2017
-
-[SINUMERIK – step ahead with coreboot](https://www.youtube.com/watch?v=tq4xSipCWEU) by Werner Zeh at ECC 2017
-
-[Booting UEFI-aware OS on coreboot enabled platform](https://www.youtube.com/watch?v=nt0BkqVUu3w) by Piotr Król and Kamil Wcisło at ECC 2017
-
-[Reverse engineering MT8173 PCM firmwares and ISA for a fully free bootchain](https://www.youtube.com/watch?v=9rKxfo7Gkqo) by Paul Kocialkowski at ECC 2017
-
-[A Tale of six motherboards, two BSDs and coreboot](https://www.youtube.com/watch?v=jlCGzML6zF8) by Piotr Kubaj at ECC 2017
-
-[Enabling TPM 2.0 on coreboot based devices](https://www.youtube.com/watch?v=Yjb9n5p3giI) by Piotr Król and Kamil Wcisło at ECC 2017
-
-[Porting coreboot to the HP ProLiant MicroServer Gen8](https://www.youtube.com/watch?v=BcmUSW2J53k) by Alexander Couzens and Felix Held at ECC 2017
-
-[Implementing coreboot in a ground breaking secure system: ORWL](https://www.youtube.com/watch?v=D4oQjcP6AVI) by Wim Vervoorn and Gerard Duynisveld at ECC 2017
-
-[Buying trustworthy hardware for federal agencies: How open source firmware saves the day](https://www.youtube.com/watch?v=DG_wfaw4zl0) by Carl-Daniel Hailfinger at ECC 2017
-
-[Verified Boot: Surviving in the Internet of Insecure Things: Randall Spangler](https://www.youtube.com/watch?v=4EvTcfcYfMY) by Randall Spangler at coreboot conference 2016
-
-[coreboot on RISC-V](https://www.youtube.com/watch?v=CDNIWuf1jAk) by Ron Minnich at coreboot conference 2016
-
-[An Open Source Embedded Controller](https://www.youtube.com/watch?v=hQb8waUBVSQ) by Bill Richardson at coreboot conference 2016
-
-[KB9012 EC Firmware Reverse Engineering](https://www.youtube.com/watch?v=B708jdCiW7o) by Paul Kocialkowski at coreboot conference 2016
-
-[coreboot on ARM](https://www.youtube.com/watch?v=z-KpAA4_afs) by Julius Werner at coreboot conference 2016
-
-[Intel FSP 2.0 overview](https://www.youtube.com/watch?v=uzfiTiP9dEM) by Giri Mudusuru and Vincent Zimmer at coreboot conference 2016
-
-[coreboot Internals](https://www.youtube.com/watch?v=7YUXr1MH9d4) by Aaron Durbin at coreboot conference 2016
-
-[Skylake FSP to coreboot integration overview](https://www.youtube.com/watch?v=SpL8LbquSVs) by Robbie Zhang at coreboot conference 2016
-
-[S3 implementation on Braswell](https://www.youtube.com/watch?v=GfwTijFnFl0) by Hannah Williams at coreboot conference 2016
--- a/Documentation/community/forums.md
+++ b/Documentation/community/forums.md
@ -1,39 +0,0 @@
-# Our forums
-
-The coreboot community has various venues to help each other and discuss the
-direction of our project.
-
-## Mailing list
-
-The first address for coreboot related discussion is our mailing list.
-You can subscribe on its
-[information page](https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org/) and
-read its
-[archives](https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/).
-
-## Real time chat
-
-We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
-also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a
-[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
-[OSF Slack](https://osfw.slack.com/), which has channels on many open source
-firmware related topics. Slack requires that people come from specific domains
-or are explicitly invited. To work around that, there's an
-[invite bot](https://slack.osfw.dev/) to let people in.
-
-## Fortnightly coreboot leadership meeting
-
-There's a leadership meeting held every 14 days (currently every other
-Wednesday at 10am Pacific Time, usually 18:00 UTC with some deviation
-possible due to daylight saving time related shifts). The meeting
-is open to everyone and provides a forum to discuss general coreboot
-topics, including community and technical matters that benefit from
-an official decision.
-
-We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
-using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
-for the agenda and meeting minutes. Neither the video conference nor
-the document require a Google account to participate, although editing
-access to the document is limited to adding comments - any desired
-agenda item added that way will be approved in time before the meeting.
--- a/Documentation/community/index.md
+++ b/Documentation/community/index.md
@ -1,6 +0,0 @@
-# Community
-
-* [Code of Conduct](code_of_conduct.md)
-* [Language style](language_style.md)
-* [Community forums](forums.md)
-* [coreboot at conferences](conferences.md)
--- a/Documentation/community/language_style.md
+++ b/Documentation/community/language_style.md
@ -1,136 +0,0 @@
-# Language style
-
-Following our [Code of Conduct](code_of_conduct.md) the project aims to
-be a space where people are considerate in natural language communication:
-
-There are terms in computing that were probably considered benign when
-introduced but are uncomfortable to some. The project aims to de-emphasize
-such terms in favor of alternatives that are at least as expressive -
-but often manage to be even more descriptive.
-
-## Political Correctness
-
-A common thread in discussions was that the project merely follows some
-fad, or that this is a "political correctness" measure, designed to please
-one particular "team". While the project doesn't exist in a vacuum and
-so there are outside influences on project members, the proposal wasn't
-made with the purpose of demonstrating allegiance to any given cause -
-except one:
-
-There are people who feel uncomfortable with some terms being used,
-_especially_ when that use takes them out of their grave context
-(e.g. slave when discussing slavery) and applies them to a rather benign
-topic (e.g. coordination of multiple technical systems), taking away
-the gravity of the term.
-
-That gets especially jarring when people aren't exposed to such terms
-in abstract sociological discussions but when they stand for real issues
-they encountered.
-
-When having to choose between using a well-established term that
-affects people negatively who could otherwise contribute more happily
-and undisturbed or an alternative just-as-good term that doesn't, the
-decision should be simple.
-
-## Token gesture
-
-The other major point of contention is that such decisions are a token
-gesture that doesn't change anything. It's true: No slave is freed
-because coreboot rejects the use of the word.
-
-coreboot is ambitious enough as-is, in that the project offers
-an alternative approach to firmware, sometimes against the vested
-interests (and deep pockets) of the leaders of a multi-billion dollar
-industry. Changing the preferred vocabulary isn't another attempt at
-changing the world, it's one thing we do to try to make coreboot (and
-coreboot only) a comfortable environment for everybody.
-
-## For everybody
-
-For everybody, but with a qualifier: We have certain community etiquette,
-and we define some behavior we don't accept in our community, both
-detailed in the Code of Conduct.
-
-Other than that, we're trying to accommodate people: The CoC lays out
-that language should be interpreted as friendly by default, and to be
-graceful in light of accidents. This also applies to the use of terms
-that the project tries to avoid: The consequence of the use of such
-terms (unless obviously employed to provoke a reaction - in that case,
-please contact the arbitration team as outlined in the Code of Conduct)
-should be a friendly reminder. The project is slow to sanction and that
-won't change just because the wrong kind of words is used.
-
-## Interfacing with the world
-
-The project doesn't exist in a vacuum, and that also applies to the choice
-of words made by other initiatives in low-level technology. When JEDEC
-calls the participants of a SPI transaction "master" and "slave", there's
-little we can do about that. We _could_ decide to use different terms,
-but that wouldn't make things easier but harder, because such a deliberate
-departure means that the original terms (and their original use) gain
-lots of visibility every time (so there's no practical advantage) while
-adding confusion, and therefore even more attention, to that situation.
-
-Sometimes there are abbreviations that can be used as substitutes,
-and in that case the recommendation is to do that.
-
-As terms that we found to be best avoided are replaced in such
-initiatives, we can follow up. Members of the community with leverage
-in such organizations are encouraged to raise the concern there.
-
-## Dealing with uses
-
-There are existing uses in our documentation and code. When we decide to
-retire a term that doesn't mean that everybody is supposed to stop doing
-whatever they're doing and spend their time on purging terms. Instead,
-ongoing development should look for alternatives (and so this could come
-up in review).
-
-People can go through existing code and docs and sort out older instances,
-and while that's encouraged it's no "stop the world" event. Changes
-in flight in review may still be merged with such terms intact, but if
-there's more work required for other reasons, we'd encourage moving away
-from such terms.
-
-This document has a section on retired terms, presenting the rationale
-as well as alternative terms that could be used instead. The main goal is
-to be expressive: There's no point in just picking any alternative term,
-choose something that explains the purpose well.
-
-As mentioned, missteps will happen. Point them out, but assume no ill
-intent for as long as you can manage.
-
-## Discussing words to remove from active use
-
-There ought to be some process when terminology is brought up as a
-negative to avoid. Do not to tell people that "they're feeling wrong"
-when they have a negative reaction to certain terms, but also try to
-avoid being offended for the sake of others.
-
-When bringing up a term, on the project's mailing list or, if you don't
-feel safe doing that, by contacting the arbitration team, explain what's
-wrong with the term and offer alternatives for uses within coreboot.
-
-With a term under discussion, see if there's particular value for us to
-continue using the term (maybe in limited situations, like continuing
-to use "slave" in SPI related code).
-
-Once the arbitration team considers the topic discussed completely and
-found a consensus, it will present a decision in a leadership meeting. It
-should explain why a term should or should not be used and in the latter
-case offer alternatives. These decisions shall then be added to this
-document.
-
-## Retired terminology
-
-### slave
-
-Replacing this term for something else had the highest approval rating
-in early discussions, so it seems pretty universally considered a bad
-choice and therefore should be avoided where possible.
-
-An exception is made where it's a term used in current standards and data
-sheets: Trying to "hide" the term in such cases only puts a spotlight
-on it every time code and data sheet are compared.
-
-Alternatives: subordinate, secondary, follower
--- a/Documentation/conf.py
+++ b/Documentation/conf.py
@ -1,18 +1,4 @@
 # -*- coding: utf-8 -*-
-import subprocess
-from recommonmark.parser import CommonMarkParser
-import sphinx
-
-# Get Sphinx version
-major = 0
-minor = 0
-patchlevel = 0
-version = sphinx.__version__.split(".")
-if len(version) > 1:
-	major = int(version[0])
-	minor = int(version[1])
-	if len(version) > 2:
-		patchlevel = int(version[2])

 # Add any paths that contain templates here, relative to this directory.
 templates_path = ['_templates']
@ -25,37 +11,24 @@ master_doc = 'index'

 # General information about the project.
 project = u'coreboot'
-copyright = u'CC-by 4.0 the coreboot project'
+copyright = u'the coreboot project'
 author = u'the coreboot project'

 # The version info for the project you're documenting, acts as replacement for
 # |version| and |release|, also used in various other places throughout the
 # built documents.
 #
-# The full version, including alpha/beta/rc tags.
-release = subprocess.check_output(('git', 'describe')).decode("utf-8")
 # The short X.Y version.
-version = release.split("-")[0]
-
-extensions = []
-# Load recommonmark, supported since 1.8+
-if major >= 2 or (major == 1 and minor >= 8):
-    extensions += ['recommonmark']
-
-# Try to load DITAA
-try:
-    import sphinxcontrib.ditaa
-except ImportError:
-    print("Error: Please install sphinxcontrib.ditaa for ASCII art conversion\n")
-else:
-    extensions += ['sphinxcontrib.ditaa']
+version = u'4.7'
+# The full version, including alpha/beta/rc tags.
+release = u'4.7' # TODO: use 'git describe'

 # The language for content autogenerated by Sphinx. Refer to documentation
 # for a list of supported languages.
 #
 # This is also used if you do content translation via gettext catalogs.
 # Usually you set "language" from the command line for these cases.
-language = 'en'
+language = None

 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
@ -87,9 +60,11 @@ html_theme = 'sphinx_rtd_theme'
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']

-html_css_files = [
-    'theme_overrides.css',  # override wide tables in RTD theme
-]
+html_context = {
+      'css_files': [
+        '_static/theme_overrides.css',  # override wide tables in RTD theme
+      ],
+}

 # Output file base name for HTML help builder.
 htmlhelp_basename = 'corebootdoc'
@ -144,7 +119,7 @@ latex_documents = [
 #
 # latex_appendices = []

-# If false, will not define \strong, \code,	itleref, \crossref ... but only
+# It false, will not define \strong, \code, 	itleref, \crossref ... but only
 # \sphinxstrong, ..., \sphinxtitleref, ... To help avoid clash with user added
 # packages.
 #
@ -180,14 +155,9 @@ texinfo_documents = [
     'Miscellaneous'),
 ]

-enable_auto_toc_tree = True
-
-class MyCommonMarkParser(CommonMarkParser):
-    # remove this hack once upstream RecommonMark supports inline code
-    def visit_code(self, mdnode):
-        from docutils import nodes
-        n = nodes.literal(mdnode.literal, mdnode.literal)
-        self.current_node.append(n)
+source_parsers = {
+    '.md': 'recommonmark.parser.CommonMarkParser',
+}

 # Documents to append as an appendix to all manuals.
 #
@ -205,16 +175,14 @@ class MyCommonMarkParser(CommonMarkParser):
 #
 # texinfo_no_detailmenu = False

+enable_auto_toc_tree = True
+

 def setup(app):
    from recommonmark.transform import AutoStructify
-    # Load recommonmark on old Sphinx
-    if major == 1 and minor < 8:
-        app.add_source_parser('.md', MyCommonMarkParser)
-
    app.add_config_value('recommonmark_config', {
        'enable_auto_toc_tree': True,
-        'enable_auto_doc_ref': False, # broken in Sphinx 1.6+
+        'enable_auto_doc_ref': True,
        'enable_eval_rst': True,
        'url_resolver': lambda url: '/' + url
    }, True)
--- a/Documentation/contributing/coding_style.md
+++ b/Documentation/contributing/coding_style.md
--- a/Documentation/contributing/documentation_ideas.md
+++ b/Documentation/contributing/documentation_ideas.md
@ -1,173 +0,0 @@
-# Documentation Ideas
-
-This section collects ideas to improve the coreboot documentation and
-should serve as a pool of ideas for people who want to improve the current
-documentation status of coreboot.
-
-The main purpose of this document is to gather documentation ideas for technical
-writers of the seasons of docs. Nevertheless anyone who wants to help improving
-the current documentation situation can take one of the projects.
-
-Each entry should outline what would be done, the benefit it brings
-to the project, the pre-requisites, both in knowledge and parts. They
-should also list people interested in supporting people who want to work
-on them.
-
-## Restructure Existing Documentation
-
-The goal is to improve the user experience and structure the documentation more
-logically. The current situation makes it very hard for beginners, but also for
-experienced developers to find anything in the coreboot documentation.
-
-One possible approach to restructure the documentation is to split it up such
-that we divide the group of users into:
-
-* (End-)users
-Most probably users which _just_ want to use coreboot as fast as possible. This
-section should include guidelines on how to build coreboot, how to flash coreboot
-and also which hardware is currently supported.
-
-* Developers
-This section should more focus on the developer side-of-view. This section would
-include how to get started developing coreboot, explaining the basic concepts of
-coreboot and also give guideance on how to proceed after the first steps.
-
-* Knowledge area
-This section is very tighlight coupled to the developer section and might be merged
-into it. The _Knowledge area_ can give a technical deep dive on various drivers,
-technologies, etc.
-
-* Community area
-This section gives some room for the community: Youtube channels, conferences,
-meetups, forums, chat, etc.
-
-A [first approach](https://review.coreboot.org/c/coreboot/+/40327) has already been made here and might be a basis for the work.
-Most of the documentation is already there, but scattered around the documentation
-folder.
-
-### Requirements
-* Understanding on how a different groups of users might use the documentation area
-* Basic understanding of how coreboot works (Can be worked out _on-the-fly_)
-
-### Mentors
-* christian.walter@9elements.com
-* TBD
-
-## Update Howto/Guides
-
-An important part to involve new people in the project, either as developer or
-as enduser, are guides and how-to's. There are already some guides which need
-to be updated to work, and could also be extended to multiple platforms, like
-Fedora or Arch-Linux. Also guidance for setting up coreboot with a Windows
-environment would be helpful.
-
-In addition, the vboot guidance needs an update/extensions, that the security
-features within coreboot can be used by non-technical people.
-
-For developers, how to debug coreboot and various debugging techniques need
-documentation.
-
-### Requirements
-* Knowledge of virtual machines, how to install different OSs and set up the
-  toolchain on different operating systems
-* Knowledge of debugging tools like gdb
-
-### Mentors
-* christian.walter@9elements.com
-* TBD
-
-## How to Support a New Board
-
-coreboot benefits from running on as many platforms as possible. Therefore we
-want to encourage new developers on porting existing hardware to coreboot.
-Guidance for those new developers need to be made such that they are able to
-take the first steps supporting new mainboards, when the SoC support already
-exists. There should be a 'how-to' guide for this. Also what are common problems
-and how to solve those.
-
-### Requirements
-* Knowledge of how to add support for a new mainboard in coreboot
-
-### Mentors
-* christian.walter@9elements.com
-* TBD
-
-## Payloads
-
-The current documentation of the payloads is not very effective. There should be
-more detailed documentation on the payloads that can be selected via the make
-menuconfig within coreboot. Also the use-cases should be described in more
-detail: When to use which payload? What are the benefits of using payload X over
-Y in a specific use-case ?
-
-In addition it should be made clear how additional functionality e.g. extend
-LinuxBoot with more commands, can be achieved.
-
-### Requirements
-* Basic knowledge of the supported payloads like SeaBIOS, TinanoCore, LinuxBoot,
-  GRUB, Linux, ...
-
-
-### Mentors
-* christian.walter@9elements.com
-* TBD
-
-
-## coreboot Util Documentation
-
-coreboot inherits a variaty of utilities. The current documentation only
-provides a "one-liner" as an explanation. The list of util should be updated
-with a more detailed explanation where possible. Also more "in-depths"
-explanations should be added with examples if possible.
-
-### Requirements
-* coreboot utilities
-
-### Mentors
-* christian.walter@9elements.com
-* TBD
-
-
-## CBMEM Developer Guide
-
-CBMEM is the API that provides memory buffers for the use at OS runtime. It's a
-core component and thus should be documented. Dos, don'ts and pitfalls when
-using CBMEM. This "in-depth" guide is clearly for developers.
-
-### Requirements
-* Deep understanding of coreboot's internals
-
-### Mentors
-* TBD
-* TBD
-
-
-## CBFS Developer Guide
-
-CBFS is the in-flash filesystem that is used by coreboot. It's a core component
-and thus should be documented. Update the existing CBFS.txt that still shows
-version 1 of the implementation. A [first approach](https://review.coreboot.org/c/coreboot/+/33663/2)
-has been made here.
-This "in-depth" guide is clearly for developers.
-
-### Requirements
-* Deep understanding of coreboot's internals
-
-### Mentors
-* TBD
-* TBD
-
-
-## Region API Developer Guide
-
-The region API is used by coreboot when dealing with memory mapped objects that
-can be split into chunks. It's a core component and thus should be documented.
-This "in-depth" guide is clearly for developers.
-
-### Requirements
-* Deep understanding of coreboot's internals
-
-### Mentors
-* TBD
-* TBD
-
--- a/Documentation/contributing/gerrit_guidelines.md
+++ b/Documentation/contributing/gerrit_guidelines.md
@ -1,440 +0,0 @@
-coreboot Gerrit Etiquette and Guidelines
-========================================
-
-The following rules are the requirements for behavior in the coreboot
-codebase in gerrit. These have mainly been unwritten rules up to this
-point, and should be familiar to most users who have been active in
-coreboot for a period of time. Following these rules will help reduce
-friction in the community.
-
-Note that as with many rules, there are exceptions. Some have been noted
-in the 'More Detail' section. If you feel there is an exception not listed
-here, please discuss it in the mailing list to get this document  updated.
-Don't just assume that it's okay, even if someone on IRC says it is.
-
-
-Summary
-------
-These are the expectations for committing, reviewing, and submitting code
-into coreboot git and gerrit. While breaking individual rules may not have
-immediate consequences, the coreboot leadership may act on repeated or
-flagrant violations with or without notice.
-
-* Don't violate the licenses.
-* Let non-trivial patches sit in a review state for at least 24 hours
-before submission.
-* Try to coordinate with platform maintainers when making changes to
-platforms.
-* If you give a patch a -2, you are responsible for giving concrete
-recommendations for what could be changed to resolve the issue the patch
-addresses.
-* Don't modify other people's patches without their consent.
-* Be respectful to others when commenting.
-* Don’t submit patches that you know will break other platforms.
-
-
-More detail
-----------
-* Don't violate the licenses. If you're submitting code that you didn't
-write yourself, make sure the license is compatible with the license of the
-project you're submitting the changes to. If you’re submitting code that
-you wrote that might be owned by your employer, make sure that your
-employer is aware and you are authorized to submit the code. For
-clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](#sign-off-procedure).
-
-* In general, patches should remain open for review for at least 24 hours
-since the last significant modification to the change. The purpose is to
-let coreboot developers around the world have a chance to review. Complex
-reworks, even if they don't change the purpose of the patch but the way
-it's implemented, should restart the wait period.
-
-* A change can go in without the wait period if its purpose is to fix
-a recently-introduced issue (build, boot or OS-level compatibility, not
-necessarily identified by coreboot.org facilities). Its commit message
-has to explain what change introduced the problem and the nature of
-the problem so that the emergency need becomes apparent. Avoid stating
-something like "fix build error" in the commit summary, describe what
-the commit does instead, just like any other commit. In addition, it is
-recommended to reference the commit that introduced the issue. The change
-itself should be as limited in scope and impact as possible to make it
-simple to assess the impact. Such a change can be merged early with 3
-Code-Review+2. For emergency fixes that affect a single project (SoC,
-mainboard, ...) it's _strongly_ recommended to get a review by somebody
-not involved with that project to ensure that the documentation of the
-issue is clear enough.
-
-* Trivial changes that deal with minor issues like inconsistencies in
-whitespace or spelling fixes that don't impact the final binary output
-also don't need to wait. Such changes should point out in their commit
-messages how the the author verified that the binary output is identical
-(e.g. a TIMELESS build for a given configuration). When submitting
-such changes early, the submitter must be different from the author
-and must document the intent in the Gerrit discussion, e.g. "landed the
-change early because it's trivial". Note that trivial fixes shouldn't
-necessarily be expedited: Just like they're not critical enough for
-things to go wrong because of them, they're not critical enough to
-require quick handling. This exception merely serves to acknowledge that
-a round-the-world review just isn't necessary for some types of changes.
-
-* As explained in our Code of Conduct, we try to assume the best of each
-other in this community. It's okay to discuss mistakes (e.g. isolated
-instances of non-trivial and non-critical changes submitted early) but
-try to keep such inquiries blameless. If a change leads to problems with
-our code, the focus should be on fixing the issue, not on assigning blame.
-
-* Do not +2 patches that you authored or own, even for something as trivial
-as whitespace fixes. When working on your own patches, it’s easy to
-overlook something like accidentally updating file permissions or git
-submodule commit IDs. Let someone else review the patch. An exception to
-this would be if two people worked in the patch together. If both +2 the
-patch, that is acceptable, as each is giving a +2 to the other's work.
-
-* Try to coordinate with platform maintainers and other significant
-contributors to the code when making changes to platforms. The platform
-maintainers are the users who initially pushed the code for that platform,
-as well as users who have made significant changes to a platform. To find
-out who maintains a piece of code, please use util/scripts/maintainers.go
-or refer to the original author of the code in git log.
-
-* If you give a patch a -2, you are responsible for giving concrete
-recommendations for what could be changed to resolve the issue the patch
-addresses. If you feel strongly that a patch should NEVER be merged, you
-are responsible for defending your position and listening to other points
-of view. Giving a -2 and walking away is not acceptable, and may cause your
- -2 to be removed by the coreboot leadership after no less than a week. A
- notification that the -2 will be removed unless there is a response will
- be sent out at least 2 days before it is removed.
-
-* Don't modify other people's patches unless you have coordinated this with
-the owner of that patch. Not only is this considered rude, but your changes
-could be unintentionally lost. An exception to this would be for patches
-that have not been updated for more than 90 days. In that case, the patch
-can be taken over if the original author does not respond to requests for
-updates. Alternatively, a new patch can be pushed with the original
-content, and both patches should be updated to reference the other.
-
-* Be respectful to others when commenting on patches. Comments should
-be kept to the code, and should be kept in a polite tone. We are a
-worldwide community and English is a difficult language. Assume your
-colleagues are intelligent and do not intend disrespect. Resist the urge to
-retaliate against perceived verbal misconduct, such behavior is not
-conducive to getting patches merged.
-
-* Don’t submit code that you know will break other platforms. If your patch
-affects code that is used by other platforms, it should be compatible with
-those platforms. While it would be nice to update any other platforms, you
-must at least provide a path that will allow other platforms to continue
-working.
-
-Sign-off Procedure
------------------
-The coreboot project employs a sign-off procedure similar to what is
-used by the Linux kernel. Each gerrit commit requires a sign-off line
-saying that the contributed code abides by the Developer's certificate
-of origin, below.
-```text
-Signed-off-by: Random J Developer <random@developer.example.org>
-```
-
-Using '-s' with 'git commit' will automatically add a Signed-off-by line
-to your commit message.  Patches without a Signed-off-by should not be
-pushed to gerrit, and will be rejected by coreboot's CI system.
-
-You must use a known identity in the Signed-off-by line. Anonymous
-contributions cannot be committed! This can be anything sufficient to
-identify and contact the source of a contribution, such as your name or
-an established alias/nickname. Refer to [this LKML thread] and the
-[SCO-Linux disputes] for the rationale behind the DCO.
-
-Developer's Certificate of Origin 1.1
-
-> By making a contribution to this project, I certify that:
->
-> (a) The contribution was created in whole or in part by me and I have
-> the right to submit it under the open source license indicated in the
-> file; or
->
-> (b) The contribution is based upon previous work that, to the best of
-> my knowledge, is covered under an appropriate open source license and
-> I have the right under that license to submit that work with
-> modifications, whether created in whole or in part by me, under the
-> same open source license (unless I am permitted to submit under a
-> different license), as indicated in the file; or
->
-> (c) The contribution was provided directly to me by some other person
-> who certified (a), (b) or (c) and I have not modified it; and
->
-> (d) In the case of each of (a), (b), or (c), I understand and agree
-> that this project and the contribution are public and that a record of
-> the contribution (including all personal information I submit with it,
-> including my sign-off) is maintained indefinitely and may be
-> redistributed consistent with this project or the open source license
-> indicated in the file.
-
-Note: The [Developer's Certificate of Origin 1.1] is licensed under the
-terms of the [Creative Commons Attribution-ShareAlike 2.5 License].
-
-
-Recommendations for gerrit activity
-----------------------------------
-These guidelines are less strict than the ones listed above. These are more
-of the “good idea” variety. You are requested to follow the below
-guidelines, but there will probably be no actual consequences if they’re
-not followed. That said, following the recommendations below will speed up
-review of your patches, and make the members of the community do less work.
-
-* Each patch should be kept to one logical change, which should be
-described in the title of the patch. Unrelated changes should be split out
-into separate patches. Fixing whitespace on a line you’re editing is
-reasonable. Fixing whitespace around the code you’re working on should be a
-separate ‘cleanup’ patch. Larger patches that touch several areas are fine,
-so long as they are one logical change. Adding new chips and doing code
-cleanup over wide areas are two examples of this.
-
-* Test your patches before submitting them to gerrit. It's also appreciated
-if you add a line to the commit message describing how the patch was
-tested. This prevents people from having to ask whether and how the patch
-was tested. Examples of this sort of comment would be ‘TEST=Built
-platform’ or ‘Tested by building and booting platform’.  Stating that the
-patch was not tested is also fine, although you might be asked to do some
-testing in cases where that would be reasonable.
-
-* Take advantage of the lint tools to make sure your patches don’t contain
-trivial mistakes. By running ‘make gitconfig’, the lint-stable tools are
-automatically put in place and will test your patches before they are
-committed. As a violation of these tools will cause the jenkins build test
-to fail, it’s to your advantage to test this before pushing to gerrit.
-
-* Don't submit patch trains longer than around 20 patches unless you
-understand how to manage long patch trains. Long patch trains can become
-difficult to handle and tie up the build servers for long periods of time
-if not managed well. Rebasing a patch train over and over as you fix
-earlier patches in the train can hide comments, and make people review the
-code multiple times to see if anything has changed between revisions. When
-pushing long patch trains, it is recommended to only push the full patch
-train once - the initial time, and only to rebase three or four patches at
-a time.
-
-* Run 'make what-jenkins-does' locally on patch trains before submitting.
-This helps verify that the patch train won’t tie up the jenkins builders
-for no reason if there are failing patches in the train. For running
-parallel builds, you can specify the number of cores to use by setting the
-the CPUS environment variable. Example:
-
-```Bash
-make what-jenkins-does CPUS=8
-```
-
-* Use a topic when pushing a train of patches. This groups the commits
-together so people can easily see the connection at the top level of
-gerrit. Topics can be set for individual patches in gerrit by going into
-the patch and clicking on the icon next to the topic line. Topics can also
-be set when you push the patches into gerrit. For example, to push a set of
-commits with the i915-kernel-x60 set, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%topic=i915-kernel-x60
-```
-
-* If one of your patches isn't ready to be merged, make sure it's obvious
-that you don't feel it's ready for merge yet. The preferred way to show
-this is by marking in the commit message that it’s not ready until X. The
-commit message can be updated easily when it’s ready to be pushed.
-Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
-mark the patch as not ready would be to give it a -1 or -2 review, but
-isn't as obvious as the commit message. These patches can also be pushed with
-the wip flag:
-
-```Bash
-git push origin HEAD:refs/for/master%wip
-```
-
-* When pushing patches that are not for submission, these should be marked
-as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
-private changes, so that only explicitly added reviewers will see them. These
-sorts of patches are frequently posted as ideas or RFCs for the community to
-look at. Note that private changes can still be fetched from Gerrit by anybody
-who knows their commit ID, so don't use this for sensitive changes. To push
-a private change, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%private
-```
-
-* Multiple push options can be combined:
-
-```Bash
-git push origin HEAD:refs/for/master%private,wip,topic=experiment
-```
-
-* Respond to anyone who has taken the time to review your patches, even if
-it's just to say that you disagree. While it may seem annoying to address a
-request to fix spelling or 'trivial' issues, it’s generally easy to handle
-in gerrit’s built-in editor. If you do use the built-in editor, remember to
-get that change to your local copy before re-pushing. It's also acceptable
-to add fixes for these sorts of comments to another patch, but it's
-recommended that that patch be pushed to gerrit before the initial patch
-gets submitted.
-
-* Consider breaking up large individual patches into smaller patches
-grouped by areas. This makes the patches easier to review, but increases
-the number of patches. The way you want to handle this is a personal
-decision, as long as each patch is still one logical change.
-
-* If you have an interest in a particular area or mainboard, set yourself
-up as a ‘maintainer’ of that area by adding yourself to the MAINTAINERS
-file in the coreboot root directory. Eventually, this should automatically
-add you as a reviewer when an area that you’re listed as a maintainer is
-changed.
-
-* Submit mainboards that you’re working on to the board-status repo. This
-helps others and shows that these mainboards are currently being
-maintained. At some point, boards that are not up to date in the
-board-status repo will probably end up getting removed from the coreboot
-master branch.
-
-* Abandon patches that are no longer useful, or that you don’t intend to
-keep working on to get submitted.
-
-* Bring attention to patches that you would like reviewed. Add reviewers,
-ask for reviewers on IRC or even just rebase it against the current
-codebase to bring it to the top of the gerrit list. If you’re not sure who
-would be a good reviewer, look in the MAINTAINERS file or git history of
-the files that you’ve changed, and add those people.
-
-* Familiarize yourself with the coreboot [commit message
-guidelines](https://www.coreboot.org/Git#Commit_messages), before pushing
-patches. This will help to keep annoying requests to fix your commit
-message to a minimum.
-
-* If there have been comments or discussion on a patch, verify that the
-comments have been addressed before giving a +2. If you feel that a comment
-is invalid, please respond to that comment instead of just ignoring it.
-
-* Be conscientious when reviewing patches. As a reviewer who approves (+2)
-a patch, you are responsible for the patch and the effect it has on the
-codebase. In the event that the patch breaks things, you are expected to
-be actively involved in the cleanup effort. This means you shouldn’t +2 a
-patch just because you trust the author of a patch - Make sure you
-understand what the implications of a patch might be, or leave the review
-to others. Partial reviews, reviewing code style, for example, can be given
-a +1 instead of a +2. This also applies if you think the patch looks good,
-but may not have the experience to know if there may be unintended
-consequences.
-
-* If there is still ongoing discussion to a patch, try to wait for a
-conclusion to the discussion before submitting it to the tree. If you feel
-that someone is just bikeshedding, maybe just state that and give a time
-that the patch will be submitted if no new objections are raised.
-
-* When working with patch trains, for minor requests it’s acceptable to
-create a fix addressing a comment in another patch at the end of the patch
-train. This minimizes rebases of the patch train while still addressing the
-request. For major problems where the change doesn’t work as intended or
-breaks other platforms, the change really needs to go into the original
-patch.
-
-* When bringing in a patch from another git repo, update the original
-git/gerrit tags by prepending the lines with 'Original-'.  Marking
-the original text this way makes it much easier to tell what changes
-happened in which repository. This applies to these lines, not the actual
-commit message itself:
-
-	* Commit-Id:
-	* Change-Id:
-	* Signed-off-by:
-	* Reviewed-on:
-	* Tested-by:
-	* Reviewed-by:
-
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
-Other tags such as 'Commit-Queue' can simply be removed.
-
-* Check if there's documentation that needs to be updated to remain current
-after your change. If there's no documentation for the part of coreboot
-you're working on, consider adding some.
-
-* When contributing a significant change to core parts of the code base (such
-as the boot state machine or the resource allocator), or when introducing
-a new way of doing something that you think is worthwhile to apply across
-the tree (e.g. board variants), please bring up your design on the [mailing
-list](../community/forums.md). When changing behavior substantially, an
-explanation of what changes and why may be useful to have, either in the
-commit message or, if the discussion of the subject matter needs way more
-space, in the documentation. Since "what we did in the past and why it isn't
-appropriate anymore" isn't the most useful reading several years down the road,
-such a description could be put into the release notes for the next version
-(that you can find in Documentation/releases/) where it will inform people
-now without cluttering up the regular documentation, and also gives a nice
-shout-out to your contribution by the next release.
-
-Expectations contributors should have
-------------------------------------
-* Don't expect that people will review your patch unless you ask them to.
-Adding other people as reviewers is the easiest way. Asking for reviews for
-individual patches in the IRC channel, or by sending a direct request to an
-individual through your favorite messenger is usually the best way to get a
-patch reviewed quickly.
-
-* Don't expect that your patch will be submitted immediately after getting
-a +2. As stated previously, non-trivial patches should wait at least 24
-hours before being submitted. That said, if you feel that your patch or
-series of patches has been sitting longer than needed, you can ask for it
-to be submitted on IRC, or comment that it's ready for submission in the
-patch. This will move it to the top of the list where it's more likely to
-be noticed and acted upon.
-
-* Reviews are about the code. It's easy to take it personally when someone
-is criticising your code, but the whole idea is to get better code into our
-codebase. Again, this also applies in the other direction: review code,
-criticize code, but don’t make it personal.
-
-Gerrit user roles
-----------------
-There are a few relevant roles a user can have on Gerrit:
-
- The anonymous user can check out source code.
- A registered user can also comment and give "+1" and "-1" code reviews.
- A reviewer can also give "+2" code reviews.
- A core developer can also give "-2" (that is, blocking) code reviews
-  and submit changes.
-
-Anybody can register an account on our instance, using either an
-OpenID provider or OAuth through GitHub or Google.
-
-The reviewer group is still quite open: Any core developer can add
-registered users to that group and should do so once some activity
-(commits, code reviews, and so on) has demonstrated rough knowledge
-of how we handle things.
-
-A core developer should be sufficiently well established in the
-community so that they feel comfortable when submitting good patches,
-when asking for improvements to less good patches and reasonably
-uncomfortable when -2'ing patches. They're typically the go-to
-person for _some_ part of the coreboot tree and ideally listed as its
-maintainer in our MAINTAINERS registry. To become part of this group,
-a candidate developer who already demonstrated proficiency with the
-code base as a reviewer should be nominated, by themselves or others,
-at the regular [coreboot leadership meetings](../community/forums.md)
-where a decision is made.
-
-Core developers are expected to use their privileges for the good of the
-project, which includes any of their own coreboot development but also beyond
-that. They should make sure that [ready changes] don't linger around needlessly
-just because their authors aren't well-connected with core developers but
-submit them if they went through review and generally look reasonable. They're
-also expected to help clean-up breakage as a result of their submissions.
-
-Since the project expects some activity by core developers, long-term absence
-(as in "years") can lead to removal from the group, which can easily be
-reversed after they come back.
-
-Requests for clarification and suggestions for updates to these guidelines
-should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
-
-[ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergeable+label:All-Comments-Resolved%253Dok+label:Code-Review%253D2+-label:Code-Review%253C0+label:Verified%253D1+-label:Verified-1
-[Developer's Certificate of Origin 1.1]: https://developercertificate.org/
-[Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/
-[this LKML thread]: https://lkml.org/lkml/2004/5/23/10
-[SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes
--- a/Documentation/contributing/gsoc.md
+++ b/Documentation/contributing/gsoc.md
@ -1,286 +0,0 @@
-# Google Summer of Code
-
-## Organization admins
-
-The *organization admins* are managing the GSoC program for the coreboot
-organization.
-
-The organization admins are:
-
-  * Felix Singer (primary)
-  * Martin Roth
-  * David Hendricks
-
-
-## Contacts
-
-If you are interested in participating in GSoC as a contributor or mentor,
-please have a look at our [community forums] and reach out to us. Working closely
-with the community is highly encouraged, as we've seen that our most successful
-contributors are generally very involved.
-
-
-## Why work on coreboot for GSoC?
-
-  * coreboot offers you the opportunity to work with various architectures
-    right on the iron. coreboot supports both current and older silicon for a
-    wide variety of chips and technologies.
-
-  * coreboot has a worldwide developer and user base.
-
-  * We are a very passionate team, so you will interact directly with the
-    project initiators and project leaders.
-
-  * We have a large, helpful community. coreboot has some extremely talented
-    and helpful experts in firmware involved in the project. They are ready to
-    assist and mentor contributors participating in GSoC.
-
-  * One of the last areas where open source software is not common is firmware.
-    Running proprietary firmware can have severe effects on user's freedom and
-    security. coreboot has a mission to change that by providing a common
-    framework for initial hardware initialization and you can help us succeed.
-
-
-## Collection of official GSoC guides & documents
-
-  * [Timeline][GSoC Timeline]
-
-  * [Roles and Responsibilities][GSoC Roles and Responsibilities]
-
-  * [Contributor Guide][GSoC Contributor Guide]
-
-  * [Contributor Advice][GSoC Contributor Advice]
-
-  * [Mentor Guide][GSoC Mentor Guide]
-
-  * [FAQ][GSoC FAQ]
-
-  * [Rules][GSoC Rules]
-
-  * [Glossary][GSoC Glossary]
-
-  * [Organization Admin Tips][GSoC Organization Admin Tips]
-
-
-## Contributor requirements & commitments
-
-Google Summer of Code is a significant time commitment for you. Medium-sized
-projects are estimated to take 175 hours, while large-sized projects are
-estimated to take 350 hours. Depending on the project size, this means we
-expect you to work roughly half-time or full-time on your project during the
-three months of coding. We expect to be able to see this level of effort in the
-results.
-
-The standard program duration is 12 weeks and in consultation with the mentor
-it can be extended up to 22 weeks. Please keep in mind that the actual number
-of hours you spend on the project highly depends on your skills and previous
-experience.
-
-Make sure that your schedule (exams, courses, day job) gives you a sufficient
-amount of spare time. If this is not the case, then you should not apply.
-
-
-### Before applying
-
-  * Join the [mailing list] and our other [community forums]. Introduce yourself
-    and mention that you are a prospective GSoC contributor. Ask questions and
-    discuss the project that you are considering. Community involvement is a
-    key component of coreboot development.
-
-  * You accept our [Code of Conduct] and [Language style].
-
-  * Demonstrate that you can work with the coreboot codebase.
-
-    * Look over some of the development processes guidelines: [Getting started],
-      [Tutorial], [Flashing firmware tutorial] and [Coding style].
-
-    * Download, build and boot coreboot in QEMU or on real hardware. Please email
-      your serial output results to the [mailing list].
-
-    * Look through some patches on Gerrit to get an understanding of the review
-      process and common issues.
-
-    * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [small project list][Project ideas] or ask for simple tasks on
-      the [mailing list] or on our other [community forums] if you need ideas.
-
-
-### During the program
-
-  * To pass and to be paid by Google requires that you meet certain milestones.
-
-    * First, you must be in good standing with the community before the official
-      start of the program. We expect you to post some design emails to the
-      [mailing list], and get feedback on them, both before applying, and during
-      the "community bonding period" between acceptance and official start.
-
-    * You must have made progress and committed significant code before the
-      mid-term point and by the final.
-
-    * We require that accepted contributors to maintain a blog, where you are
-      expected to write about your project *WEEKLY*. This is a way to measure
-      progress and for the community at large to be able to help you. GSoC is
-      *NOT* a private contract between your mentor and you.
-
-  * You must be active in the community on IRC and the [mailing list].
-
-  * You are expected to work on development publicly, and to push commits to the
-    project on a regular basis. Depending on the project and what your mentor
-    agrees to, these can be published directly to the project or to a public
-    repository such as Gitlab or Github. If you are not publishing directly to
-    the project codebase, be aware that we do not want large dumps of code that
-    need to be rushed to meet the mid-term and final goals.
-
-We don't expect our contributors to be experts in our problem domain, but we
-don't want you to fail because some basic misunderstanding was in your way of
-completing the task.
-
-
-## Projects
-
-There are many development tasks available in coreboot. We prepared some ideas
-for Summer of Code projects. These are projects that we think can be managed in
-the timeline of GSoC, and they cover areas where coreboot is trying to reach
-new users and new use cases.
-
-Of course your application does not have to be based on any of the ideas listed.
-It is entirely possible that you have a great idea that we just didn't think of
-yet. Please let us know!
-
-The blog posts related to previous GSoC projects might give some insights to
-what it is like to be a coreboot GSoC contributor.
-
-
-## coreboot Summer of Code Application
-
-coreboot welcomes contributors from all backgrounds and levels of experience.
-
-Your application should include a complete project proposal. You should
-document that you have the knowledge and the ability to complete your proposed
-project. This may require a little research and understanding of coreboot prior
-to sending your application. The community and coreboot project mentors are your
-best resource in fleshing out your project ideas and helping with a project
-timeline. We recommend that you get feedback and recommendations on your
-proposal before the application deadline.
-
-Please complete the standard GSoC application and project proposal. Provide the
-following information as part of your application. Make sure to provide multiple
-ways of communicating in case your equipment (such as a laptop) is lost,
-damaged, or stolen, or in case of a natural disaster that disrupts internet
-service. You risk automatically failing if your mentor cannot contact you and if
-you cannot provide updates according to GSoC deadlines.
-
-**Personal Information**
-
-  * Name
-
-  * Email and contact options (IRC, Matrix, …)
-
-  * Phone number (optional, but recommended)
-
-  * Timezone, Usual working hours (UTC)
-
-  * School / University, Degree Program, expected graduation date
-
-  * Short bio / Overview of your background
-
-  * What are your other time commitments? Do you have a job, classes, vacations?
-    When and how long?
-
-**Software experience**
-
-If applicable, please provide the following information:
-
-  * Portfolio, Website, blog, microblog, Github, Gitlab, ...
-
-  * Links to one or more patches submitted
-
-  * Links to posts on the [mailing list] with the serial output of your build.
-
-  * Please comment on your software and firmware experience.
-
-  * Have you contributed to an open source project? Which one? What was your
-    experience?
-
-  * What was your experience while building and running coreboot? Did you have
-    problems?
-
-**Your project**
-
-  * Provide an overview of your project (in your own words).
-
-  * Provide a breakdown of your project in small specific weekly goals. Think
-    about the potential timeline.
-
-  * How will you accomplish this goal? What is your working style?
-
-  * Explain what risks or potential problems your project might experience.
-
-  * What would you expect as a minimum level of success?
-
-  * Do you have a stretch goal?
-
-**Other**
-
-  * Resume (optional)
-
-
-### Advice on how to apply
-
-  * [GSoC Contributor Guide]
-
-  * The Drupal project has a great page on how to write an GSoC application.
-
-  * Secrets for GSoC success: [2]
-
-
-## Mentors
-
-Each accepted project will have at least one mentor. We will match mentors and
-contributors based on the project and experience level. If possible, we also
-will try to match their time zones.
-
-Mentors are expected to stay in frequent contact with the contributor and
-provide guidance such as code reviews, pointers to useful documentation, etc.
-This should generally be a time commitment of several hours per week.
-
-Some projects might have more than one mentor, who can serve as a backup. They
-are expected to coordinate with each other and a contributor on a regular basis,
-and keep track of the contributor process. They should be able to take over
-mentoring duty if one of the mentors is unavailable (vacations, sickness,
-emergencies).
-
-
-### Volunteering to be a mentor
-
-If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide].
-This will give you a better idea of expectations, and where to go for help.
-After that, contact Org Admins (see coreboot contacts section above).
-
-The following coreboot developers have volunteered to be GSoC 2022 mentors.
-Please stop by in our community forums and say hi to them and ask them
-questions.
-
-  * Tim Wawrzynczak
-  * Raul Rangel
-  * Ron Minnich
-
-
-[community forums]: ../community/forums.md
-[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
-[Getting started]: ../getting_started/index.md
-[Tutorial]: ../tutorial/index.md
-[Flashing firmware tutorial]: ../tutorial/flashing_firmware/index.md
-[Coding style]: coding_style.md
-[Code of Conduct]: ../community/code_of_conduct.md
-[Language style]: ../community/language_style.md
-[Project ideas]: project_ideas.md
-[GSoC Timeline]: https://developers.google.com/open-source/gsoc/timeline
-[GSoC Roles and Responsibilities]: https://developers.google.com/open-source/gsoc/help/responsibilities
-[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
-[GSoC Contributor Advice]: https://developers.google.com/open-source/gsoc/help/student-advice
-[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor
-[GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
-[GSoC Rules]: https://summerofcode.withgoogle.com/rules
-[GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
-[GSoC Organization Admin Tips]: https://developers.google.com/open-source/gsoc/help/oa-tips
--- a/Documentation/contributing/index.md
+++ b/Documentation/contributing/index.md
@ -1,7 +0,0 @@
-# Contributing
-
-* [Coding Style](coding_style.md)
-* [Gerrit Guidelines](gerrit_guidelines.md)
-* [Project Ideas](project_ideas.md)
-* [Documentation Ideas](documentation_ideas.md)
-* [Google Summer of Code](gsoc.md)
--- a/Documentation/contributing/project_ideas.md
+++ b/Documentation/contributing/project_ideas.md
@ -1,246 +0,0 @@
-# Project Ideas
-
-This section collects ideas to improve coreboot and related projects and
-should serve as a pool of ideas for people who want to enter the field
-of firmware development but need some guidance what to work on.
-
-These tasks can be adopted as part of programs like Google Summer of
-Code or by motivated individuals outside such programs.
-
-Each entry should outline what would be done, the benefit it brings
-to the project, the pre-requisites, both in knowledge and parts. They
-should also list people interested in supporting people who want to work
-on them - since we started building this list for Google Summer of Code,
-we'll adopt its term for those people and call them mentors.
-
-The requirements for each project aim for productive work on the project,
-but it's always possible to learn them "on the job". If you have any
-doubt if you can bring yourself up to speed in a required time frame
-(e.g. for GSoC), feel free to ask in the community or the mentors listed
-with the projects. We can then try together to figure out if you're a
-good match for a project, even when requirements might not all be met.
-
-## Small projects
-
-This is a collection of tasks which don't require deep knowledge on
-coreboot itself. If you are a beginner and want to get familiar with the
-the project and the code base, or if you just want to get your hands
-dirty with some small tasks, then these are for you.
-
-  * Resolve static analysis issues reported by [scan-build] and
-    [Coverity scan]. More details on the page for
-    [Coverity scan integration].
-
-  * Resolve issues reported by the [linter][Linter issues]
-
-[scan-build]: https://coreboot.org/scan-build/
-[Coverity scan]: https://scan.coverity.com/projects/coreboot
-[Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
-
-## Provide toolchain binaries
-Our crossgcc subproject provides a uniform compiler environment for
-working on coreboot and related projects. Sadly, building it takes hours,
-which is a bad experience when trying to build coreboot the first time.
-
-Provide packages/installers of our compiler toolchain for Linux distros,
-Windows, Mac OS. For Windows, this should also include the environment
-(shell, make, ...). A student doesn't have to cover _all_ platforms, but
-pick a set of systems that match their interest and knowledge and lay
-out a plan on how to do this.
-
-The scripts to generate these packages should be usable on a Linux
-host, as that's what we're using for our automated build testing system
-that we could extend to provide current packages going forward. This
-might include automating some virtualization system (eg. QEMU or CrosVM) for
-non-Linux builds or Docker for different Linux distributions.
-
-### Requirements
-* coreboot knowledge: Should know how to build coreboot images and where
-  the compiler comes into play in our build system.
-* other knowledge: Should know how packages or installers for their
-  target OS work. Knowledge of the GCC build system is a big plus
-* hardware requirements: Nothing special
-
-### Mentors
-
-## Support Power9/Power8 in coreboot
-There are some basic PPC64 stubs in coreboot, and there's open hardware
-in TALOS2 and its family. While they already have fully open source
-firmware, coreboot support adds a unified story for minimal firmware
-across architectures.
-
-### Requirements
-* coreboot knowledge: Should be familiar with making chipset level
-  changes to the code.
-* other knowledge: A general idea of the Power architecture, the more,
-  the better
-* hardware requirements: QEMU Power bring-up exists, and even if it
-  probably needs to be fixed up, that shouldn't be an exceedingly large
-  task. For everything else, access to real Power8/9 hardware and recovery
-  tools (e.g. for external flashing) is required.
-
-### Mentors
-* Timothy Pearson <tpearson@raptorengineering.com>
-
-## Port payloads to ARM, AArch64 or RISC-V
-While we have a rather big set of payloads for x86 based platforms, all other
-architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
-FILO, or Linux-as-Payload.
-
-Since this is a bit of a catch-all idea, an application to GSoC should pick a
-combination of payload and architecture to support.
-
-### Requirements
-* coreboot knowledge: Should know the general boot flow in coreboot
-* other knowledge: It helps to be familiar with the architecture you want to
-  work on.
-* hardware requirements: Much of this can be done in QEMU or other emulators,
-  but the ability to test on real hardware is a plus.
-
-### Mentors
-* Simon Glass <sjg@chromium.org> for U-Boot payload projects
-
-## Fully support building coreboot with the Clang compiler
-Most coreboot code is written in C, and it would be useful to support
-a second compiler suite in addition to gcc. Clang is another popular
-compiler suite and the build system generally supports building coreboot
-with it, but firmware is a rather special situation and we need to
-adjust coreboot and Clang some more to get usable binaries out of that
-combination.
-
-The goal would be to get the emulation targets to boot reliably first,
-but also to support real hardware. If you don't have hardware around,
-you likely will find willing testers for devices they own and work from
-their bug reports.
-
-### Requirements
-* coreboot knowledge: Have a general concept of the build system
-* Clang knowledge: It may be necessary to apply minor modifications to Clang
-  itself, but at least there will be Clang-specific compiler options etc to
-  adapt, so some idea how compilers work and how to modify their behavior is
-  helpful.
-* hardware requirements: If you have your own hardware that is already
-  supported by coreboot that can be a good test target, but you will debug
-  other people's hardware, too.
-* debugging experience: It helps if you know how to get the most out of a bug
-  report, generate theories, build patches to test them and figure out what's
-  going on from the resulting logs.
-
-### Mentors
-
-## Extend Ghidra to support analysis of firmware images
-[Ghidra](https://ghidra-sre.org) is a recently released cross-platform
-disassembler and decompiler that is extensible through plugins. Make it
-useful for firmware related work: Automatically parse formats (eg. by
-integrating UEFITool, cbfstool, decompressors), automatically identify
-16/32/64bit code on x86/amd64, etc.
-
-This has been done in 2019 with [some neat
-features](https://github.com/al3xtjames/ghidra-firmware-utils) being
-developed, but it may be possible to expand support for all kinds of firmware
-analyses.
-
-## Learn hardware behavior from I/O and memory access logs
-[SerialICE](https://www.serialice.com) is a tool to trace the behavior of
-executable code like firmware images. One result of that is a long log file
-containing the accesses to hardware resources.
-
-It would be useful to have a tool that assists a developer-analyst in deriving
-knowledge about hardware from such logs. This likely can't be entirely
-automatic, but a tool that finds patterns and can propagate them across the
-log (incrementially raising the log from plain I/O accesses to a high-level
-description of driver behavior) would be of great use.
-
-This is a research-heavy project.
-
-### Requirements
-* Driver knowledge: Somebody working on this should be familiar with
-  how hardware works (eg. MMIO based register access, index/data port
-  accesses) and how to read data sheets.
-* Machine Learning: ML techniques may be useful to find structure in traces.
-
-### Mentors
-* Ron Minnich <rminnich@google.com>
-
-## Libpayload based memtest payload
-[Memtest86+](https://www.memtest.org/) has some limitations: first and
-foremost it only works on x86, while it can print to serial console the
-GUI only works in legacy VGA mode.
-
-This project would involve porting the memtest suite to libpayload and
-build a payload around it.
-
-### Requirements
-* coreboot knowledge: Should know how to build coreboot images and
-  include payloads.
-* other knowledge: Knowledge on how dram works is a plus.
-* hardware requirements: Initial work can happen on qemu targets,
-  being able to test on coreboot supported hardware is a plus.
-
-### Mentors
-* TODO
-
-## Fix POST code handling
-coreboot supports writing POST codes to I/O port 80.
-There are various Kconfigs that deal with POST codes, which don't have
-effect on most platforms.
-The code to send POST codes is scattered in C and Assembly, some use
-functions, some use macros and others simply use the `outb` instruction.
-The POST codes are duplicated between stages and aren't documented properly.
-
-
-Tasks:
-* Guard Kconfigs with a *depends on* to only show on supported platforms
-* Remove duplicated Kconfigs
-* Replace `outb(0x80, ...)` with calls to `post_code(...)`
-* Update Documentation/POSTCODES
-* Use defines from console/post_codes.h where possible
-* Drop duplicated POST codes
-* Make use of all possible 255 values
-
-### Requirements
-* knowledge in the coreboot build system and the concept of stages
-* other knowledge: Little experience with C and x86 Assembly
-* hardware requirements: Nothing special
-
-### Mentors
-* Patrick Rudolph <patrick.rudolph@9elements.com>
-* Christian Walter <christian.walter@9elements.com>
-
-## Board status replacement
-The [Board status page](https://coreboot.org/status/board-status.html) allows
-to see last working commit of a board. The page is generated by a cron job
-that runs on a huge git repository.
-
-Build an open source replacement written in Golang using existing tools
-and libraries, consisting of a backend, a frontend and client side
-scripts. The backend should connect to an SQL database with can be
-controlled using a RESTful API. The RESTful API should have basic authentication
-for management tasks and new board status uploads.
-
-At least one older test result should be kept in the database.
-
-The frontend should use established UI libraries or frameworks (for example
-Angular) to display the current board status, that is if it's working or not
-and some details provided with the last test. If a board isn't working the last
-working commit (if any) should be shown in addition to the broken one.
-
-Provide a script/tool that allows to:
-1. Push mainboard details from coreboot master CI
-2. Push mainboard test results from authenticated users containing
-   * working
-   * commit hash
-   * bootlog (if any)
-   * dmesg (if it's booting)
-   * timestamps (if it's booting)
-   * coreboot config
-
-### Requirements
-* coreboot knowledge: Non-technical, needed to perform requirements analysis
-* software knowledge: Golang, SQL for the backend, JS for the frontend
-
-### Mentors
-* Patrick Rudolph <patrick.rudolph@9elements.com>
-* Christian Walter <christian.walter@9elements.com>
--- a/Documentation/core/Kconfig.md
+++ b/Documentation/core/Kconfig.md
--- a/Documentation/coreboot_logo.bmp
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--- a/Documentation/distributions.md
+++ b/Documentation/distributions.md
@ -1,109 +0,0 @@
-# Distributions
-
-coreboot doesn't provide binaries but provides a toolbox that others can use
-to build boot firmware for all kinds of purposes. These third-parties can be
-broadly separated in two groups: Those shipping coreboot on their hardware,
-and those providing after-market firmware to extend the usefulness of devices.
-
-
-## Hardware shipping with coreboot
-
-### NovaCustom laptops
-
-[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
-[Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
-[3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
-Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
-and the firmware is equipped with important security features such as measured
-boot, verified boot, TPM integration and UEFI Secure Boot.
-
-### ChromeOS Devices
-
-All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
-Chromebit, etc) released from 2012 onward use coreboot for their main system
-firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
-running on the Embedded Controller (EC) – a small microcontroller which provides
-functions like battery management, keyboard support, and sensor interfacing –
-is open source as well.
-
-### PC Engines APUs
-
-[PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that
-ships with coreboot and support upstream maintenance for the devices through a
-third party, [3mdeb](https://3mdeb.com). They provide current and tested
-firmware binaries on [GitHub](https://pcengines.github.io).
-
-### Star Labs
-
-[Star Labs](https://starlabs.systems/) offers a range of laptops designed and
-built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
-
-### System76
-
-[System76](https://system76.com/) manufactures Linux laptops, desktops, and
-servers. Some models are sold with [System76 Open
-Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
-
-### Purism
-
-[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
-security; part of that effort is to minimize the amount of proprietary and/or
-binary code. Their laptops ship with a blob-free OS and coreboot firmware
-with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
-
-## After-market firmware
-
-### Libreboot
-
-[Libreboot](https://libreboot.org) is a downstream coreboot distribution that
-provides ready-made firmware images for supported devices: those which can be
-built entirely from source code. Their copy of the coreboot repository is
-therefore stripped of all devices that require binary components to boot.
-
-
-### Dasharo
-
-[Dasharo](https://dasharo.com/) is an open-source based firmware distribution
-focusing on clean and simple code, long-term maintenance, transparent
-validation, privacy-respecting implementation, liberty for the owners, and
-trustworthiness for all.
-
-Contributions are welcome,
-[this document](https://docs.dasharo.com/ways-you-can-help-us/).
-
-### MrChromebox
-
-[MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
-images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
-coreboot with coreboot? Mr Chromebox's images are built using upstream
-coreboot (vs Google's older, static tree/branch), include many features and
-fixes not found in the stock firmware, and offer much broader OS compatibility
-(i.e., they run Windows as well as Linux). They also offer updated CPU
-microcode, as well as firmware updates for the device's embedded controller
-(EC). This firmware "takes the training wheels off" your ChromeOS device :)
-
-### Heads
-
-[Heads](http://osresearch.net) is an open source custom firmware and OS
-configuration for laptops and servers that aims to provide slightly better
-physical security and protection for data on the system. Unlike
-[Tails](https://tails.boum.org/), which aims to be a stateless OS that leaves
-no trace on the computer of its presence, Heads is intended for the case where
-you need to store data and state on the computer.
-
-Heads is not just another Linux distribution – it combines physical hardening
-of specific hardware platforms and flash security features with custom coreboot
-firmware and a Linux boot loader in ROM.
-
-### Skulls
-
-[Skulls](https://github.com/merge/skulls) provides firmware images for
-laptops like the Lenovo Thinkpad X230. It uses upstream coreboot, an easy
-to use payload like SeaBIOS and Intel's latest microcode update.
-
-It simplifies installation and includes compact documentation. Skulls also
-enables easy switching to [Heads](#heads) and back.
--- a/Documentation/documentation_license.md
+++ b/Documentation/documentation_license.md
@ -1,164 +0,0 @@
-# coreboot documentation license
-
-Files under Documentation/ are licensed under CC-BY 4.0 terms, printed below.
-As an exception, files under Documentation/ with a history older than 2017-05-24
-might be under different licenses (but should be cleared up ASAP).
-
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-### Section 3 – License Conditions.
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-   4. If You Share Adapted Material You produce, the Adapter's License You apply must not prevent recipients of the Adapted Material from complying with this Public License.
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-### Section 4 – Sui Generis Database Rights.
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-
--- a/Documentation/doxygen/Doxyfile.coreboot_platform
+++ b/Documentation/doxygen/Doxyfile.coreboot_platform
@ -0,0 +1,319 @@
+# Doxyfile 1.8.11
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
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+PROJECT_NUMBER         =
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+EXTENSION_MAPPING      =
+MARKDOWN_SUPPORT       = YES
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+CPP_CLI_SUPPORT        = NO
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+IDL_PROPERTY_SUPPORT   = YES
+DISTRIBUTE_GROUP_DOC   = NO
+GROUP_NESTED_COMPOUNDS = NO
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+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS  = NO
+TYPEDEF_HIDES_STRUCT   = NO
+LOOKUP_CACHE_SIZE      = 0
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = NO
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+EXTRACT_STATIC         = YES
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+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
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+WARN_NO_PARAMDOC       = YES
+WARN_AS_ERROR          = NO
+WARN_FORMAT            = "$file:$line: $text"
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+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
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+FILTER_SOURCE_PATTERNS =
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+#---------------------------------------------------------------------------
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+#---------------------------------------------------------------------------
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+#---------------------------------------------------------------------------
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+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
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+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
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+GENERATE_XML           = NO
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+# Configuration options related to the DOCBOOK output
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+DOCBOOK_OUTPUT         = docbook
+DOCBOOK_PROGRAMLISTING = NO
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
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+SKIP_FUNCTION_MACROS   = YES
+#---------------------------------------------------------------------------
+# Configuration options related to external references
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+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
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+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = YES
+CALLER_GRAPH           = YES
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+INTERACTIVE_SVG        = NO
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DIAFILE_DIRS           =
+PLANTUML_JAR_PATH      =
+PLANTUML_INCLUDE_PATH  =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = YES
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES
--- a/Documentation/drivers/cbfs_smbios.md
+++ b/Documentation/drivers/cbfs_smbios.md
@ -1,143 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS Serial Number
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information and type 2 Baseboard Information called Serial Number. It
-is a null-terminated string field assumed to be unique per platform. Certain
-mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
-data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
-provide an option to populate the Serial Numbers from CBFS for boards that
-can't generate the it from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `Serial number in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the serial number:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
-```
-
-Where `serial_file.txt` is the unterminated string representation of the SMBIOS
-type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
-partitions you will have to specify the RW regions where the file is going to
-be added too. By default the RW CBFS partitions are truncated, so the files
-would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the Serial Number from running system (if it exists) using one
-of the following commands:
-
-```shell
-# Type 1
-echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
-# OR Type 2
-echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
-```
-
-Ensure the file does not end with whitespaces like LF and/or CR. The above
-commands will not add any whitespaces. The driver automatically terminates the
-Serial Number with the NULL character. If the CBFS file is not present, the
-driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
-option.
-
-Please note that this driver provides `smbios_mainboard_serial_number` hook
-overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
-build option. If you wish to populate only type 2 Serial Number field your
-board code needs to implement `smbios_system_serial_number`, otherwise the weak
-implementation of `smbios_system_serial_number` will call
-`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
-implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
-has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
-if the board does not implement its own `smbios_system_serial_number`.
-
-There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
-populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
-implementation (returns empty string). If you wish to populate type 3 Serial
-Number, your board code should override the default
-`smbios_chassis_serial_number` weak implementation.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt
--- a/Documentation/drivers/dptf.md
+++ b/Documentation/drivers/dptf.md
@ -1,329 +0,0 @@
-# Intel DPTF implementations in coreboot
-
-## Introduction
-
-Intel Dynamic Platform and Thermal Framework is a framework that can be used to
-help regulate the thermal properties (i.e., temperature) of an Intel-based
-computer. It does this by allowing the system designer to specify the different
-components that can generate heat, and/or dissipate heat. Under DPTF, the
-different components are referred to as `participants`. The different types of
-functionality available in DPTF are specified in terms of different `policies`.
-
-## Components ("Participants")
-
-The participants that can be involved in the current implementation are:
- CPU (monolithic from a DPTF point-of-view)
-  - Note that the CPU's internal temperature sensor is used here
- 1 fan
- Up to 4 temperature sensors (TSRs)
- Battery charger
-
-## Policies
-
-In the current implementation, there are 3 different policies available:
-
-### Passive Policy
-
-The purpose of this policy is to monitor participant temperatures and is capable
-of controlling performance and throttling available on platform devices in order
-to regulate the temperatures of each participant. The temperature threshold
-points are defined by a `_PSV` ACPI object within each participant.
-
-### Critical Policy
-
-The Critical Policy is used for gracefully suspending or powering off the system
-when the temperature of participants exceeds critical threshold
-temperatures. Suspend is effected by specifying temperatures in a `_CRT` object
-for a participant, and poweroff is effected by specifying a temperature
-threshold in a `_HOT` ACPI object.
-
-### Active Policy
-
-This policy monitors the temperature of participants and controls fans to spin
-at varying speeds. These speeds are defined by the platform, and will be enabled
-depending on the various temperatures reported by participants.
-
-## Note about units
-
-ACPI uses unusual units for specifying various physical measurements. For
-example, temperatures are specified in 10ths of a degree K, and time is measured
-in tenths of a second. Those oddities are abstracted away in the DPTF library,
-by using degrees C for temperature, milliseconds for time, mW for power, and mA
-for current.
-
-## Differences from the static ASL files (soc/intel/common/acpi/dptf/*.asl)
-
-1) TCPU had many redundant methods. The many references to \_SB.CP00._* are not
-created anymore in recent SoCs and the ACPI spec says these are optional objects
-anyway. The defaults that were returned by these methods were redundant (all
-data was a 0). The following Methods were removed:
-
-* _TSS
-* _TPC
-* _PTC
-* _TSD
-* _TDL
-* _PSS
-* _PDL
-
-2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
-   specified in the devicetree entries or by calling the DPTF acpigen API).
-
-## ACPI Tables
-
-DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
-application. We will discuss the more important ones here.
-
-1) _TRT - Thermal Relationship Table
-
-This table is used when the Passive Policy is enabled, and is used to represent
-the thermal relationships in the system that can be controlled passively (i.e.,
-by throttling participants). A passive policy is defined by a Source (which
-generates heat), a Target (typically a temperature sensor), a Sampling Period
-(how often to check the temperature), an activation temperature threshold (for
-when to begin throttling), and a relative priority.
-
-2) _ART - Active Relationship Table
-
-This table is used when the Active Policy is enabled, and is used to represent
-active cooling relationships (i.e., which TSRs the fan can cool). An active
-policy contains a Target (the device the fan can cool), a Weight to control
-which participant needs more attention than others, and a list of temperature /
-fan percentage pairs. The list of pairs defines the fan control percentage that
-should be applied when the TSR reaches each successive threshold (_AC0 is the
-highest threshold, and represents the highest fan control percentage).
-
-3) PPCC - Participant Power Control Capabilities
-
-This table is used to describe parameters for controlling the SoC's Running
-Average Power Limits (RAPL, see below).
-
-4) _FPS - Fan Performance States
-
-This table describes the various fan speeds available for DPTF to use, along with
-various informational properties.
-
-5) PPSS - Participant Performance Supported States
-
-This table describes performance states supported by a participant (typically
-the battery charger).
-
-## ACPI Methods
-
-The Active and Passive policies also provide for short Methods to define
-different kinds of temperature thresholds.
-
-1) _AC0, _AC1, _AC2, _AC3, ..., _AC9
-
-These Methods can provide up to 10 temperature thresholds. What these do is set
-temperatures which act as the thresholds to active rows (fan speeds) in the
-ART. _AC0 is intended to be the highest temperature thresholds, and the lowest
-one can be any of them; leave the rest defined as 0 and they will be omitted
-from the output.
-
-These are optional and are enabled by selecting the Active Policy.
-
-2) _PSV
-
-_PSV is a temperature threshold that is used to indicate to DPTF that it should
-begin taking passive measures (i.e., throttling of the Source) in order to
-reduce the temperature of the Target in question. It will check on the
-temperature according to the given sampling period.
-
-This is optional and is enabled by selecting the Passive Policy.
-
-3) _CRT and _HOT
-
-When the temperature of the Source reaches the threshold specified in _CRT, then
-the system is supposed to execute a "graceful suspend". Similarly, when the Source
-reaches the temperature specified in _HOT, then the system is supposed to execute
-a "graceful shutdown".
-
-These are optional, and are enabled by selecting the Critical Policy.
-
-## How to use the devicetree entries
-
-The `drivers/intel/dptf` chip driver is organized into several sections:
- Policies
- Controls
- Options
-
-The Policies section (`policies.active`, `policies.passive`, and
-`policies.critical`) is where the components of each policy are defined.
-
-### Active Policy
-
-Each Active Policy is defined in terms of 4 parts:
-1) A Source (this is implicitly defined as TFN1, the system fan)
-2) A Target (this is the device that can be affected by the policy, i.e.,
-   this is a device that can be cooled by the fan)
-3) A 'Weight', which is defined as the Source's contribution to the Target's
-   cooling capability (as a percentage, 0-100, often just left at 100).
-4) A list of temperature-fan percentage pairs, which define temperature
-   thresholds that, when the Target reaches, the fan is defined to spin
-   at the corresponding percentage of full duty cycle.
-
-An example definition in the devicetree:
-```C
-register "policies.active[0]" = "{
-    .target=DPTF_CPU,
-    .weight=100,
-    .thresholds={TEMP_PCT(85, 90),
-                 TEMP_PCT(80, 69),
-                 TEMP_PCT(75, 56),
-                 TEMP_PCT(70, 46),
-                 TEMP_PCT(65, 36),}}"
-```
-
-This example sets up a policy wherein the CPU temperature sensor can be cooled
-by the fan. The 'weight' of this policy is 100% (this policy contributes 100% of
-the CPU's active cooling capability). When the CPU temperature first crosses
-65C, the fan is defined to spin at 36% of its duty cycle, and so forth up the
-rest of the table (note that it *must* be defined from highest temperature/
-percentage on down to the lowest).
-
-### Passive Policy
-
-Each Passive Policy is defined in terms of 5 parts:
-1) Source - The device that can be throttled
-2) Target - The device that controls the amount of throttling
-3) Period - How often to check the temperature of the Target
-4) Trip point - What temperature threshold to start throttling
-5) Priority - A number indicating the relative priority between different
-   Policies
-
-An example definition in the devicetree:
-```C
-register "policies.passive[0]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 65, 60000)"
-```
-
-This example sets up a policy to begin throttling the charger performance when
-temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
-The Priority is defaulted to 100 in this case.
-
-### Critical Policy
-
-Each Critical Policy is defined in terms of 3 parts:
-1) Source - A device that can trigger a critical event
-2) Type - What type of critical event to trigger (S4-entry or shutdown)
-3) Temperature - The temperature threshold that will cause the entry into S4 or
-   to shutdown the system.
-
-An example definition in the devicetree:
-
-```C
-register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
-```
-
-This example sets up a policy wherein ACPI will cause the system to shutdown
-(in a "graceful" manner) when the CPU temperature reaches 75C.
-
-### Power Limits
-
-Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
-that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
-the PPCC table is provided for the TCPU object. Each power limit is given the
-following options:
-1) Minimum power (in mW)
-2) Maximum power (in mW)
-3) Minimum time window (in ms)
-4) Maximum time window (in ms)
-5) Granularity, or minimum step size to control limits (in mW)
-
-An example:
-```C
-register "controls.power_limits.pl1" = "{
-        .min_power = 3000,
-        .max_power = 15000,
-        .time_window_min = 28 * MSECS_PER_SEC,
-        .time_window_max = 32 * MSECS_PER_SEC,
-        .granularity = 200,}"
-```
-
-This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
-over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
-increments of 200 mW.
-
-### Charger Performance
-
-The battery charger can be a large contributor of unwanted heat in a system that
-has one. Controlling the rate of charging is another tool that DPTF uses to enact
-Passive Policies. Each entry in the PPSS table consists of:
-1) A 'Control' value - an opaque value that the platform firmware uses
-   to initiate a transition to the specified performance state. DPTF will call an
-   ACPI method called `TCHG.SPPC` (Set Participant Performance Capability) if
-   applicable, and will pass this opaque control value as its argument.
-2) The intended charging rate (in mA).
-
-Example:
-```C
-register "controls.charger_perf[0]" = "{ 255, 1700 }"
-register "controls.charger_perf[1]" = "{  24, 1500 }"
-register "controls.charger_perf[2]" = "{  16, 1000 }"
-register "controls.charger_perf[3]" = "{   8,  500 }"
-```
-
-In this example, when DPTF decides to throttle the charger, it has four different
-performance states to choose from.
-
-### Fan Performance
-
-When using DPTF, the system fan (`TFN1`) is the device responsible for actively
-cooling the other temperature sensors on the mainboard. A fan speed table can be
-provided to DPTF to assist with fan control. Each entry holds the following:
-1) Percentage of full duty to spin the fan at
-2) Speed - Speed of the fan at that percentage; informational only, but given in
-   RPM
-3) Noise - Amount of noise created by the fan at that percentage; informational
-   only, but given in tenths of a decibel (centibel).
-4) Power - Amount of power consumed by the fan at that percentage; informational
-   only, but given in mA.
-
-Example:
-```C
-register "controls.fan_perf[0]" = "{  90, 6700, 220, 2200, }"
-register "controls.fan_perf[1]" = "{  80, 5800, 180, 1800, }"
-register "controls.fan_perf[2]" = "{  70, 5000, 145, 1450, }"
-register "controls.fan_perf[3]" = "{  60, 4900, 115, 1150, }"
-register "controls.fan_perf[4]" = "{  50, 3838,  90,  900, }"
-register "controls.fan_perf[5]" = "{  40, 2904,  55,  550, }"
-register "controls.fan_perf[6]" = "{  30, 2337,  30,  300, }"
-register "controls.fan_perf[7]" = "{  20, 1608,  15,  150, }"
-register "controls.fan_perf[8]" = "{  10,  800,  10,  100, }"
-register "controls.fan_perf[9]" = "{   0,    0,   0,   50, }"
-```
-
-In this example, the fan has 10 different performance states, each in an even
-increment of 10 percentage points. This is common when specifying fine-grained
-control of the fan, wherein DPTF will interpolate between the percentages in the
-table for a given temperature threshold.
-
-### Options
-
-#### Fan
-1) Fine-grained control - a boolean (see Fan Performance section above)
-2) Step-size - Recommended minimum step size (in percentage points) to adjust
-   the fan speed when using fine-grained control (ranges from 1 - 9).
-3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
-   fan device if a low fan speed is detected.
-
-#### Temperature sensors
-1) Hysteresis - The amount of hysteresis implemented in either circuitry or
-   the firmware that reads the temperature sensor (in degrees C).
-2) Name - This name is applied to the _STR property of the sensor
-
-### OEM Variables
-Platform vendors can define an array of OEM-specific values as OEM variables
-to be used under DPTF policy. There are total six OEM variables available.
-These can be used in AP policy for more specific actions. These OEM variables
-can be defined as below mentioned example and can be used any variable between
-[0], [1],...,[5]. Platform vendors can enable and use this for specific platform
-by defining OEM variables macro under board variant.
-
-Example:
-```C
-register "oem_data.oem_variables" = "{
-   [1] = 0x6,
-   [3] = 0x1
-}"
-```
--- a/Documentation/drivers/dt_entries.md
+++ b/Documentation/drivers/dt_entries.md
@ -1,309 +0,0 @@
-# Driver Devicetree Entries
-
-Let's take a look at an example entry from
-``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
-
-```
-device pci 15.0 on
-	chip drivers/i2c/generic
-		register "hid" = ""ELAN0000""
-		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
-		register "wake" = "GPE0_DW0_21"
-		device i2c 15 on end
-	end
-end # I2C #0
-```
-
-When this entry is processed during ramstage, it will create a device in the
-ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
-generation routines in coreboot actually generate the raw bytecode that
-represents the device's structure, but looking at ASL code is easier to
-understand; see below for what the disassembled bytecode looks like:
-
-```
-Scope (\_SB.PCI0.I2C0)
-{
-    Device (D015)
-    {
-        Name (_HID, "ELAN0000")  // _HID: Hardware ID
-        Name (_UID, Zero)  // _UID: Unique ID
-        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
-        Method (_STA, 0, NotSerialized)  // _STA: Status
-        {
-            Return (0x0F)
-        }
-        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-        {
-            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-            {
-                0x0000002D,
-            }
-        })
-        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
-        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
-        {
-            0x15, // GPE #21
-            0x03  // Sleep state S3
-        })
-    }
-}
-```
-
-You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
-names/methods in the Device's scope.
-
-## Utilizing a device driver
-
-The device driver must be enabled for your build.  There will be a CONFIG option
-in the Kconfig file in the directory that the driver is in (e.g.,
-``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
-CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
-mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
-to be compiled into your build.
-
-## Diving into the above example:
-
-Let's take a look at how the devicetree language corresponds to the generated
-ASL.
-
-First, note this:
-
-```
-    chip drivers/i2c/generic
-```
-
-This means that the device driver we're using has a corresponding structure,
-located at ``src/drivers/i2c/generic/chip.h``, named **struct
-drivers_i2c_generic_config** and it contains many properties you can specify to
-be included in the ACPI table.
-
-### hid
-
-```
-    register "hid" = ""ELAN0000""
-```
-
-This corresponds to **const char \*hid** in the struct.  In the ACPI ASL, it
-translates to:
-
-```
-    Name (_HID, "ELAN0000") // _HID: Hardware ID
-```
-
-under the device.  **This property is used to match the device to its driver
-during enumeration in the OS.**
-
-### desc
-
-```
-    register "desc" = ""ELAN Touchpad""
-```
-
-corresponds to **const char \*desc** and in ASL:
-
-```
-    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
-```
-
-### irq
-
-It also adds the interrupt,
-
-```
-    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-    {
-        0x0000002D,
-    }
-```
-
-which comes from:
-
-```
-    register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-```
-
-The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
-means it is a level-triggered interrupt as opposed to
-edge-triggered; active low means the interrupt is triggered when the signal is
-low).
-
-Also note that the IRQ names are SoC-specific, and you will need to
-find the names in your SoC's header file.  The ACPI_* macros are defined in
-``src/arch/x86/include/acpi/acpi_device.h``.
-
-Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
-This is often done in a mainboard-specific file named ``gpio.c``.
-
-AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
-GPIO controller needs to be used directly. You can do this by setting the
-`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
-
-i.e.,
-```
-register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
-```
-
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
-mainboards in the tree to implement this are google/skyrim and google/guybrush.
-This feature has also been used in downstream forks without issue for some time
-now on several other boards.
-
-### wake
-
-The last register is:
-
-```
-    register "wake" = "GPE0_DW0_21"
-```
-
-which indicates that the method of waking the system using the touchpad will be
-through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
-this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
-elsewhere in the devicetree.
-
-### device
-
-The last bit of the definition of that device includes:
-
-```
-    device i2c 15 on end
-```
-
-which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
-meaning it will be exposed in the ACPI table.  The PCI device that the
-controller is located in determines which I2C bus the device is expected to be
-found on.  In this example, this is I2C bus 0.  This also determines the ACPI
-"Scope" that the device names and methods will live under, in this case
-"\_SB.PCI0.I2C0".
-
-## Wake sources
-
-The ACPI spec defines two methods to describe how a device can wake the system.
-Only one of these methods should be used, otherwise duplicate wake events will
-be generated.
-
-### Using GPEs as a wake source
-
-The `wake` property specified above is used to tell the ACPI subsystem that the
-device can use a GPE to wake the system. The OS can control whether to enable
-or disable the wake source by unmasking/masking off the GPE.
-
-The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
-generally done by a mainboard specific `gpio.c` file that defines the GPIO
-using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
-`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
-file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
-`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
-GPEs (the rest are available as `tier-2` GPEs).
-
-Windows has a large caveat when using this method. If you use the `gpio_irq`
-property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
-to define a `GPE`, Windows will
-[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
-complaining about an invalid ACPI configuration.
-> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
-
-In order to avoid this error, you should use the `irq` property instead. AMD
-platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
-feasible. The other option is to use a wake capable GPIO as described below.
-
-### Using GPIO interrupts as a wake source
-
-The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
-`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
-`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
-
-This method has a few caveats:
-* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
-  the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
-  system. Instead you need to use the `gpio_irq` property, or a `GPE` as
-  described above.
-* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
-  means the platform specific GPIO controller driver must implement the
-  `irq_set_wake` callback. For AMD systems this wasn't
-  [implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
-  until linux v5.15. If the controller doesn't define this callback, it's
-  possible for the firmware to manually set the `wake` bit on the GPIO. This is
-  often done in a mainboard-specific file named `gpio.c`. This is not
-  recommended because then it's not possible for the OS to disable the wake
-  source.
-* As of
-  [linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
-  the ACPI subsystem doesn't take the interrupt `wake` bit into account when
-  deciding on which power state to put the device in before suspending the
-  system. This means that if you define a power resource for a device via
-  `has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
-  device into D3Cold. i.e., power off the device.
-
-## Other auto-generated names
-
-(see [ACPI specification
-6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
-for more details on ACPI methods)
-
-### _S0W (S0 Device Wake State)
-\_S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
-D3Hot means the `PR3` power resources are still on and the device is still
-responsive on the bus. For i2c devices this is generally the same state as `D0`.
-
-### \_PRW (Power Resources for Wake)
-\_PRW indicates the power resources and events required for wake.  There are no
-dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
-as well as the deepest sleep state supporting waking the system (3), which is
-S3.
-
-### \_STA (Status)
-The \_STA method is generated automatically, and its values, 0xF, indicates the
-following:
-
-    Bit [0] – Set if the device is present.
-    Bit [1] – Set if the device is enabled and decoding its resources.
-    Bit [2] – Set if the device should be shown in the UI.
-    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
-
-### \_CRS (Current resource settings)
-The \_CRS method is generated automatically, as the driver knows it is an I2C
-controller, and so specifies how to configure the controller for proper
-operation with the touchpad.
-
-```
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                    0x00, ResourceConsumer, , Exclusive, )
-```
-
-## Notes
-
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)
--- a/Documentation/drivers/index.md
+++ b/Documentation/drivers/index.md
@ -1,17 +0,0 @@
-# Platform independent drivers documentation
-
-The drivers can be found in `src/drivers`. They are intended for onboard
-and plugin devices, significantly reducing integration complexity and
-they allow to easily reuse existing code across platforms.
-
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
-
-* [Intel DPTF](dptf.md)
-* [IPMI KCS](ipmi_kcs.md)
-* [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
-* [SoundWire](soundwire.md)
-* [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)
--- a/Documentation/drivers/ipmi_kcs.md
+++ b/Documentation/drivers/ipmi_kcs.md
@ -1,56 +0,0 @@
-# IPMI KCS driver
-
-The driver can be found in `src/drivers/ipmi/`. It works with BMC that provide
-a KCS I/O interface as specified in the [IPMI] standard.
-
-The driver detects the IPMI version, reserves the I/O space in coreboot's
-resource allocator and writes the required ACPI and SMBIOS tables.
-
-## For developers
-
-To use the driver, select the `IPMI_KCS` Kconfig and add the following PNP
-device under the LPC bridge device (in example for the KCS at 0xca2):
-
-```
- chip drivers/ipmi
-   device pnp ca2.0 on end         # IPMI KCS
- end
-```
-
-**Note:** The I/O base address needs to be aligned to 2.
-
-The following registers can be set:
-
-* `have_nv_storage`
-  * Boolean
-  * If true `nv_storage_device_address` will be added to SMBIOS type 38.
-* `nv_storage_device_address`
-  * Integer
-  * The NV storage address as defined in SMBIOS spec for type 38.
-* `bmc_i2c_address`
-  * Integer
-  * The i2c address of the BMC. zero if not applicable.
-* `have_apic`
-  * Boolean
-  * If true the `apic_interrupt` will be added to SPMI table.
-* `apic_interrupt`
-  * Integer
-  * The APIC interrupt used to notify about a change on the KCS.
-* `have_gpe`
-  * Boolean
-  * If true the `gpe_interrupt` will be added to SPMI table.
-* `gpe_interrupt`
-  * Integer
-  * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
-
-
-[IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf
--- a/Documentation/drivers/retimer.md
+++ b/Documentation/drivers/retimer.md
@ -1,40 +0,0 @@
-# USB4 Retimers
-
-## Introduction
-As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
-newer revisions of the spec), it becomes more difficult to maintain signal
-integrity for longer traces. Devices such as retimers and redrivers can be used
-to help signals maintain their integrity over long distances.
-
-A redriver is a device that boosts the high-frequency content of a signal in
-order to compensate for the attenuation typically caused by travelling through
-various circuit components (PCB, connectors, CPU, etc.). Redrivers are not
-protocol-aware, which makes them relatively simple. However, their effectiveness
-is limited, and may not work at all in some scenarios.
-
-A retimer is a device that retransmits a fresh copy of the signal it receives,
-by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
-this is a digital component, it may have firmware.
-
-
-## Driver Usage
-
-Some operating systems may have the ability to update firmware on USB4 retimers,
-and ultimately will need some way to power the device on and off so that its new
-firmware can be loaded. This is achieved by providing a GPIO signal that can be
-used for this purpose; its active state must be the one in which power is
-applied to the retimer. This driver will generate the required ACPI AML code
-which will toggle the GPIO in response to the kernel's request (through the
-`_DSM` ACPI method). Simply put something like the following in your devicetree:
-
-```
-device pci 0.0 on
-	chip drivers/intel/usb4/retimer
-		register "power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A0)"
-		device generic 0 on end
-	end
-end
-```
-
-replacing the GPIO with the appropriate pin and polarity.
-
--- a/Documentation/drivers/smmstore.md
+++ b/Documentation/drivers/smmstore.md
@ -1,134 +0,0 @@
-# SMM based flash storage driver
-
-This documents the API exposed by the x86 system management based
-storage driver.
-
-## SMMSTORE
-
-SMMSTORE is a [SMM] mediated driver to read from, write to and erase a
-predefined region in flash. It can be enabled by setting
-`CONFIG_SMMSTORE=y` in menuconfig.
-
-This can be used by the OS or the payload to implement persistent
-storage to hold for instance configuration data, without needing
-to implement a (platform specific) storage driver in the payload
-itself.
-
-The API provides append-only semantics for key/value pairs.
-
-## API
-
-### Storage region
-
-By default SMMSTORE will operate on a separate FMAP region called
-`SMMSTORE`. The default generated FMAP will include such a region.
-On systems with a locked FMAP, e.g. in an existing vboot setup
-with a locked RO region, the option exists to add a cbfsfile
-called `smm_store` in the `RW_LEGACY` (if CHROMEOS) or in the
-`COREBOOT` FMAP regions. It is recommended for new builds using
-a handcrafted FMD that intend to make use of SMMSTORE to include a
-sufficiently large `SMMSTORE` FMAP region. It is recommended to
-align the `SMMSTORE` region to 64KiB for the largest flash erase
-op compatibility.
-
-When a default generated FMAP is used the size of the FMAP region
-is equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least
-64KiB. Given that the current implementation lacks a way to rewrite
-key-value pairs at least a multiple of this is recommended.
-
-### generating the SMI
-
-SMMSTORE is called via an SMI, which is generated via a write to the
-IO port defined in the smi_cmd entry of the FADT ACPI table. `%al`
-contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO
-port. `%ah` contains the SMMSTORE command. `%ebx` contains the
-parameter buffer to the SMMSTORE command.
-
-### Return values
-
-If a command succeeds, SMMSTORE will return with
-`SMMSTORE_RET_SUCCESS=0` on `%eax`. On failure SMMSTORE will return
-`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands
-`SMMSTORE_REG_UNSUPPORTED=2` is returned.
-
-**NOTE1**: The caller **must** check the return value and should make
-no assumption on the returned data if `%eax` does not contain
-`SMMSTORE_RET_SUCCESS`.
-
-**NOTE2**: If the SMI returns without changing `%ax` assume that the
-SMMSTORE feature is not installed.
-
-### Calling arguments
-
-SMMSTORE supports 3 subcommands that are passed via `%ah`, the additional
-calling arguments are passed via `%ebx`.
-
-**NOTE**: The size of the struct entries are in the native word size of
-smihandler. This means 32 bits in almost all cases.
-
-
-#### - SMMSTORE_CMD_CLEAR = 1
-
-This clears the `SMMSTORE` storage region. The argument in `%ebx` is
-unused.
-
-#### - SMMSTORE_CMD_READ = 2
-
-The additional parameter buffer `%ebx` contains a pointer to
-the following struct:
-
-```C
-struct smmstore_params_read {
-	void *buf;
-	ssize_t bufsize;
-};
-```
-
-INPUT:
- `buf`: is a pointer to where the data needs to be read
- `bufsize`: is the size of the buffer
-
-OUTPUT:
- `buf`
- `bufsize`: returns the amount of data that has actually been read.
-
-#### - SMMSTORE_CMD_APPEND = 3
-
-SMMSTORE takes a key-value approach to appending data. key-value pairs
-are never updated, they are always appended. It is up to the caller to
-walk through the key-value pairs after reading SMMSTORE to find the
-latest one.
-
-The additional parameter buffer `%ebx` contains a pointer to
-the following struct:
-
-```C
-struct smmstore_params_append {
-	void *key;
-	size_t keysize;
-	void *val;
-	size_t valsize;
-};
-```
-
-INPUT:
- `key`: pointer to the key data
- `keysize`: size of the key data
- `val`: pointer to the value data
- `valsize`: size of the value data
-
-#### Security
-
-Pointers provided by the payload or OS are checked to not overlap with the SMM.
-That protects the SMM handler from being manipulated.
-
-*However there's no validation done on the source or destination pointing to
-DRAM. A malicious application that is able to issue SMIs could extract arbitrary
-data or modify the currently running kernel.*
-
-## External links
-
-* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
-Note, this differs significantly from coreboot's implementation.
-
-[SMM]: ../security/smm.md
--- a/Documentation/drivers/smmstorev2.md
+++ b/Documentation/drivers/smmstorev2.md
@ -1,221 +0,0 @@
-# SMM based flash storage driver Version 2
-
-This documents the API exposed by the x86 system management based
-storage driver.
-
-## SMMSTOREv2
-
-SMMSTOREv2 is a [SMM] mediated driver to read from, write to and erase
-a predefined region in flash. It can be enabled by setting
-`CONFIG_SMMSTORE=y` and `CONFIG_SMMSTORE_V2=y` in menuconfig.
-
-This can be used by the OS or the payload to implement persistent
-storage to hold for instance configuration data, without needing to
-implement a (platform specific) storage driver in the payload itself.
-
-### Storage size and alignment
-
-SMMSTORE version 2 requires a minimum alignment of 64 KiB, which should
-be supported by all flash chips. Not having to perform read-modify-write
-operations is desired, as it reduces complexity and potential for bugs.
-
-This can be used by a FTW (FaultTolerantWrite) implementation that uses
-at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
-
- The variable store
- The FTW spare block
- The FTW working block
-
-All regions must be block-aligned, and the FTW spare size must be larger
-than that of the variable store. FTW working block can be much smaller.
-With 64 KiB as block size, the minimum size of the FTW-enabled store is:
-
- The variable store: 1 block = 64 KiB
- The FTW spare block: 2 blocks = 2 * 64 KiB
- The FTW working block: 1 block = 64 KiB
-
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
-
-## API
-
-The API provides read and write access to an unformatted block storage.
-
-### Storage region
-
-By default SMMSTOREv2 will operate on a separate FMAP region called
-`SMMSTORE`. The default generated FMAP will include such a region. On
-systems with a locked FMAP, e.g. in an existing vboot setup with a
-locked RO region, the option exists to add a cbfsfile called `smm_store`
-in the `RW_LEGACY` (if CHROMEOS) or in the `COREBOOT` FMAP regions. It
-is recommended for new builds using a handcrafted FMD that intend to
-make use of SMMSTORE to include a sufficiently large `SMMSTORE` FMAP
-region. It is mandatory to align the `SMMSTORE` region to 64KiB for
-compatibility with the largest flash erase operation.
-
-When a default generated FMAP is used, the size of the FMAP region is
-equal to `CONFIG_SMMSTORE_SIZE`. UEFI payloads expect at least 64 KiB.
-To support a fault tolerant write mechanism, at least a multiple of
-this size is recommended.
-
-### Communication buffer
-
-To prevent malicious ring0 code to access arbitrary memory locations,
-SMMSTOREv2 uses a communication buffer in CBMEM/HOB for all transfers.
-This buffer has to be at least 64 KiB in size and must be installed
-before calling any of the SMMSTORE read or write operations. Usually,
-coreboot will install this buffer to transfer data between ring0 and
-the [SMM] handler.
-
-In order to get the communication buffer address, the payload or OS
-has to read the coreboot table with tag `0x0039`, containing:
-
-```C
-struct lb_smmstorev2 {
-	uint32_t tag;
-	uint32_t size;
-	uint32_t num_blocks;	/* Number of writeable blocks in SMM */
-	uint32_t block_size;	/* Size of a block in byte. Default: 64 KiB */
-	uint32_t mmap_addr;	/* MMIO address of the store for read only access */
-	uint32_t com_buffer;	/* Physical address of the communication buffer */
-	uint32_t com_buffer_size;	/* Size of the communication buffer in byte */
-	uint8_t apm_cmd;	/* The command byte to write to the APM I/O port */
-	uint8_t unused[3];	/* Set to zero */
-};
-```
-
-The absence of this coreboot table entry indicates that there's no
-SMMSTOREv2 support.
-
-### Blocks
-
-The SMMSTOREv2 splits the SMMSTORE FMAP partition into smaller chunks
-called *blocks*. Every block is at least the size of 64KiB to support
-arbitrary NOR flash erase ops. A payload or OS must make no further
-assumptions about the block or communication buffer size.
-
-### Generating the SMI
-
-SMMSTOREv2 is called via an SMI, which is generated via a write to the
-IO port defined in the smi_cmd entry of the FADT ACPI table. `%al`
-contains `APM_CNT_SMMSTORE=0xed` and is written to the smi_cmd IO
-port. `%ah` contains the SMMSTOREv2 command. `%ebx` contains the
-parameter buffer to the SMMSTOREv2 command.
-
-### Return values
-
-If a command succeeds, SMMSTOREv2 will return with
-`SMMSTORE_RET_SUCCESS=0` in `%eax`. On failure SMMSTORE will return
-`SMMSTORE_RET_FAILURE=1`. For unsupported SMMSTORE commands
-`SMMSTORE_REG_UNSUPPORTED=2` is returned.
-
-**NOTE 1**: The caller **must** check the return value and should make
-no assumption on the returned data if `%eax` does not contain
-`SMMSTORE_RET_SUCCESS`.
-
-**NOTE 2**: If the SMI returns without changing `%ax`, it can be assumed
-that the SMMSTOREv2 feature is not installed.
-
-### Calling arguments
-
-SMMSTOREv2 supports 3 subcommands that are passed via `%ah`, the
-additional calling arguments are passed via `%ebx`.
-
-**NOTE**: The size of the struct entries are in the native word size of
-smihandler. This means 32 bits in almost all cases.
-
-#### - SMMSTORE_CMD_INIT = 4
-
-This installs the communication buffer to use and thus enables the
-SMMSTORE handler. This command can only be executed once and is done
-by the firmware. Calling this function at runtime has no effect.
-
-The additional parameter buffer `%ebx` contains a pointer to the
-following struct:
-
-```C
-struct smmstore_params_init {
-	uint32_t com_buffer;
-	uint32_t com_buffer_size;
-} __packed;
-```
-
-INPUT:
- `com_buffer`: Physical address of the communication buffer (CBMEM)
- `com_buffer_size`: Size in bytes of the communication buffer
-
-#### - SMMSTORE_CMD_RAW_READ = 5
-
-SMMSTOREv2 allows reading arbitrary data. It is up to the caller to
-initialize the store with meaningful data before using it.
-
-The additional parameter buffer `%ebx` contains a pointer to the
-following struct:
-
-```C
-struct smmstore_params_raw_read {
-	uint32_t bufsize;
-	uint32_t bufoffset;
-	uint32_t block_id;
-} __packed;
-```
-
-INPUT:
- `bufsize`: Size of data to read within the communication buffer
- `bufoffset`: Offset within the communication buffer
- `block_id`: Block to read from
-
-#### - SMMSTORE_CMD_RAW_WRITE = 6
-
-SMMSTOREv2 allows writing arbitrary data. It is up to the caller to
-erase a block before writing it.
-
-The additional parameter buffer `%ebx` contains a pointer to
-the following struct:
-
-```C
-struct smmstore_params_raw_write {
-        uint32_t bufsize;
-        uint32_t bufoffset;
-        uint32_t block_id;
-} __packed;
-```
-
-INPUT:
- `bufsize`: Size of data to write within the communication buffer
- `bufoffset`: Offset within the communication buffer
- `block_id`: Block to write to
-
-#### - SMMSTORE_CMD_RAW_CLEAR = 7
-
-SMMSTOREv2 allows clearing blocks. A cleared block will read as `0xff`.
-By providing multiple blocks the caller can implement a fault tolerant
-write mechanism. It is up to the caller to clear blocks before writing
-to them.
-
-
-```C
-struct smmstore_params_raw_clear {
-	uint32_t block_id;
-} __packed;
-```
-
-INPUT:
- `block_id`: Block to erase
-
-#### Security
-
-Pointers provided by the payload or OS are checked to not overlap with
-SMM. This protects the SMM handler from being compromised.
-
-As all information is exchanged using the communication buffer and
-coreboot tables, there's no risk that a malicious application capable
-of issuing SMIs could extract arbitrary data or modify the currently
-running kernel.
-
-## External links
-
-* [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf)
-Note that this differs significantly from coreboot's implementation.
-
-[SMM]: ../security/smm.md
--- a/Documentation/drivers/soundwire.md
+++ b/Documentation/drivers/soundwire.md
@ -1,496 +0,0 @@
-# SoundWire Implementation in coreboot
-
-## Introduction
-
-SoundWire is an audio interface specification from the MIPI Alliance.
-
- Low complexity
- Low power
- Low latency
- Two pins (clock and data)
- Multi-drop capable
- Multiple audio streams
- Embedded control/command channel
-
-The main *SoundWire Specification* is at version 1.2 and can be downloaded from
-<https://mipi.org> but it is unfortunately only available to MIPI Alliance members.
-
-There is a separate *SoundWire Discovery and Configuration (DisCo) Specification* which
-is at version 1.0 and is available for non-members after providing name and email at
-<https://resources.mipi.org/disco_soundwire>.
-
-The coreboot implementation is based on the SoundWire DisCo Specification which defines
-object hierarchy and properties for providing topology and configuration information to
-OS kernel drivers via ACPI or DeviceTree.
-
-SoundWire itself is architecture independent and the coreboot basic definition is also not
-specific to any to any SoC.  The examples in this document use ACPI to generate properties,
-but the same structures and properties would be needed in a DeviceTree implementation.
-
-## Bus
-
-The SoundWire bus commonly consists of two pins:
-
-* Clock: A common clock signal distributed from the master to all of the slaves.
-* Data: A shared data signal that can be driven by any of the devices, and has a defined
-value when no device is driving it.
-
-While most designs have one data lane it is possible for a multi-lane device to have up
-to 8 data lanes and thus would have more than two pins.
-
-A SoundWire bus consists of one master device, up to 11 slave devices, and an optional
-monitor interface for debug.
-
-SoundWire is an enumerable bus, but not a discoverable one.  That means it is required
-for firmware to provide details about the connected devices to the OS.
-
-### Controller
-
-A SoundWire controller contains one or more master devices.  The handling of multiple
-masters is left up to the implementation, they may share a clock or be operated
-independently or entirely in tandem.  The master devices connected to a controller are
-also referred to as links.
-
-In coreboot the controller device is provided by the SoC or an add-in PCI card.
-
-### Master
-
-A SoundWire master (or link) device is responsible for clock and data handling, bus
-management, and bit slot allocation.
-
-In coreboot the definition of the master device is left up to the controller and the
-mainboard should only need to know the controller's SoundWire topology (number of masters)
-to configure `devicetree.cb`.
-
-It may however be expected to provide some additional SoC-specific configuration data to
-the controller, such as an input clock rate or a list of available masters that cannot
-be determined at run time.
-
-### Slave
-
-SoundWire slave devices are connected to a master and respond to the two-wire control
-information on the SoundWire bus.  There can be up to 11 slave devices on a bus and they
-are capable of interrupting and waking the host.
-
-Slave devices may also have master links which can be connected to other slave devices.
-It is also possible for a multi-lane slave device to have multiple data lanes connected
-to different combinations of master and slave devices.
-
-In coreboot the slave device is defined by a codec driver which should be found in the
-source tree at `src/drivers/soundwire`.
-
-The mainboard provides:
-
-* Master link that this slave device is connected to.
-* Unique ID that this codec responds to on the SoundWire bus.
-* Multi-lane mapping. (optional)
-
-The codec driver provides:
-
-* Slave device properties.
-* Audio Mode properties including bus frequencies and sampling rates.
-* Data Port 1-14 properties such as word lengths, interrupt support, channels.
-* Data Port 0 and Bulk Register Access properties. (optional)
-
-### Monitor
-
-A SoundWire monitor device is defined that allows for test equipment to snoop the bus and
-take over and issue commands.  The monitor interface is not defined for coreboot.
-
-### Example SoundWire Bus
-
-```
-+---------------+                                       +---------------+
-|               |                       Clock Signal    |               |
-|    Master     |-------+-------------------------------|    Slave      |
-|   Interface   |       |               Data Signal     |  Interface 1  |
-|               |-------|-------+-----------------------|               |
-+---------------+       |       |                       +---------------+
-                        |       |
-                        |       |
-                        |       |
-                     +--+-------+--+
-                     |             |
-                     |   Slave     |
-                     | Interface 2 |
-                     |             |
-                     +-------------+
-```
-
-## coreboot
-
-The coreboot implementation of SoundWire integrates with the device model and takes
-advantage of the hierarchical nature of `devicetree.cb` to populate the topology.
-
-The architecture-independent SoundWire tables are defined at
-
-    src/include/device/soundwire.h
-
-Support for new devices comes in three forms:
-
-1. New controller and master drivers.  The first implementation in coreboot is for an Intel
-SoC but the SoundWire specification is in wide use on various ARM SoCs.
-
-    Controller drivers can be implemented in `src/soc` or `src/drivers` and should
-    strive to re-use code as much as possible between different SoC generations from the
-    same vendor.
-
-2. New codec drivers.  These should be implemented for each codec that is added which
-supports SoundWire.  The properties vary between codecs and careful study of the data sheet
-is necessary to ensure proper operation.
-
-    Codec drivers should be implemented in `src/drivers/soundwire` as separate chip drivers.
-    As every codec is different there may not be opportunities of code re-use except between
-    similar codecs from the same vendor.
-
-3. New mainboards with SoundWire support.  The mainboard will combine controllers and codecs
-to form a topology that is described in `devicetree.cb`.  Some devices may need to provide
-board-specific configuration information, and multi-lane devices will need to provide the
-master/slave lane map.
-
-## ACPI Implementation
-
-The implementation for x86 devices relies on ACPI for providing device properties to the OS
-kernel drivers.
-
-The ACPI implementation can be found at
-
-    src/acpi/soundwire.c
-
-And used by including
-
-    #include <acpi/acpi_soundwire.h>
-
-### Controller
-
-The controller driver should populate a `struct soundwire_controller`:
-
-```c
-/**
- * struct soundwire_controller - SoundWire controller properties.
- * @master_count: Number of masters present on this device.
- * @master_list: One entry for each master device.
- */
-struct soundwire_controller {
-	unsigned int master_list_count;
-	struct soundwire_link master_list[SOUNDWIRE_MAX_DEV];
-};
-```
-
-Once the detail of the master links are specified in the `master_list` variable, the controller
-properties for the ACPI object can be generated:
-
-```c
-struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
-soundwire_gen_controller(dsd, &soc_controller, NULL);
-acpi_dp_write(dsd);
-```
-
-If the controller needs to generate custom properties for links it can provide a callback
-function to `soundwire_gen_controller()` instead of passing NULL:
-
-```c
-static void controller_link_prop_cb(struct acpi_dp *dsd, unsigned int id,
-                                    struct soundwire_controller *controller)
-{
-	acpi_dp_add_integer(dsd, "custom-link-property", 1);
-}
-```
-
-### Codec
-
-The codec driver should populate a *struct soundwire_codec* with necessary properties:
-
-```c
-/**
- * struct soundwire_codec - Contains all configuration for a SoundWire codec slave device.
- * @slave: Properties for slave device.
- * @audio_mode: Properties for Audio Mode for Data Ports 1-14.
- * @dpn: Properties for Data Ports 1-14.
- * @multilane: Properties for slave multilane device. (optional)
- * @dp0_bra_mode: Properties for Bulk Register Access mode for Data Port 0. (optional)
- * @dp0: Properties for Data Port 0 for Bulk Register Access. (optional)
- */
-struct soundwire_codec {
-	struct soundwire_slave *slave;
-	struct soundwire_audio_mode *audio_mode[SOUNDWIRE_MAX_DEV];
-	struct soundwire_dpn_entry dpn[SOUNDWIRE_MAX_DPN - SOUNDWIRE_MIN_DPN];
-	struct soundwire_multilane *multilane;
-	struct soundwire_bra_mode *dp0_bra_mode[SOUNDWIRE_MAX_DEV];
-	struct soundwire_dp0 *dp0;
-};
-```
-
-Many of these properties are optional, and depending on the codec will not be supported.
-
-#### Slave Device Properties
-
-These properties provide information about the codec device and what features it supports:
-
-* Wake capability
-* Clock stop behavior
-* Clock and channel state machine behavior
-* Features like register pages, broadcast read, bank delay, and high performance PHY
-
-#### Multi-lane Slave Device Properties
-
-Most slave devices have a single data pin and a single lane, but it is possible for up to
-7 other lanes to be supported on a device.  These lanes can be connected to other master
-links or to other slave devices.
-
-If a codec supports this feature it must indicate that by providing an entry for
-`struct soundwire_multilane` in the chip configuration.
-
-```c
-/**
- * struct drivers_soundwire_example_config - Example codec configuration.
- * @multilane: Multi-lane slave configuration.
- */
-struct drivers_soundwire_example_config {
-	struct soundwire_multilane multilane;
-};
-```
-
-The mainboard is required to provide the lane map in `devicetree.cb` for any codec that has
-multiple lanes connected.  This includes the definition up to 7 entries that indicate which
-lane number on the slave devices (array index starting at 1) maps to which other device:
-
-```
-chip drivers/soundwire/multilane_codec
-	register "multilane.lane_mapping" = "{
-		{
-			# Slave Lane 1 maps to Master Lane 2
-			.lane = 1,
-			.direction = MASTER_LANE,
-			.connection.master_lane = 2
-		},
-		{
-			# Slave Lane 3 maps to Slave Link B
-			.lane = 3,
-			.direction = SLAVE_LINK,
-			.connection.slave_link = 1
-		}
-	}"
-	device generic 0.0 on end
-end
-```
-
-#### Data Port 0 Properties
-
-SoundWire Data Port 0 (DP0) is a special port used for control and status operation relating
-to the whole device interface, and as a special data port for bulk read/write operations.
-
-The properties for data port 0 are different from that of data ports 1-14 and are about the
-control channel behavior and the overall bulk register mode.
-
-Data port 0 is not required to be supported by the slave device.
-
-#### Bulk Register Access Mode Properties
-
-Bulk Register Access (BRA) is an optional mechanism for transporting higher bandwidth of
-register operations than the typical command mechanism.  The BRA protocol is a particular
-format of the data on the (optional) data port 0 connection between the master and slave.
-
-The BRA protocol may have alignment or timing requirements that are directly related to the
-bus frequencies.  As a result there may be several configurations listed, for symmetry with
-the audio modes paired with data ports 1-14.
-
-#### Data Port 1-14 Properties
-
-Data ports 1-14 are typically dedicated to streaming audio payloads, and each data port can
-have from 1 to 8 channels.  There are different levels of data ports, with some registers
-being required and supported on all data ports and some optional registers only being used
-on some data ports.
-
-Data ports can have both a sink and a source component, and the codec may support one or
-both of these on each port.
-
-Similar to data port 0 the properties defined here describe the capabilities and supported
-features of each data port, and they may be configured separately.  For example the Maxim
-MAX98373 codec supports a 32bit source data port for speaker output, and a 16bit sink data
-port for speaker sense data.
-
-#### Audio Mode Properties
-
-Each data port may be tied to one or more audio modes.  The audio mode describes the actual
-audio capabilities of the codec, including supported frequencies and sample rates.  These
-modes can be shared by multiple data ports and do not need to be duplicated.
-
-For example:
-
-```
-static struct soundwire_audio_mode audio_mode = {
-	.bus_frequency_max = 24 * MHz,
-	.bus_frequency_min = 24 * KHz,
-	.max_sampling_frequency = 192 * KHz,
-	.min_sampling_frequency = 8 * KHz,
-};
-static struct soundwire_dpn codec_dp1 = {
-    [...]
-	.port_audio_mode_count = 1,
-	.port_audio_mode_list = {0}
-};
-static struct soundwire_dpn codec_dp3 = {
-    [...]
-	.port_audio_mode_count = 1,
-	.port_audio_mode_list = {0}
-};
-```
-
-### Generating Codec Properties
-
-Once the properties are known it can generate the ACPI code with:
-
-```c
-struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
-soundwire_gen_codec(dsd, &soundwire_codec, NULL);
-acpi_dp_write(dsd);
-```
-
-If the codec needs to generate custom properties for links it can provide a callback
-function to `soundwire_gen_codec()` instead of passing NULL:
-
-```c
-static void codec_dp_prop_cb(struct acpi_dp *dsd, unsigned int id,
-                             struct soundwire_codec *codec)
-{
-	acpi_dp_add_integer(dsd, "custom-dp-property", 1);
-}
-```
-
-#### Codec Address
-
-SoundWire slave devices use a SoundWire defined ACPI _ADR that requires a 64-bit integer
-and uses the master link ID and slave device unique ID to form a unique address for the
-device on this controller.
-
-SoundWire addresses must be distinguishable from all other slave devices on the same master
-link, so multiple instances of the same manufacturer and part on the same master link will
-need different unique IDs.  The value is typically determined by strapping pins on the codec
-chip and can be decoded for this table with the codec datasheet and board schematics.
-
-```c
-/**
- * struct soundwire_address - SoundWire ACPI Device Address Encoding.
- * @version: SoundWire specification version from &enum soundwire_version.
- * @link_id: Zero-based SoundWire Link Number.
- * @unique_id: Unique ID for multiple devices.
- * @manufacturer_id: Manufacturer ID from include/mipi/ids.h.
- * @part_id: Vendor defined part ID.
- * @class: MIPI class encoding in &enum mipi_class.
- */
-struct soundwire_address {
-	enum soundwire_version version;
-	uint8_t link_id;
-	uint8_t unique_id;
-	uint16_t manufacturer_id;
-	uint16_t part_id;
-	enum mipi_class class;
-};
-```
-
-This ACPI address can be generated by calling the provided acpigen function:
-
-    acpigen_write_ADR_soundwire_device(const struct soundwire_address *sdw);
-
-### Mainboard
-
-The mainboard needs to select appropriate drivers in `Kconfig` and define the topology in
-`devicetree.cb` with the controllers and codecs that exist on the board.
-
-The topology uses the **generic** device to describe SoundWire:
-
-```c
-struct generic_path {
-	unsigned int id;       /* SoundWire Master Link ID */
-	unsigned int subid;    /* SoundWire Slave Unique ID */
-};
-```
-
-This allows devices to be specified in `devicetree.cb` with the necessary information to
-generate ACPI address and device properties.
-
-```
-chip drivers/intel/soundwire
-	# SoundWire Controller 0
-	device generic 0 on
-		chip drivers/soundwire/codec1
-			# SoundWire Link 0 ID 0
-			device generic 0.0 on end
-		end
-		chip drivers/soundwire/codec2
-			# SoundWire Link 1 ID 2
-			device generic 1.2 on end
-		end
-	end
-end
-```
-
-## Volteer Example
-
-This is an example of an Intel Tiger Lake reference board using SoundWire Link 0 for the
-headphone codec connection, and Link 1 for connecting two speaker amps for stereo speakers.
-
-The mainboard can be found at
-
-    src/mainboard/google/volteer
-
-```
-  +------------------+         +-------------------+
-  |                  |         | Headphone Codec   |
-  | Intel Tiger Lake |    +--->| Realtek ALC5682   |
-  |    SoundWire     |    |    |       ID 1        |
-  |    Controller    |    |    +-------------------+
-  |                  |    |
-  |           Link 0 +----+    +-------------------+
-  |                  |         | Left Speaker Amp  |
-  |           Link 1 +----+--->| Maxim MAX98373    |
-  |                  |    |    |       ID 3        |
-  |           Link 2 |    |    +-------------------+
-  |                  |    |
-  |           Link 3 |    |    +-------------------+
-  |                  |    |    | Right Speaker Amp |
-  +------------------+    +--->| Maxim MAX98373    |
-                               |       ID 7        |
-                               +-------------------+
-```
-
-This implementation requires a controller driver for the Intel Tigerlake SoC and a codec
-driver for the Realtek and Maxim chips.  If those drivers did not already exist they would
-need to be added and reviewed separately before adding the support to the mainboard.
-
-The volteer example requires some `Kconfig` options to be selected:
-
-```
-config BOARD_GOOGLE_BASEBOARD_VOLTEER
-	select DRIVERS_INTEL_SOUNDWIRE
-	select DRIVERS_SOUNDWIRE_ALC5682
-	select DRIVERS_SOUNDWIRE_MAX98373
-```
-
-And the following `devicetree.cb` entries to define this topology:
-
-```
-device pci 1f.3 on
-	chip drivers/intel/soundwire
-		# SoundWire Controller 0
-		device generic 0 on
-			chip drivers/soundwire/alc5682
-				# SoundWire Link 0 ID 1
-				register "desc" = ""Headphone Jack""
-				device generic 0.1 on end
-			end
-			chip drivers/soundwire/max98373
-				# SoundWire Link 0 ID 1
-				register "desc" = ""Left Speaker Amp""
-				device generic 1.3 on end
-			end
-			chip drivers/soundwire/max98373
-				# SoundWire Link 1 ID 7
-				register "desc" = ""Right Speaker Amp""
-				device generic 1.7 on end
-			end
-		end
-	end
-end
-```
--- a/Documentation/external_docs.md
+++ b/Documentation/external_docs.md
@ -1,136 +0,0 @@
-# External Resources
-
-This is a list of resources that could be useful to coreboot developers.
-These are not endorsed or officially recommended by the coreboot project,
-but simply listed here in the hopes that someone will find something
-useful.
-
-Please add any helpful or informational links and sections as you see fit.
-
-## Articles
-
-* External Interrupts in the x86 system.
-  * [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
-  * [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
-  * [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
-* System address map initialization in x86/x64 architecture.
-  * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
-  * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
-  * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
-* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
-
-
-## General Information
-
-* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
-* [Interface BUS](http://www.interfacebus.com/)
-
-## OpenSecurityTraining2
-
-OpenSecurityTraining2 is dedicated to sharing training material for any topic
-related to computer security, including coreboot.
-
-There are various ways to learn firmware, some are more efficient than others,
-depending on the people. Before going straight to practice and experimenting
-with hardware, it can be beneficial to learn the basics of computing. OST2
-focuses on conveying computer architecture and security information in the form
-of structured instructor-led classes, available to everyone for free.
-
-All material is licensed [CC BY-SA 4.0](http://creativecommons.org/licenses/by-sa/4.0/),
-allowing anyone to use the material however they see fit, so long as they share
-modified works back to the community.
-
-Below is a list of currently available courses that can help understand the
-inner workings of coreboot and other firmware-related topics:
-
-* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-
-There are [additional security courses](https://p.ost2.fyi/courses) at the site
-as well (such as
-[how to avoid writing exploitable code in C/C++](https://ost2.fyi/Vulns1001).)
-
-## Firmware Specifications & Information
-
-* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
-* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
-* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
-
-
-### ACPI
-
-* [ACPI Specs](https://uefi.org/acpi/specs)
-* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
-* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
-* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
-
-
-### Security
-
-* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
-
-
-## Hardware information
-
-* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
-* [Sandpile](https://www.sandpile.org/)
-* [CPU-World](https://www.cpu-world.com/index.html)
-* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
-
-
-### Hardware Specifications & Standards
-
-* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
-* [eMMC](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
-* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
-  [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
-* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
-* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
-* [Memory](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
-* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
-* [PCI / PCIe / M.2](https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED)
-* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
-* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
-* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
-* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
-* [USB](https://www.usb.org/documents) - USB Implementers Forum
-* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
-
-
-### Chip Vendor Documentation
-
-* AMD
-  * [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
-  * [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
-* ARM
-  * [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
-* Intel
-  * [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
-  * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
-  * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
-  * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
-
-* Rockchip
-  * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
-
-
-## Software
-
- * [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
- * [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
- * [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
- * [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
- * [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
- * [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
-* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
-* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
-
-
-## Infrastructure software
-
-* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
-* [GNU Make](https://www.gnu.org/software/make/manual/)
--- a/Documentation/gcov.txt
+++ b/Documentation/gcov.txt
@ -19,7 +19,7 @@ time). The file gcov-io.c is unchanged.
 +#define BITS_PER_UNIT 8
 +#define LONG_LONG_TYPE_SIZE 64
 +
-+/* There are many gcc_assertions. Set the value to 1 if we want a warning
+/* There are many gcc_assertions. Set the vaule to 1 if we want a warning
 +   message if the assertion fails.  */
 +#ifndef ENABLE_ASSERT_CHECKING
 +#define ENABLE_ASSERT_CHECKING 1
--- a/Documentation/gerrit_guidelines.md
+++ b/Documentation/gerrit_guidelines.md
@ -0,0 +1,277 @@
+coreboot Gerrit Etiquette and Guidelines
+========================================
+
+The following rules are the requirements for behavior in the coreboot
+codebase in gerrit. These have mainly been unwritten rules up to this
+point, and should be familiar to most users who have been active in
+coreboot for a period of time. Following these rules will help reduce
+friction in the community.
+
+Note that as with many rules, there are exceptions. Some have been noted
+in the 'More Detail' section. If you feel there is an exception not listed
+here, please discuss it in the mailing list to get this document  updated.
+Don't just assume that it's okay, even if someone on IRC says it is.
+
+
+Summary:
+--------
+These are the expectations for committing, reviewing, and submitting code
+into coreboot git and gerrit. While breaking individual rules may not have
+immediate consequences, the coreboot leadership may act on repeated or
+flagrant violations with or without notice.
+
+* Don't violate the licenses.
+* Let non-trivial patches sit in a review state for at least 24 hours
+before submission.
+* Try to coordinate with platform maintainers when making changes to
+platforms.
+* If you give a patch a -2, you are responsible for giving concrete
+recommendations for what could be changed to resolve the issue the patch
+addresses.
+* Don't modify other people's patches without their consent.
+* Be respectful to others when commenting.
+* Don’t submit patches that you know will break other platforms.
+
+
+More detail:
+------------
+* Don't violate the licenses. If you're submitting code that you didn't
+write yourself, make sure the license is compatible with the license of the
+project you're submitting the changes to. If you’re submitting code that
+you wrote that might be owned by your employer, make sure that your
+employer is aware and you are authorized to submit the code. For
+clarification, see the Developer's Certificate of Origin in the coreboot
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
+
+* Let non-trivial patches sit in a review state for at least 24 hours
+before submission. Remember that there are coreboot developers in timezones
+all over the world, and everyone should have a chance to contribute.
+Trivial patches would be things like whitespace changes or spelling fixes.
+In general, small changes that don’t impact the final binary output. The
+24-hour period would start at submission, and would be restarted at any
+update which significantly changes any part of the patch. Patches can be
+'Fast-tracked' and submitted in under this 24 hour with the agreement of at
+least 3 +2 votes.
+
+* Do not +2 patches that you authored or own, even for something as trivial
+as whitespace fixes. When working on your own patches, it’s easy to
+overlook something like accidentally updating file permissions or git
+submodule commit IDs. Let someone else review the patch. An exception to
+this would be if two people worked in the patch together. If both +2 the
+patch, that is acceptable, as each is giving a +2 to the other's work.
+
+* Try to coordinate with platform maintainers and other significant
+contributors to the code when making changes to platforms. The platform
+maintainers are the users who initially pushed the code for that platform,
+as well as users who have made significant changes to a platform. To find
+out who maintains a piece of code, please use util/scripts/maintainers.go
+or refer to the original author of the code in git log.
+
+* If you give a patch a -2, you are responsible for giving concrete
+recommendations for what could be changed to resolve the issue the patch
+addresses. If you feel strongly that a patch should NEVER be merged, you
+are responsible for defending your position and listening to other points
+of view. Giving a -2 and walking away is not acceptable, and may cause your
+ -2 to be removed by the coreboot leadership after no less than a week. A
+ notification that the -2 will be removed unless there is a response will
+ be sent out at least 2 days before it is removed.
+
+* Don't modify other people's patches unless you have coordinated this with
+the owner of that patch. Not only is this considered rude, but your changes
+could be unintentionally lost. An exception to this would be for patches
+that have not been updated for more than 90 days. In that case, the patch
+can be taken over if the original author does not respond to requests for
+updates. Alternatively, a new patch can be pushed with the original
+content, and both patches should be updated to reference the other.
+
+* Be respectful to others when commenting on patches. Comments should
+be kept to the code, and should be kept in a polite tone. We are a
+worldwide community and English is a difficult language. Assume your
+colleagues are intelligent and do not intend disrespect. Resist the urge to
+retaliate against perceived verbal misconduct, such behavior is not
+conducive to getting patches merged.
+
+* Don’t submit code that you know will break other platforms. If your patch
+affects code that is used by other platforms, it should be compatible with
+those platforms. While it would be nice to update any other platforms, you
+must at least provide a path that will allow other platforms to continue
+working.
+
+
+Recommendations for gerrit activity:
+------------------------------------
+These guidelines are less strict than the ones listed above. These are more
+of the “good idea” variety. You are requested to follow the below
+guidelines, but there will probably be no actual consequences if they’re
+not followed. That said, following the recommendations below will speed up
+review of your patches, and make the members of the community do less work.
+
+* Each patch should be kept to one logical change, which should be
+described in the title of the patch. Unrelated changes should be split out
+into separate patches. Fixing whitespace on a line you’re editing is
+reasonable. Fixing whitespace around the code you’re working on should be a
+separate ‘cleanup’ patch. Larger patches that touch several areas are fine,
+so long as they are one logical change. Adding new chips and doing code
+cleanup over wide areas are two examples of this.
+
+* Test your patches before submitting them to gerrit. It's also appreciated
+if you add a line to the commit message describing how the patch was
+tested. This prevents people from having to ask whether and how the patch
+was tested. Examples of this sort of comment would be ‘TEST=Built
+platform’ or ‘Tested by building and booting platform’.  Stating that the
+patch was not tested is also fine, although you might be asked to do some
+testing in cases where that would be reasonable.
+
+* Take advantage of the lint tools to make sure your patches don’t contain
+trivial mistakes. By running ‘make gitconfig’, the lint-stable tools are
+automatically put in place and will test your patches before they are
+committed. As a violation of these tools will cause the jenkins build test
+to fail, it’s to your advantage to test this before pushing to gerrit.
+
+* Don't submit patch trains longer than around 20 patches unless you
+understand how to manage long patch trains. Long patch trains can become
+difficult to handle and tie up the build servers for long periods of time
+if not managed well. Rebasing a patch train over and over as you fix
+earlier patches in the train can hide comments, and make people review the
+code multiple times to see if anything has changed between revisions. When
+pushing long patch trains, it is recommended to only push the full patch
+train once - the initial time, and only to rebase three or four patches at
+a time.
+
+* Run 'make what-jenkins-does' locally on patch trains before submitting.
+This helps verify that the patch train won’t tie up the jenkins builders
+for no reason if there are failing patches in the train. For running
+parallel builds, you can specify the number of cores to use by setting the
+the CPUS environment variable. Example:
+        make what-jenkins-does CPUS=8
+
+* Use a topic when pushing a train of patches. This groups the commits
+together so people can easily see the connection at the top level of
+gerrit. Topics can be set for individual patches in gerrit by going into
+the patch and clicking on the icon next to the topic line. Topics can also
+be set when you push the patches into gerrit. For example, to push a set of
+commits with the the i915-kernel-x60 set, use the command:
+        git push origin HEAD:refs/for/master/i915-kernel-x60
+
+* If one of your patches isn't ready to be merged, make sure it's obvious
+that you don't feel it's ready for merge yet. The preferred way to show
+this is by marking in the commit message that it’s not ready until X. The
+commit message can be updated easily when it’s ready to be pushed.
+Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
+mark the patch as not ready would be to give it a -1 or -2 review, but
+isn't as obvious as the commit message. These patches can also be pushed as
+drafts as shown in the next guideline.
+
+* When pushing patches that are not for submission, these should be marked
+as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
+draft commits, so that only explicitly added reviewers will see them. These
+sorts of patches are frequently posted as ideas or RFCs for the community
+to look at. To push a draft, use the command:
+        git push origin HEAD:refs/drafts/master
+
+* Respond to anyone who has taken the time to review your patches, even if
+it's just to say that you disagree. While it may seem annoying to address a
+request to fix spelling or 'trivial' issues, it’s generally easy to handle
+in gerrit’s built-in editor. If you do use the built-in editor, remember to
+get that change to your local copy before re-pushing. It's also acceptable
+to add fixes for these sorts of comments to another patch, but it's
+recommended that that patch be pushed to gerrit before the initial patch
+gets submitted.
+
+* Consider breaking up large individual patches into smaller patches
+grouped by areas. This makes the patches easier to review, but increases
+the number of patches. The way you want to handle this is a personal
+decision, as long as each patch is still one logical change.
+
+* If you have an interest in a particular area or mainboard, set yourself
+up as a ‘maintainer’ of that area by adding yourself to the MAINTAINERS
+file in the coreboot root directory. Eventually, this should automatically
+add you as a reviewer when an area that you’re listed as a maintainer is
+changed.
+
+* Submit mainboards that you’re working on to the board-status repo. This
+helps others and shows that these mainboards are currently being
+maintained. At some point, boards that are not up to date in the
+board-status repo will probably end up getting removed from the coreboot
+master branch.
+
+* Abandon patches that are no longer useful, or that you don’t intend to
+keep working on to get submitted.
+
+* Bring attention to patches that you would like reviewed. Add reviewers,
+ask for reviewers on IRC or even just rebase it against the current
+codebase to bring it to the top of the gerrit list. If you’re not sure who
+would be a good reviewer, look in the MAINTAINERS file or git history of
+the files that you’ve changed, and add those people.
+
+* Familiarize yourself with the coreboot [commit message
+guidelines](https://www.coreboot.org/Git#Commit_messages), before pushing
+patches. This will help to keep annoying requests to fix your commit
+message to a minimum.
+
+* If there have been comments or discussion on a patch, verify that the
+comments have been addressed before giving a +2. If you feel that a comment
+is invalid, please respond to that comment instead of just ignoring it.
+
+* Be conscientious when reviewing patches. As a reviewer who approves (+2)
+a patch, you are responsible for the patch and the effect it has on the
+codebase. In the event that the patch breaks things, you are expected to
+be actively involved in the cleanup effort. This means you shouldn’t +2 a
+patch just because you trust the author of a patch - Make sure you
+understand what the implications of a patch might be, or leave the review
+to others. Partial reviews, reviewing code style, for example, can be given
+a +1 instead of a +2. This also applies if you think the patch looks good,
+but may not have the experience to know if there may be unintended
+consequences.
+
+* If there is still ongoing discussion to a patch, try to wait for a
+conclusion to the discussion before submitting it to the tree. If you feel
+that someone is just bikeshedding, maybe just state that and give a time
+that the patch will be submitted if no new objections are raised.
+
+* When working with patch trains, for minor requests it’s acceptable to
+create a fix addressing a comment in another patch at the end of the patch
+train. This minimizes rebases of the patch train while still addressing the
+request. For major problems where the change doesn’t work as intended or
+breaks other platforms, the change really needs to go into the original
+patch.
+
+* When bringing in a patch from another git repo, update the original
+git/gerrit tags by prepending the lines with 'Original-'.  Marking
+the original text this way makes it much easier to tell what changes
+happened in which repository. This applies to these lines, not the actual
+commit message itself:
+        Commit-Id:
+        Change-Id:
+        Signed-off-by:
+        Reviewed-on:
+        Tested-by:
+        Reviewed-by:
+The script 'util/gitconfig/rebase.sh' can be used to help automate this.
+Other tags such as 'Commit-Queue' can simply be removed.
+
+
+Expectations contributors should have:
+--------------------------------------
+* Don't expect that people will review your patch unless you ask them to.
+Adding other people as reviewers is the easiest way. Asking for reviews for
+individual patches in the IRC channel, or by sending a direct request to an
+individual through your favorite messenger is usually the best way to get a
+patch reviewed quickly.
+
+* Don't expect that your patch will be submitted immediately after getting
+a +2. As stated previously, non-trivial patches should wait at least 24
+hours before being submitted. That said, if you feel that your patch or
+series of patches has been sitting longer than needed, you can ask for it
+to be submitted on IRC, or comment that it's ready for submission in the
+patch. This will move it to the top of the list where it's more likely to
+be noticed and acted upon.
+
+* Reviews are about the code. It's easy to take it personally when someone
+is criticising your code, but the whole idea is to get better code into our
+codebase. Again, this also applies in the other direction: review code,
+criticize code, but don’t make it personal.
+
+
+Requests for clarification and suggestions for updates to these guidelines
+should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
--- a/Documentation/getting_started/architecture.md
+++ b/Documentation/getting_started/architecture.md
@ -1,105 +0,0 @@
-# coreboot architecture
-
-## Overview
-![][architecture]
-
-[architecture]: comparison_coreboot_uefi.svg
-
-## Stages
-coreboot consists of multiple stages that are compiled as separate binaries and
-are inserted into the CBFS with custom compression. The bootblock usually doesn't
-have compression while the ramstage and payload are compressed with LZMA.
-
-Each stage loads the next stage at given address (possibly decompressing it).
-
-Some stages are relocatable and can be placed anywhere in DRAM. Those stages are
-usually cached in CBMEM for faster loading times on ACPI S3 resume.
-
-Supported stage compressions:
-* none
-* LZ4
-* LZMA
-
-## bootblock
-The bootblock is the first stage executed after CPU reset. It is written in
-assembly language and its main task is to set up everything for a C-environment:
-
-Common tasks:
-
-* Cache-As-RAM for heap and stack
-* Set stack pointer
-* Clear memory for BSS
-* Decompress and load the next stage
-
-On x86 platforms that includes:
-
-* Microcode updates
-* Timer init
-* Switching from 16-bit real-mode to 32-bit protected mode
-
-The bootblock loads the romstage or the verstage if verified boot is enabled.
-
-### Cache-As-Ram
-The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the
-CPU cache like regular SRAM. This is particullary useful for high level
-languages like `C`, which need RAM for heap and stack.
-
-The CAR needs to be activated using vendor specific CPU instructions.
-
-The following stages run when Cache-As-Ram is active:
-* bootblock
-* romstage
-* verstage
-* postcar
-
-## verstage
-The verstage is where the root-of-trust starts. It's assumed that
-it cannot be overwritten in-field (together with the public key) and
-it starts at the very beginning of the boot process.
-The verstage installs a hook to verify a file before it's loaded from
-CBFS or a partition before it's accessed.
-
-The verified boot mechanism allows trusted in-field firmware updates
-combined with a fail-safe recovery mode.
-
-## romstage
-The romstage initializes the DRAM and prepares everything for device init.
-
-Common tasks:
-
-* Early device init
-* DRAM init
-
-## postcar
-To leave the CAR setup and run code from regular DRAM the postcar-stage tears
-down CAR and loads the ramstage. Compared to other stages it's minimal in size.
-
-## ramstage
-
-The ramstage does the main device init:
-
-* PCI device init
-* On-chip device init
-* TPM init (if not done by verstage)
-* Graphics init (optional)
-* CPU init (like set up SMM)
-
-After initialization tables are written to inform the payload or operating system
-about the current hardware existence and state. That includes:
-
-* ACPI tables (x86 specific)
-* SMBIOS tables (x86 specific)
-* coreboot tables
-* devicetree updates (ARM specific)
-
-It also does hardware and firmware lockdown:
-* Write-protection of boot media
-* Lock security related registers
-* Lock SMM mode (x86 specific)
-
-## payload
-The payload is the software that is run after coreboot is done. It resides in
-the CBFS and there's no possibility to choose it at runtime.
-
-For more details have a look at [payloads](../payloads.md).
-
--- a/Documentation/getting_started/comparison_coreboot_uefi.dia
+++ b/Documentation/getting_started/comparison_coreboot_uefi.dia
--- a/Show More
+++ b/Show More