mb/system76/gaze16: 3060: Add variant for I219-V GbE

Some models use Intel I219-V instead of the Realtek RTL8111 controller.
Introduce a new variant so the IFD of the Realtek board does not have
the onboard LAN enabled when it is not connected.

Change-Id: I1961a7a8fac2dc6e81ebae013ff62cd491fba43c
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -4,7 +4,6 @@
 # Ignore aspects we don't follow here.
 --ignore C99_COMMENTS
 --ignore GLOBAL_INITIALISERS
---ignore COMPARISON_TO_NULL
 --ignore INITIALISED_STATIC
 --ignore LINE_SPACING
 --ignore NEW_TYPEDEFS
@@ -21,9 +20,6 @@
 --ignore SPDX_LICENSE_TAG
 --ignore UNDOCUMENTED_DT_STRING
 --ignore PRINTK_WITHOUT_KERN_LEVEL
---ignore ASSIGN_IN_IF
---ignore UNNECESSARY_ELSE
---ignore GERRIT_CHANGE_ID
 
 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file
@@ -34,8 +30,5 @@
 # some commits unnecessarily.
 --ignore EXECUTE_PERMISSIONS
 
-# Exclude vendorcode directories that don't follow coreboot's coding style.
---exclude src/vendorcode/amd
---exclude src/vendorcode/cavium
---exclude src/vendorcode/intel
---exclude src/vendorcode/mediatek
+# Exclude the vendorcode directory
+--exclude src/vendorcode

.gitignore

@@ -31,9 +31,6 @@ site-local
 # Development friendly files
 tags
 .clang_complete
-.cache
-compile_commands.json
-.vscode/
 
 # Cross-compile toolkits
 xgcc/
@@ -43,3 +40,5 @@ tarballs/
 *~
 *.kate-swp
 *.kdev4
+
+doxygen/*

.gitmodules

@@ -1,67 +1,60 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
-	branch = main
+	url = https://review.coreboot.org/vboot.git
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
-	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
-	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
-[submodule "util/goswid"]
-	path = util/goswid
-	url = ../goswid
-	branch = trunk

.mailmap

@@ -1,425 +0,0 @@
-# Map author and committer names and email addresses to canonical real names and
-# email addresses. https://git-scm.com/docs/gitmailmap
-#
-# Note that this is only needed in the case where someone has contributed
-# with multiple different email addresses or Names.
-#
-# Forms: Proper Name <commit@email.xx>
-#        Proper Name <proper@email.xx> <commit@email.xx>
-#        Proper Name <proper@email.xx> Commit Name <commit@email.xx>
-
-
-Aamir Bohra <aamirbohra@gmail.com> <aamir.bohra@intel.com>
-Aaron Durbin <adurbin@chromium.org>
-Aaron Durbin <adurbin@chromium.org> <adurbin@adurbin.bld.corp.google.com>
-Aaron Durbin <adurbin@chromium.org> <adurbin@google.com>
-Abhay Kumar <abhay.kumar@intel.com>
-Abhinav Hardikar <realdevmaster64@gmail.com> devmaster64 <devmaster64@gmail.com>
-Alex Levin <levinale@google.com> <levinale@chromium.org>
-Alex Miao <alex.miao@mediatek.corp-partner.google.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> <alexandrux.gagniuc@intel.com>
-Alexandru Gagniuc <mr.nuke.me@gmail.com> mrnuke <mrnuke@nukelap.gtech>
-Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
-Amol N Sukerkar <amol.n.sukerkar@intel.com>
-Andrea Barberio <barberio@fb.com> <insomniac@slackware.it>
-Andrey Petrov <anpetrov@fb.com> <andrey.petrov@intel.com>
-Andrey Pronin <apronin@chromium.org> <apronin@google.com>
-Andriy Gapon <avg@FreeBSD.org> <avg@icyb.net.ua>
-Anil Kumar <anil.kumar.k@intel.com> <anil.kumar.k@intel.corp-partner.google.com>
-Anish K. Patel <anishp@win-ent.com>
-Anton Kochkov <anton.kochkov@gmail.com> <a.kochkov@securitycode.ru>
-Antonello Dettori <dev@dettori.io> <dettori.an@gmail.com>
-Ariel Fang <ariel_fang@wistron.corp-partner.google.com>
-Arne Georg Gleditsch <arne.gleditsch@numascale.com> <arne.gleditsch@numscale.com>
-Asami Doi <d0iasm.pub@gmail.com> <doiasami1219@gmail.com>
-Ashwin Kumar <ashk@codeaurora.org>
-Axel Holewa <mono@posteo.de> Mono <mono-for-coreboot@donderklumpen.de>
-Axel Holewa <mono@posteo.de> Mono <mono@posteo.de>
-Bao Zheng <fishbaozi@gmail.com>
-Bao Zheng <fishbaozi@gmail.com> <Zheng Bao zheng.bao@amd.com>
-Bao Zheng <fishbaozi@gmail.com> <zheng.bao@amd.com>
-Bayi Cheng <bayi.cheng@mediatek.com>
-Ben Zhang <benzh@google.com> <benzh@chromium.org>
-Bernhard M. Wiedermann <corebootbmw@lsmod.de>
-Bill Xie <persmule@hardenedlinux.org> <persmule@gmail.com>
-Bill Xie <persmule@hardenedlinux.org> Bill XIE <persmule@hardenedlinux.org>
-Bingxun Shi <bingxunshi@gmail.com>
-Bingxun Shi <bingxunshi@gmail.com> <bxshi@msik.com.cn>
-Brandon Breitenstein <brandon.breitenstein@intel.com> <brandon.breitenstein@intel.corp-partner.google.com>
-Bruce Griffith <bruce.griffith@se-eng.com> <Bruce.Griffith@se-eng.com>
-Bryant Ou <Bryant.Ou.Q@gmail.com>
-Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> <Carl-Daniel Hailfinger>
-Casper Chang<casper_chang@wistron.corp-partner.google.com> <casper.chang@bitland.corp-partner.google.com>
-Caveh Jalali <caveh@chromium.org> <caveh@google.com>
-Caveh Jalali <caveh@chromium.org> caveh jalali <caveh@chromium.org>
-Charles Marslett <charles@scarlettechnologies.com> <charles.marslett@silverbackltd.com>
-Chee Soon Lew <chee.soon.lew@intel.com>
-Cheng-Yi Chiang <cychiang@chromium.org> <cychiang@google.com>
-Chris Ching <chris@ching.codes> <chingcodes@chromium.org>
-Chris Ching <chris@ching.codes> <chingcodes@google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> <chriswang@ami.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris Wang <chris.wang@amd-corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> chris wang <chris.wang@amd.corp-partner.google.com>
-Chris Wang <chris.wang@amd-corp-partner.google.com> Chris.Wang <chris.wang@amd.corp-partner.google.com>
-Chris Zhou <chris_zhou@compal.corp-partner.google.com>
-Christian Ruppert <idl0r@qasl.de> <idl0r@gentoo.org>
-Chun-Jie Chen <chun-jie.chen@mediatek.corp-partner.google.com>
-Clay Daniels Jr <clay.daniels.jr@gmail.com>
-Cole Nelson<colex.nelson@intel.com>
-Corey Osgood <corey.osgod@gmail.com> <corey_osgood@verizon.net>
-Corey Osgood <corey.osgod@gmail.com> <corey.osgood@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
-Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com> Cristi Magherusan <cristi.magherusan@net.utcluj.ro>
-Da Lao <dalao@tutanota.com> dalao <dalao@tutanota.com>
-Daisuke Nojiri <dnojiri@chromium.org> dnojiri <dnojiri@chromium.org>
-Dan Elkouby <streetwalkermc@gmail.com> <streetwalrus@codewalr.us>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@chromium.org>
-Daphne Jansen <dcjansen@chromium.org> Justin TerAvest <teravest@google.com>
-Dave Parker <dparker@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <david.hendricks@gmail.com>
-David Hendricks <davidhendricks@gmail.com> <dhendricks@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@chromium.org>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@fb.com>
-David Hendricks <davidhendricks@gmail.com> <dhendrix@google.com>
-David Hendricks <davidhendricks@gmail.com> David W. Hendricks <dwh@lanl.gov>
-David Wu <david_wu@quantatw.com> <david_wu@quanta.corp-partner.google.com>
-David Wu <david_wu@quantatw.com> david <david_wu@quantatw.com>
-Dawei Chien <dawei.chien@mediatek.com>
-Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org> <GNUtoo@no-log.org>
-Derek Huang <derek.huang@intel.com> <derek.huang@intel.corp-partner.google.com>
-Dmitry Ponamorev <dponamorev@gmail.com>
-Douglas Anderson <dianders@chromium.org>
-Duncan Laurie <dlaurie@chromium.org> <dlaurie@google.com>
-Ed Swierk <eswierk@aristanetworks.com> <eswierk@arastra.com>
-Edward O'Callaghan <quasisec@google.com> <edward.ocallaghan@koparo.com>
-Edward O'Callaghan <quasisec@google.com> <eocallaghan@alterapraxis.com>
-Edward O'Callaghan <quasisec@google.com> <funfunctor@folklore1984.net>
-Edward O'Callaghan <quasisec@google.com> <quasisec@chromium.org>
-Eric Biederman <ebiederm@xmission.com> <ebiederman@lnxi.com>
-Eric Biederman <ebiederm@xmission.com> Eric W. Biederman <ebiederm@xmission.com>
-Eugene Myers <edmyers@tycho.nsa.gov> <cedarhouse@comcast.net>
-Evgeny Zinoviev <me@ch1p.io> <me@ch1p.com>
-Felix Durairaj <felixx.durairaj@intel.com>
-Felix Held <felix-coreboot@felixheld.de> <felix-github@felixheld.de>
-Felix Held <felix-coreboot@felixheld.de> <felix.held@amd.corp-partner.google.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@9elements.com>
-Felix Singer <felixsinger@posteo.net> <felix.singer@secunet.com>
-Felix Singer <felixsinger@posteo.net> <migy@darmstadt.ccc.de>
-Francois Toguo Fotso <francois.toguo.fotso@intel.com> Francois Toguo <francois.toguo.fotso@intel.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Chu <frank_chu@pegatron.corp-partner.google.com> FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
-Frank Vibrans <efdesign98@gmail.com> efdesign98 <efdesign98@gmail.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@amd.com>
-Frank Vibrans <efdesign98@gmail.com> frank vibrans <frank.vibrans@scarletltd.com>
-Frank Vibrans <efdesign98@gmail.com> Frank Vibrans <frank.vibrans@se-eng.com>
-Frank Vibrans <efdesign98@gmail.com> Frank.Vibrans <frank.vibrans@amd.com>
-Furquan Shaikh <furquan@chromium.org> <furquan@google.com>
-G. Pangao <gtk_pangao@mediatek.com> <gtk_pangao@mediatek.corp-partner.google.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@chromium.com>
-Gabe Black <gabeblack@chromium.org> <gabeblack@google.com>
-Gaggery Tsai <gaggery.tsai@intel.com>
-Georg Wicherski <gwicherski@gmail.com> <gw@oxff.net>
-Gomathi Kumar <gomathi.kumar@intel.com>
-Greg V <greg@unrelenting.technology>
-Greg Watson <gwatson@lanl.gov> <jarrah@users.sourceforge.net>
-Hannah Williams <hannah.williams@dell.com> <hannah.williams@intel.com>
-Hao Chou <hao_chou@pegatron.corp-partner.google.com>
-Haridhar Kalvala <haridhar.kalvala@intel.com> haridhar <haridhar.kalvala@intel.com>
-Harsha Priya <harshapriya.n@intel.com>
-Harsha Priya <harshapriya.n@intel.com> <harhapriya.n@intel.com>
-Harshit Sharma <harshitsharmajs@gmail.com> harshit <harshitsharmajs@gmail.com>
-Henry C Chen <henryc.chen@mediatek.com> henryc.chen <henryc.chen@mediatek.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> <himanshusah@hcl.com>
-Himanshu Sahdev <sahdev.himan@gmail.com> Himanshu Sahdev aka CunningLearner <sahdev.himan@gmail.com>
-Hsuan Ting Chen <roccochen@chromium.org> Hsuan-ting Chen <roccochen@google.com>
-Huang Lin <hl@rock-chips.com>
-Huayang Duan <huayang.duan@mediatek.com>
-Huki Huang <huki.huang@intel.com>
-Idwer Vollering <vidwer@gmail.com> <idwer_v@hotmail.com>
-Igor Bagnucki <bagnucki02@gmail.com> <igor.bagnucki@3mdeb.com>
-Indrek Kruusa <indrek.kruusa@artecdesign.ee>  <Indrek Kruusa>
-Ivy Jian <ivy_jian@compal.com> <ivy_jian@compal.corp-partner.google.com>
-Jacob Laska <jlaska91@gmail.com> <jlaska@xes-inc.com>
-Jakub Czapiga <jacz@semihalf.com>
-Jason Wang <Qingpei.Wang@amd.com> Jason WangQingpei.wang <Jason WangQingpei.wang@amd.com>
-JasonX Z Chen <jasonx.z.chen@intel.com>
-Jens Kühnel <coreboot@jens.kuehnel.org> Jens Kuehnel <coreboot@jens.kuehnel.org>
-Jens Rottmann <JRottmann@LiPPERTembedded.de> <JRottmann@LiPPERTEmbedded.de>
-Jeremy Compostella  <jeremy.compostella@intel.com> <jeremy.compostella@gmail.com>
-Jeremy Soller <jackpot51@gmail.com> <jeremy@system76.com>
-Jiaxin Yu <jiaxin.yu@mediatek.com>
-Jiazi Yang <Tomato_Yang@asus.com>
-Jim Lai <jim.lai@intel.com>
-Jingle Hsu <jingle_hsu@wiwynn.com>
-Jinkun Hong <jinkun.hong@rock-chips.com>
-Joe Moore <awokd@danwin1210.me>
-Joe Pillow <joseph.a.pillow@gmail.com>
-Johanna Schander <coreboot@mimoja.de>
-John Zhao <john.zhao@intel.com>
-Jonathan Kollasch <jakllsch@kollasch.net>
-Jordan Crouse <jordan@cosmicpenguin.net>  <Jordan Crouse>
-Jordan Crouse <jordan@cosmicpenguin.net> <jordan.crouse@amd.com>
-Josef Kellermann <Joseph.Kellermann@heitec.de> <seppk@arcor.de>
-Josef Kellermann <Joseph.Kellermann@heitec.de> Josef Kellermannseppk <Josef Kellermannseppk@arcor.de>
-Joseph Smith <joe@settoplinux.org> <joe@settoplinux.org Acked-by: Joseph Smith joe@settoplinux.org>
-Joseph Smith <joe@settoplinux.org> <joe@smittys.pointclark.net>
-Juergen Beisert <juergen@kreuzholzen.de> <juergen127@kreuzholzen.de>
-Julian Schroeder <julianmarcusschroeder@gmail.com> <julian.schroeder@amd.com>
-Julien Viard de Galbert <julien@vdg.name> <jviarddegalbert@online.net>
-Justin Wu <amersel@runbox.me>
-Kaiyen Chang <kaiyen.chang@intel.com> <kaiyen.chang@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> <kane.chen@intel.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> Kane Chenffd <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> kane_chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
-Kane Chen <kane.chen@intel.com> YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
-Karthikeyan Ramasubramanian <kramasub@google.com> <kramasub@chromium.org>
-Katie Roberts-Hoffman <katierh@chromium.org>  <katierh@google.com>
-Kerry She <kerry.she@amd.com> <Kerry.she@amd.com>
-Kerry Sheh <shekairui@gmail.com>
-Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quanta.corp-partner.google.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <kevin.chiu@quantatw.com>
-Kevin Chiu <kevin.chiu.17802@gmail.com> <Kevin.Chiu@quantatw.com>
-Kevin Paul Herbert <kph@platinasystems.com> <kevin@trippers.org>
-Kevin Paul Herbert <kph@platinasystems.com> <kph@meraki.net>
-Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> kirk_wang <kirk_wang@pegatron.corp-partner.google.com>
-Konstantin Aladyshev <aladyshev22@gmail.com> <aladyshev@nicevt.ru>
-Kyösti Mälkki <kyosti.malkki@gmail.com>
-Kyösti Mälkki <kyosti.malkki@gmail.com> <kyosti.malkki@3mdeb.com>
-Lean Sheng Tan <sheng.tan@9elements.com> <lean.sheng.tan@intel.com>
-Lee Leahy <lpleahyjr@gmail.com> <leroy.p.leahy@intel.com>
-Li Cheng Sooi <li.cheng.sooi@intel.com>
-Lijian Zhao <lijian.zhao@intel.com>
-Lin Huang <hl@rock-chips.com>
-Maciej Matuszczyk <maccraft123mc@gmail.com>
-Maggie Li <maggie.li@amd.com> <Maggie.li@amd.com>
-Manideep Kurumella <mkurumel@qualcomm.corp-partner.google.com> <mkurumel@codeaurora.org>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@scarletltd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marc.jones@se-eng.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj.jones@amd.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@gmail.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcj303@yahoo.com>
-Marc Jones <marc@marcjonesconsulting.com> <marcjones@sysproconsulting.com>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones (marc.jones <Marc Jones (marc.jones@amd.com)>
-Marc Jones <marc@marcjonesconsulting.com> Marc Jones(marc.jones <Marc Jones(marc.jones@amd.com)>
-Marcello Sylvester Bauer <sylv@sylv.io>
-Marcello Sylvester Bauer <sylv@sylv.io> <info@marcellobauer.com>
-Marcello Sylvester Bauer <sylv@sylv.io> <sylvblck@sylv.io>
-Marco Chen <marcochen@google.com> <marcochen@chromium.org>
-Mariusz Szafrański <mariuszx.szafranski@intel.com> Mariusz Szafranski <mariuszx.szafranski@intel.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@amd.corp-partner.google.com>
-Marshall Dawson <marshalldawson3rd@gmail.com> <marshall.dawson@scarletltd.com>
-Mart Raudsepp <leio@gentoo.org> <mart.raudsepp@artecdesign.ee>
-Martin Kepplinger <martink@posteo.de> <martin.kepplinger@puri.sm>
-Martin Roth <gaumless@gmail.com> <martin.roth@se-eng.com>
-Martin Roth <gaumless@gmail.com> <martin@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinr@coreboot.org>
-Martin Roth <gaumless@gmail.com> <martinroth@chromium.org>
-Martin Roth <gaumless@gmail.com> <martinroth@google.com>
-Martin Roth <gaumless@gmail.com> Martin Roth <martin@se-eng.com>
-Marx Wang <marx.wang@intel.com>
-Mathias Krause <minipli@googlemail.com> <mathias.krause@secunet.com>
-Mathias Krause <minipli@googlemail.com> <Mathias.Krause@secunet.com>
-Mats Erik Andersson <mats.andersson@gisladisker.org> <mats.andersson@gisladisker.se>
-Matt DeVillier <matt.devillier@gmail.com> <matt.devillier@puri.sm>
-Matt Papageorge <matthewpapa07@gmail.com> <matt.papageorge@amd.corp-partner.google.com>
-Matt Ziegelbaum <ziegs@google.com> <ziegs@chromium.org>
-Maulik V Vaghela <maulik.v.vaghela@intel.com>
-Maulik V Vaghela <maulik.v.vaghela@intel.com> <maulik.v.vaghela@intel.corp-partner.google.com>
-Max Blau <tripleshiftone@gmail.com> Bluemax <1403092+BlueMax@users.noreply.github.com>
-Maxim Polyakov <max.senia.poliak@gmail.com> <m.poliakov@yahoo.com>
-Mengqi Zhang <Mengqi.Zhang@mediatek.com> mengqi.zhang <mengqi.zhang@mediatek.com>
-Michael Niewöhner <foss@mniewoehner.de> <michael.niewoehner@8com.de>
-Michael Xie <Michael.Xie@amd.com> <Michael Xie Michael.Xie@amd.com>
-Michele Guerini Rocco <rnhmjoj@inventati.org>
-Mike Banon <mikebdp2@gmail.com> <mike.banon@3mdeb.com>
-Mike Hsieh <Mike_Hsieh@wistron.com> <mike_hsieh@wistron.corp-partner.google.com>
-Mike Loptien <loptienm@gmail.com> <mike.loptien@se-eng.com>
-Mondrian Nuessle <nuessle@uni-hd.de>
-Mondrian Nuessle <nuessle@uni-hd.de> <nuessle@uni-mannheim.de>
-Motiejus Jakštys <desired.mta@gmail.com>
-Myles Watson <mylesgw@gmail.com>  <myles@pel.cs.byu.edu>
-Nancy Lin <nancy.lin@mediatek.com>
-Naresh Solanki <naresh.solanki@intel.com>
-Naresh Solanki <naresh.solanki@intel.com> <Naresh.Solanki@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Naveen Manohar <naveen.m@intel.com>
-Neil Chen <neilc@nvidia.com> <neilc%nvidia.com@gtempaccount.com>
-Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
-Nick Vaccaro <nvaccaro@google.com> <nvaccaro@chromium.org>
-Nicky Sielicki <nlsielicki@wisc.edu>
-Nico Huber <nico.h@gmx.de> <nico.huber@secunet.com>
-Nicolas Boichat <drinkcat@chromium.org> <drinkcat@google.com>
-Nicolas Reinecke <nr@das-labor.org>
-Nils Jacobs <njacobs8@adsltotaal.nl> <njacobs8@hetnet.nl>
-Nina Wu <nina-cm.wu@mediatek.com> <nina-cm.wu@mediatek.corp-partner.google.com>
-Oskar Enoksson <enok@lysator.liu.se>
-Oskar Enoksson <enok@lysator.liu.se> <oskeno@foi.se>
-Pablo Moyano <42.pablo.ms@gmail.com> p4block <p4block@users.noreply.github.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <Patrick Georgi patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@coresystems.de>
-Patrick Georgi <patrick@coreboot.org> <patrick.georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <Patrick.Georgi@secunet.com>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi-clan.de>
-Patrick Georgi <patrick@coreboot.org> <patrick@georgi.software>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@chromium.org>
-Patrick Georgi <patrick@coreboot.org> Patrick Georgi <pgeorgi@google.com>
-Patrick Rudolph  <siro@das-labor.org> <patrick.rudolph@9elements.com>
-Paul Fagerburg <pfagerburg@chromium.org> <pfagerburg@google.com>
-Paul Kocialkowski <contact@paulk.fr>
-Paul Ma <magf@bitland.com.cn> <magf@bitland.corp-partner.google.com>
-Paul Ma <magf@bitland.com.cn> Magf - <magf@bitland.corp-partner.google.com>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@mailbox.org>
-Paul Menzel <pmenzel@molgen.mpg.de> <paulepanter@users.sourceforge.net>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
-Philip Chen <philipchen@google.com>
-Philip Chen <philipchen@google.com> <philipchen@chromium.org>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <philipp.deppenwiese@9elements.com>
-Philipp Deppenwiese <zaolin.daisuki@gmail.com> <zaolin@das-labor.org>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Ping-chung Chen <ping-chung.chen@intel.com>
-Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> <piotr.kleins@gmail.com>
-Piotr Szymaniak <szarpaj@grubelek.pl>
-Po Xu <jg_poxu@mediatek.com>
-Po Xu <jg_poxu@mediatek.com> <jg_poxu@mediatek.corp-partner.google.com>
-Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
-Preetham Chandrian <preetham.chandrian@intel.com>
-Puthikorn Voravootivat <puthik@chromium.org> <puthik@google.com>
-QingPei Wang <wangqingpei@gmail.com>
-Quan Tran <qeed.quan@gmail.com>
-Rasheed Hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
-Raul Rangel <rrangel@chromium.org>
-Ravi Kumar Bokka <rbokka@codeaurora.org>
-Ravindra <ravindra@intel.com>
-Ravindra <ravindra@intel.com> Ravindra N <ravindra@intel.corp-partner.google.com>
-Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
-Raymond Chung <raymondchung@ami.corp-partner.google.com>
-Raymond Danks <raymonddanks@gmail.com> <ray.danks@se-eng.com>
-Reka Norman <rekanorman@google.com> <rekanorman@chromium.org>
-Ren Kuo <ren.kuo@quantatw.com>
-Ren Kuo <ren.kuo@quantatw.com> <ren.kuo@quanta.corp-partner.google.com>
-Rex-BC Chen <rex-bc.chen@mediatek.com> <rex-bc.chen@mediatek.corp-partner.google.com>
-Ricardo Ribalda <ribalda@chromium.org> <ricardo.ribalda@gmail.com>
-Richard Spiegel <richard.spiegel@silverbackltd.com> <richard.spiegel@amd.corp-partner.google.com>
-Rishavnath Satapathy <rishavnath.satapathy@intel.com>
-Ritul Guru <ritul.bits@gmail.com>
-Rizwan Qureshi <rizwan.qureshi@intel.com> <rizwan.qureshi@intel.corp-partner.google.com>
-Robbie Zhang <robbie.zhang@intel.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com>
-Robert Chen <robert.chen@quanta.corp-partner.google.com> = <robert.chen@quanta.corp-partner.google.com>
-Roger Pau Monne <roger.pau@citrix.com>
-Roman Kononov <kononov@dls.net> <kononov195-lbl@yahoo.com>
-Ron Minnich <rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> <Ron Minnich>
-Ron Minnich <rminnich@gmail.com> <Ronald G. Minnich rminnich@gmail.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <minnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@chromium.org>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@google.com>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <rminnich@lanl.gov>
-Ron Minnich <rminnich@gmail.com> ronald g. minnich <ronald g. minnich>
-Ron Minnich <rminnich@gmail.com> Ronald G. Minnich <Ronald G. Minnich>
-Ronak Kanabar <ronak.kanabar@intel.com>
-Rudolf Marek <r.marek@assembler.cz> <r.marek@asssembler.cz>
-Ryan Chuang <ryan.chuang@mediatek.com> <ryan.chuang@mediatek.corp-partner.google.com>
-Santhosh Janardhana Hassan <sahassan@google.com>
-Scott Chao <scott_chao@wistron.corp-partner.google.com> <scott.chao@bitland.corp-partner.google.com>
-Scott Duplichan <scott@notabs.org> <sc...@notabs.org>
-Scott Tsai <AT>
-Sebastian "Swift Geek" Grzywna <swiftgeek@gmail.com>
-Selma Bensaid <selma.bensaid@intel.com>
-Seunghwan Kim <sh_.kim@samsung.com>
-Seunghwan Kim <sh_.kim@samsung.com> <sh_.kim@samsung.corp-partner.google.com>
-Seunghwan Kim <sh_.kim@samsung.com> sh.kim <sh_.kim@samsung.corp-partner.google.com>
-Shawn Chang <citypw@gmail.com>
-Shawn Nematbakhsh <shawnn@google.com> <shawnn@chromium.org>
-Shelley Chen <shchen@google.com> <shchen@chromium.org>
-Sheng-Liang Pan <Sheng-Liang.Pan@quantatw.com> <sheng-liang.pan@quanta.corp-partner.google.com>
-Shreesh Chhabbi <shreesh.chhabbi@intel.com> <shreesh.chhabbi@intel.corp-partner.google.com>
-Shunqian Zheng <zhengsq@rock-chips.com>
-Siyuan Wang <wangsiyuanbuaa@gmail.com>
-Sowmya <v.sowmya@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com>
-Sridhar Siricilla <sridhar.siricilla@intel.com> <sridhar.siricilla@intel.corp-partner.google.com>
-Srinidhi Kaushik <srinidhi.n.kaushik@intel.com>
-Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
-Stefan Ott <stefan@ott.net> <coreboot@desire.ch>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@chromium.org>
-Stefan Reinauer <stepan@coreboot.org> <reinauer@google.com>
-Stefan Reinauer <stepan@coreboot.org> <Stefan Reinauerstepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stefan.reinauer@coreboot.org>
-Stefan Reinauer <stepan@coreboot.org> <stepan@coresystems.de>
-Stefan Reinauer <stepan@coreboot.org> <stepan@openbios.org>
-Stephan Guilloux <stephan.guilloux@free.fr> <mailto:stephan.guilloux@free.fr>
-Subrata Banik <subratabanik@google.com> <subi.banik@gmail.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Subrata Banik <subratabanik@google.com> <subrata.banik@intel.com>
-Sudheer Kumar Amrabadi <samrab@codeaurora.org>
-Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
-Sunwei Li <lisunwei@huaqin.corp-partner.google.com>
-Susendra Selvaraj <susendra.selvaraj@intel.com>
-Sylvain "ythier" Hitier <sylvain.hitier@gmail.com>
-T Michael Turney <mturney@codeaurora.org> mturney mturney <quic_mturney@quicinc.com>
-T Michael Turney <mturney@codeaurora.org> T Michael Turney <quic_mturney@quicinc.com>
-T.H. Lin <T.H_Lin@quantatw.com> <t.h_lin@quanta.corp-partner.google.com>
-T.H. Lin <T.H_Lin@quantatw.com> T.H.Lin <T.H_Lin@quantatw.com>
-Taniya Das <quic_tdas@quicinc.com> <tdas@codeaurora.org>
-Tao Xia <xiatao5@huaqin.corp-partner.google.com>
-Thejaswani Putta  <thejaswani.putta@intel.com> <thejaswani.putta@intel.corp-partner.google.com>
-Thejaswani Putta <thejaswani.putta@intel.com>
-Thejaswani Putta <thejaswani.putta@intel.com> Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
-Thomas Heijligen <thomas.heijligen@secunet.com> <src@posteo.de>
-Tim Chen <Tim-Chen@quantatw.com> <tim-chen@quanta.corp-partner.google.com>
-Tim Chu <Tim.Chu@quantatw.com>
-Tim Wawrzynczak <twawrzynczak@chromium.org> <twawrzynczak@google.com>
-Timothy Pearson <tpearson@raptorengineering.com> <tpearson@raptorengineeringinc.com>
-Tinghan Shen <tinghan.shen@mediatek.com>
-Tobias Diedrich <ranma+coreboot@tdiedrich.de> <ranma+openocd@tdiedrich.de>
-Tracy Wu <tracy.wu@intel.com> <tracy.wu@intel.corp-partner.google.com>
-Tristan Corrick <tristan@corrick.kiwi> <tristancorrick86@gmail.com>
-Tyler Wang <tyler.wang@quanta.corp-partner.google.com> <Tyler.Wang@quanta.corp-partner.google.com>
-Usha P <usha.p@intel.com> <usha.p@intel.corp-partner.google.com>
-V Sujith Kumar Reddy <vsujithk@codeaurora.org>
-Vadim Bendebury <vbendeb@chromium.org> <vbendeb@google.com>
-Vaibhav Shankar <vaibhav.shankar@intel.com>
-Van Chen <van_chen@compal.corp-partner.google.com>
-Varshit Pandya <varshit.b.pandya@intel.com>
-Varshit Pandya <varshit.b.pandya@intel.com> Varshit B Pandya <varshit.b.pandya@intel.com>
-Varun Joshi <varun.joshi@intel.com> <varun.joshi@intel.corp-partner.google.com>
-Vincent Lim <vincent.lim@amd.com>  <Vincent Lim vincent.lim@amd.com>
-Vladimir Serbinenko <phcoder@gmail.com>
-Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> <Wayne3_Wang@pegatron.corp-partner.google.com>
-William Wu <wulf@rock-chips.com>
-Wim Vervoorn <wvervoorn@eltan.com>
-Wisley Chen <wisley.chen@quantatw.com>
-Wisley Chen <wisley.chen@quantatw.com> <wisley.chen@quanta.corp-partner.google.com>
-Xi Chen <xixi.chen@mediatek.com> <xixi.chen@mediatek.corp-partner.google.com>
-Xiang Wang <merle@hardenedlinux.org> <wxjstz@126.com>
-Xingyu Wu <wuxy@bitland.corp-partner.google.com>
-Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
-Yang A Fang <yang.a.fang@intel.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu at amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai.lu@amd.com>
-Yinghai Lu <yinghailu@gmail.com> <yinghai@kernel.org>
-Yongkun Yu <yuyongkun@huaqin.corp-partner.google.com>
-Yongqiang Niu <yongqiang.niu@mediatek.com>
-Youness Alaoui <snifikino@gmail.com> <kakaroto@kakaroto.homelinux.net>
-Youness Alaoui <snifikino@gmail.com> <youness.alaoui@puri.sm>
-Yu-Hsuan Hsu <yuhsuan@google.com>
-Yu-Hsuan Hsu <yuhsuan@google.com> <yuhsuan@chromium.org>
-Yu-Ping Wu <yupingso@google.com> <yupingso@chromium.org>
-Yuanlidingm <yuanliding@huaqin.corp-partner.google.com>
-Yuchen Huang <yuchen.huang@mediatek.com> <yuchen.huang@mediatek.corp-partner.google.com>
-Yuji Sasaki <sasakiy@chromium.org> <sasakiy@google.com>
-Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
-Zhi Li <lizhi7@huaqin.corp-partner.google.com>
-Zhongze Hu <frankhu@chromium.org> <frankhu@google.com>
-Zhuo-Hao Lee <zhuo-hao.lee@intel.com>
-Zhuohao Lee <zhuohao@chromium.org> <zhuohao@google.com>

AUTHORS

@@ -108,7 +108,6 @@ Jonas 'Sortie' Termansen
 Jonathan A. Kollasch
 Jonathan Neuschäfer
 Jordan Crouse
-Jörg Mische
 Joseph Smith
 Keith Hui
 Keith Packard

Documentation/.mdl_style.rb

@@ -1,9 +0,0 @@
-# See one of the following URLs for explanations of all the rules
-# https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-# https://web.archive.org/web/20220424164542/https://github.com/markdownlint/markdownlint/blob/master/docs/RULES.md
-
-all
-exclude_rule 'no-multiple-blanks'
-exclude_rule 'blanks-around-headers'
-exclude_rule 'blanks-around-lists'
-rule 'line-length', :line_length => 72

Documentation/Intel/Board/board.html

@@ -0,0 +1,239 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Board</title>
+  </head>
+  <body>
+
+<h1>x86 Board Development</h1>
+<p>
+  Board development requires System-on-a-Chip (SoC) support.
+  The combined steps are listed
+  <a target="_blank" href="../development.html">here</a>.
+  The development steps for the board are listed below:
+</p>
+<ol>
+  <li><a href="#RequiredFiles">Required Files</a></li>
+  <li>Enable <a href="#SerialOutput">Serial Output</a></li>
+  <li>Load the <a href="#SpdData">Memory Timing Data</a></li>
+  <li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
+  <li><a href="#AcpiTables">ACPI Tables</a></li>
+</ol>
+
+
+<hr>
+<h2><a name="RequiredFiles">Required Files</a></h2>
+<p>
+  Create the board directory as src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;.
+</p>
+
+<p>
+  The following files are required to build a new board:
+</p>
+<ol>
+  <li>Kconfig.name - Defines the Kconfig value for the board</li>
+  <li>Kconfig
+    <ol type="A">
+      <li>Selects the SoC for the board and specifies the SPI flash size
+        <ol type="I">
+          <li>BOARD_ROMSIZE_KB_&lt;Size&gt;</li>
+          <li>SOC_&lt;Vendor&gt;_&lt;Chip Family&gt;</li>
+        </ol>
+      </li>
+      <li>Declare the Kconfig values for:
+        <ol type="I">
+          <li>MAINBOARD_DIR</li>
+          <li>MAINBOARD_PART_NUMBER</li>
+          <li>MAINBOARD_VENDOR</li>
+        </ol>
+      </li>
+    </ol>
+  </li>
+  <li>devicetree.cb - Enable root bridge and serial port
+    <ol type="A">
+      <li>The first line must be "chip soc/Intel/&lt;soc family&gt;";
+        this path is used by the generated static.c to include the chip.h
+        header file
+      </li>
+    </ol>
+  </li>
+  <li>romstage.c
+    <ol type="A">
+      <li>Add routine mainboard_romstage_entry which calls romstage_common</li>
+    </ol>
+  </li>
+  <li>Configure coreboot build:
+    <ol type="A">
+      <li>Set LOCALVERSION</li>
+      <li>Select vendor for the board</li>
+      <li>Select the board</li>
+      <li>CBFS_SIZE = 0x00100000</li>
+      <li>Set the CPU_MICROCODE_CBFS_LEN</li>
+      <li>Set the CPU_MICROCODE_CBFS_LOC</li>
+      <li>Set the FSP_IMAGE_ID_STRING</li>
+      <li>Set the FSP_LOC</li>
+      <li>No payload</li>
+      <li>Choose the default value for all other options</li>
+    </ol>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="SerialOutput">Enable Serial Output</a></h2>
+<p>
+  Use the following steps to enable serial output:
+</p>
+<ol>
+  <li>Implement the car_mainboard_pre_console_init routine in the com_init.c
+    file:
+    <ol type="A">
+      <li>Power on and enable the UART controller</li>
+      <li>Connect the UART receive and transmit data lines to the
+        appropriate SoC pins
+      </li>
+    </ol>
+  </li>
+  <li>Add Makefile.inc
+    <ol type="A">
+      <li>Add com_init.c to romstage</li>
+    </ol>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="SpdData">Memory Timing Data</a></h2>
+<p>
+  Memory timing data is located in the flash.  This data is in the format of
+  <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
+  (SPD) data.
+  Use the following steps to load the SPD data:
+</p>
+<ol>
+  <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
+    display of the SPD data being passed to MemoryInit
+  </li>
+  <li>Create an "spd" subdirectory</li>
+  <li>Create an spd/spd.c file for the SPD implementation
+    <ol type="A">
+      <li>Implement the mainboard_fill_spd_data routine
+        <ol type="i">
+          <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
+          <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
+          <li>Set the DIMM channel configuration</li>
+        </ol>
+      </li>
+    </ol>
+  </li>
+  <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
+  <li>Create spd/Makefile.inc
+    <ol type="A">
+      <li>Add spd.c to romstage</li>
+      <li>Add the .spd.hex file to SPD_SOURCES</li>
+    </ol>
+  </li>
+  <li>Edit Makefile.inc to add the spd subdirectory</li>
+  <li>Edit romstage.c
+    <ol type="A">
+      <li>Call mainboard_fill_spd_data</li>
+      <li>Add mainboard_memory_init_params to copy the SPD and DRAM
+        configuration data from the pei_data structure into the UPDs
+        for MemoryInit
+      </li>
+    </ol>
+  </li>
+  <li>Edit devicetree.cb
+    <ol type="A">
+      <li>Include the UPD parameters for MemoryInit except for:
+        <ul>
+          <li>Address of SPD data</li>
+          <li>DRAM configuration set above</li>
+        </ul>
+      </li>
+    </ol>
+  </li>
+  <li>A working FSP
+    <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
+    routine is required to complete debugging</li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x34:
+        - Just after entering
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
+      </li>
+      <li>0x36:
+        - Just before displaying the
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
+        for FSP MemoryInit
+      </li>
+      <li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
+        - Just before calling FSP
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
+      </li>
+      <li>0x37:
+        - Just after returning from FSP
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
+      </li>
+    </ol>
+  </li>
+  <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
+</ol>
+
+
+
+<hr>
+<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2>
+<p>
+  Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
+  of the devices in the system.  Edit the devicetree.cb file:
+</p>
+<ol>
+  <li>Edit the devicetree.cb file:
+    <ol type="A">
+      <li>Add an entry for a PCI device.function and turn it off.  The entry
+        should look similar to:
+<pre><code>device pci 14.0 off end</code></pre>
+      </li>
+      <li>Turn on the devices for:
+        <ul>
+          <li>Memory Controller</li>
+          <li>Debug serial device</li>
+        </ul>
+      </li>
+    </ol>
+  </li>
+  <li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
+</ol>
+
+
+
+<hr>
+<h2><a name="AcpiTables">ACPI Tables</a></h2>
+<ol>
+  <li>Edit Kconfig
+    <ol type="A">
+      <li>Add "select HAVE_ACPI_TABLES"</li>
+    </ol>
+  </li>
+  <li>Add the acpi_tables.c module:
+    <ol type="A">
+      <li>Include soc/acpi.h</li>
+      <li>Add the acpi_create_fadt routine
+        <ol type="I">
+          <li>fill in the ACPI header</li>
+          <li>Call the acpi_fill_fadt routine</li>
+        </ol>
+      </li>
+    </ol>
+  </li>
+  <li>Add the dsdt.asl module:
+  </li>
+</ol>
+
+
+
+<hr>
+<p>Modified: 20 February 2016</p>
+  </body>
+</html>

Documentation/Intel/Board/galileo.html

@@ -0,0 +1,113 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Galileo</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; Galileo Development Board</h1>
+<table>
+  <tr>
+    <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td>
+    <td>
+      The Intel&reg; Galileo Gen 2 mainboard code was developed along with the Intel&reg;
+      <a target="_blank" href="../SoC/quark.html">Quark&trade;</a> SoC:
+      <ul>
+        <li><a target="_blank" href="../development.html">Overall</a> development</li>
+        <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li>
+        <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
+        <li><a target="_blank" href="board.html">Board</a> support</li>
+      </ul>
+    </td>
+  </tr>
+</table>
+
+
+
+<hr>
+<h2>Galileo Board Documentation</h2>
+<ul>
+  <li>Common Components
+    <ul>
+      <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li>
+      <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li>
+      <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li>
+      <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li>
+      <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li>
+      <li>SoC: Intel&reg; Quark&trade; <a target="_blank" href="../SoC/quark.html">X-1000</a></li>
+      <li>Serial EEPROM (1 KiB): ON Semiconductor&reg; <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li>
+      <li>SPI Flash (8 MiB): Winbond&trade; <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li>
+      <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li>
+      <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li>
+      <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li>
+    </ul>
+  </li>
+  <li>Make a bootable <a target="_blank" href="https://software.intel.com/en-us/get-started-galileo-linux-step1">micro SD card</a></li>
+</ul>
+
+<h3>Galileo Gen 2 Board Documentation</h3>
+<ul>
+  <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li>
+  <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li>
+  <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li>
+  <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li>
+  <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li>
+  <li>Components
+    <ul>
+      <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li>
+      <li>I2C 16-channel, 12-bit PWM: NXP Semiconductors <a target="_blank" href="http://cache.nxp.com/documents/data_sheet/PCA9685.pdf">PCA9685</a></li>
+      <li>I2C I/O Ports: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf">PCAL9535A</a></li>
+      <li>Octal Buffer/Driver: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf">SN74LV541AT</a></li>
+      <li>Quadruple Bus Buffer: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf">SN74LV125A</a></li>
+      <li>Quadruple Bus Buffer with 3-State Outputs: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf">SN74LVC126A</a></li>
+      <li>Serial EEPROM (1 KiB): ON Semiconductor&reg; <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li>
+      <li>Single 2-input multiplexer: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf">74LVC1G157</a></li>
+      <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li>
+    </ul>
+  </li>
+</ul>
+
+<h3>Galileo Gen 1 Board Documentation</h3>
+<ul>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/galileo-g1-datasheet.pdf">Datasheet</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g1-schematic.pdf">Schematic</a></li>
+  <li>Components
+    <ul>
+      <li>A/D: Analog Devices <a target="_blank" href="http://www.analog.com/media/en/technical-documentation/data-sheets/AD7298-1.pdf">AD7298</a></li>
+      <li>Analog Switch, 2 channel: Texas Instruments <a target="_blank" href="http://www.ti.com.cn/cn/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li>
+      <li>EEPROM & GPIO: Cypress <a target="_blank" href="http://www.cypress.com/file/37971/download">CY8C9540A</a></li>
+      <li>Power Distribution Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps2044b.pdf">TPS2051BDBVR</a></li>
+      <li>RS232 Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/max3232.pdf">MAX3232</a></li>
+      <li>Voltage-Level Translator: Texas Instruments<a target="_blank" href="http://www.ti.com/lit/ds/symlink/txs0108e.pdf">TXS0108E</a></li>
+    </ul>
+  </li>
+</ul>
+
+
+
+<hr>
+<h2>Debug Tools</h2>
+<ul>
+  <li>Flash Programmer:
+    <ul>
+      <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li>
+    </ul>
+  </li>
+  <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li>
+  <li>JTAG Debugger:
+    <ul>
+      <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li>
+      <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li>
+    </ul>
+  </li>
+  <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li>
+  <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li>
+</ul>
+
+
+<hr>
+<p>Modified: 29 February 2016</p>
+  </body>
+</html>

Documentation/Intel/SoC/quark.html

@@ -0,0 +1,220 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Quark&trade; SoC</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; Quark&trade; SoC</h1>
+<table>
+  <tr>
+    <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td>
+    <td>
+      The Quark&trade; SoC code was developed using the
+      <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a>
+      board:
+      <ul>
+        <li><a target="_blank" href="../development.html">Overall</a> development</li>
+        <li><a target="_blank" href="soc.html">SoC</a> support</li>
+        <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
+        <li><a target="_blank" href="../Board/board.html">Board</a> support</li>
+        <li><a target="_blank" href="#QuarkFsp">Quark&trade; FSP</a></li>
+        <li><a target="_blank" href="#CorebootPayloadPkg">CorebootPayloadPkg</a></li>
+      </ul>
+    </td>
+  </tr>
+</table>
+
+
+
+<hr>
+<h2>Quark&trade; Documentation</h2>
+<ul>
+  <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li>
+  <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>:
+    <ul>
+      <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a>
+        - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>:
+        <ul>
+          <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li>
+          <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li>
+          <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li>
+        </ul>
+      </li>
+    </ul>
+  </li>
+  <li><a target="_blank" href="../index.html#Documentation">More documentation</a></li>
+</ul>
+
+
+
+<hr>
+<h2><a name="CorebootPayloadPkg">Quark&trade; EDK2 CorebootPayloadPkg</a></h2>
+<p>
+Build Instructions:
+</p>
+<ol>
+  <li>Set up <a href="#BuildEnvironment">build environment</a></li>
+  <li>Linux (assumes GCC48):
+<pre><code>build  -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc  -a IA32  \
+    -t GCC48  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  \
+    -DDEBUG_PRINT_ERROR_LEVEL=0x80000042  -DSHELL_TYPE=BUILD_SHELL  \
+    -DMAX_LOGICAL_PROCESSORS=1
+ls Build/CorebootPayloadPkgIA32/DEBUG_GCC48/FV/UEFIPAYLOAD.fd
+</code></pre>
+  </li>
+  <li>Windows (assumes Visual Studio 2015):
+<pre><code>build  -p CorebootPayloadPkg\CorebootPayloadPkgIa32.dsc  -a IA32  -t VS2015x86  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042  -DSHELL_TYPE=BUILD_SHELL  -DMAX_LOGICAL_PROCESSORS=1
+dir Build\CorebootPayloadPkgIA32\DEBUG_VS2015x86\FV\UEFIPAYLOAD.fd
+</code></pre>
+  </li>
+  <li>In the .config for coreboot, set the following Kconfig values:
+    <ul>
+      <li>CONFIG_PAYLOAD_ELF=y</li>
+      <li>CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"</li>
+    </ul>
+  </li>
+  <li>Build coreboot</li>
+  <li>Copy the image build/coreboot.rom into flash</li>
+</ol>
+
+
+
+<hr>
+<h2><a name="BuildEnvironment">Quark&trade; EDK2 Build Environment</a></h2>
+<p>
+  Use the following steps to setup a build environment:
+</p>
+<ol>
+  <li>Get the EDK2 sources:
+    <ol type="A">
+      <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li>
+      <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li>
+      <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li>
+    </ol>
+  </li>
+  <li>Set up a build window:
+    <ul>
+      <li>Linux:
+<pre><code>export WORKSPACE=$PWD
+export PACKAGES_PATH="$PWD/edk2:$PWD/edk2-non-osi"
+cd edk2
+export WORKSPACE=$PWD
+. edksetup.sh
+</code></pre>
+      </li>
+      <li>Windows:
+<pre><code>set WORKSPACE=%CD%
+set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\edk2-non-osi
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+cd edk2
+edksetup.bat
+</code></pre>
+      </li>
+    </ul>
+  </li>
+</ol>
+
+
+
+<hr>
+<h2><a name="QuarkFsp">Quark&trade; FSP</a></h2>
+<p>
+Getting the Quark FSP source:
+</p>
+<ol>
+  <li>Set up an EDK-II <a href="#BuildEnvironment">Build Environment</a></li>
+  <li>cd edk2</li>
+  <li>mkdir QuarkFspPkg</li>
+  <li>cd QuarkFspPkg</li>
+  <li>Use git to clone <a target="_blank" href="https://review.gerrithub.io/#/admin/projects/LeeLeahy/quarkfsp">QuarkFspPkg</a> into the QuarkFpsPkg directory (.)</li>
+</ol>
+
+<h3>Building QuarkFspPkg</h3>
+<p>
+There are two versions of FSP: FSP 1.1 and FSP 2.0.  There are also two
+different implementations of FSP, one using subroutines without SEC and
+PEI core and the original implementation which relies on SEC and PEI core.
+Finally there are two different build x86 types release (r32) and debug (d32).
+</p>
+<p>Note that the subroutine implementations are a <b>work in progress</b>.</p>
+<p>
+Build commands shown building debug FSP:
+</p>
+<ul>
+  <li>Linux:
+    <ul>
+      <li>QuarkFspPkg/BuildFsp1_1.sh  -d32</li>
+      <li>QuarkFspPkg/BuildFsp1_1Pei.sh  -d32</li>
+      <li>QuarkFspPkg/BuildFsp2_0.sh  -d32</li>
+      <li>QuarkFspPkg/BuildFsp2_0Pei.sh  -d32</li>
+    </ul>
+  <li>Windows:
+    <ul>
+      <li>QuarkFspPkg/BuildFsp1_1.bat  -d32</li>
+      <li>Windows: QuarkFspPkg/BuildFsp2_0.bat  -d32</li>
+    </ul>
+  </li>
+</ul>
+
+<h3>Copying FSP files into coreboot Source Tree</h3>
+<p>
+There are some helper scripts to copy the FSP output into the coreboot
+source tree.  The parameters to these scripts are:
+</p>
+<ol>
+  <li>EDK2 tree root</li>
+  <li>coreboot tree root</li>
+  <li>Build type: DEBUG or RELEASE</li>
+</ol>
+<p>
+Script files:
+</p>
+<ul>
+  <li>Linux:
+    <ul>
+      <li>QuarkFspPkg/coreboot_fsp1_1.sh</li>
+      <li>QuarkFspPkg/coreboot_fsp1_1Pei.sh</li>
+      <li>QuarkFspPkg/coreboot_fsp2_0.sh</li>
+      <li>QuarkFspPkg/coreboot_fsp2_0Pei.sh</li>
+    </ul>
+</ul>
+
+
+<hr>
+<h2>Quark&trade; EDK2 BIOS</h2>
+<p>
+Build Instructions:
+</p>
+<ol>
+  <li>Set up <a href="#BuildEnvironment">build environment</a></li>
+  <li>Build the image:
+    <ul>
+      <li>Linux:
+<pre><code>build -p QuarkPlatformPkg/Quark.dsc  -a IA32  -t GCC48  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+ls Build/Quark/DEBUG_GCC48/FV/Quark.fd
+</code></pre>
+      </li>
+      <li>Windows:
+<pre><code>build -p QuarkPlatformPkg/Quark.dsc  -a IA32  -t VS2012x86  -b DEBUG  -DDEBUG_PROPERTY_MASK=0x27  -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+dir Build\Quark\DEBUG_VS2012x86\FV\Quark.fd
+</code></pre>
+  </li>
+    </ul>
+  </li>
+</ol>
+
+<p>
+Documentation:
+</p>
+<ul>
+  <li><a target="_blank" href="https://github.com/tianocore/edk2/tree/master/QuarkPlatformPkg">EDK II firmware for Intel&reg; Quark&trade; SoC X1000 based platforms</a></li>
+  <li>Intel&reg; Quark&trade; SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li>
+</ul>
+
+
+
+<hr>
+<p>Modified: 17 May 2016</p>
+  </body>
+</html>

Documentation/Intel/SoC/soc.html

@@ -0,0 +1,730 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>SoC</title>
+  </head>
+  <body>
+
+<h1>x86 System on a Chip (SoC) Development</h1>
+<p>
+  SoC development is best done in parallel with development for a specific
+  board.  The combined steps are listed
+  <a target="_blank" href="../development.html">here</a>.
+  The development steps for the SoC are listed below:
+</p>
+<ol>
+  <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
+  <li>SoC <a href="#RequiredFiles">Required Files</a></li>
+  <li><a href="#Descriptor">Start Booting</a></li>
+  <li><a href="#EarlyDebug">Early Debug</a></li>
+  <li><a href="#Bootblock">Bootblock</a></li>
+  <li><a href="#TempRamInit">TempRamInit</a></li>
+  <li><a href="#Romstage">Romstage</a>
+    <ol type="A">
+      <li>Enable <a href="#SerialOutput">Serial Output"</a></li>
+      <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li>
+      <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li>
+      <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li>
+    </ol>
+  </li>
+  <li><a href="#Ramstage">Ramstage</a>
+    <ol type="A">
+      <li><a href="#DeviceTree">Start Device Tree Processing</a></li>
+      <li>Set up the <a href="#MemoryMap">Memory Map"</a></li>
+    </ol>
+  </li>
+  <li><a href="#AcpiTables">ACPI Tables</a></li>
+  <li><a href="#LegacyHardware">Legacy Hardware</a></li>
+</ol>
+
+
+<hr>
+<h2><a name="RequiredFiles">Required Files</a></h2>
+<p>
+  Create the directory as src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;.
+</p>
+
+<p>
+  The following files are required to build a new SoC:
+</p>
+<ul>
+  <li>Include files
+    <ul>
+      <li>include/soc/pei_data.h</li>
+      <li>include/soc/pm.h</li>
+    </ul>
+  </li>
+  <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
+    chains for the various stages:
+    <ul>
+      <li>select ARCH_BOOTBLOCK_&lt;Tool Chain&gt;</li>
+      <li>select ARCH_RAMSTAGE_&lt;Tool Chain&gt;</li>
+      <li>select ARCH_ROMSTAGE_&lt;Tool Chain&gt;</li>
+      <li>select ARCH_VERSTAGE_&lt;Tool Chain&gt;</li>
+    </ul>
+  </li>
+  <li>Makefile.inc - Specify the include paths</li>
+  <li>memmap.c - Top of usable RAM</li>
+</ul>
+
+
+<hr>
+<h2><a name="Descriptor">Start Booting</a></h2>
+<p>
+  Some SoC parts require additional firmware components in the flash.
+  This section describes how to add those pieces.
+</p>
+
+<h3>Intel Firmware Descriptor</h3>
+<p>
+  The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
+  The following command overwrites the base of the flash image with the Intel
+  Firmware Descriptor:
+</p>
+<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
+
+
+<h3><a name="MEB">Management Engine Binary</a></h3>
+<p>
+  Some SoC parts contain and require that the Management Engine (ME) be running
+  before it is possible to bring the x86 processor out of reset.  A binary file
+  containing the management engine code must be added to the firmware using the
+  ifdtool.  The following commands add this binary blob:
+</p>
+<pre><code>util/ifdtool/ifdtool -i ME:me.bin  build/coreboot.rom
+mv build/coreboot.rom.new build/coreboot.rom
+</code></pre>
+
+
+<h3><a name="EarlyDebug">Early Debug</a></h3>
+<p>
+  Early debugging between the reset vector and the time the serial port is enabled
+  is most easily done by writing values to port 0x80.
+</p>
+
+
+<h3>Success</h3>
+<p>
+  When the reset vector is successfully invoked, port 0x80 will output the following value:
+</p>
+<ul>
+  <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+    - Bootblock successfully executed the
+    <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+    and entered the 16-bit code at
+    <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+  </li>
+</ul>
+
+
+<hr>
+<h2><a name="Bootblock">Bootblock</a></h2>
+<p>
+  Implement the bootblock using the following steps:
+</p>
+<ol>
+  <li>Create the directory as src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock</li>
+  <li>Add the timestamp.inc file which initializes the floating point registers and saves
+    the initial timestamp.
+  </li>
+  <li>Add the bootblock.c file which:
+    <ol type="A">
+      <li>Enables memory-mapped PCI config access</li>
+      <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li>
+      <li>Enable ROM caching</li>
+    </ol>
+  </li>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Kconfig file
+    <ol type="A">
+      <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li>
+      <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li>
+    </ol>
+  </li>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Makefile.inc file
+    <ol type="A">
+      <li>Add the bootblock subdirectory</li>
+    </ol>
+  </li>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/memmap.c file
+    <ol type="A">
+      <li>Add the fsp/memmap.h include file</li>
+    </ol>
+  </li>
+  <li>Add the necessary .h files to define the necessary values and structures</li>
+  <li>When successful port 0x80 will output the following values:
+    <ol type="A">
+      <li>0x01: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
+        - Bootblock successfully executed the
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
+        and entered the 16-bit code at
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
+      </li>
+      <li>0x10: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l53">POST_ENTER_PROTECTED_MODE</a>
+        - Bootblock executing in
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc;hb=HEAD#l55">32-bit mode</a>
+      </li>
+      <li>0x10 - Verstage/romstage reached 32-bit mode</li>
+    </ol>
+  </li>
+</ol>
+
+<p>
+  <b>Build Note:</b> The following files are included into the default bootblock image:
+</p>
+<ul>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S;hb=HEAD">src/arch/x86/bootblock_romcc.S</a>
+    added by   <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l133">src/arch/x86/Makefile.inc</a>
+    and includes the following files:
+    <ul>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prologue.inc">src/arch/x86/prologue.inc</a></li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc">src/cpu/x86/16bit/reset16.inc</a></li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc">src/cpu/x86/16bit/entry16.inc</a></li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit/entry32.inc">src/cpu/x86/32bit/entry32.inc</a></li>
+      <li>The code in
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/bootblock_romcc.S">src/arch/x86/bootblock_romcc.S</a>
+        includes src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock/timestamp.inc using the
+        CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above
+      </li>
+      <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_enable.inc">src/cpu/x86/sse_enable.inc</a></li>
+      <li>The code in
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l156">src/arch/x86/Makefile.inc</a>
+        invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc:
+        <ul>
+          <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/arch/bootblock_romcc.h">src/arch/x86/include/arch/bootblock_romcc.h</a></li>
+          <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic/boot_cpu.c">src/cpu/x86/lapic/boot_cpu.c</a></li>
+          <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in
+            src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/bootblock/bootblock.c
+          </li>
+        </ul>
+      </li>
+    </ul>
+  </li>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a>
+    added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l110">src/arch/x86/Makefile.inc</a>
+  </li>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/fit.S">src/cpu/intel/fit/fit.S</a>
+    added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit/Makefile.inc;hb=HEAD">src/cpu/intel/fit/Makefile.inc</a>
+  </li>
+  <li><a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walkcbfs.S">src/arch/x86/walkcbfs.S</a>
+    added by <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Makefile.inc;hb=HEAD#l137">src/arch/x86/Makefile.inc</a>
+  </li>
+</ul>
+
+
+<hr>
+<h2><a name="TempRamInit">TempRamInit</a></h2>
+<p>
+  Enable the call to TempRamInit in two stages:
+</p>
+<ol>
+  <li>Finding the FSP binary in the read-only CBFS region</li>
+  <li>Call TempRamInit</li>
+</ol>
+
+
+<h3>Find FSP Binary</h3>
+<p>
+Use the following steps to locate the FSP binary:
+</p>
+<ol>
+  <li>Edit the src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/Kconfig file
+    <ol type="A">
+      <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc">src/drivers/intel/fsp1_1/cache_as_ram.inc</a>
+      </li>
+      <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common
+      </li>
+    </ol>
+  </li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+        - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+      </li>
+      <li>Alternating 0xba and 0x01 - The FSP image was not found</li>
+    </ol>
+  </li>
+  <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li>
+  <li>Set the following Kconfig values:
+    <ul>
+      <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li>
+      <li>CONFIG_FSP_IMAGE_ID_STRING</li>
+    </ul>
+  </li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+        - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+      </li>
+      <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li>
+    </ol>
+  </li>
+</ol>
+
+
+<h3>Calling TempRamInit</h3>
+<p>
+Use the following steps to debug the call to TempRamInit:
+</p>
+<ol>
+  <li>Add the CPU microcode update file
+    <ol type="A">
+      <li>Add the microcode file with the following command
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b &lt;base address&gt; -f cpu_microcode_blob.bin</code></pre>
+      </li>
+      <li>Set the Kconfig values
+        <ul>
+          <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li>
+          <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li>
+        </ul>
+      </li>
+    </ol>
+  </li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x90: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>
+        - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">TempRamInit</a>
+      </li>
+      <li>0x2A - Just before calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">cache_as_ram_main</a>
+        which is the start of the verstage code which may be part of romstage
+      </li>
+    </ol>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="Romstage">Romstage</a></h2>
+
+<h3><a name="SerialOutput">Serial Output</a></h3>
+<p>
+  The following steps add the serial output support for romstage:
+</p>
+<ol>
+  <li>Create the romstage subdirectory</li>
+  <li>Add romstage/romstage.c
+    <ol type="A">
+      <li>Program the necessary base addresses</li>
+      <li>Disable the TCO</li>
+    </ol>
+  </li>
+  <li>Add romstage/Makefile.inc
+    <ol type="A">
+      <li>Add romstage.c to romstage</li>
+    </ol>
+  </li>
+  <li>Add gpio configuration support if necessary</li>
+  <li>Add the necessary .h files to support the build</li>
+  <li>Update Makefile.inc
+    <ol type="A">
+      <li>Add the romstage subdirectory</li>
+      <li>Add the gpio configuration support file to romstage</li>
+    </ol>
+  </li>
+  <li>Set the necessary Kconfig values to enable serial output:
+    <ul>
+      <li>CONFIG_DRIVERS_UART_&lt;driver&gt;=y</li>
+      <li>CONFIG_CONSOLE_SERIAL=y</li>
+      <li>CONFIG_UART_FOR_CONSOLE=&lt;port&gt;</li>
+      <li>CONFIG_CONSOLE_SERIAL_115200=y</li>
+    </ul>
+  </li>
+</ol>
+
+
+<h3><a name="PreviousSleepState">Determine Previous Sleep State</a></h3>
+<p>
+  The following steps implement the code to get the previous sleep state:
+</p>
+<ol>
+  <li>Implement the fill_power_state routine which determines the previous sleep state</li>
+  <li>Debug the result until port 0x80 outputs
+    <ol type="A">
+      <li>0x32:
+        - Just after entering
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l99">romstage_common</a>
+      </li>
+      <li>0x33 - Just after calling
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/romstage.c;hb=HEAD#l113">soc_pre_ram_init</a>
+      </li>
+      <li>0x34:
+        - Just after entering
+        <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
+      </li>
+    </ol>
+</ol>
+
+
+<h3><a name="MemoryInit">MemoryInit Support</a></h3>
+<p>
+  The following steps implement the code to support the FSP MemoryInit call:
+</p>
+<ol>
+  <li>Add the chip.h header file to define the UPD values which get passed
+    to MemoryInit.  Skip the values containing SPD addresses and DRAM
+    configuration data which is determined by the board.
+    <p>
+      <b>Build Note</b>: The src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/devicetree.cb
+      file specifies the default values for these parameters.  The build
+      process creates the static.c module which contains the config data
+      structure containing these values.
+    </p>
+  </li>
+  <li>Edit romstage/romstage.c
+    <ol type="A">
+      <li>Implement the romstage/romstage.c/soc_memory_init_params routine to
+        copy the values from the config structure into the UPD structure
+      </li>
+      <li>Implement the soc_display_memory_init_params routine to display
+        the updated UPD parameters by calling fsp_display_upd_value
+      </li>
+    </ol>
+  </li>
+</ol>
+
+
+<h3><a name="DisableShadowRom">Disable Shadow ROM</a></h3>
+<p>
+  A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff.
+  This shadow needs to be disabled to allow RAM to properly respond to
+  this address range.
+</p>
+<ol>
+  <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li>
+</ol>
+
+
+<hr>
+<h2><a name="Ramstage">Ramstage</a></h2>
+
+<h3><a name="DeviceTree">Start Device Tree Processing</a></h3>
+<p>
+  The src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/devicetree.cb file drives the
+  execution during ramstage.  This file is processed by the util/sconfig utility
+  to generate build/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/static.c.  The various
+  state routines in
+  src/lib/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/lib/hardwaremain.c;hb=HEAD#l128">hardwaremain.c</a>
+  call dev_* routines which use the tables in static.c to locate operation tables
+  associated with the various chips and devices.  After location the operation
+  tables, the state routines call one or more functions depending upon the
+  state of the state machine.
+</p>
+
+<h4><a name="ChipOperations">Chip Operations</a></h4>
+<p>
+  Kick-starting the ramstage state machine requires creating the operation table
+  for the chip listed in devicetree.cb:
+</p>
+<ol>
+  <li>Edit src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/chip.c:
+    <ol type="A">
+      <li>
+        This chip's operation table has the name
+        soc_&lt;SoC Vendor&gt;_&lt;SoC Family&gt;_ops which is derived from the
+        chip path specified in the devicetree.cb file.
+      </li>
+      <li>Use the CHIP_NAME macro to specify the name for the chip</li>
+      <li>For FSP 1.1, specify a .init routine which calls intel_silicon_init</li>
+    </ol>
+  </li>
+  <li>Edit src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/Makefile.inc and add chip.c to ramstage</li>
+</ol>
+
+<h4>Domain Operations</h4>
+<p>
+  coreboot uses the domain operation table to initiate operations on all of the
+  devices in the domain.  By default coreboot enables all PCI devices which it
+  finds.  Listing a device in devicetree.cb gives the board vendor control over
+  the device state.  Non-PCI devices may also be listed under PCI device such as
+  the LPC bus or SMbus devices.
+</p>
+<ol>
+  <li>Edit src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/chip.c:
+    <ol type="A">
+      <li>
+        The domain operation table is typically placed in
+        src/soc/&lt;SoC Vendor&gt;/&lt;SoC Family&gt;/chip.c.
+        The table typically looks like the following:
+<pre><code>static struct device_operations pci_domain_ops = {
+	.read_resources	= pci_domain_read_resources,
+	.set_resources	= pci_domain_set_resources,
+	.scan_bus	= pci_domain_scan_bus,
+};
+</code></pre>
+      </li>
+      <li>
+        Create a .enable_dev entry in the chip operations table which points to a
+        routine which sets the domain table for the device with the DEVICE_PATH_DOMAIN.
+<pre><code>	if (dev->path.type == DEVICE_PATH_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	}
+</code></pre>
+      </li>
+      <li>
+        During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+        for the PCI devices on the bus.
+      </li>
+    </ol>
+  </li>
+  <li>Set CONFIG_DEBUG_BOOT_STATE=y in the .config file</li>
+  <li>
+    Debug the result until the PCI vendor and device IDs are displayed
+    during the BS_DEV_ENUMERATE state.
+  </li>
+</ol>
+
+
+<h3><a name="DeviceDrivers">PCI Device Drivers</a></h3>
+<p>
+  PCI device drivers consist of a ".c" file which contains a "pci_driver" data
+  structure at the end of the file with the attribute tag "__pci_driver".  This
+  attribute tag places an entry into a link time table listing the various
+  coreboot device drivers.
+</p>
+<p>
+  Specify the following fields in the table:
+</p>
+<ol>
+  <li>.vendor - PCI vendor ID value of the device</li>
+  <li>.device - PCI device ID value of the device or<br>
+  .devices - Address of a zero terminated array of PCI device IDs
+  </li>
+  <li>.ops - Operations table for the device.  This is the address
+    of a "static struct device_operations" data structure specifying
+    the routines to execute during the different states and sub-states
+    of ramstage's processing.
+  </li>
+  <li>Turn on the device in mainboard/&lt;Vendor&gt;/&lt;Board&gt;/devicetree.cb</li>
+  <li>
+    Debug until the device is on and properly configured in coreboot and
+    usable by the payload
+  </li>
+</ol>
+
+<h4><a name="SubsystemIds">Subsystem IDs</a></h4>
+<p>
+  PCI subsystem IDs are assigned during the BS_DEV_ENABLE state.  The device
+  driver may use the common mechanism to assign subsystem IDs by adding
+  the ".ops_pci" to the pci_driver data structure.  This field points to
+  a "struct pci_operations" that specifies a routine to set the subsystem
+  IDs for the device.  The routine might look something like this:
+</p>
+<pre><code>static void pci_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		vendor = pci_read_config32(dev, PCI_VENDOR_ID);
+		device = vendor >> 16;
+	}
+	printk(BIOS_SPEW,
+		"PCI: %02x:%02x:%d subsystem vendor: 0x%04x, device: 0x%04x\n",
+		0, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn),
+		vendor & 0xffff, device);
+	pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+			((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+</code></pre>
+
+
+
+<h3>Set up the <a name="MemoryMap">Memory Map</a></h3>
+<p>
+  The memory map is built by the various PCI device drivers during the
+  BS_DEV_RESOURCES state of ramstage.  The northcluster driver will typically
+  specify the DRAM resources while the other drivers will typically specify
+  the IO resources.  These resources are hung off the struct device *data structure by
+  src/device/device_util.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/device/device_util.c;hb=HEAD#l448">new_resource</a>.
+</p>
+<p>
+  During the BS_WRITE_TABLES state, coreboot collects these resources and
+  places them into a data structure identified by LB_MEM_TABLE.
+</p>
+<p>
+  Edit the device driver file:
+</p>
+<ol>
+  <li>
+    Implement a read_resources routine which calls macros defined in
+    src/include/device/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/device/device.h;hb=HEAD#l237">device.h</a>
+    like:
+    <ul>
+      <li>ram_resource</li>
+      <li>reserved_ram_resource</li>
+      <li>bad_ram_resource</li>
+      <li>uma_resource</li>
+      <li>mmio_resource</li>
+    </ul>
+  </li>
+</ol>
+
+<p>
+  Testing: Verify that the resources are properly displayed by coreboot during the BS_WRITE_TABLES state.
+</p>
+
+
+
+<hr>
+<h2><a name="AcpiTables">ACPI Tables</a></h2>
+<p>
+  One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
+</p>
+
+<h3>FADT</h3>
+<p>
+  The EDK2 module
+  CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l450">CbParseLib.c</a>
+  requires that the FADT contains the values in the table below.
+  These values are placed into a HOB identified by
+  <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootModulePkg.dec#l36">gUefiAcpiBoardInfoGuid</a>
+  by routine
+  CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPei/CbSupportPei.c#l364">CbPeiEntryPoint</a>.
+</p>
+<table border="1">
+  <tr bgcolor="#c0ffc0">
+    <td>coreboot Field</td>
+    <td>EDK2 Field</td>
+    <td>gUefiAcpiBoardInfoGuid</td>
+    <td>Use</li>
+    <td>
+      <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a>
+      Section
+    </td>
+  </tr>
+  <tr>
+    <td>gpe0_blk<br>gpe0_blk_len</td>
+    <td>Gpe0Blk<br>Gpe0BlkLen</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbParseLib/CbParseLib.c#l477">PmGpeEnBase</a>
+    </td>
+    <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l129">Shutdown</a></td>
+    <td>4.8.4.1</td>
+  </tr>
+  <tr>
+    <td>pm1a_cnt_blk</td>
+    <td>Pm1aCntBlk</td>
+    <td>PmCtrlRegBase</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l139">Shutdown</a><br>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l40">Suspend</a>
+    </td>
+    <td>4.8.3.2.1</td>
+  </tr>
+  <tr>
+    <td>pm1a_evt_blk</td>
+    <td>Pm1aEvtBlk</td>
+    <td>PmEvtBase</td>
+    <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l134">Shutdown</a></td>
+    <td>4.8.3.1.1</td>
+  </tr>
+  <tr>
+    <td>pm_tmr_blk</td>
+    <td>PmTmrBlk</td>
+    <td>PmTimerRegBase</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/AcpiTimerLib/AcpiTimerLib.c#l55">Timer</a>
+    </td>
+    <td>4.8.3.3</td>
+  </tr>
+  <tr>
+    <td>reset_reg.</td>
+    <td>ResetReg.Address</td>
+    <td>ResetRegAddress</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a>
+      and
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a>
+      resets
+    </td>
+    <td>4.3.3.6</td>
+  </tr>
+  <tr>
+    <td>reset_value</td>
+    <td>ResetValue</td>
+    <td>ResetValue</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l71">Cold</a>
+      and
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/ResetSystemLib/ResetSystemLib.c#l98">Warm</a>
+      resets
+    </td>
+    <td>4.8.3.6</td>
+  </tr>
+</table>
+<p>
+  The EDK2 data structure is defined in
+  MdeModulePkg/Include/IndustryStandard/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/MdePkg/Include/IndustryStandard/Acpi61.h#l111">Acpi61.h</a>
+  The coreboot data structure is defined in
+  src/arch/x86/include/arch/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/include/acpi/acpi.h;hb=HEAD#l237">acpi.h</a>
+</p>
+
+<ol>
+  <li>
+    Select <a target="_blank" href="../Board/board.html#AcpiTables">HAVE_ACPI_TABLES</a>
+    in the board's Kconfig file
+  </li>
+  <li>Create a acpi.c module:
+    <ol type="A">
+      <li>Add the acpi_fill_fadt routine and initialize the values above</li>
+    </ol>
+  </li>
+</ol>
+
+
+
+<hr>
+<h2><a name="LegacyHardware">Legacy Hardware</a></h2>
+<p>
+  One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
+</p>
+
+<table border="1">
+  <tr bgcolor="c0ffc0">
+    <th>Peripheral</th>
+    <th>Use</th>
+    <th>8259 Interrupt Vector</th>
+    <th>IDT Base Offset</th>
+    <th>Interrupt Handler</th>
+  </tr>
+  <tr>
+    <td>
+      <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a>
+      Programmable Interval Timer
+    </td>
+    <td>
+      EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a>
+    </td>
+    <td>0</td>
+    <td>0x340</td>
+    <td>
+      <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a>
+    </td>
+  </tr>
+  <tr>
+    <td>
+      <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a>
+      Programmable Interrupt Controller
+    </td>
+    <td>
+      EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a>
+    </td>
+    <td>
+      Master interrupts: 0, 2 - 7<br>
+      Slave interrupts: 8 - 15<br>
+      Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15
+    </td>
+    <td>
+      Master: 0x340, 0x350 - 0x378<br>
+      Slave: 0x380 - 0x3b8<br>
+      Interrupt descriptors are 8 bytes each
+    </td>
+    <td>&nbsp;</td>
+  </tr>
+</table>
+
+<hr>
+<p>Modified: 4 March 2016</p>
+  </body>
+</html>

Documentation/Intel/development.html

@@ -0,0 +1,377 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Development</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; x86 coreboot/FSP Development Process</h1>
+<p>
+  The x86 development process for coreboot is broken into the following components:
+</p>
+<ul>
+  <li>coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li>
+  <li>coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li>
+  <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li>
+</ul>
+<p>
+  The development process has two main phases:
+</p>
+<ol>
+  <li>Minimal coreboot; This phase is single threaded</li>
+  <li>Adding coreboot features</li>
+</ol>
+
+<h2>Minimal coreboot</h2>
+<p>
+  The combined steps below describe how to bring up a minimal coreboot for a
+  system-on-a-chip (SoC) and a development board:
+</p>
+<table>
+  <tr bgcolor="#ffffc0">
+    <td>The initial coreboot steps are single threaded!
+      The initial minimal FSP development is also single threaded.
+      Progress can speed up by adding more developers after the minimal coreboot/FSP
+      implementation reaches the payload.
+    </td>
+  </tr>
+</table>
+<ol>
+  <li>Get the necessary tools:
+    <ul>
+      <li>Linux: Use your package manager to install m4 bison flex and the libcurses development
+        package.
+        <ul>
+          <li>Ubuntu or other Linux distribution that use apt, run:
+<pre><code>sudo apt-get install m4 bison flex libncurses5-dev
+</code></pre>
+          </li>
+        </ul>
+      </li>
+    </ul>
+  </li>
+  <li>Build the cross tools for i386:
+    <ul>
+      <li>Linux:
+<pre><code>make crossgcc-i386</code></pre>
+        To use multiple processors for the toolchain build (which takes a long time), use:
+<pre><code>make crossgcc-i386 CPUS=N</code></pre>
+        where N is the number of cores to use for the build.
+      </li>
+    </ul>
+  </li>
+  <li>Get something to build:
+    <ol type="A">
+      <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
+      <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li>
+      <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li>
+    </ol>
+  </li>
+  <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li>
+  <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li>
+  <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li>
+  <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li>
+  <li>Enable the serial port
+    <ol type="A">
+      <li>Power on, enable and configure GPIOs for the
+        <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a>
+      </li>
+      <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a>
+        support to romstage
+      </li>
+    </ol>
+  </li>
+  <li>Enable <a target="_blank" href="fsp1_1.html#corebootFspDebugging">coreboot/FSP</a> debugging</li>
+  <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li>
+  <li>Enable DRAM:
+    <ol type="A">
+      <li>Implement the SoC
+        <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a>
+        Support
+      </li>
+      <li>Implement the board support to read the
+        <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a>
+      </li>
+    </ol>
+  </li>
+  <li>Disable the
+    <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
+  </li>
+  <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li>
+  <li>
+    Implement the .init routine for the
+    <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
+    structure which calls FSP SiliconInit
+  </li>
+  <li>
+    Start ramstage's
+    <a target="_blank" href="SoC/soc.html#DeviceTree">device tree processing</a>
+    to display the PCI vendor and device IDs
+  </li>
+  <li>
+    Disable the
+    <a target="_blank" href="Board/board.html#DisablePciDevices">PCI devices</a>
+  </li>
+  <li>
+    Implement the
+    <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
+  </li>
+  <li>coreboot should now attempt to load the payload</li>
+</ol>
+
+
+
+<h2>Add coreboot Features</h2>
+<p>
+  Most of the coreboot development gets done in this phase.  Implementation tasks in this
+  phase are easily done in parallel.
+</p>
+<ul>
+  <li>Payload and OS Features:
+    <ul>
+      <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
+      <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
+    </ul>
+  </li>
+</ul>
+
+
+
+<hr>
+<table border="1">
+  <tr bgcolor="#c0ffc0">
+    <th colspan=3><h1>Features</h1></th>
+  </tr>
+  <tr bgcolor="#c0ffc0">
+    <th>SoC</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>8254 Programmable Interval Timer</td>
+    <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
+    <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
+  </tr>
+  <tr>
+    <td>8259 Programmable Interrupt Controller</td>
+    <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
+    <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
+  </tr>
+  <tr>
+    <td>Cache-as-RAM</td>
+    <td>
+      <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a>
+      FSP binary:
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l38">cache_as_ram.inc</a><br>
+      Enable: FSP 1.1 <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a>
+      called from
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l73">cache_as_ram.inc</a><br>
+      Disable: FSP 1.1 TempRamExit called from
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
+    </td>
+    <td>FindFSP: POST code 0x90
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+      is displayed<br>
+      Enable: POST code
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
+      is displayed<br>
+      Disable: CONFIG_DISPLAY_MTRRS=y, MTRRs displayed after call to TempRamExit
+    </td>
+  </tr>
+  <tr>
+    <td>Memory Map</td>
+    <td>
+      Implement a device driver for the
+      <a target="_blank" href="SoC/soc.html#MemoryMap">north cluster</a>
+    </td>
+    <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
+  </tr>
+  <tr>
+    <td>MTRRs</td>
+    <td>
+      Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br>
+      Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a>
+    </td>
+    <td>Set: Post code 0x91
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>)
+      is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
+      Load: Post code 0x3C is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br>
+      and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td>
+  </tr>
+  <tr>
+    <td>PCI Device Support</td>
+    <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>
+    <td>The device is detected by coreboot and usable by the payload</td>
+  </tr>
+  <tr>
+    <td>Ramstage state machine</td>
+    <td>
+      Implement the chip and domain operations to start the
+      <a target="_blank" href="SoC/soc.html#DeviceTree">device tree</a>
+      processing
+    </td>
+    <td>
+      During the BS_DEV_ENUMERATE state, ramstage now display the device IDs
+      for the PCI devices on the bus.
+    </td>
+  </tr>
+  <tr>
+    <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td>
+    <td>
+      Disable: src/soc/&lt;Vendor&gt;/&lt;Chip Family&gt;/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a>
+    </td>
+    <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td>
+  </tr>
+
+
+  <tr bgcolor="#c0ffc0">
+    <th>Board</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>Device Tree</td>
+    <td>
+      <a target="_blank" href="SoC/soc.html#DeviceTree">List</a> PCI vendor and device IDs by starting
+      the device tree processing<br>
+      <a target="_blank" href="Board/board.html#DisablePciDevices">Disable</a> PCI devices<br>
+      Enable: Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a>
+    <td>
+      List: BS_DEV_ENUMERATE state displays PCI vendor and device IDs<br>
+      Disable: BS_DEV_ENUMERATE state shows the devices as disabled<br>
+      Enable: BS_DEV_ENUMERATE state shows the device as on and the device works for the payload
+    </td>
+  </tr>
+  <tr>
+    <td>DRAM</td>
+    <td>
+      Load SPD data: src/soc/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/spd/<a target="_blank" href="Board/board.html#SpdData">spd.c</a><br>
+      UPD Setup:
+      <ul>
+        <li>src/soc&lt;Vendor&gt;//&lt;Chip Family&gt;/romstage/<a target="_blank" href="SoC/soc.html#MemoryInit">romstage.c</a></li>
+        <li>src/mainboard/&lt;Vendor&gt;/&lt;Board&gt;/<a target="_blank" href="Board/board.html#SpdData">romstage.c</a></li>
+      </ul>
+      FSP 1.1 MemoryInit called from src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l126">raminit.c</a>
+    </td>
+    <td>Select the following Kconfig values
+      <ul>
+        <li>DISPLAY_HOBS</li>
+        <li>DISPLAY_UPD_DATA</li>
+      </ul>
+      Testing successful if:
+      <ul>
+        <li>MemoryInit UPD values are correct</li>
+        <li>MemoryInit returns 0 (success) and</li>
+        <li>The message "ERROR - coreboot's requirements not met by FSP binary!"
+          is not displayed
+        </li>
+      </ul>
+    </td>
+  </tr>
+  <tr>
+    <td>Serial Port</td>
+    <td>
+      SoC <a target="_blank" href="SoC/soc.html#SerialOutput">Support</a><br>
+      Enable: src/soc/mainboard/&lt;Board&gt;/com_init.c/<a target="_blank" href="Board/board.html#SerialOutput">car_mainboard_pre_console_init</a>
+    </td>
+    <td>Debug serial output works</td>
+  </tr>
+
+
+  <tr bgcolor="#c0ffc0">
+    <th>Payload</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>ACPI Tables</td>
+    <td>
+      SoC <a target="_blank" href="SoC/soc.html#AcpiTables">Support</a><br>
+    </td>
+    <td>Verified by payload or OS</td>
+  </tr>
+
+
+  <tr bgcolor="#c0ffc0">
+    <th>FSP</th>
+    <th>Where</th>
+    <th>Testing</th>
+  </tr>
+  <tr>
+    <td>TempRamInit</td>
+    <td>FSP <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></td>
+    <td>FSP binary found: POST code 0x90
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l205">POST_FSP_TEMP_RAM_INIT</a>)
+      is displayed<br>
+      TempRamInit successful: POST code
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/cache_as_ram.inc;hb=HEAD#l151">0x2A</a>
+      is displayed<br>
+    </td>
+  </tr>
+  <tr>
+    <td>MemoryInit</td>
+    <td><a target="_blank" href="SoC/soc.html#MemoryInit">SoC</a> support<br>
+      <a target="_blank" href="Board/board.html#SpdData">Board</a> support<br>
+    </td>
+    <td>Select the following Kconfig values
+      <ul>
+        <li>DISPLAY_HOBS</li>
+        <li>DISPLAY_UPD_DATA</li>
+      </ul>
+      Testing successful if:
+      <ul>
+        <li>MemoryInit UPD values are correct</li>
+        <li>MemoryInit returns 0 (success) and</li>
+        <li>The message "ERROR - coreboot's requirements not met by FSP binary!"
+          is not displayed
+        </li>
+      </ul>
+    </td>
+  </tr>
+  <tr>
+    <td>TempRamExit</td>
+    <td>src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l51">after_raminit.S</a></td>
+    <td>Post code 0x91
+      (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l212">POST_FSP_TEMP_RAM_EXIT</a>)
+      is displayed before calling TempRamExit by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a>,
+      CONFIG_DISPLAY_MTRRS=y displays the correct memory regions and
+      Post code 0x39 is displayed by
+      <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l141">after_raminit.S</a><br>
+    </td>
+  </tr>
+  <tr>
+    <td>SiliconInit</td>
+    <td>
+      Implement the .init routine for the
+      <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> structure
+    </td>
+    <td>During BS_DEV_INIT_CHIPS state, SiliconInit gets called and returns 0x00000000</td>
+  </tr>
+  <tr>
+    <td>FspNotify</td>
+    <td>
+      The code which calls FspNotify is located in
+      src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/fsp_util.c;hb=HEAD#l182">fsp_util.c</a>.
+      The fsp_notify_boot_state_callback routine is called three times as specified
+      by the BOOT_STATE_INIT_ENTRY macros below the routine.
+    </td>
+    <td>
+      The FspNotify routines are called during:
+      <ul>
+        <li>BS_DEV_RESOURCES - on exit</li>
+        <li>BS_PAYLOAD_LOAD - on exit</li>
+        <li>BS_OS_RESUME - on entry (S3 resume)</li>
+      </ul>
+    </td>
+  </tr>
+</table>
+
+
+
+<hr>
+<p>Modified: 4 March 2016</p>
+  </body>
+</html>

Documentation/Intel/fsp1_1.html

@@ -0,0 +1,79 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>FSP 1.1</title>
+  </head>
+  <body>
+
+<h1>FSP 1.1</h1>
+
+<h2>x86 FSP 1.1 Integration</h2>
+<p>
+  Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC)
+  and board support.  The combined steps are listed
+  <a target="_blank" href="development.html">here</a>.
+  The development steps for FSP are listed below:
+</p>
+<ol>
+  <li><a href="#RequiredFiles">Required Files</a></li>
+  <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
+  <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
+</ol>
+
+<p>
+  FSP Documentation:
+</p>
+<ul>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
+</ul>
+
+<hr>
+<h2><a name="RequiredFiles">Required Files</a></h2>
+<h3><a name="corebootRequiredFiles">coreboot Required Files</a></h3>
+<ol>
+  <li>Create the following directories if they do not already exist:
+    <ul>
+      <li>src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;</li>
+      <li>3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;</li>
+    </ul>
+  </li>
+  <li>
+    The following files may need to be copied from the FSP build or release into the
+    directories above if they are not present or are out of date:
+    <ul>
+      <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;/FspUpdVpd.h</li>
+      <li>FSP.bin: 3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;/fsp.bin</li>
+    </ul>
+  </li>
+</ol>
+
+
+<hr>
+<h2><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h2>
+<p>
+  Add the FSP binary to the coreboot flash image using the following command:
+</p>
+<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b &lt;base address&gt; -f fsp.bin</code></pre>
+<p>
+  This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
+  FSP code for TempRamInit may be executed in place.
+</p>
+
+
+<hr>
+<h2><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h2>
+<p>
+  Set the following Kconfig values:
+</p>
+<ul>
+  <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
+  <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
+  <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
+  <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
+</ul>
+
+
+<hr>
+<p>Modified: 17 May 2016</p>
+  </body>
+</html>

Documentation/Intel/index.html

@@ -0,0 +1,128 @@
+<!DOCTYPE html>
+<html>
+  <head>
+    <title>Intel&reg; x86</title>
+  </head>
+  <body>
+
+<h1>Intel&reg; x86</h1>
+
+<h2>Intel&reg; x86 Boards</h2>
+<ul>
+  <li><a target="_blank" href="Board/galileo.html">Galileo</a></li>
+  <li><a target="_blank" href="http://wiki.minnowboard.org/Coreboot">MinnowBoard MAX</a></li>
+</ul>
+
+<h2>Intel&reg; x86 SoCs</h2>
+<ul>
+  <li><a target="_blank" href="SoC/quark.html">Quark&trade;</a></li>
+</ul>
+
+
+
+<hr>
+<h2>x86 coreboot Development</h2>
+<ul>
+  <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li>
+  <li><a target="_blank" href="development.html">Overall</a> development</li>
+  <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration
+  </li>
+  <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li>
+  <li><a target="_blank" href="Board/board.html">Board</a> support</li>
+</ul>
+
+
+
+<hr>
+<h2>Payload Development</h2>
+<ul>
+  <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>
+    <ul>
+      <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li>
+      <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li>
+      <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li>
+      <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li>
+    </ul>
+  </li>
+</ul>
+
+
+
+<hr>
+<h2><a name="Documentation">Documentation</a></h2>
+<ul>
+  <li>Intel&reg; 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li>
+  <li><a target="_blank" href="http://www.uefi.org/specifications">UEFI Specifications</a></li>
+</ul>
+
+<h3><a name="Edk2Documentation">EDK-II Documentation</a></h3>
+<ul>
+  <li>Build <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/Build_Spec_1_26.pdf">V1.26</a></li>
+  <li>Coding Standards <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf">V2.1</a></li>
+  <li>DEC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DEC_Spec_1_25.pdf">V1.25</a></li>
+  <li>DSC <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/DSC_Spec_1_26.pdf">V1.26</a></li>
+  <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/UEFI-Driver-Writer's-Guide">Driver Writer's Guide</a></li>
+  <li>Expression Syntax <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/ExpressionSyntax_1.1.pdf">V1.1</a></li>
+  <li>FDF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/FDF_Spec_1_26.pdf">V1.26</a></li>
+  <li>INF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/INF_Spec_1_25.pdf">V1.25</a></li>
+  <li>PCD <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/PCD_Infrastructure.pdf">PCD</a>V0.55</li>
+  <li>UNI <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/UNI_File_Spec_v1_2_Errata_A.pdf">V1.2 Errata A</a></li>
+  <li>VRF <a target="_blank" href="https://github.com/tianocore-docs/Docs/raw/master/Specifications/VFR_1_9.pdf">V1.9</a></li>
+</ul>
+
+<h3><a name="FspDocumentation">FSP Documentation</a></h3>
+<ul>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v2.pdf">V2.0</a></li>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
+  <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec.pdf">V1.0</a></li>
+</ul>
+
+<h3><a name="FeatureDocumentation">Feature Documentation</a></h3>
+<table border="1">
+  <tr bgcolor="#c0ffc0"><th>Feature/Specification</th><th>Linux View/Test</th><th>EDK-II View/Test</th></tr>
+  <tr>
+    <td><a target="_blank" href="https://en.wikipedia.org/wiki/E820">e820</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/dmesg.1.html">dmesg</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.uefi.org/specifications">ACPI</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/precise/man1/acpidump.1.html">acpidump</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="https://en.wikipedia.org/wiki/Extended_Display_Identification_Data">EDID</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/get-edid.1.html">get-edid | parse-edid</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.nxp.com/documents/user_manual/UM10204.pdf">I2C</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/get-edid.1.html">i2cdetect</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.intel.com/design/archives/processors/pro/docs/242016.htm">Multiprocessor</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man1/lscpu.1.html">lscpu</a></td>
+    <td>&nbsp;</td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="https://pcisig.com/specifications">PCI</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man8/lspci.8.html">lspci</a></td>
+    <td><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI_Shell_Spec_2_0.pdf">pci</a></td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf">SMBIOS</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/trusty/man8/dmidecode.8.html">dmidecode</a></td>
+    <td><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI_Shell_Spec_2_0.pdf">smbiosview</a></td>
+  </tr>
+  <tr>
+    <td><a target="_blank" href="http://www.usb.org/developers/docs/">USB</a></td>
+    <td><a target="_blank" href="http://manpages.ubuntu.com/manpages/xenial/man8/lsusb.8.html">lsusb</a></td>
+    <td>&nbsp;</td>
+  </tr>
+</table>
+
+<hr>
+<p>Modified: 18 June 2016</p>
+  </body>
+</html>

Documentation/Makefile

@@ -1,19 +1,17 @@
-## SPDX-License-Identifier: GPL-2.0-only
 #
 # Makefile for coreboot paper.
 # hacked together by Stefan Reinauer <stepan@openbios.org>
 #
 
-PDFLATEX  = pdflatex -t a4
-BUILDDIR ?= _build
+PDFLATEX=pdflatex -t a4
 
 FIGS=codeflow.pdf hypertransport.pdf
 
-all: sphinx corebootPortingGuide.pdf
+all: corebootPortingGuide.pdf
 
-SVG2PDF=$(shell command -v svg2pdf)
-INKSCAPE=$(shell command -v inkscape)
-CONVERT=$(shell command -v convert)
+SVG2PDF=$(shell which svg2pdf)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)
 
 codeflow.pdf: codeflow.svg
 ifneq ($(strip $(SVG2PDF)),)
@@ -33,9 +31,6 @@ else ifneq ($(strip $(CONVERT)),)
 	convert $< $@
 endif
 
-$(BUILDDIR):
-	mkdir -p $(BUILDDIR)
-
 corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 	# 2 times to make sure we have a current toc.
 	$(PDFLATEX) corebootBuildingGuide.tex
@@ -44,11 +39,11 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
 	$(PDFLATEX) corebootBuildingGuide.tex
 
-sphinx: $(BUILDDIR)
-	$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)"
+sphinx:
+	$(MAKE) -f Makefile.sphinx html
 
 clean-sphinx:
-	$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx clean
 
 clean: clean-sphinx
 	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
@@ -56,25 +51,5 @@ clean: clean-sphinx
 distclean: clean
 	rm -f corebootPortingGuide.pdf
 
-livesphinx: $(BUILDDIR)
-	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)" BUILDDIR="$(BUILDDIR)"
-
-test:
-	@echo "Test for logging purposes - Failing tests will not fail the build"
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
-
-help:
-	@echo "all            - Builds coreboot porting guide PDF (outdated)"
-	@echo "sphinx         - Builds html documentation in _build directory"
-	@echo "clean          - Cleans intermediate files"
-	@echo "clean-sphinx   - Removes sphinx output files"
-	@echo "distclean      - Removes PDF files as well"
-	@echo "test           - Runs documentation tests"
-	@echo
-	@echo "  Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
-	@echo
-	@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
-
-.phony: help livesphinx sphinx test
-.phony: distclean clean clean-sphinx
+livesphinx:
+	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)"

Documentation/Makefile.sphinx

@@ -1,4 +1,3 @@
-## SPDX-License-Identifier: GPL-2.0-only
 # Makefile for Sphinx documentation
 #
 

Documentation/RFC/chip.tex

@@ -7,7 +7,7 @@ change.
 
 \section{Scope}
 This document defines how LinuxBIOS programmers can specify chips that
-are used, specified, and initialized. The current scope is for superio
+are used, specified, and initalized. The current scope is for superio
 chips, but the architecture should allow for specification of other chips such
 as southbridges. Multiple chips of same or different type are supported.
 

Documentation/RFC/intel-gpio-cleanup.md

@@ -1,98 +0,0 @@
-# Background
-
-CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
-done") introduced a workaround in coreboot for `soc/intel/cannonlake`
-platforms to save and restore GPIO configuration performed by
-mainboard across call to FSP Silicon Init (FSP-S). This workaround was
-required because FSP-S was configuring GPIOs differently than
-mainboard resulting in boot and runtime issues because of
-misconfigured GPIOs. This issue was observed on `google/hatch`
-mainboard and was raised with Intel to get the FSP behavior
-fixed. Until the fix in FSP was available, this workaround was used to
-ensure that the mainboards can operate correctly and were not impacted
-by the GPIO misconfiguration in FSP-S.
-
-The issues observed on `google/hatch` mainboard were fixed by adding
-(if required) and initializing appropriate FSP UPDs. This UPD
-initialization ensured that FSP did not configure any GPIOs
-differently than the mainboard configuration. Fixes included:
- * CB:31375 ("soc/intel/cannonlake: Configure serial debug uart")
- * CB:31520 ("soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports")
- * CB:32176 ("mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip select")
- * CB:34900 ("soc/intel/cnl: Add provision to configure SD controller write protect pin")
-
-With the above changes merged, it was verified on `google/hatch`
-mainboard that the workaround for GPIO reconfiguration was not
-needed. However, at the time, we missed dropping the workaround in
-'soc/intel/cannonlake`. Currently, this workaround is used by the
-following mainboards:
- * `google/drallion`
- * `google/sarien`
- * `purism/librem_cnl`
- * `system76/lemp9`
-
-As verified on `google/hatch`, FSP v1263 included all UPD additions
-that were required for addressing this issue.
-
-# Proposal
-
-* The workaround can be safely dropped from `soc/intel/cannonlake`
-  only after the above mainboards have verified that FSP-S does not
-  configure any pads differently than the mainboard in coreboot. Since
-  the fix included initialization of FSP UPDs correctly, the above
-  mainboards can use the following diff to check what pads change
-  after FSP-S has run:
-
-```
-diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
-index 28e78fb366..0cce41b316 100644
---- a/src/soc/intel/common/block/gpio/gpio.c
-+++ b/src/soc/intel/common/block/gpio/gpio.c
-@@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
-                /* Patch GPIO settings for SoC specifically */
-                soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
-
--               if (CONFIG(DEBUG_GPIO))
-+               if (soc_pad_conf != pad_conf)
-                        printk(BIOS_DEBUG,
--                       "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
--                       " : 0x%08x]\n",
-+                       "%d: gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
-+                       " : 0x%08x]\n", cfg->pad,
-                        comm->port, relative_pad_in_comm(comm, cfg->pad), i,
-                        pad_conf,/* old value */
-                        cfg->pad_config[i],/* value passed from gpio table */
-```
-
-Depending upon the pads that are misconfigured by FSP-S, these
-mainboards will have to set UPDs appropriately. Once this is verified
-by the above mainboards, the workaround implemented in CB:31250 can be
-dropped.
-
-* The fix implemented in FSP/coreboot for `soc/intel/cannonlake`
-  platforms is not really the right long term solution for the
-  problem. Ideally, FSP should not be touching any GPIO configuration
-  and letting coreboot configure the pads as per mainboard
-  design. This recommendation was accepted and implemented by Intel
-  starting with Jasper Lake and Tiger Lake platforms using a single
-  UPD `GpioOverride` that coreboot can set so that FSP does not change
-  any GPIO configuration. However, this implementation is not
-  backported to any older platforms. Given the issues that we have
-  observed across different platforms, the second proposal is to:
-
-  - Add a Kconfig `CHECK_GPIO_CONFIG_CHANGES` that enables checks
-    in coreboot to stash GPIO pad configuration before various calls
-    to FSP and compares the configuration on return from FSP.
-  - This will have to be implemented as part of
-    drivers/intel/fsp/fsp2_0/ to check for the above config selection
-    and make callbacks `gpio_snapshot()` and `gpio_verify_snapshot()`
-    to identify and print information about pads that have changed
-    configuration after calls to FSP.
-  - This config can be kept disabled by default and mainboard
-    developers can enable them as and when required for debug.
-  - This will be helpful not just for the `soc/intel/cannonlake`
-    platforms that want to get rid of the above workaround, but also
-    for all future platforms using FSP to identify and catch any GPIO
-    misconfigurations that might slip in to any platforms (in case the
-    `GpioOverride` UPD is not honored by any code path within FSP).
-

Documentation/acpi/devicetree.md

@@ -0,0 +1,234 @@
+# Adding new devices to a device tree
+
+## Introduction
+
+ACPI exposes a platform-independent interface for operating systems to perform
+power management and other platform-level functions.  Some operating systems
+also use ACPI to enumerate devices that are not immediately discoverable, such
+as those behind I2C or SPI busses (in contrast to PCI).  This document discusses
+the way that coreboot uses the concept of a "device tree" to generate ACPI
+tables for usage by the operating system.
+
+## Devicetree and overridetree (if applicable)
+
+For mainboards that are organized around a "reference board" or "baseboard"
+model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
+typically a devicetree.cb file that all boards share, and any differences for a
+specific board ("variant") are captured in the overridetree.cb file.  Any
+settings changed in the overridetree take precedence over those in the main
+devicetree.  Note, not all mainboards will have the devicetree/overridetree
+distinction, and may only have a devicetree.cb file.  Or you can always just
+write the ASL (ACPI Source Language) code yourself.
+
+## Device drivers
+
+Let's take a look at an example entry from
+``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
+
+```
+device pci 15.0 on
+	chip drivers/i2c/generic
+		register "hid" = ""ELAN0000""
+		register "desc" = ""ELAN Touchpad""
+		register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+		register "wake" = "GPE0_DW0_21"
+		device i2c 15 on end
+	end
+end # I2C #0
+```
+
+When this entry is processed during ramstage, it will create a device in the
+ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
+generation routines in coreboot actually generate the raw bytecode that
+represents the device's structure, but looking at ASL code is easier to
+understand; see below for what the disassembled bytecode looks like:
+
+```
+Scope (\_SB.PCI0.I2C0)
+{
+    Device (D015)
+    {
+        Name (_HID, "ELAN0000")  // _HID: Hardware ID
+        Name (_UID, Zero)  // _UID: Unique ID
+        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
+        Method (_STA, 0, NotSerialized)  // _STA: Status
+        {
+            Return (0x0F)
+        }
+        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+        {
+            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                0x00, ResourceConsumer, , Exclusive, )
+            Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
+            {
+                0x0000002D,
+            }
+        })
+        Name (_S0W, 0x04)  // _S0W: S0 Device Wake State
+        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
+        {
+            0x15, // GPE #21
+            0x03  // Sleep state S3
+        })
+    }
+}
+```
+
+You can see it generates _HID, _UID, _DDN, _STA, _CRS, _S0W, and _PRW
+names/methods in the Device's scope.
+
+## Utilizing a device driver
+
+The device driver must be enabled for your build.  There will be a CONFIG option
+in the Kconfig file in the directory that the driver is in (e.g.,
+``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
+CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
+mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
+to be compiled into your build.
+
+## Diving into the above example:
+
+Let's take a look at how the devicetree language corresponds to the generated
+ASL.
+
+First, note this:
+
+```
+    chip drivers/i2c/generic
+```
+
+This means that the device driver we're using has a corresponding structure,
+located at ``src/drivers/i2c/generic/chip.h``, named **struct
+drivers_i2c_generic_config** and it contains many properties you can specify to
+be included in the ACPI table.
+
+### hid
+
+```
+    register "hid" = ""ELAN0000""
+```
+
+This corresponds to **const char *hid** in the struct.  In the ACPI ASL, it
+translates to:
+
+```
+    Name (_HID, "ELAN0000") // _HID: Hardware ID
+```
+
+under the device.  **This property is used to match the device to its driver
+during enumeration in the OS.**
+
+### desc
+
+```
+    register "desc" = ""ELAN Touchpad""
+```
+
+corresponds to **const char *desc** and in ASL:
+
+```
+    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
+```
+
+### irq
+
+It also adds the interrupt,
+
+```
+    Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
+    {
+        0x0000002D,
+    }
+```
+
+which comes from:
+
+```
+    register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
+```
+
+The GPIO pin IRQ settings control the "Edge", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (edge means it is an edge-triggered
+interrupt as opposed to level-triggered; active low means the interrupt is
+triggered on a falling edge).
+
+Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO
+will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
+source.  Also note that the IRQ names are SoC-specific, and you will need to
+find the names in your SoC's header file.  The ACPI_* macros are defined in
+``src/arch/x86/include/acpi/acpi_device.h``.
+
+Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
+This is often done in a mainboard-specific file named ``gpio.c``.
+
+### wake
+
+The last register is:
+
+```
+    register "wake" = "GPE0_DW0_21"
+```
+
+which indicates that the method of waking the system using the touchpad will be
+through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
+this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
+elsewhere in the devicetree.
+
+The last bit of the definition of that device includes:
+
+```
+    device i2c 15 on end
+```
+
+which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
+meaning it will be exposed in the ACPI table.  The PCI device that the
+controller is located in determines which I2C bus the device is expected to be
+found on.  In this example, this is I2C bus 0.  This also determines the ACPI
+"Scope" that the device names and methods will live under, in this case
+"\_SB.PCI0.I2C0".
+
+## Other auto-generated names
+
+(see [ACPI specification
+6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
+for more details on ACPI methods)
+
+### _S0W (S0 Device Wake State)
+_S0W indicates the deepest S0 sleep state this device can wake itself from,
+which in this case is 4, representing _D3cold_.
+
+### _PRW (Power Resources for Wake)
+_PRW indicates the power resources and events required for wake.  There are no
+dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
+as well as the deepest sleep state supporting waking the system (3), which is
+S3.
+
+### _STA (Status)
+The _STA method is generated automatically, and its values, 0xF, indicates the
+following:
+
+    Bit [0] – Set if the device is present.
+    Bit [1] – Set if the device is enabled and decoding its resources.
+    Bit [2] – Set if the device should be shown in the UI.
+    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
+
+### _CRS (Current resource settings)
+The _CRS method is generated automatically, as the driver knows it is an I2C
+controller, and so specifies how to configure the controller for proper
+operation with the touchpad.
+
+```
+Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+{
+    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
+                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
+                    0x00, ResourceConsumer, , Exclusive, )
+```
+
+## Notes
+
+ - **All fields that are left unspecified in the devicetree are initialized to
+   zero.**
+ - **All devices in devicetrees end up in the SSDT table, and are generated in
+   coreboot's ramstage**

Documentation/acpi/gpio.md

@@ -84,6 +84,15 @@ the raw Rx gpio value.
 
 ## Implementation Details
 
+ACPI library in coreboot will provide weak definitions for all the
+above functions with error messages indicating that these functions
+are being used. This allows drivers to conditionally make use of GPIOs
+based on device-tree entries or any other config option. It is
+recommended that the SoC code in coreboot should provide
+implementations of all the above functions generating ACPI AML code
+irrespective of them being used in any driver. This allows mainboards
+to use any drivers and take advantage of this common infrastructure.
+
 Platforms are restricted to using Local5, Local6 and Local7 variables
 only in implementations of the above functions. Any AML methods called
 by the above functions do not have any such restrictions on use of
@@ -150,6 +159,7 @@ for the GPIO.
 	 */
 	acpigen_write_if_and(Local5, TX_BIT);
 	acpigen_write_store_args(ONE_OP, LOCAL0_OP);
+	acpigen_pop_len();
 	acpigen_write_else();
 	acpigen_write_store_args(ZERO_OP, LOCAL0_OP);
 	acpigen_pop_len();

Documentation/acpi/index.md

@@ -11,12 +11,6 @@ upwards.
 
 - [GPIO toggling in ACPI AML](gpio.md)
 
-## Windows-specific ACPI documentation
+## devicetree
 
-- [Windows-specific documentation](windows.md)
-
-##  ACPI specification - Useful links
-
-- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
-- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
-- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)
+- [Adding devices to a device tree](devicetree.md)

Documentation/acpi/windows.md

@@ -1,9 +0,0 @@
-# Testing ACPI changes under Windows
-
-When testing ACPI changes in coreboot against Windows 8 or newer, beware that
-during a normal boot after a clean shutdown, Windows will use the fast startup
-mechanism which results in it not evaluating the changed ACPI code but instead
-using some cached version which won't include the changes that were supposed to
-be tested. In order for Windows to actually use the new ACPI tables, either
-disable the fast startup or just tell Windows to do a reboot which will make it
-read and use the ACPI tables in memory instead of an outdated cached version.

Documentation/arch/x86/index.md

@@ -26,7 +26,9 @@ In order to add support for x86_64 the following assumptions were made:
 * A stage can install new page tables in RAM
 
 ## Page tables
-A `pagetables` cbfs file is generated based on an assembly file.
+Page tables are generated by a tool in `util/pgtblgen/pgtblgen`. It writes
+the page tables to a file which is then included into the CBFS as file called
+`pagetables`.
 
 To generate the static page tables it must know the physical address where to
 place the file.
@@ -90,6 +92,6 @@ Here's a list of known issues:
   page tables in ROM will be loaded and used, which breaks code and data as
   the page table doesn't contain the expected data. This in turn leads to
   undefined behaviour whenever the 'wrong' address is being read.
-* Disabling paging in compatibility mode crashes the CPU.
-* Returning from long mode to compatibility mode crashes the CPU.
+* Disabling paging in compability mode crashes the CPU.
+* Returning from long mode to compability mode crashes the CPU.
 * Entering long mode crashes on AMD host platforms.

Documentation/coding_style.md

@@ -0,0 +1,938 @@
+# Coding Style
+
+This is a short document describing the preferred coding style for the
+coreboot project. It is in many ways exactly the same as the Linux
+kernel coding style. In fact, most of this document has been copied from
+the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD)
+
+Please at least consider the points made here.
+
+First off, I'd suggest printing out a copy of the GNU coding standards,
+and NOT read it. Burn them, it's a great symbolic gesture.
+
+Anyway, here goes:
+
+## Indentation
+
+Tabs are 8 characters, and thus indentations are also 8 characters.
+There are heretic movements that try to make indentations 4 (or even 2!)
+characters deep, and that is akin to trying to define the value of PI to
+be 3.
+
+Rationale: The whole idea behind indentation is to clearly define where
+a block of control starts and ends. Especially when you've been looking
+at your screen for 20 straight hours, you'll find it a lot easier to
+see how the indentation works if you have large indentations.
+
+Now, some people will claim that having 8-character indentations makes
+the code move too far to the right, and makes it hard to read on a
+80-character terminal screen. The answer to that is that if you need
+more than 3 levels of indentation, you're screwed anyway, and should
+fix your program.
+
+In short, 8-char indents make things easier to read, and have the added
+benefit of warning you when you're nesting your functions too deep.
+Heed that warning.
+
+The preferred way to ease multiple indentation levels in a switch
+statement is to align the "switch" and its subordinate "case" labels
+in the same column instead of "double-indenting" the "case" labels.
+E.g.:
+
+```c
+switch (suffix) {
+case 'G':
+case 'g':
+	mem <<= 30;
+	break;
+case 'M':
+case 'm':
+	mem <<= 20;
+	break;
+case 'K':
+case 'k':
+	mem <<= 10;
+	/* fall through */
+default:
+	break;
+}
+```
+
+Don't put multiple statements on a single line unless you have
+something to hide:
+
+```c
+if (condition) do_this;
+  do_something_everytime;
+```
+
+Don't put multiple assignments on a single line either. Kernel coding
+style is super simple. Avoid tricky expressions.
+
+Outside of comments, documentation and except in Kconfig, spaces are
+never used for indentation, and the above example is deliberately
+broken.
+
+Get a decent editor and don't leave whitespace at the end of lines.
+
+## Breaking long lines and strings
+
+Coding style is all about readability and maintainability using commonly
+available tools.
+
+The limit on the length of lines is 96 columns and this is a strongly
+preferred limit.
+
+Statements longer than 96 columns will be broken into sensible chunks,
+unless exceeding 96 columns significantly increases readability and does
+not hide information. Descendants are always substantially shorter than
+the parent and are placed substantially to the right. The same applies
+to function headers with a long argument list. However, never break
+user-visible strings such as printk messages, because that breaks the
+ability to grep for them.
+
+## Placing Braces and Spaces
+
+The other issue that always comes up in C styling is the placement of
+braces. Unlike the indent size, there are few technical reasons to
+choose one placement strategy over the other, but the preferred way, as
+shown to us by the prophets Kernighan and Ritchie, is to put the opening
+brace last on the line, and put the closing brace first, thusly:
+
+```c
+if (x is true) {
+	we do y
+}
+```
+
+This applies to all non-function statement blocks (if, switch, for,
+while, do). E.g.:
+
+```c
+switch (action) {
+case KOBJ_ADD:
+	return "add";
+case KOBJ_REMOVE:
+	return "remove";
+case KOBJ_CHANGE:
+	return "change";
+default:
+	return NULL;
+}
+```
+
+However, there is one special case, namely functions: they have the
+opening brace at the beginning of the next line, thus:
+
+```c
+int function(int x)
+{
+	body of function
+}
+```
+
+Heretic people all over the world have claimed that this inconsistency
+is ... well ... inconsistent, but all right-thinking people know that
+(a) K&R are _right_ and (b) K&R are right. Besides, functions are
+special anyway (you can't nest them in C).
+
+Note that the closing brace is empty on a line of its own, _except_ in
+the cases where it is followed by a continuation of the same statement,
+ie a "while" in a do-statement or an "else" in an if-statement, like
+this:
+
+```c
+do {
+	body of do-loop
+} while (condition);
+```
+
+and
+
+```c
+if (x == y) {
+	..
+} else if (x > y) {
+	...
+} else {
+	....
+}
+```
+
+Rationale: K&R.
+
+Also, note that this brace-placement also minimizes the number of empty
+(or almost empty) lines, without any loss of readability. Thus, as the
+supply of new-lines on your screen is not a renewable resource (think
+25-line terminal screens here), you have more empty lines to put
+comments on.
+
+Do not unnecessarily use braces where a single statement will do.
+
+```c
+if (condition)
+	action();
+```
+
+and
+
+```c
+if (condition)
+	do_this();
+else
+	do_that();
+```
+
+This does not apply if only one branch of a conditional statement is a
+single statement; in the latter case use braces in both branches:
+
+```c
+if (condition) {
+	do_this();
+	do_that();
+} else {
+	otherwise();
+}
+```
+
+### Spaces
+
+Linux kernel style for use of spaces depends (mostly) on
+function-versus-keyword usage. Use a space after (most) keywords. The
+notable exceptions are sizeof, typeof, alignof, and __attribute__,
+which look somewhat like functions (and are usually used with
+parentheses in Linux, although they are not required in the language, as
+in: "sizeof info" after "struct fileinfo info;" is declared).
+
+So use a space after these keywords:
+
+```
+if, switch, case, for, do, while
+```
+
+but not with sizeof, typeof, alignof, or __attribute__. E.g.,
+
+```c
+s = sizeof(struct file);
+```
+
+Do not add spaces around (inside) parenthesized expressions. This
+example is
+
+-   bad*:
+
+```c
+s = sizeof( struct file );
+```
+
+When declaring pointer data or a function that returns a pointer type,
+the preferred use of '*' is adjacent to the data name or function
+name and not adjacent to the type name. Examples:
+
+```c
+char *linux_banner;
+unsigned long long memparse(char *ptr, char **retptr);
+char *match_strdup(substring_t *s);
+```
+
+Use one space around (on each side of) most binary and ternary
+operators, such as any of these:
+
+```
+=  +  -  <  >  *  /  %  |  &  ^  <=  >=  ==  !=  ?  :
+```
+
+but no space after unary operators:
+
+```
+&  *  +  -  ~  !  sizeof  typeof  alignof  __attribute__  defined
+```
+
+no space before the postfix increment & decrement unary operators:
+
+```
+++  --
+```
+
+no space after the prefix increment & decrement unary operators:
+
+```
+++  --
+```
+
+and no space around the '.' and "->" structure member operators.
+
+Do not leave trailing whitespace at the ends of lines. Some editors with
+"smart" indentation will insert whitespace at the beginning of new
+lines as appropriate, so you can start typing the next line of code
+right away. However, some such editors do not remove the whitespace if
+you end up not putting a line of code there, such as if you leave a
+blank line. As a result, you end up with lines containing trailing
+whitespace.
+
+Git will warn you about patches that introduce trailing whitespace, and
+can optionally strip the trailing whitespace for you; however, if
+applying a series of patches, this may make later patches in the series
+fail by changing their context lines.
+
+### Naming
+
+C is a Spartan language, and so should your naming be. Unlike Modula-2
+and Pascal programmers, C programmers do not use cute names like
+ThisVariableIsATemporaryCounter. A C programmer would call that variable
+"tmp", which is much easier to write, and not the least more difficult
+to understand.
+
+HOWEVER, while mixed-case names are frowned upon, descriptive names for
+global variables are a must. To call a global function "foo" is a
+shooting offense.
+
+GLOBAL variables (to be used only if you _really_ need them) need to
+have descriptive names, as do global functions. If you have a function
+that counts the number of active users, you should call that
+"count_active_users()" or similar, you should _not_ call it
+"cntusr()".
+
+Encoding the type of a function into the name (so-called Hungarian
+notation) is brain damaged - the compiler knows the types anyway and can
+check those, and it only confuses the programmer. No wonder MicroSoft
+makes buggy programs.
+
+LOCAL variable names should be short, and to the point. If you have some
+random integer loop counter, it should probably be called "i". Calling
+it "loop_counter" is non-productive, if there is no chance of it
+being mis-understood. Similarly, "tmp" can be just about any type of
+variable that is used to hold a temporary value.
+
+If you are afraid to mix up your local variable names, you have another
+problem, which is called the function-growth-hormone-imbalance syndrome.
+See chapter 6 (Functions).
+
+## Typedefs
+
+Please don't use things like "vps_t".
+
+It's a _mistake_ to use typedef for structures and pointers. When you
+see a
+
+```c
+vps_t a;
+```
+
+in the source, what does it mean?
+
+In contrast, if it says
+
+```c
+struct virtual_container *a;
+```
+
+you can actually tell what "a" is.
+
+Lots of people think that typedefs "help readability". Not so. They
+are useful only for:
+
+(a) totally opaque objects (where the typedef is actively used to
+_hide_ what the object is).
+
+Example: "pte_t" etc. opaque objects that you can only access using
+the proper accessor functions.
+
+NOTE! Opaqueness and "accessor functions" are not good in themselves.
+The reason we have them for things like pte_t etc. is that there really
+is absolutely _zero_ portably accessible information there.
+
+(b) Clear integer types, where the abstraction _helps_ avoid confusion
+whether it is "int" or "long".
+
+u8/u16/u32 are perfectly fine typedefs, although they fit into category
+(d) better than here.
+
+NOTE! Again - there needs to be a _reason_ for this. If something is
+"unsigned long", then there's no reason to do
+
+```c
+typedef unsigned long myflags_t;
+```
+
+but if there is a clear reason for why it under certain circumstances
+might be an "unsigned int" and under other configurations might be
+"unsigned long", then by all means go ahead and use a typedef.
+
+(c) when you use sparse to literally create a _new_ type for
+type-checking.
+
+(d) New types which are identical to standard C99 types, in certain
+exceptional circumstances.
+
+Although it would only take a short amount of time for the eyes and
+brain to become accustomed to the standard types like 'uint32_t',
+some people object to their use anyway.
+
+Therefore, the Linux-specific 'u8/u16/u32/u64' types and their signed
+equivalents which are identical to standard types are permitted --
+although they are not mandatory in new code of your own.
+
+When editing existing code which already uses one or the other set of
+types, you should conform to the existing choices in that code.
+
+(e) Types safe for use in userspace.
+
+In certain structures which are visible to userspace, we cannot require
+C99 types and cannot use the 'u32' form above. Thus, we use __u32
+and similar types in all structures which are shared with userspace.
+
+Maybe there are other cases too, but the rule should basically be to
+NEVER EVER use a typedef unless you can clearly match one of those
+rules.
+
+In general, a pointer, or a struct that has elements that can reasonably
+be directly accessed should _never_ be a typedef.
+
+## Functions
+
+Functions should be short and sweet, and do just one thing. They should
+fit on one or two screenfuls of text (the ISO/ANSI screen size is 80x24,
+as we all know), and do one thing and do that well.
+
+The maximum length of a function is inversely proportional to the
+complexity and indentation level of that function. So, if you have a
+conceptually simple function that is just one long (but simple)
+case-statement, where you have to do lots of small things for a lot of
+different cases, it's OK to have a longer function.
+
+However, if you have a complex function, and you suspect that a
+less-than-gifted first-year high-school student might not even
+understand what the function is all about, you should adhere to the
+maximum limits all the more closely. Use helper functions with
+descriptive names (you can ask the compiler to in-line them if you think
+it's performance-critical, and it will probably do a better job of it
+than you would have done).
+
+Another measure of the function is the number of local variables. They
+shouldn't exceed 5-10, or you're doing something wrong. Re-think the
+function, and split it into smaller pieces. A human brain can generally
+easily keep track of about 7 different things, anything more and it gets
+confused. You know you're brilliant, but maybe you'd like to
+understand what you did 2 weeks from now.
+
+In source files, separate functions with one blank line. If the function
+is exported, the EXPORT* macro for it should follow immediately after
+the closing function brace line. E.g.:
+
+```c
+int system_is_up(void)
+{
+	return system_state == SYSTEM_RUNNING;
+}
+EXPORT_SYMBOL(system_is_up);
+```
+
+In function prototypes, include parameter names with their data types.
+Although this is not required by the C language, it is preferred in
+Linux because it is a simple way to add valuable information for the
+reader.
+
+## Centralized exiting of functions
+
+Albeit deprecated by some people, the equivalent of the goto statement
+is used frequently by compilers in form of the unconditional jump
+instruction.
+
+The goto statement comes in handy when a function exits from multiple
+locations and some common work such as cleanup has to be done. If there
+is no cleanup needed then just return directly.
+
+The rationale is:
+
+-   unconditional statements are easier to understand and follow
+-   nesting is reduced
+-   errors by not updating individual exit points when making
+    modifications are prevented
+-   saves the compiler work to optimize redundant code away ;)
+
+```c
+int fun(int a)
+{
+	int result = 0;
+	char *buffer = kmalloc(SIZE);
+
+	if (buffer == NULL)
+		return -ENOMEM;
+
+	if (condition1) {
+		while (loop1) {
+			...
+		}
+		result = 1;
+		goto out;
+	}
+	...
+	out:
+	kfree(buffer);
+	return result;
+}
+```
+
+## Commenting
+
+Comments are good, but there is also a danger of over-commenting. NEVER
+try to explain HOW your code works in a comment: it's much better to
+write the code so that the _working_ is obvious, and it's a waste of
+time to explain badly written code.
+
+Generally, you want your comments to tell WHAT your code does, not HOW.
+Also, try to avoid putting comments inside a function body: if the
+function is so complex that you need to separately comment parts of it,
+you should probably go back to chapter 6 for a while. You can make small
+comments to note or warn about something particularly clever (or ugly),
+but try to avoid excess. Instead, put the comments at the head of the
+function, telling people what it does, and possibly WHY it does it.
+
+When commenting the kernel API functions, please use the kernel-doc
+format. See the files Documentation/kernel-doc-nano-HOWTO.txt and
+scripts/kernel-doc for details.
+
+coreboot style for comments is the C89 "/* ... */" style. You may
+use C99-style "// ..." comments.
+
+The preferred style for *short* (multi-line) comments is:
+
+```c
+/* This is the preferred style for short multi-line
+   comments in the Linux kernel source code.
+   Please use it consistently. */
+```
+
+The preferred style for *long* (multi-line) comments is:
+
+```c
+/*
+ * This is the preferred style for multi-line
+ * comments in the Linux kernel source code.
+ * Please use it consistently.
+ *
+ * Description:  A column of asterisks on the left side,
+ * with beginning and ending almost-blank lines.
+ */
+```
+
+It's also important to comment data, whether they are basic types or
+derived types. To this end, use just one data declaration per line (no
+commas for multiple data declarations). This leaves you room for a small
+comment on each item, explaining its use.
+
+## You've made a mess of it
+That's OK, we all do. You've probably been told by your long-time Unix user
+helper that "GNU emacs" automatically formats the C sources for you, and
+you've noticed that yes, it does do that, but the defaults it uses are less
+than desirable (in fact, they are worse than random typing - an infinite
+number of monkeys typing into GNU emacs would never make a good program).
+
+So, you can either get rid of GNU emacs, or change it to use saner values.
+To do the latter, you can stick the following in your .emacs file: 
+
+```lisp
+(defun c-lineup-arglist-tabs-only (ignored)
+  "Line up argument lists by tabs, not spaces"
+  (let* ((anchor (c-langelem-pos c-syntactic-element))
+	 (column (c-langelem-2nd-pos c-syntactic-element))
+	 (offset (- (1+ column) anchor))
+	 (steps (floor offset c-basic-offset)))
+    (* (max steps 1)
+       c-basic-offset)))
+
+(add-hook 'c-mode-common-hook
+          (lambda ()
+            ;; Add kernel style
+            (c-add-style
+             "linux-tabs-only"
+             '("linux" (c-offsets-alist
+                        (arglist-cont-nonempty
+                         c-lineup-gcc-asm-reg
+                         c-lineup-arglist-tabs-only))))))
+
+(add-hook 'c-mode-hook
+          (lambda ()
+            (let ((filename (buffer-file-name)))
+              ;; Enable kernel mode for the appropriate files
+              (when (and filename
+                         (string-match (expand-file-name "~/src/linux-trees")
+                                        filename))
+                (setq indent-tabs-mode t)
+                (c-set-style "linux-tabs-only")))))
+```
+
+This will make emacs go better with the kernel coding style for C files
+below ~/src/linux-trees.
+
+But even if you fail in getting emacs to do sane formatting, not
+everything is lost: use "indent".
+
+Now, again, GNU indent has the same brain-dead settings that GNU emacs
+has, which is why you need to give it a few command line options.
+However, that's not too bad, because even the makers of GNU indent
+recognize the authority of K&R (the GNU people aren't evil, they are
+just severely misguided in this matter), so you just give indent the
+options "-kr -i8" (stands for "K&R, 8 character indents"), or use
+"scripts/Lindent", which indents in the latest style.
+
+"indent" has a lot of options, and especially when it comes to comment
+re-formatting you may want to take a look at the man page. But remember:
+"indent" is not a fix for bad programming.
+
+## Kconfig configuration files
+
+For all of the Kconfig* configuration files throughout the source tree,
+the indentation is somewhat different. Lines under a "config"
+definition are indented with one tab, while help text is indented an
+additional two spaces. Example:
+
+```kconfig
+config AUDIT
+	bool "Auditing support"
+	depends on NET
+	help
+	  Enable auditing infrastructure that can be used with another
+	  kernel subsystem, such as SELinux (which requires this for
+	  logging of avc messages output).  Does not do system-call
+	  auditing without CONFIG_AUDITSYSCALL.
+```
+
+Seriously dangerous features (such as write support for certain
+filesystems) should advertise this prominently in their prompt string:
+
+```kconfig
+config ADFS_FS_RW
+	bool "ADFS write support (DANGEROUS)"
+	depends on ADFS_FS
+	...
+```
+
+For full documentation on the configuration files, see the file
+Documentation/kbuild/kconfig-language.txt.
+
+Data structures
+---------------
+
+Data structures that have visibility outside the single-threaded
+environment they are created and destroyed in should always have
+reference counts. In the kernel, garbage collection doesn't exist (and
+outside the kernel garbage collection is slow and inefficient), which
+means that you absolutely _have_ to reference count all your uses.
+
+Reference counting means that you can avoid locking, and allows multiple
+users to have access to the data structure in parallel - and not having
+to worry about the structure suddenly going away from under them just
+because they slept or did something else for a while.
+
+Note that locking is _not_ a replacement for reference counting.
+Locking is used to keep data structures coherent, while reference
+counting is a memory management technique. Usually both are needed, and
+they are not to be confused with each other.
+
+Many data structures can indeed have two levels of reference counting,
+when there are users of different "classes". The subclass count counts
+the number of subclass users, and decrements the global count just once
+when the subclass count goes to zero.
+
+Examples of this kind of "multi-level-reference-counting" can be found
+in memory management ("struct mm_struct": mm_users and mm_count),
+and in filesystem code ("struct super_block": s_count and
+s_active).
+
+Remember: if another thread can find your data structure, and you don't
+have a reference count on it, you almost certainly have a bug.
+
+Macros, Enums and RTL
+---------------------
+
+Names of macros defining constants and labels in enums are capitalized.
+
+```c
+#define CONSTANT 0x12345
+```
+
+Enums are preferred when defining several related constants.
+
+CAPITALIZED macro names are appreciated but macros resembling functions
+may be named in lower case.
+
+Generally, inline functions are preferable to macros resembling
+functions.
+
+Macros with multiple statements should be enclosed in a do - while
+block:
+
+```c
+#define macrofun(a, b, c)   \
+    do {                    \
+        if (a == 5)         \
+            do_this(b, c);  \
+    } while (0)
+```
+
+Things to avoid when using macros:
+
+1) macros that affect control flow:
+
+```c
+#define FOO(x)              \
+    do {                        \
+	    if (blah(x) < 0)        \
+		    return -EBUGGERED;  \
+    } while(0)
+```
+
+is a *very* bad idea. It looks like a function call but exits the
+"calling" function; don't break the internal parsers of those who
+will read the code.
+
+2) macros that depend on having a local variable with a magic name:
+
+```c
+#define FOO(val) bar(index, val)
+```
+
+might look like a good thing, but it's confusing as hell when one reads
+the code and it's prone to breakage from seemingly innocent changes.
+
+3) macros with arguments that are used as l-values: FOO(x) = y; will
+bite you if somebody e.g. turns FOO into an inline function.
+
+4) forgetting about precedence: macros defining constants using
+expressions must enclose the expression in parentheses. Beware of
+similar issues with macros using parameters.
+
+```c
+#define CONSTANT 0x4000
+#define CONSTEXP (CONSTANT | 3)
+```
+
+The cpp manual deals with macros exhaustively. The gcc internals manual
+also covers RTL which is used frequently with assembly language in the
+kernel.
+
+Printing kernel messages
+------------------------
+
+Kernel developers like to be seen as literate. Do mind the spelling of
+kernel messages to make a good impression. Do not use crippled words
+like "dont"; use "do not" or "don't" instead. Make the messages
+concise, clear, and unambiguous.
+
+Kernel messages do not have to be terminated with a period.
+
+Printing numbers in parentheses (%d) adds no value and should be
+avoided.
+
+There are a number of driver model diagnostic macros in
+<linux/device.h> which you should use to make sure messages are
+matched to the right device and driver, and are tagged with the right
+level: dev_err(), dev_warn(), dev_info(), and so forth. For messages
+that aren't associated with a particular device, <linux/printk.h>
+defines pr_debug() and pr_info().
+
+Coming up with good debugging messages can be quite a challenge; and
+once you have them, they can be a huge help for remote troubleshooting.
+Such messages should be compiled out when the DEBUG symbol is not
+defined (that is, by default they are not included). When you use
+dev_dbg() or pr_debug(), that's automatic. Many subsystems have
+Kconfig options to turn on -DDEBUG. A related convention uses
+VERBOSE_DEBUG to add dev_vdbg() messages to the ones already enabled
+by DEBUG.
+
+Allocating memory
+-----------------
+
+coreboot provides a single general purpose memory allocator: malloc()
+
+The preferred form for passing a size of a struct is the following:
+
+```c
+p = malloc(sizeof(*p));
+```
+
+The alternative form where struct name is spelled out hurts readability
+and introduces an opportunity for a bug when the pointer variable type
+is changed but the corresponding sizeof that is passed to a memory
+allocator is not.
+
+Casting the return value which is a void pointer is redundant. The
+conversion from void pointer to any other pointer type is guaranteed by
+the C programming language.
+
+You should contain your memory usage to stack variables whenever
+possible. Only use malloc() as a last resort. In ramstage, you may also
+be able to get away with using static variables. Never use malloc()
+outside of ramstage.
+
+Since coreboot only runs for a very short time, there is no memory
+deallocator, although a corresponding free() is offered. It is a no-op.
+Use of free() is not required though it is accepted. It is useful when
+sharing code with other codebases that make use of free().
+
+The inline disease
+------------------
+
+There appears to be a common misperception that gcc has a magic "make
+me faster" speedup option called "inline". While the use of inlines
+can be appropriate (for example as a means of replacing macros, see
+Chapter 12), it very often is not. Abundant use of the inline keyword
+leads to a much bigger kernel, which in turn slows the system as a whole
+down, due to a bigger icache footprint for the CPU and simply because
+there is less memory available for the pagecache. Just think about it; a
+pagecache miss causes a disk seek, which easily takes 5 milliseconds.
+There are a LOT of cpu cycles that can go into these 5 milliseconds.
+
+A reasonable rule of thumb is to not put inline at functions that have
+more than 3 lines of code in them. An exception to this rule are the
+cases where a parameter is known to be a compiletime constant, and as a
+result of this constantness you *know* the compiler will be able to
+optimize most of your function away at compile time. For a good example
+of this later case, see the kmalloc() inline function.
+
+Often people argue that adding inline to functions that are static and
+used only once is always a win since there is no space tradeoff. While
+this is technically correct, gcc is capable of inlining these
+automatically without help, and the maintenance issue of removing the
+inline when a second user appears outweighs the potential value of the
+hint that tells gcc to do something it would have done anyway.
+
+Function return values and names
+--------------------------------
+
+Functions can return values of many different kinds, and one of the most
+common is a value indicating whether the function succeeded or failed.
+Such a value can be represented as an error-code integer (-Exxx =
+failure, 0 = success) or a "succeeded" boolean (0 = failure, non-zero
+= success).
+
+Mixing up these two sorts of representations is a fertile source of
+difficult-to-find bugs. If the C language included a strong distinction
+between integers and booleans then the compiler would find these
+mistakes for us... but it doesn't. To help prevent such bugs, always
+follow this convention:
+
+If the name of a function is an action or an imperative command,
+the function should return an error-code integer.  If the name
+is a predicate, the function should return a "succeeded" boolean.
+
+For example, "add work" is a command, and the add_work() function
+returns 0 for success or -EBUSY for failure. In the same way, "PCI
+device present" is a predicate, and the pci_dev_present() function
+returns 1 if it succeeds in finding a matching device or 0 if it
+doesn't.
+
+All EXPORTed functions must respect this convention, and so should all
+public functions. Private (static) functions need not, but it is
+recommended that they do.
+
+Functions whose return value is the actual result of a computation,
+rather than an indication of whether the computation succeeded, are not
+subject to this rule. Generally they indicate failure by returning some
+out-of-range result. Typical examples would be functions that return
+pointers; they use NULL or the ERR_PTR mechanism to report failure.
+
+Don't re-invent the kernel macros
+----------------------------------
+
+The header file include/linux/kernel.h contains a number of macros that
+you should use, rather than explicitly coding some variant of them
+yourself. For example, if you need to calculate the length of an array,
+take advantage of the macro
+
+```c
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+```
+
+There are also min() and max() macros that do strict type checking if
+you need them. Feel free to peruse that header file to see what else is
+already defined that you shouldn't reproduce in your code.
+
+Editor modelines and other cruft
+--------------------------------
+
+Some editors can interpret configuration information embedded in source
+files, indicated with special markers. For example, emacs interprets
+lines marked like this:
+
+```
+-*- mode: c -*-
+```
+
+Or like this:
+
+```
+/*
+Local Variables:
+compile-command: "gcc -DMAGIC_DEBUG_FLAG foo.c"
+End:
+*/
+```
+
+Vim interprets markers that look like this:
+
+```
+/* vim:set sw=8 noet */
+```
+
+Do not include any of these in source files. People have their own
+personal editor configurations, and your source files should not
+override them. This includes markers for indentation and mode
+configuration. People may use their own custom mode, or may have some
+other magic method for making indentation work correctly.
+
+Inline assembly
+---------------
+
+In architecture-specific code, you may need to use inline assembly to
+interface with CPU or platform functionality. Don't hesitate to do so
+when necessary. However, don't use inline assembly gratuitously when C
+can do the job. You can and should poke hardware from C when possible.
+
+Consider writing simple helper functions that wrap common bits of inline
+assembly, rather than repeatedly writing them with slight variations.
+Remember that inline assembly can use C parameters.
+
+Large, non-trivial assembly functions should go in .S files, with
+corresponding C prototypes defined in C header files. The C prototypes
+for assembly functions should use "asmlinkage".
+
+You may need to mark your asm statement as volatile, to prevent GCC from
+removing it if GCC doesn't notice any side effects. You don't always
+need to do so, though, and doing so unnecessarily can limit
+optimization.
+
+When writing a single inline assembly statement containing multiple
+instructions, put each instruction on a separate line in a separate
+quoted string, and end each string except the last with nt to
+properly indent the next instruction in the assembly output:
+
+```c
+asm ("magic %reg1, #42nt"
+	"more_magic %reg2, %reg3"
+	: /* outputs */ : /* inputs */ : /* clobbers */);
+```
+
+References
+----------
+
+The C Programming Language, Second Edition by Brian W. Kernighan and
+Dennis M. Ritchie. Prentice Hall, Inc., 1988. ISBN 0-13-110362-8
+(paperback), 0-13-110370-9 (hardback). URL:
+<http://cm.bell-labs.com/cm/cs/cbook/>
+
+The Practice of Programming by Brian W. Kernighan and Rob Pike.
+Addison-Wesley, Inc., 1999. ISBN 0-201-61586-X. URL:
+<http://cm.bell-labs.com/cm/cs/tpop/>
+
+GNU manuals - where in compliance with K&R and this text - for cpp, gcc,
+gcc internals and indent, all available from
+<http://www.gnu.org/manual/>
+
+WG14 is the international standardization working group for the
+programming language C, URL: <http://www.open-std.org/JTC1/SC22/WG14/>
+
+Kernel CodingStyle, by greg@kroah.com at OLS 2002:
+<http://www.kroah.com/linux/talks/ols_2002_kernel_codingstyle_talk/html/>

Documentation/community/code_of_conduct.md

@@ -95,17 +95,6 @@ If you feel you have been falsely or unfairly accused of violating this
 Code of Conduct, you should notify the arbitration team with a concise
 description of your grievance.
 
-## Legal action
-
-Threatening or starting legal action against the project, sibling
-projects hosted on coreboot.org infrastructure, project or infrastructure
-maintainers leads to an immediate ban from coreboot.org and related
-systems.
-
-The ban can be reconsidered, but it's the default action because the
-people who pour lots of time and money into the projects aren't interested
-in seeing their resources used against them.
-
 ## Scope
 
 We expect all community participants (contributors, paid or otherwise;
@@ -126,4 +115,4 @@ Our arbitration team consists of the following people
 This Code of Conduct is distributed under
 a [Creative Commons Attribution-ShareAlike
 license](http://creativecommons.org/licenses/by-sa/3.0/).  It is based
-on the [Citizen Code of Conduct](https://web.archive.org/web/20200330154000/http://citizencodeofconduct.org/)
+on the [Citizen Code of Conduct](http://citizencodeofconduct.org/)

Documentation/community/conferences.md

@@ -14,7 +14,7 @@ their development kit with them and conduct development sessions.
 
 [Open Source Firmware at Facebook](https://fosdem.org/2019/schedule/event/open_source_firmware_at_facebook/)  by [David Hendricks](https://github.com/dhendrix) and [Andrea Barberio](https://github.com/insomniacslk) at [FOSDEM 2019](https://fosdem.org/2019/) ([video](https://video.fosdem.org/2019/K.4.401/open_source_firmware_at_facebook.mp4)) ([slides](https://insomniac.slackware.it/static/2019_fosdem_linuxboot_at_facebook.pdf)) (2019-02-03)
 
-[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://web.archive.org/web/20211027210118/https://events.ccc.de/congress/2018/wiki/index.php/Main_Page)
+[Open Source Firmware - A love story](https://www.youtube.com/watch?v=xfqKm190dbU) by [Philipp Deppenwiese](https://cybersecurity.9elements.com) at [35c3](https://events.ccc.de/congress/2018)
 ([slides](https://cdn.media.ccc.de/congress/2018/slides-h264-hd/35c3-9778-deu-eng-Open_Source_Firmware_hd-slides.mp4)) (2018-12-27)
 
 [coreboot mainboard porting with Intel FSP 2.0](https://www.youtube.com/watch?v=qUgo-AVsSCI) by Subrata Banik at OSFC 2018

Documentation/community/forums.md

@@ -11,29 +11,8 @@ You can subscribe on its
 read its
 [archives](https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/).
 
-## Real time chat
+## IRC
 
-We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
-also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a
-[Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
-[OSF Slack](https://osfw.slack.com/), which has channels on many open source
-firmware related topics. Slack requires that people come from specific domains
-or are explicitly invited. To work around that, there's an
-[invite bot](https://slack.osfw.dev/) to let people in.
-
-## Fortnightly coreboot leadership meeting
-
-There's a leadership meeting held every 14 days (currently every other
-Wednesday at 10am Pacific Time, usually 18:00 UTC with some deviation
-possible due to daylight saving time related shifts). The meeting
-is open to everyone and provides a forum to discuss general coreboot
-topics, including community and technical matters that benefit from
-an official decision.
-
-We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/pyt-newq-rbb),
-using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
-for the agenda and meeting minutes. Neither the video conference nor
-the document require a Google account to participate, although editing
-access to the document is limited to adding comments - any desired
-agenda item added that way will be approved in time before the meeting.
+We also have a
+[real time chat](https://webchat.freenode.net?channels=%23coreboot)
+on the Freenode IRC network's #coreboot channel.

Documentation/community/index.md

@@ -1,6 +0,0 @@
-# Community
-
-* [Code of Conduct](code_of_conduct.md)
-* [Language style](language_style.md)
-* [Community forums](forums.md)
-* [coreboot at conferences](conferences.md)

Documentation/community/services.md

@@ -0,0 +1,45 @@
+# Accounts on coreboot.org
+
+There are a number of places where you can benefit from creaating an account
+in our community. Since there is no single sign-on system in place (at this
+time), they come with their own setup routines.
+
+## Gerrit code review
+We exchange and review patches to the code using our [Gerrit code review
+system](https://review.coreboot.org).
+
+It allows logging in with a Google or GitHub account using OAuth2 as well
+as with any OpenID provider that you may already use.
+
+On the [settings screen](https://review.coreboot.org/settings) you can register
+all your email addresses you intend to use in the context of coreboot
+development so that commits with your email address in them are associated with
+you properly.
+
+### https push access
+When using the https URLs to git repositories, you can push with the "HTTP
+Credentials" you can have Gerrit generate for you on that page. By default,
+git uses `$HOME/.netrc` for http authentication data, so add a line there
+stating:
+
+    machine review.coreboot.org login $your-user-name password $your-password
+
+### Gerrit user avatar
+To setup an avatar to show in Gerrit, clone the avatars repository at
+https://review.coreboot.org/gerrit-avatars.git and add a file named
+$your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)).
+The image must be provided in JPEG format, must be square and have at most 50000
+bytes.
+
+After you push for review, the system will automatically verify your change
+and, if adhering to these constraints, approve it. You can then immediately
+submit it.
+
+## Issue tracker
+We have an [issue tracker](https://ticket.coreboot.org) that is used for
+coreboot and related code, such as libpayload, as well as for the project's
+infrastructure.
+
+It can be helpful to refer to issues we track there in commit messages:
+
+    Fixes: https://ticket.coreboot.org/issues/$id

Documentation/conf.py

@@ -55,7 +55,7 @@ else:
 #
 # This is also used if you do content translation via gettext catalogs.
 # Usually you set "language" from the command line for these cases.
-language = 'en'
+language = None
 
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
@@ -87,9 +87,11 @@ html_theme = 'sphinx_rtd_theme'
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']
 
-html_css_files = [
-    'theme_overrides.css',  # override wide tables in RTD theme
-]
+html_context = {
+      'css_files': [
+        '_static/theme_overrides.css',  # override wide tables in RTD theme
+      ],
+}
 
 # Output file base name for HTML help builder.
 htmlhelp_basename = 'corebootdoc'
@@ -183,7 +185,7 @@ texinfo_documents = [
 enable_auto_toc_tree = True
 
 class MyCommonMarkParser(CommonMarkParser):
-    # remove this hack once upstream RecommonMark supports inline code
+    # remove this hack once upsteam RecommonMark supports inline code
     def visit_code(self, mdnode):
         from docutils import nodes
         n = nodes.literal(mdnode.literal, mdnode.literal)

Documentation/contributing/gsoc.md

@@ -1,286 +0,0 @@
-# Google Summer of Code
-
-## Organization admins
-
-The *organization admins* are managing the GSoC program for the coreboot
-organization.
-
-The organization admins are:
-
-  * Felix Singer (primary)
-  * Martin Roth
-  * David Hendricks
-
-
-## Contacts
-
-If you are interested in participating in GSoC as a contributor or mentor,
-please have a look at our [community forums] and reach out to us. Working closely
-with the community is highly encouraged, as we've seen that our most successful
-contributors are generally very involved.
-
-
-## Why work on coreboot for GSoC?
-
-  * coreboot offers you the opportunity to work with various architectures
-    right on the iron. coreboot supports both current and older silicon for a
-    wide variety of chips and technologies.
-
-  * coreboot has a worldwide developer and user base.
-
-  * We are a very passionate team, so you will interact directly with the
-    project initiators and project leaders.
-
-  * We have a large, helpful community. coreboot has some extremely talented
-    and helpful experts in firmware involved in the project. They are ready to
-    assist and mentor contributors participating in GSoC.
-
-  * One of the last areas where open source software is not common is firmware.
-    Running proprietary firmware can have severe effects on user's freedom and
-    security. coreboot has a mission to change that by providing a common
-    framework for initial hardware initialization and you can help us succeed.
-
-
-## Collection of official GSoC guides & documents
-
-  * [Timeline][GSoC Timeline]
-
-  * [Roles and Responsibilities][GSoC Roles and Responsibilities]
-
-  * [Contributor Guide][GSoC Contributor Guide]
-
-  * [Contributor Advice][GSoC Contributor Advice]
-
-  * [Mentor Guide][GSoC Mentor Guide]
-
-  * [FAQ][GSoC FAQ]
-
-  * [Rules][GSoC Rules]
-
-  * [Glossary][GSoC Glossary]
-
-  * [Organization Admin Tips][GSoC Organization Admin Tips]
-
-
-## Contributor requirements & commitments
-
-Google Summer of Code is a significant time commitment for you. Medium-sized
-projects are estimated to take 175 hours, while large-sized projects are
-estimated to take 350 hours. Depending on the project size, this means we
-expect you to work roughly half-time or full-time on your project during the
-three months of coding. We expect to be able to see this level of effort in the
-results.
-
-The standard program duration is 12 weeks and in consultation with the mentor
-it can be extended up to 22 weeks. Please keep in mind that the actual number
-of hours you spend on the project highly depends on your skills and previous
-experience.
-
-Make sure that your schedule (exams, courses, day job) gives you a sufficient
-amount of spare time. If this is not the case, then you should not apply.
-
-
-### Before applying
-
-  * Join the [mailing list] and our other [community forums]. Introduce yourself
-    and mention that you are a prospective GSoC contributor. Ask questions and
-    discuss the project that you are considering. Community involvement is a
-    key component of coreboot development.
-
-  * You accept our [Code of Conduct] and [Language style].
-
-  * Demonstrate that you can work with the coreboot codebase.
-
-    * Look over some of the development processes guidelines: [Getting started],
-      [Tutorial], [Flashing firmware tutorial] and [Coding style].
-
-    * Download, build and boot coreboot in QEMU or on real hardware. Please email
-      your serial output results to the [mailing list].
-
-    * Look through some patches on Gerrit to get an understanding of the review
-      process and common issues.
-
-    * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [small project list][Project ideas] or ask for simple tasks on
-      the [mailing list] or on our other [community forums] if you need ideas.
-
-
-### During the program
-
-  * To pass and to be paid by Google requires that you meet certain milestones.
-
-    * First, you must be in good standing with the community before the official
-      start of the program. We expect you to post some design emails to the
-      [mailing list], and get feedback on them, both before applying, and during
-      the "community bonding period" between acceptance and official start.
-
-    * You must have made progress and committed significant code before the
-      mid-term point and by the final.
-
-    * We require that accepted contributors to maintain a blog, where you are
-      expected to write about your project *WEEKLY*. This is a way to measure
-      progress and for the community at large to be able to help you. GSoC is
-      *NOT* a private contract between your mentor and you.
-
-  * You must be active in the community on IRC and the [mailing list].
-
-  * You are expected to work on development publicly, and to push commits to the
-    project on a regular basis. Depending on the project and what your mentor
-    agrees to, these can be published directly to the project or to a public
-    repository such as Gitlab or Github. If you are not publishing directly to
-    the project codebase, be aware that we do not want large dumps of code that
-    need to be rushed to meet the mid-term and final goals.
-
-We don't expect our contributors to be experts in our problem domain, but we
-don't want you to fail because some basic misunderstanding was in your way of
-completing the task.
-
-
-## Projects
-
-There are many development tasks available in coreboot. We prepared some ideas
-for Summer of Code projects. These are projects that we think can be managed in
-the timeline of GSoC, and they cover areas where coreboot is trying to reach
-new users and new use cases.
-
-Of course your application does not have to be based on any of the ideas listed.
-It is entirely possible that you have a great idea that we just didn't think of
-yet. Please let us know!
-
-The blog posts related to previous GSoC projects might give some insights to
-what it is like to be a coreboot GSoC contributor.
-
-
-## coreboot Summer of Code Application
-
-coreboot welcomes contributors from all backgrounds and levels of experience.
-
-Your application should include a complete project proposal. You should
-document that you have the knowledge and the ability to complete your proposed
-project. This may require a little research and understanding of coreboot prior
-to sending your application. The community and coreboot project mentors are your
-best resource in fleshing out your project ideas and helping with a project
-timeline. We recommend that you get feedback and recommendations on your
-proposal before the application deadline.
-
-Please complete the standard GSoC application and project proposal. Provide the
-following information as part of your application. Make sure to provide multiple
-ways of communicating in case your equipment (such as a laptop) is lost,
-damaged, or stolen, or in case of a natural disaster that disrupts internet
-service. You risk automatically failing if your mentor cannot contact you and if
-you cannot provide updates according to GSoC deadlines.
-
-**Personal Information**
-
-  * Name
-
-  * Email and contact options (IRC, Matrix, …)
-
-  * Phone number (optional, but recommended)
-
-  * Timezone, Usual working hours (UTC)
-
-  * School / University, Degree Program, expected graduation date
-
-  * Short bio / Overview of your background
-
-  * What are your other time commitments? Do you have a job, classes, vacations?
-    When and how long?
-
-**Software experience**
-
-If applicable, please provide the following information:
-
-  * Portfolio, Website, blog, microblog, Github, Gitlab, ...
-
-  * Links to one or more patches submitted
-
-  * Links to posts on the [mailing list] with the serial output of your build.
-
-  * Please comment on your software and firmware experience.
-
-  * Have you contributed to an open source project? Which one? What was your
-    experience?
-
-  * What was your experience while building and running coreboot? Did you have
-    problems?
-
-**Your project**
-
-  * Provide an overview of your project (in your own words).
-
-  * Provide a breakdown of your project in small specific weekly goals. Think
-    about the potential timeline.
-
-  * How will you accomplish this goal? What is your working style?
-
-  * Explain what risks or potential problems your project might experience.
-
-  * What would you expect as a minimum level of success?
-
-  * Do you have a stretch goal?
-
-**Other**
-
-  * Resume (optional)
-
-
-### Advice on how to apply
-
-  * [GSoC Contributor Guide]
-
-  * The Drupal project has a great page on how to write an GSoC application.
-
-  * Secrets for GSoC success: [2]
-
-
-## Mentors
-
-Each accepted project will have at least one mentor. We will match mentors and
-contributors based on the project and experience level. If possible, we also
-will try to match their time zones.
-
-Mentors are expected to stay in frequent contact with the contributor and
-provide guidance such as code reviews, pointers to useful documentation, etc.
-This should generally be a time commitment of several hours per week.
-
-Some projects might have more than one mentor, who can serve as a backup. They
-are expected to coordinate with each other and a contributor on a regular basis,
-and keep track of the contributor process. They should be able to take over
-mentoring duty if one of the mentors is unavailable (vacations, sickness,
-emergencies).
-
-
-### Volunteering to be a mentor
-
-If you'd like to volunteer to be a mentor, please read the [GSoC Mentor Guide].
-This will give you a better idea of expectations, and where to go for help.
-After that, contact Org Admins (see coreboot contacts section above).
-
-The following coreboot developers have volunteered to be GSoC 2022 mentors.
-Please stop by in our community forums and say hi to them and ask them
-questions.
-
-  * Tim Wawrzynczak
-  * Raul Rangel
-  * Ron Minnich
-
-
-[community forums]: ../community/forums.md
-[mailing list]: https://mail.coreboot.org/postorius/lists/coreboot.coreboot.org
-[Getting started]: ../getting_started/index.md
-[Tutorial]: ../tutorial/index.md
-[Flashing firmware tutorial]: ../tutorial/flashing_firmware/index.md
-[Coding style]: coding_style.md
-[Code of Conduct]: ../community/code_of_conduct.md
-[Language style]: ../community/language_style.md
-[Project ideas]: project_ideas.md
-[GSoC Timeline]: https://developers.google.com/open-source/gsoc/timeline
-[GSoC Roles and Responsibilities]: https://developers.google.com/open-source/gsoc/help/responsibilities
-[GSoC Contributor Guide]: https://google.github.io/gsocguides/student
-[GSoC Contributor Advice]: https://developers.google.com/open-source/gsoc/help/student-advice
-[GSoC Mentor Guide]: https://google.github.io/gsocguides/mentor
-[GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
-[GSoC Rules]: https://summerofcode.withgoogle.com/rules
-[GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
-[GSoC Organization Admin Tips]: https://developers.google.com/open-source/gsoc/help/oa-tips

Documentation/contributing/index.md

@@ -1,7 +0,0 @@
-# Contributing
-
-* [Coding Style](coding_style.md)
-* [Gerrit Guidelines](gerrit_guidelines.md)
-* [Project Ideas](project_ideas.md)
-* [Documentation Ideas](documentation_ideas.md)
-* [Google Summer of Code](gsoc.md)

Documentation/contributing/project_ideas.md

@@ -20,24 +20,6 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Small projects
-
-This is a collection of tasks which don't require deep knowledge on
-coreboot itself. If you are a beginner and want to get familiar with the
-the project and the code base, or if you just want to get your hands
-dirty with some small tasks, then these are for you.
-
-  * Resolve static analysis issues reported by [scan-build] and
-    [Coverity scan]. More details on the page for
-    [Coverity scan integration].
-
-  * Resolve issues reported by the [linter][Linter issues]
-
-[scan-build]: https://coreboot.org/scan-build/
-[Coverity scan]: https://scan.coverity.com/projects/coreboot
-[Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
-
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
 working on coreboot and related projects. Sadly, building it takes hours,
@@ -63,6 +45,7 @@ non-Linux builds or Docker for different Linux distributions.
 * hardware requirements: Nothing special
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Support Power9/Power8 in coreboot
 There are some basic PPC64 stubs in coreboot, and there's open hardware
@@ -83,11 +66,30 @@ across architectures.
 ### Mentors
 * Timothy Pearson <tpearson@raptorengineering.com>
 
+## Add Kernel Address Sanitizer functionality to coreboot
+The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector.
+The idea is to check every memory access (variables) for its validity
+during runtime and find bugs like stack overflow or out-of-bounds accesses.
+Implementing this stub into coreboot like "Undefined behavior sanitizer support"
+would help to ensure code quality and make the runtime code more robust.
+
+### Requirements
+* knowledge in the coreboot build system and the concept of stages
+* the KASAN feature can be improved in a way so that the memory space needed
+  during runtime is not on a fixed address provided during compile time but
+  determined during runtime. For this to achieve a small patch to the GCC will
+  be helpful. Therefore minor GCC knowledge would be beneficial.
+* Implementation can be initially done in QEMU and improved on different
+  mainboards and platforms
+
+### Mentors
+* Werner Zeh <werner.zeh@gmx.net>
+
 ## Port payloads to ARM, AArch64 or RISC-V
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
-to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
-FILO, or Linux-as-Payload.
+to one of the platforms, for example GRUB2, U-Boot (the UI part), Tianocore,
+yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a
 combination of payload and architecture to support.
@@ -129,6 +131,7 @@ their bug reports.
   going on from the resulting logs.
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Extend Ghidra to support analysis of firmware images
 [Ghidra](https://ghidra-sre.org) is a recently released cross-platform
@@ -218,9 +221,9 @@ Build an open source replacement written in Golang using existing tools
 and libraries, consisting of a backend, a frontend and client side
 scripts. The backend should connect to an SQL database with can be
 controlled using a RESTful API. The RESTful API should have basic authentication
-for management tasks and new board status uploads.
+for managment tasks and new board status uploads.
 
-At least one older test result should be kept in the database.
+At least one older test result should be keept in the database.
 
 The frontend should use established UI libraries or frameworks (for example
 Angular) to display the current board status, that is if it's working or not

Documentation/coreboot_logo.svg

@@ -1,40 +0,0 @@
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Documentation/distributions.md

@@ -8,24 +8,28 @@ and those providing after-market firmware to extend the usefulness of devices.
 
 ## Hardware shipping with coreboot
 
-### NovaCustom laptops
+### Purism
 
-[NovaCustom](https://configurelaptop.eu/) sells configurable laptops with
-[Dasharo](https://dasharo.com/) coreboot based firmware on board, maintained by
-[3mdeb](https://3mdeb.com/). NovaCustom offers full GNU/Linux and Microsoft
-Windows compatibility. NovaCustom ensures security updates via fwupd for 5 years
-and the firmware is equipped with important security features such as measured
-boot, verified boot, TPM integration and UEFI Secure Boot.
+[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
+security; part of that effort is to minimize the amount of proprietary and/or
+binary code. Their laptops ship with a blob-free OS and coreboot firmware
+with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
 
 ### ChromeOS Devices
 
 All ChromeOS devices ([Chromebooks](https://chromebookdb.com/), Chromeboxes,
 Chromebit, etc) released from 2012 onward use coreboot for their main system
 firmware. Additionally, starting with the 2013 Chromebook Pixel, the firmware
-running on the Embedded Controller (EC) – a small microcontroller which provides
-functions like battery management, keyboard support, and sensor interfacing –
+running on the Embedded Controller (EC - a small microcontroller which provides
+functions like battery management, keyboard support, and sensor interfacing)
 is open source as well.
 
+### Libretrend
+
+[Libretrend](https://libretrend.com) sells the Librebox, a NUC-like PC which
+ships with coreboot firmware.
+
+
 ### PC Engines APUs
 
 [PC Engines](https://pcengines.ch) designs and sells embedded PC hardware that
@@ -33,27 +37,6 @@ ships with coreboot and support upstream maintenance for the devices through a
 third party, [3mdeb](https://3mdeb.com). They provide current and tested
 firmware binaries on [GitHub](https://pcengines.github.io).
 
-### Star Labs
-
-[Star Labs](https://starlabs.systems/) offers a range of laptops designed and
-built specifically for Linux that are available with coreboot firmware. They
-use edk2 as the payload and include an NVRAM option to disable the Intel
-Management Engine.
-
-### System76
-
-[System76](https://system76.com/) manufactures Linux laptops, desktops, and
-servers. Some models are sold with [System76 Open
-Firmware](https://github.com/system76/firmware-open), an open source
-distribution of coreboot, edk2, and System76 firmware applications.
-
-### Purism
-
-[Purism](https://www.puri.sm) sells laptops with a focus on user privacy and
-security; part of that effort is to minimize the amount of proprietary and/or
-binary code. Their laptops ship with a blob-free OS and coreboot firmware
-with a neutralized Intel Management Engine (ME) and SeaBIOS as the payload.
-
 ## After-market firmware
 
 ### Libreboot
@@ -63,22 +46,11 @@ provides ready-made firmware images for supported devices: those which can be
 built entirely from source code. Their copy of the coreboot repository is
 therefore stripped of all devices that require binary components to boot.
 
-
-### Dasharo
-
-[Dasharo](https://dasharo.com/) is an open-source based firmware distribution
-focusing on clean and simple code, long-term maintenance, transparent
-validation, privacy-respecting implementation, liberty for the owners, and
-trustworthiness for all.
-
-Contributions are welcome,
-[this document](https://docs.dasharo.com/ways-you-can-help-us/).
-
 ### MrChromebox
 
 [MrChromebox](https://mrchromebox.tech/) provides upstream coreboot firmware
 images for the vast majority of x86-based Chromebooks and Chromeboxes, using
-edk2 as the payload to provide a modern UEFI bootloader. Why replace
+Tianocore as the payload to provide a modern UEFI bootloader. Why replace
 coreboot with coreboot? Mr Chromebox's images are built using upstream
 coreboot (vs Google's older, static tree/branch), include many features and
 fixes not found in the stock firmware, and offer much broader OS compatibility

Documentation/doxygen/Doxyfile.coreboot_platform

@@ -0,0 +1,319 @@
+# Doxyfile 1.8.11
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+DOXYFILE_ENCODING      = UTF-8
+PROJECT_NAME           = "coreboot for $(DOXYGEN_PLATFORM)"
+PROJECT_NUMBER         =
+PROJECT_BRIEF          = "coreboot is an Open Source project aimed at replacing the proprietary BIOS found in most computers."
+PROJECT_LOGO           = Documentation/coreboot_logo.png
+OUTPUT_DIRECTORY       = $(DOXYGEN_OUTPUT_DIR)
+CREATE_SUBDIRS         = YES
+ALLOW_UNICODE_NAMES    = NO
+OUTPUT_LANGUAGE        = English
+BRIEF_MEMBER_DESC      = YES
+REPEAT_BRIEF           = YES
+ABBREVIATE_BRIEF       =
+ALWAYS_DETAILED_SEC    = YES
+INLINE_INHERITED_MEMB  = NO
+FULL_PATH_NAMES        = YES
+STRIP_FROM_PATH        =
+STRIP_FROM_INC_PATH    =
+SHORT_NAMES            = NO
+JAVADOC_AUTOBRIEF      = YES
+QT_AUTOBRIEF           = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS           = YES
+SEPARATE_MEMBER_PAGES  = NO
+TAB_SIZE               = 8
+ALIASES                =
+TCL_SUBST              =
+OPTIMIZE_OUTPUT_FOR_C  = YES
+OPTIMIZE_OUTPUT_JAVA   = NO
+OPTIMIZE_FOR_FORTRAN   = NO
+OPTIMIZE_OUTPUT_VHDL   = NO
+EXTENSION_MAPPING      =
+MARKDOWN_SUPPORT       = YES
+AUTOLINK_SUPPORT       = YES
+BUILTIN_STL_SUPPORT    = NO
+CPP_CLI_SUPPORT        = NO
+SIP_SUPPORT            = NO
+IDL_PROPERTY_SUPPORT   = YES
+DISTRIBUTE_GROUP_DOC   = NO
+GROUP_NESTED_COMPOUNDS = NO
+SUBGROUPING            = YES
+INLINE_GROUPED_CLASSES = NO
+INLINE_SIMPLE_STRUCTS  = NO
+TYPEDEF_HIDES_STRUCT   = NO
+LOOKUP_CACHE_SIZE      = 0
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL            = YES
+EXTRACT_PRIVATE        = NO
+EXTRACT_PACKAGE        = NO
+EXTRACT_STATIC         = YES
+EXTRACT_LOCAL_CLASSES  = YES
+EXTRACT_LOCAL_METHODS  = NO
+EXTRACT_ANON_NSPACES   = NO
+HIDE_UNDOC_MEMBERS     = NO
+HIDE_UNDOC_CLASSES     = NO
+HIDE_FRIEND_COMPOUNDS  = NO
+HIDE_IN_BODY_DOCS      = NO
+INTERNAL_DOCS          = NO
+CASE_SENSE_NAMES       = YES
+HIDE_SCOPE_NAMES       = NO
+HIDE_COMPOUND_REFERENCE= NO
+SHOW_INCLUDE_FILES     = YES
+SHOW_GROUPED_MEMB_INC  = NO
+FORCE_LOCAL_INCLUDES   = NO
+INLINE_INFO            = YES
+SORT_MEMBER_DOCS       = YES
+SORT_BRIEF_DOCS        = NO
+SORT_MEMBERS_CTORS_1ST = NO
+SORT_GROUP_NAMES       = NO
+SORT_BY_SCOPE_NAME     = NO
+STRICT_PROTO_MATCHING  = NO
+GENERATE_TODOLIST      = YES
+GENERATE_TESTLIST      = YES
+GENERATE_BUGLIST       = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS       =
+MAX_INITIALIZER_LINES  = 30
+SHOW_USED_FILES        = YES
+SHOW_FILES             = YES
+SHOW_NAMESPACES        = YES
+FILE_VERSION_FILTER    =
+LAYOUT_FILE            =
+CITE_BIB_FILES         =
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET                  = YES
+WARNINGS               = YES
+WARN_IF_UNDOCUMENTED   = YES
+WARN_IF_DOC_ERROR      = YES
+WARN_NO_PARAMDOC       = YES
+WARN_AS_ERROR          = NO
+WARN_FORMAT            = "$file:$line: $text"
+WARN_LOGFILE           =
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT                  = $(DOXYFILES)
+INPUT_ENCODING         = UTF-8
+FILE_PATTERNS          =
+RECURSIVE              = NO
+EXCLUDE                =
+EXCLUDE_SYMLINKS       = NO
+EXCLUDE_PATTERNS       =
+EXCLUDE_SYMBOLS        =
+EXAMPLE_PATH           =
+EXAMPLE_PATTERNS       =
+EXAMPLE_RECURSIVE      = NO
+IMAGE_PATH             =
+INPUT_FILTER           =
+FILTER_PATTERNS        =
+FILTER_SOURCE_FILES    = NO
+FILTER_SOURCE_PATTERNS =
+USE_MDFILE_AS_MAINPAGE =
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER         = YES
+INLINE_SOURCES         = NO
+STRIP_CODE_COMMENTS    = NO
+REFERENCED_BY_RELATION = YES
+REFERENCES_RELATION    = YES
+REFERENCES_LINK_SOURCE = YES
+SOURCE_TOOLTIPS        = YES
+USE_HTAGS              = NO
+VERBATIM_HEADERS       = YES
+CLANG_ASSISTED_PARSING = NO
+CLANG_OPTIONS          =
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX     = YES
+COLS_IN_ALPHA_INDEX    = 5
+IGNORE_PREFIX          =
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML          = YES
+HTML_OUTPUT            = html
+HTML_FILE_EXTENSION    = .html
+HTML_HEADER            =
+HTML_FOOTER            =
+HTML_STYLESHEET        =
+HTML_EXTRA_STYLESHEET  =
+HTML_EXTRA_FILES       =
+HTML_COLORSTYLE_HUE    = 220
+HTML_COLORSTYLE_SAT    = 100
+HTML_COLORSTYLE_GAMMA  = 80
+HTML_TIMESTAMP         = NO
+HTML_DYNAMIC_SECTIONS  = NO
+HTML_INDEX_NUM_ENTRIES = 100
+GENERATE_DOCSET        = NO
+DOCSET_FEEDNAME        = "Doxygen documentation"
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+DOCSET_PUBLISHER_NAME  = Publisher
+GENERATE_HTMLHELP      = NO
+CHM_FILE               =
+HHC_LOCATION           =
+GENERATE_CHI           = NO
+CHM_INDEX_ENCODING     =
+BINARY_TOC             = NO
+TOC_EXPAND             = NO
+GENERATE_QHP           = NO
+QCH_FILE               =
+QHP_NAMESPACE          = org.doxygen.Project
+QHP_VIRTUAL_FOLDER     = doc
+QHP_CUST_FILTER_NAME   =
+QHP_CUST_FILTER_ATTRS  =
+QHP_SECT_FILTER_ATTRS  =
+QHG_LOCATION           =
+GENERATE_ECLIPSEHELP   = NO
+ECLIPSE_DOC_ID         = org.doxygen.Project
+DISABLE_INDEX          = NO
+GENERATE_TREEVIEW      = YES
+ENUM_VALUES_PER_LINE   = 4
+TREEVIEW_WIDTH         = 250
+EXT_LINKS_IN_WINDOW    = NO
+FORMULA_FONTSIZE       = 10
+FORMULA_TRANSPARENT    = YES
+USE_MATHJAX            = NO
+MATHJAX_FORMAT         = HTML-CSS
+MATHJAX_RELPATH        = http://cdn.mathjax.org/mathjax/latest
+MATHJAX_EXTENSIONS     =
+MATHJAX_CODEFILE       =
+SEARCHENGINE           = YES
+SERVER_BASED_SEARCH    = NO
+EXTERNAL_SEARCH        = NO
+SEARCHENGINE_URL       =
+SEARCHDATA_FILE        = searchdata.xml
+EXTERNAL_SEARCH_ID     =
+EXTRA_SEARCH_MAPPINGS  =
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX         = NO
+LATEX_OUTPUT           = latex
+LATEX_CMD_NAME         = latex
+MAKEINDEX_CMD_NAME     = makeindex
+COMPACT_LATEX          = NO
+PAPER_TYPE             = a4wide
+EXTRA_PACKAGES         =
+LATEX_HEADER           =
+LATEX_FOOTER           =
+LATEX_EXTRA_STYLESHEET =
+LATEX_EXTRA_FILES      =
+PDF_HYPERLINKS         = NO
+USE_PDFLATEX           = NO
+LATEX_BATCHMODE        = NO
+LATEX_HIDE_INDICES     = NO
+LATEX_SOURCE_CODE      = NO
+LATEX_BIB_STYLE        = plain
+LATEX_TIMESTAMP        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF           = NO
+RTF_OUTPUT             = rtf
+COMPACT_RTF            = NO
+RTF_HYPERLINKS         = NO
+RTF_STYLESHEET_FILE    =
+RTF_EXTENSIONS_FILE    =
+RTF_SOURCE_CODE        = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN           = NO
+MAN_OUTPUT             = man
+MAN_EXTENSION          = .3
+MAN_SUBDIR             =
+MAN_LINKS              = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML           = NO
+XML_OUTPUT             = xml
+XML_PROGRAMLISTING     = YES
+#---------------------------------------------------------------------------
+# Configuration options related to the DOCBOOK output
+#---------------------------------------------------------------------------
+GENERATE_DOCBOOK       = NO
+DOCBOOK_OUTPUT         = docbook
+DOCBOOK_PROGRAMLISTING = NO
+#---------------------------------------------------------------------------
+# Configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF   = NO
+#---------------------------------------------------------------------------
+# Configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD       = NO
+PERLMOD_LATEX          = NO
+PERLMOD_PRETTY         = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING   = YES
+MACRO_EXPANSION        = YES
+EXPAND_ONLY_PREDEF     = YES
+SEARCH_INCLUDES        = YES
+INCLUDE_PATH           =
+INCLUDE_FILE_PATTERNS  =
+PREDEFINED             = __attribute__(x)=
+EXPAND_AS_DEFINED      =
+SKIP_FUNCTION_MACROS   = YES
+#---------------------------------------------------------------------------
+# Configuration options related to external references
+#---------------------------------------------------------------------------
+TAGFILES               =
+GENERATE_TAGFILE       =
+ALLEXTERNALS           = NO
+EXTERNAL_GROUPS        = YES
+EXTERNAL_PAGES         = YES
+PERL_PATH              = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS         = YES
+MSCGEN_PATH            =
+DIA_PATH               =
+HIDE_UNDOC_RELATIONS   = NO
+HAVE_DOT               = NO
+DOT_NUM_THREADS        = 0
+DOT_FONTNAME           = Helvetica
+DOT_FONTSIZE           = 10
+DOT_FONTPATH           =
+CLASS_GRAPH            = YES
+COLLABORATION_GRAPH    = YES
+GROUP_GRAPHS           = YES
+UML_LOOK               = YES
+UML_LIMIT_NUM_FIELDS   = 10
+TEMPLATE_RELATIONS     = NO
+INCLUDE_GRAPH          = YES
+INCLUDED_BY_GRAPH      = YES
+CALL_GRAPH             = YES
+CALLER_GRAPH           = YES
+GRAPHICAL_HIERARCHY    = YES
+DIRECTORY_GRAPH        = YES
+DOT_IMAGE_FORMAT       = png
+INTERACTIVE_SVG        = NO
+DOT_PATH               =
+DOTFILE_DIRS           =
+MSCFILE_DIRS           =
+DIAFILE_DIRS           =
+PLANTUML_JAR_PATH      =
+PLANTUML_INCLUDE_PATH  =
+DOT_GRAPH_MAX_NODES    = 50
+MAX_DOT_GRAPH_DEPTH    = 0
+DOT_TRANSPARENT        = NO
+DOT_MULTI_TARGETS      = YES
+GENERATE_LEGEND        = YES
+DOT_CLEANUP            = YES

Documentation/drivers/cbfs_smbios.md

@@ -1,143 +0,0 @@
-# CBFS SMBIOS hooks
-
-The document describes the coreboot options how to make CBFS files populate
-platform-unique SMBIOS data.
-
-## SMBIOS Serial Number
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information and type 2 Baseboard Information called Serial Number. It
-is a null-terminated string field assumed to be unique per platform. Certain
-mainboard ports have SMBIOS hooks to generate the Serial Numbers from external
-data, e.g. Lenovo Thinkpads (see DRIVER_LENOVO_SERIALS). This driver aims to
-provide an option to populate the Serial Numbers from CBFS for boards that
-can't generate the it from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `Serial number in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_SERIAL` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the serial number:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw -f /path/to/serial_file.txt
-```
-
-Where `serial_file.txt` is the unterminated string representation of the SMBIOS
-type 1 or type 2 Serial Number, e.g. `5Q4Q7Y1`. If you use vboot with 1 or 2 RW
-partitions you will have to specify the RW regions where the file is going to
-be added too. By default the RW CBFS partitions are truncated, so the files
-would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n serial_number -t raw \
-	-f /path/to/serial_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the Serial Number from running system (if it exists) using one
-of the following commands:
-
-```shell
-# Type 1
-echo -n `sudo dmidecode -s system-serial-number` > serial_file.txt
-# OR Type 2
-echo -n `sudo dmidecode -s baseboard-serial-number` > serial_file.txt
-```
-
-Ensure the file does not end with whitespaces like LF and/or CR. The above
-commands will not add any whitespaces. The driver automatically terminates the
-Serial Number with the NULL character. If the CBFS file is not present, the
-driver will fall back to the string defined in `MAINBOARD_SERIAL_NUMBER` build
-option.
-
-Please note that this driver provides `smbios_mainboard_serial_number` hook
-overriding the default implementation which returns `MAINBOARD_SERIAL_NUMBER`
-build option. If you wish to populate only type 2 Serial Number field your
-board code needs to implement `smbios_system_serial_number`, otherwise the weak
-implementation of `smbios_system_serial_number` will call
-`smbios_mainboard_serial_number` from the `DRIVERS_GENERIC_CBFS_SERIAL`
-implementation overriding it. So selecting the `DRIVERS_GENERIC_CBFS_SERIAL`
-has a side-effect of populating both SMBIOS type 1 and type 2 Serial Numbers
-if the board does not implement its own `smbios_system_serial_number`.
-
-There is also SMBIOS type 3 Chassis Information Serial Number, but it is not
-populated by `DRIVERS_GENERIC_CBFS_SERIAL` nor by the default weak
-implementation (returns empty string). If you wish to populate type 3 Serial
-Number, your board code should override the default
-`smbios_chassis_serial_number` weak implementation.
-
-## SMBIOS System UUID
-
-The [DMTF SMBIOS specification] defines a field in the type 1 System
-Information Structure called System UUID. It is a 16 bytes value compliant with
-[RFC4122] and assumed to be unique per platform. Certain mainboard ports have
-SMBIOS hooks to generate the UUID from external data, e.g. Lenovo Thinkpads
-(see DRIVER_LENOVO_SERIALS). This driver aims to provide an option to populate
-the UUID from CBFS for boards that can't generate the UUID from any source.
-
-### Usage
-
-In the coreboot configuration menu (`make menuconfig`) go to `Generic Drivers`
-and select an option `System UUID in CBFS`. The Kconfig system will enable
-`DRIVERS_GENERIC_CBFS_UUID` and the relevant code parts will be compiled into
-coreboot image.
-
-After the coreboot build for your board completes, use the cbfstool to include
-the file containing the UUID:
-
-```shell
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw -f /path/to/uuid_file.txt
-```
-
-Where `uuid_file.txt` is the unterminated string representation of the SMBIOS
-type 1 UUID, e.g. `4c4c4544-0051-3410-8051-b5c04f375931`. If you use vboot with
-1 or 2 RW partitions you will have to specify the RW regions where the file is
-going to be added too. By default the RW CBFS partitions are truncated, so the
-files would probably not fit, one needs to expand them first.
-
-```shell
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_A
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_A
-
-./build/cbfstool build/coreboot.rom expand -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom add -n system_uuid -t raw \
-	-f /path/to/uuid_file.txt -r FW_MAIN_B
-./build/cbfstool build/coreboot.rom truncate -r FW_MAIN_B
-```
-
-By default cbfstool adds files to COREBOOT region only, so when vboot is
-enabled and the platform is booting from RW partition, the file would not be
-picked up by the driver.
-
-One may retrieve the UUID from running system (if it exists) using the
-following command:
-
-```shell
-echo -n `sudo dmidecode -s system-uuid` > uuid_file.txt
-```
-
-The above command ensures the file does not end with whitespaces like LF and/or
-CR. The above command will not add any whitespaces. But the driver will handle
-situations where up to 2 additional bytes like CR and LF will be included in
-the file. Any more than that will make the driver fail to populate UUID in
-SMBIOS.
-
-[DMTF SMBIOS specification]: https://www.dmtf.org/standards/smbios
-[RFC4122]: https://www.ietf.org/rfc/rfc4122.txt

Documentation/drivers/dptf.md

@@ -43,7 +43,7 @@ This policy monitors the temperature of participants and controls fans to spin
 at varying speeds. These speeds are defined by the platform, and will be enabled
 depending on the various temperatures reported by participants.
 
-## Note about units
+# Note about units
 
 ACPI uses unusual units for specifying various physical measurements. For
 example, temperatures are specified in 10ths of a degree K, and time is measured
@@ -69,7 +69,7 @@ data was a 0). The following Methods were removed:
 2) There is no more implicit inclusion of _ACn methods for TCPU (these must be
    specified in the devicetree entries or by calling the DPTF acpigen API).
 
-## ACPI Tables
+# ACPI Tables
 
 DPTF relies on an assortment of ACPI tables to provide parameters to the DPTF
 application. We will discuss the more important ones here.
@@ -108,7 +108,7 @@ various informational properties.
 This table describes performance states supported by a participant (typically
 the battery charger).
 
-## ACPI Methods
+# ACPI Methods
 
 The Active and Passive policies also provide for short Methods to define
 different kinds of temperature thresholds.
@@ -141,7 +141,7 @@ a "graceful shutdown".
 
 These are optional, and are enabled by selecting the Critical Policy.
 
-## How to use the devicetree entries
+# How to use the devicetree entries
 
 The `drivers/intel/dptf` chip driver is organized into several sections:
 - Policies
@@ -151,7 +151,7 @@ The `drivers/intel/dptf` chip driver is organized into several sections:
 The Policies section (`policies.active`, `policies.passive`, and
 `policies.critical`) is where the components of each policy are defined.
 
-### Active Policy
+## Active Policy
 
 Each Active Policy is defined in terms of 4 parts:
 1) A Source (this is implicitly defined as TFN1, the system fan)
@@ -182,7 +182,7 @@ the CPU's active cooling capability). When the CPU temperature first crosses
 rest of the table (note that it *must* be defined from highest temperature/
 percentage on down to the lowest).
 
-### Passive Policy
+## Passive Policy
 
 Each Passive Policy is defined in terms of 5 parts:
 1) Source - The device that can be throttled
@@ -201,7 +201,7 @@ This example sets up a policy to begin throttling the charger performance when
 temperature sensor 1 reaches 65C. The sampling period here is 60000 ms (60 s).
 The Priority is defaulted to 100 in this case.
 
-### Critical Policy
+## Critical Policy
 
 Each Critical Policy is defined in terms of 3 parts:
 1) Source - A device that can trigger a critical event
@@ -218,7 +218,7 @@ register "policies.critical[1]" = "DPTF_CRITICAL(CPU, 75, SHUTDOWN)"
 This example sets up a policy wherein ACPI will cause the system to shutdown
 (in a "graceful" manner) when the CPU temperature reaches 75C.
 
-### Power Limits
+## Power Limits
 
 Control over the SoC's Running Average Power Limits (RAPL) is one of the tools
 that DPTF uses to enact Passive policies. DPTF can control both PL1 and PL2, if
@@ -244,7 +244,7 @@ This example allow DPTF to control the SoC's PL1 level to between 3W and 15W,
 over a time interval ranging from 28 to 32 seconds, and it can move PL1 in
 increments of 200 mW.
 
-### Charger Performance
+## Charger Performance
 
 The battery charger can be a large contributor of unwanted heat in a system that
 has one. Controlling the rate of charging is another tool that DPTF uses to enact
@@ -266,7 +266,7 @@ register "controls.charger_perf[3]" = "{   8,  500 }"
 In this example, when DPTF decides to throttle the charger, it has four different
 performance states to choose from.
 
-### Fan Performance
+## Fan Performance
 
 When using DPTF, the system fan (`TFN1`) is the device responsible for actively
 cooling the other temperature sensors on the mainboard. A fan speed table can be
@@ -298,32 +298,16 @@ increment of 10 percentage points. This is common when specifying fine-grained
 control of the fan, wherein DPTF will interpolate between the percentages in the
 table for a given temperature threshold.
 
-### Options
+## Options
 
-#### Fan
+### Fan
 1) Fine-grained control - a boolean (see Fan Performance section above)
 2) Step-size - Recommended minimum step size (in percentage points) to adjust
    the fan speed when using fine-grained control (ranges from 1 - 9).
 3) Low-speed notify - If true, the platform will issue a `Notify (0x80)` to the
    fan device if a low fan speed is detected.
 
-#### Temperature sensors
+### Temperature sensors
 1) Hysteresis - The amount of hysteresis implemented in either circuitry or
    the firmware that reads the temperature sensor (in degrees C).
 2) Name - This name is applied to the _STR property of the sensor
-
-### OEM Variables
-Platform vendors can define an array of OEM-specific values as OEM variables
-to be used under DPTF policy. There are total six OEM variables available.
-These can be used in AP policy for more specific actions. These OEM variables
-can be defined as below mentioned example and can be used any variable between
-[0], [1],...,[5]. Platform vendors can enable and use this for specific platform
-by defining OEM variables macro under board variant.
-
-Example:
-```C
-register "oem_data.oem_variables" = "{
-   [1] = 0x6,
-   [3] = 0x1
-}"
-```

Documentation/drivers/dt_entries.md

@@ -1,309 +0,0 @@
-# Driver Devicetree Entries
-
-Let's take a look at an example entry from
-``src/mainboard/google/hatch/variants/hatch/overridetree.cb``:
-
-```
-device pci 15.0 on
-	chip drivers/i2c/generic
-		register "hid" = ""ELAN0000""
-		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-		register "detect" = "1"
-		register "wake" = "GPE0_DW0_21"
-		device i2c 15 on end
-	end
-end # I2C #0
-```
-
-When this entry is processed during ramstage, it will create a device in the
-ACPI SSDT table (all devices in devicetrees end up in the SSDT table).  The ACPI
-generation routines in coreboot actually generate the raw bytecode that
-represents the device's structure, but looking at ASL code is easier to
-understand; see below for what the disassembled bytecode looks like:
-
-```
-Scope (\_SB.PCI0.I2C0)
-{
-    Device (D015)
-    {
-        Name (_HID, "ELAN0000")  // _HID: Hardware ID
-        Name (_UID, Zero)  // _UID: Unique ID
-        Name (_DDN, "ELAN Touchpad")  // _DDN: DOS Device Name
-        Method (_STA, 0, NotSerialized)  // _STA: Status
-        {
-            Return (0x0F)
-        }
-        Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-        {
-            I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-            {
-                0x0000002D,
-            }
-        })
-        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
-        Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
-        {
-            0x15, // GPE #21
-            0x03  // Sleep state S3
-        })
-    }
-}
-```
-
-You can see it generates \_HID, \_UID, \_DDN, \_STA, \_CRS, \_S0W, and \_PRW
-names/methods in the Device's scope.
-
-## Utilizing a device driver
-
-The device driver must be enabled for your build.  There will be a CONFIG option
-in the Kconfig file in the directory that the driver is in (e.g.,
-``src/drivers/i2c/generic`` contains a Kconfig file; the option here is named
-CONFIG_DRIVERS_I2C_GENERIC).  The config option will need to be added to your
-mainboard's Kconfig file (e.g., ``src/mainboard/google/hatch/Kconfig``) in order
-to be compiled into your build.
-
-## Diving into the above example:
-
-Let's take a look at how the devicetree language corresponds to the generated
-ASL.
-
-First, note this:
-
-```
-    chip drivers/i2c/generic
-```
-
-This means that the device driver we're using has a corresponding structure,
-located at ``src/drivers/i2c/generic/chip.h``, named **struct
-drivers_i2c_generic_config** and it contains many properties you can specify to
-be included in the ACPI table.
-
-### hid
-
-```
-    register "hid" = ""ELAN0000""
-```
-
-This corresponds to **const char \*hid** in the struct.  In the ACPI ASL, it
-translates to:
-
-```
-    Name (_HID, "ELAN0000") // _HID: Hardware ID
-```
-
-under the device.  **This property is used to match the device to its driver
-during enumeration in the OS.**
-
-### desc
-
-```
-    register "desc" = ""ELAN Touchpad""
-```
-
-corresponds to **const char \*desc** and in ASL:
-
-```
-    Name (_DDN, "ELAN Touchpad") // _DDN: DOS Device Name
-```
-
-### irq
-
-It also adds the interrupt,
-
-```
-    Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, ,, )
-    {
-        0x0000002D,
-    }
-```
-
-which comes from:
-
-```
-    register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A21_IRQ)"
-```
-
-The IRQ settings control the "Trigger" and "Polarity" settings seen above (level
-means it is a level-triggered interrupt as opposed to
-edge-triggered; active low means the interrupt is triggered when the signal is
-low).
-
-Also note that the IRQ names are SoC-specific, and you will need to
-find the names in your SoC's header file.  The ACPI_* macros are defined in
-``src/arch/x86/include/acpi/acpi_device.h``.
-
-Using a GPIO as an IRQ requires that it is configured in coreboot correctly.
-This is often done in a mainboard-specific file named ``gpio.c``.
-
-AMD platforms don't have the ability to route GPIOs to the IO-APIC. Instead the
-GPIO controller needs to be used directly. You can do this by setting the
-`irq_gpio` register and using the `ACPI_GPIO_IRQ_X_X` macros.
-
-i.e.,
-```
-register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_40)"
-```
-
-### detect
-
-The next register is:
-
-```
-    register "detect" = "1"
-```
-
-This flag tells the I2C driver that it should attempt to detect the presence of
-the device (using an I2C zero-byte write), and only generate a SSDT entry if the
-device is actually present. This alleviates the OS from having to determine if
-a device is present or not (ChromeOS/Linux) and prevents resource conflict/
-driver issues (Windows).
-
-Currently, the detect feature works and is hooked up for all I2C touchpads,
-and should be used any time a board has multiple touchpad options.
-I2C audio devices should also work without issue.
-
-Touchscreens can use this feature as well, but special care is needed to
-implement the proper power sequencing for the device to be detected. Generally,
-this means driving the enable GPIO high and holding the reset GPIO low in early
-GPIO init (bootblock/romstage), then releasing reset in ramstage. The first
-mainboards in the tree to implement this are google/skyrim and google/guybrush.
-This feature has also been used in downstream forks without issue for some time
-now on several other boards.
-
-### wake
-
-The last register is:
-
-```
-    register "wake" = "GPE0_DW0_21"
-```
-
-which indicates that the method of waking the system using the touchpad will be
-through a GPE, #21 associated with DW0, which is set up in devicetree.cb from
-this example.  The "21" indicates GPP_X21, where GPP_X is mapped onto DW0
-elsewhere in the devicetree.
-
-### device
-
-The last bit of the definition of that device includes:
-
-```
-    device i2c 15 on end
-```
-
-which means it's an I2C device, with 7-bit address 0x15, and the device is "on",
-meaning it will be exposed in the ACPI table.  The PCI device that the
-controller is located in determines which I2C bus the device is expected to be
-found on.  In this example, this is I2C bus 0.  This also determines the ACPI
-"Scope" that the device names and methods will live under, in this case
-"\_SB.PCI0.I2C0".
-
-## Wake sources
-
-The ACPI spec defines two methods to describe how a device can wake the system.
-Only one of these methods should be used, otherwise duplicate wake events will
-be generated.
-
-### Using GPEs as a wake source
-
-The `wake` property specified above is used to tell the ACPI subsystem that the
-device can use a GPE to wake the system. The OS can control whether to enable
-or disable the wake source by unmasking/masking off the GPE.
-
-The `GPIO` -> `GPE` mapping must be configured in firmware. On AMD platforms this is
-generally done by a mainboard specific `gpio.c` file that defines the GPIO
-using `PAD_SCI`. The `GPIO` -> `GPE` mapping is returned by the
-`soc_get_gpio_event_table` method that is defined in the SoC specific `gpio.c`
-file. On Intel platforms, you fill in the `pmc_gpe0_dw0`, `pmc_gpe0_dw1`, and
-`pmc_gpe0_dw2` fields in the devicetree to map 3 GPIO communities to `tier-1`
-GPEs (the rest are available as `tier-2` GPEs).
-
-Windows has a large caveat when using this method. If you use the `gpio_irq`
-property to define a `GpioInt` in the `_CRS`, and then use the `wake` property
-to define a `GPE`, Windows will
-[BSOD](https://github.com/MicrosoftDocs/windows-driver-docs/blob/staging/windows-driver-docs-pr/debugger/bug-check-0xa5--acpi-bios-error.md)
-complaining about an invalid ACPI configuration.
-> 0x1000D - A device used both GPE and GPIO interrupts, which is not supported.
-
-In order to avoid this error, you should use the `irq` property instead. AMD
-platforms don't support routing GPIOs to the IO-APIC, so this workaround isn't
-feasible. The other option is to use a wake capable GPIO as described below.
-
-### Using GPIO interrupts as a wake source
-
-The `ACPI_IRQ_WAKE_{EDGE,LEVEL}_{LOW,HIGH}` macros can be used when setting the
-`irq` or `gpio_irq` properties. This ends up setting `ExclusiveAndWake` or
-`SharedAndWake` on the `Interrupt` or `GpioInt` ACPI resource.
-
-This method has a few caveats:
-* On Intel and AMD platforms the IO-APIC can't wake the system. This means using
-  the `ACPI_IRQ_WAKE_*` macros with the `irq` property won't actually wake the
-  system. Instead you need to use the `gpio_irq` property, or a `GPE` as
-  described above.
-* The OS needs to know how to enable the `wake` bit on the GPIO. For linux this
-  means the platform specific GPIO controller driver must implement the
-  `irq_set_wake` callback. For AMD systems this wasn't
-  [implemented](https://github.com/torvalds/linux/commit/d62bd5ce12d79bcd6a6c3e4381daa7375dc21158)
-  until linux v5.15. If the controller doesn't define this callback, it's
-  possible for the firmware to manually set the `wake` bit on the GPIO. This is
-  often done in a mainboard-specific file named `gpio.c`. This is not
-  recommended because then it's not possible for the OS to disable the wake
-  source.
-* As of
-  [linux v6.0-rc5](https://github.com/torvalds/linux/releases/tag/v6.0-rc5),
-  the ACPI subsystem doesn't take the interrupt `wake` bit into account when
-  deciding on which power state to put the device in before suspending the
-  system. This means that if you define a power resource for a device via
-  `has_power_resource`, `enable_gpio`, etc, then the linux kernel will place the
-  device into D3Cold. i.e., power off the device.
-
-## Other auto-generated names
-
-(see [ACPI specification
-6.3](https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf)
-for more details on ACPI methods)
-
-### _S0W (S0 Device Wake State)
-\_S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is `ACPI_DEVICE_SLEEP_D3_HOT`, representing _D3hot_.
-D3Hot means the `PR3` power resources are still on and the device is still
-responsive on the bus. For i2c devices this is generally the same state as `D0`.
-
-### \_PRW (Power Resources for Wake)
-\_PRW indicates the power resources and events required for wake.  There are no
-dependent power resources, but the GPE (GPE0_DW0_21) is mentioned here (0x15),
-as well as the deepest sleep state supporting waking the system (3), which is
-S3.
-
-### \_STA (Status)
-The \_STA method is generated automatically, and its values, 0xF, indicates the
-following:
-
-    Bit [0] – Set if the device is present.
-    Bit [1] – Set if the device is enabled and decoding its resources.
-    Bit [2] – Set if the device should be shown in the UI.
-    Bit [3] – Set if the device is functioning properly (cleared if device failed its diagnostics).
-
-### \_CRS (Current resource settings)
-The \_CRS method is generated automatically, as the driver knows it is an I2C
-controller, and so specifies how to configure the controller for proper
-operation with the touchpad.
-
-```
-Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
-{
-    I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
-                    AddressingMode7Bit, "\\_SB.PCI0.I2C0",
-                    0x00, ResourceConsumer, , Exclusive, )
-```
-
-## Notes
-
- - **All device driver entries in devicetrees end up in the SSDT table, and are
-   generated in coreboot's ramstage**
-   (The lone exception to this rule is i2c touchpads with the 'detect' flag set;
-    in this case, devices not present will not be added to the SSDT)

Documentation/drivers/index.md

@@ -2,16 +2,11 @@
 
 The drivers can be found in `src/drivers`. They are intended for onboard
 and plugin devices, significantly reducing integration complexity and
-they allow to easily reuse existing code across platforms.
-
-For details on how to connect device drivers to a mainboard, see [Driver Devicetree Entries](dt_entries.md).
-
-Some of the drivers currently available include:
+they allow to easily reuse existing code accross platforms.
 
 * [Intel DPTF](dptf.md)
 * [IPMI KCS](ipmi_kcs.md)
 * [SMMSTORE](smmstore.md)
-* [SMMSTOREv2](smmstorev2.md)
 * [SoundWire](soundwire.md)
+* [SMMSTOREv2](smmstorev2.md)
 * [USB4 Retimer](retimer.md)
-* [CBFS SMBIOS hooks](cbfs_smbios.md)

Documentation/drivers/ipmi_kcs.md

@@ -42,15 +42,6 @@ The following registers can be set:
 * `gpe_interrupt`
   * Integer
   * The bit in GPE (SCI) used to notify about a change on the KCS.
-* `wait_for_bmc`
-  * Boolean
-  * Wait for BMC to boot. This can be used if the BMC takes a long time to boot
-    after PoR:
-     - AST2400 on Supermicro X11SSH: 34 s
-* `bmc_boot_timeout`
-  * Integer
-  * The timeout in seconds to wait for the IPMI service to be loaded.
-    Will be used if wait_for_bmc is true.
 
 
 [IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/drivers/retimer.md

@@ -1,6 +1,6 @@
 # USB4 Retimers
 
-## Introduction
+# Introduction
 As USB speeds continue to increase (up to 5G, 10G, and even 20G or higher in
 newer revisions of the spec), it becomes more difficult to maintain signal
 integrity for longer traces. Devices such as retimers and redrivers can be used
@@ -17,7 +17,7 @@ by doing CDR and retransmitting the data (i.e., it is protocol-aware). Since
 this is a digital component, it may have firmware.
 
 
-## Driver Usage
+# Driver Usage
 
 Some operating systems may have the ability to update firmware on USB4 retimers,
 and ultimately will need some way to power the device on and off so that its new

Documentation/drivers/smmstorev2.md

@@ -21,7 +21,7 @@ operations is desired, as it reduces complexity and potential for bugs.
 
 This can be used by a FTW (FaultTolerantWrite) implementation that uses
 at least two regions in an A/B update scheme. The FTW implementation in
-edk2 uses three different regions in the store:
+EDK2 uses three different regions in the store:
 
 - The variable store
 - The FTW spare block
@@ -35,7 +35,7 @@ With 64 KiB as block size, the minimum size of the FTW-enabled store is:
 - The FTW spare block: 2 blocks = 2 * 64 KiB
 - The FTW working block: 1 block = 64 KiB
 
-Therefore, the minimum size for edk2 FTW is 4 blocks, or 256 KiB.
+Therefore, the minimum size for EDK2 FTW is 4 blocks, or 256 KiB.
 
 ## API
 

Documentation/drivers/soundwire.md

@@ -375,7 +375,7 @@ chip and can be decoded for this table with the codec datasheet and board schema
  * @version: SoundWire specification version from &enum soundwire_version.
  * @link_id: Zero-based SoundWire Link Number.
  * @unique_id: Unique ID for multiple devices.
- * @manufacturer_id: Manufacturer ID from include/mipi/ids.h.
+ * @manufacturer_id: Manufacturer ID from include/device/mipi_ids.h.
  * @part_id: Vendor defined part ID.
  * @class: MIPI class encoding in &enum mipi_class.
  */

Documentation/external_docs.md

@@ -1,136 +0,0 @@
-# External Resources
-
-This is a list of resources that could be useful to coreboot developers.
-These are not endorsed or officially recommended by the coreboot project,
-but simply listed here in the hopes that someone will find something
-useful.
-
-Please add any helpful or informational links and sections as you see fit.
-
-## Articles
-
-* External Interrupts in the x86 system.
-  * [Part 1: Interrupt controller evolution](https://habr.com/en/post/446312/)
-  * [Part 2: Linux kernel boot options](https://habr.com/en/post/501660/)
-  * [Part 3: Interrupt routing setup in a chipset](https://habr.com/en/post/501912/)
-* System address map initialization in x86/x64 architecture.
-  * [Part 1: PCI-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-in-x86x64-architecture-part-1-pci-based-systems/)
-  * [Part 2: PCI express-based systems](https://resources.infosecinstitute.com/topic/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/)
-  * [PCIe elastic buffer](https://www.mindshare.com/files/resources/mindshare_pcie_elastic_buffer.pdf)
-* [Boot Guard and PSB have user-hostile defaults](https://mjg59.dreamwidth.org/58424.html)
-
-
-## General Information
-
-* [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
-* [Interface BUS](http://www.interfacebus.com/)
-
-## OpenSecurityTraining2
-
-OpenSecurityTraining2 is dedicated to sharing training material for any topic
-related to computer security, including coreboot.
-
-There are various ways to learn firmware, some are more efficient than others,
-depending on the people. Before going straight to practice and experimenting
-with hardware, it can be beneficial to learn the basics of computing. OST2
-focuses on conveying computer architecture and security information in the form
-of structured instructor-led classes, available to everyone for free.
-
-All material is licensed [CC BY-SA 4.0](http://creativecommons.org/licenses/by-sa/4.0/),
-allowing anyone to use the material however they see fit, so long as they share
-modified works back to the community.
-
-Below is a list of currently available courses that can help understand the
-inner workings of coreboot and other firmware-related topics:
-
-* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-
-There are [additional security courses](https://p.ost2.fyi/courses) at the site
-as well (such as
-[how to avoid writing exploitable code in C/C++](https://ost2.fyi/Vulns1001).)
-
-## Firmware Specifications & Information
-
-* [System Management BIOS - SMBIOS](https://www.dmtf.org/standards/smbios)
-* [Desktop and Mobile Architecture for System Hardware - DASH](https://www.dmtf.org/standards/dash)
-* [PNP BIOS](https://www.intel.com/content/dam/support/us/en/documents/motherboards/desktop/sb/pnpbiosspecificationv10a.pdf)
-
-
-### ACPI
-
-* [ACPI Specs](https://uefi.org/acpi/specs)
-* [ACPI in Linux](https://www.kernel.org/doc/ols/2005/ols2005v1-pages-59-76.pdf)
-* [ACPI 5 Linux](https://blog.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/LPC2012-ACPI5.pdf)
-* [ACPI 6 Linux](https://events.static.linuxfound.org/sites/events/files/slides/ACPI_6_and_Linux_0.pdf)
-
-
-### Security
-
-* [Intel Boot Guard](https://edk2-docs.gitbook.io/understanding-the-uefi-secure-boot-chain/secure_boot_chain_in_uefi/intel_boot_guard)
-
-
-## Hardware information
-
-* [WikiChip](https://en.wikichip.org/wiki/WikiChip)
-* [Sandpile](https://www.sandpile.org/)
-* [CPU-World](https://www.cpu-world.com/index.html)
-* [CPU-Upgrade](https://www.cpu-upgrade.com/index.html)
-
-
-### Hardware Specifications & Standards
-
-* [Bluetooth](https://www.bluetooth.com/specifications/specs/) - Bluetooth SIG
-* [eMMC](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [eSPI](https://cdrdv2.intel.com/v1/dl/getContent/645987) - Intel
-* [I2c Spec](https://web.archive.org/web/20170704151406/https://www.nxp.com/docs/en/user-guide/UM10204.pdf),
-  [Appnote](https://www.nxp.com/docs/en/application-note/AN10216.pdf) - NXP
-* [I2S](https://www.nxp.com/docs/en/user-manual/UM11732.pdf) - NXP
-* [I3C](https://www.mipi.org/specifications/i3c-sensor-specification) - MIPI Alliance (LOGIN REQUIRED)
-* [Memory](https://www.jedec.org/)  - JEDEC - (LOGIN REQUIRED)
-* [NVMe](https://nvmexpress.org/developers/) - NVMe Specifications
-* [LPC](https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf) - Intel
-* [PCI / PCIe / M.2](https://pcisig.com/specifications) -  PCI-SIG - (LOGIN REQUIRED)
-* [Power Delivery](https://www.usb.org/documents) - USB Implementers Forum
-* [SATA](https://sata-io.org/developers/purchase-specification) - SATA-IO (LOGIN REQUIRED)
-* [SMBus](http://www.smbus.org/specs/) - System Management Interface Forum
-* [Smart Battery](http://smartbattery.org/specs/) - Smart Battery System Implementers Forum
-* [USB](https://www.usb.org/documents) - USB Implementers Forum
-* [WI-FI](https://www.wi-fi.org/discover-wi-fi/specifications) - Wi-Fi Alliance
-
-
-### Chip Vendor Documentation
-
-* AMD
-  * [Developer Guides, Manuals & ISA Documents](https://developer.amd.com/resources/developer-guides-manuals/)
-  * [AMD Tech Docs - Official Documentation Page](https://www.amd.com/en/support/tech-docs)
-* ARM
-  * [Tools and Software - Specifications](https://developer.arm.com/tools-and-software/software-development-tools/specifications)
-* Intel
-  * [Developer Zone](https://www.intel.com/content/www/us/en/developer/overview.html)
-  * [Resource & Documentation Center](https://www.intel.com/content/www/us/en/resources-documentation/developer.html)
-  * [Architecture Software Developer Manuals](https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html)
-  * [Intel specific ACPI](https://www.intel.com/content/www/us/en/standards/processor-vendor-specific-acpi-specification.html)
-
-* Rockchip
-  * [Open Source Wiki](https://opensource.rock-chips.com/wiki_Main_Page)
-
-
-## Software
-
- * [Fiedka](https://github.com/fiedka/fiedka) - A graphical Firmware Editor
- * [IOTools](https://github.com/adurbin/iotools) - Command line tools to access hardware registers
- * [UEFITool](https://github.com/LongSoft/UEFITool) - Editor for UEFI PI compliant firmware images
- * [CHIPSEC](https://chipsec.github.io) - Framework for analyzing platform level security & configuration
- * [SPDEditor](https://github.com/integralfx/SPDEditor) - GUI to edit DDR3 SPD files
- * [DDR4XMPEditor](https://github.com/integralfx/DDR4XMPEditor) - Editor for DDR4 SPD and XMP
-* [overclockSPD](https://github.com/baboomerang/overclockSPD) - Fast and easy way to read and write data to RAM SPDs.
-* [VBiosFinder](https://github.com/coderobe/VBiosFinder) - This tool attempts to extract a VBIOS from a BIOS update.
-
-
-## Infrastructure software
-
-* [Kconfig](https://www.kernel.org/doc/html/latest/kbuild/kconfig-language.html)
-* [GNU Make](https://www.gnu.org/software/make/manual/)

Documentation/flash_tutorial/ext_standalone.md

@@ -0,0 +1,23 @@
+# Flashing firmware standalone
+
+If none of the other methods work, there are three possibilities:
+
+## Desolder
+You must remove or desolder the flash IC before you can flash it.
+It's recommended to solder a socket in place of the flash IC.
+
+When flashing the IC, always connect all input pins.
+If in doubt, pull /WP, /HOLD, /RESET and alike up towards Vcc.
+
+## SPI flash emulator
+If you are a developer, you might want to use an [EM100Pro] instead, which sets
+the onboard flash on hold, and allows to run custom firmware.
+It provides a very fast development cycle without actually writing to flash.
+
+## SPI flash overwrite
+It is possible to set the onboard flash on hold and use another flash chip.
+Connect all lines one-to-one, except /HOLD. Pull /HOLD of the soldered flash IC
+low, and /HOLD of your replacement flash IC high.
+
+
+[EM100Pro]: https://www.dediprog.com/product/EM100Pro

Documentation/flash_tutorial/index.md

@@ -0,0 +1,111 @@
+# Flashing firmware tutorial
+
+Updating the firmware is possible using the **internal method**, where the updates
+happen from a running system, or using the **external method**, where the system
+is in a shut down state and an external programmer is attached to write into the
+flash IC.
+
+## Contents
+
+* [Flashing internaly](int_flashrom.md)
+* [Flashing firmware standalone](ext_standalone.md)
+* [Flashing firmware externally supplying direct power](ext_power.md)
+* [Flashing firmware externally without supplying direct power](no_ext_power.md)
+
+## General advice
+
+* It's recommended to only flash the BIOS region.
+* Always verify the firmware image.
+* If you flash externally and have transmission errors:
+  * Use short wires
+  * Reduce clock frequency
+  * Check power supply
+  * Make sure that there are no other bus masters (EC, ME, SoC, ...)
+
+## Internal method
+
+This method using [flashrom] is available on many platforms, as long as they
+aren't locked down.
+
+There are various protection schemes that make it impossible to modify or
+replace a firmware from a running system. coreboot allows to disable these
+mechanisms, making it possible to overwrite (or update) the firmware from a
+running system.
+
+Usually you must use the **external method** once to install a retrofitted
+coreboot and then you can use the **internal method** for future updates.
+
+There are multiple ways to update the firmware:
+* Using flashrom's *internal* programmer to directly write into the firmware
+  flash IC, running on the target machine itself
+* A proprietary software to update the firmware, running on the target machine
+  itself
+* A UEFI firmware update capsule
+
+More details on flashrom's
+* [internal programmer](int_flashrom.md)
+
+## External method
+
+External flashing is possible on many platforms, but requires disassembling
+the target hardware. You need to buy a flash programmer, that
+exposes the same interface as your flash IC (likely SPI).
+
+Please also have a look at the mainboard-specific documentation for details.
+
+After exposing the firmware flash IC, read the schematics and use one of the
+possible methods:
+
+* [Flashing firmware standalone](ext_standalone.md)
+* [Flashing firmware externally supplying direct power](ext_power.md)
+* [Flashing firmware externally without supplying direct power](no_ext_power.md)
+
+**WARNING:** Using the wrong method or accidentally using the wrong pinout might
+  permanently damage your hardware!
+
+**WARNING:** Do not rely on dots *painted* on flash ICs to orient the pins!
+Any dots painted on flash ICs may only indicate if they've been tested.  Dots
+that appear in datasheets to indicate pin 1 correspond to some kind of physical
+marker, such as a drilled hole, or one side being more flat than the other.
+
+## Using a layout file
+On platforms where the flash IC is shared with other components you might want
+to write only a part of the flash IC. On Intel for example there are IFD, ME and
+GBE which don't need to be updated to install coreboot.
+To make [flashrom] only write the *bios* region, leaving Intel ME and Intel IFD
+untouched, you can use a layout file, which can be created with ifdtool and a backup
+of the original firmware.
+
+```bash
+ifdtool -f rom.layout backup.rom
+```
+
+and looks similar to:
+
+```
+00000000:00000fff fd
+00500000:00bfffff bios
+00003000:004fffff me
+00001000:00002fff gbe
+```
+
+By specifying *-l* and *-i* [flashrom] writes a single region:
+```bash
+flashrom -l rom.layout -i bios -w coreboot.rom -p <programmer>
+```
+
+## Using an IFD to determine the layout
+flashrom version 1.0 supports reading the layout from the IFD (first 4KiB of
+the ROM). You don't need to manually specify a layout it, but it only works
+under the following conditions:
+
+* Only available on Intel ICH7+
+* There's only one flash IC when flashing externally
+
+```bash
+flashrom --ifd -i bios -w coreboot.rom -p <programmer>
+```
+
+**TODO** explain FMAP regions, normal/fallback mechanism, flash lock mechanisms
+
+[flashrom]: https://www.flashrom.org/Flashrom

Documentation/gcov.txt

@@ -19,7 +19,7 @@ time). The file gcov-io.c is unchanged.
 +#define BITS_PER_UNIT 8
 +#define LONG_LONG_TYPE_SIZE 64
 +
-+/* There are many gcc_assertions. Set the value to 1 if we want a warning
++/* There are many gcc_assertions. Set the vaule to 1 if we want a warning
 +   message if the assertion fails.  */
 +#ifndef ENABLE_ASSERT_CHECKING
 +#define ENABLE_ASSERT_CHECKING 1

Documentation/getting_started/architecture.md

@@ -3,7 +3,7 @@
 ## Overview
 ![][architecture]
 
-[architecture]: comparison_coreboot_uefi.svg
+[architecture]: comparision_coreboot_uefi.svg
 
 ## Stages
 coreboot consists of multiple stages that are compiled as separate binaries and
@@ -41,7 +41,7 @@ The bootblock loads the romstage or the verstage if verified boot is enabled.
 
 ### Cache-As-Ram
 The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the
-CPU cache like regular SRAM. This is particullary useful for high level
+CPU cache like regular SRAM. This is particullary usefull for high level
 languages like `C`, which need RAM for heap and stack.
 
 The CAR needs to be activated using vendor specific CPU instructions.
@@ -85,7 +85,7 @@ The ramstage does the main device init:
 * CPU init (like set up SMM)
 
 After initialization tables are written to inform the payload or operating system
-about the current hardware existence and state. That includes:
+about the current hardware existance and state. That includes:
 
 * ACPI tables (x86 specific)
 * SMBIOS tables (x86 specific)

Documentation/getting_started/build_system.md

@@ -62,23 +62,6 @@ supported options are:
 
 `position` and `align` are mutually exclusive.
 
-### Adding Makefile fragments
-
-You can use the `add_intermediate` helper to add new post-processing steps for
-the final `coreboot.rom` image. For example you can add new files to CBFS by
-adding something like this to `site-local/Makefile.inc`
-
-```
-$(call add_intermediate, add_mrc_data)
-	$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
-```
-
-Note that the second line must start with a tab, not spaces.
-
-```eval_rst
-See also :doc:`../tutorial/managing_local_additions`.
-```
-
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a
 need to extend the specification of files to provide more precise control

Documentation/getting_started/devicetree.md

@@ -1,87 +0,0 @@
-# Adding new devices to a device tree
-
-## Introduction
-
-ACPI exposes a platform-independent interface for operating systems to perform
-power management and other platform-level functions.  Some operating systems
-also use ACPI to enumerate devices that are not immediately discoverable, such
-as those behind I2C or SPI buses (in contrast to PCI).  This document discusses
-the way that coreboot uses the concept of a "device tree" to generate ACPI
-tables for usage by the operating system.
-
-## Devicetree and overridetree (if applicable)
-
-For mainboards that are organized around a "reference board" or "baseboard"
-model (see ``src/mainboard/google/octopus`` or ``hatch`` for examples), there is
-typically a devicetree.cb file that all boards share, and any differences for a
-specific board ("variant") are captured in the overridetree.cb file.  Any
-settings changed in the overridetree take precedence over those in the main
-devicetree.  Note, not all mainboards will have the devicetree/overridetree
-distinction, and may only have a devicetree.cb file.  Or you can always just
-write the ASL (ACPI Source Language) code yourself.
-
-### Naming and referencing devices
-
-When declaring a device, it can optionally be given an alias that can be
-referred to elsewhere. This is particularly useful to declare a device in one
-device tree while allowing its configuration to be more easily changed in an
-overlay. For instance, the AMD Picasso SoC definition
-(`soc/amd/picasso/chipset.cb`) declares an IOMMU on a PCI bus that is disabled
-by default:
-
-```
-chip soc/amd/picasso
-	device domain 0 on
-		...
-		device pci 00.2 alias iommu off end
-		...
-	end
-end
-```
-
-A device based on this SoC can override the configuration for the IOMMU without
-duplicating addresses, as in
-`mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb`:
-
-```
-chip soc/amd/picasso
-	device domain 0
-		...
-		device ref iommu on end
-		...
-	end
-end
-```
-
-In this example the override simply enables the IOMMU, but it could also
-set additional properties (or even add child devices) inside the IOMMU `device`
-block.
-
----
-
-It is important to note that devices that use `device ref` syntax to override
-previous definitions of a device by alias must be placed at **exactly the same
-location in the device tree** as the original declaration. If not, this will
-actually create another device rather than overriding the properties of the
-existing one. For instance, if the above snippet from `devicetree_trembyle.cb`
-were written as follows:
-
-```
-chip soc/amd/picasso
-	# NOTE: not inside domain 0!
-	device ref iommu on end
-end
-```
-
-Then this would leave the SoC's IOMMU disabled, and instead create a new device
-with no properties as a direct child of the SoC.
-
-## Device drivers
-
-Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](../drivers/dt_entries.md) for more info.
-
-## Notes
-
- - **All fields that are left unspecified in the devicetree are initialized to
-   zero.**

Documentation/getting_started/gerrit_guidelines.md

@@ -41,7 +41,7 @@ project you're submitting the changes to. If you’re submitting code that
 you wrote that might be owned by your employer, make sure that your
 employer is aware and you are authorized to submit the code. For
 clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](#sign-off-procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
 
 * In general, patches should remain open for review for at least 24 hours
 since the last significant modification to the change. The purpose is to
@@ -53,10 +53,7 @@ it's implemented, should restart the wait period.
 a recently-introduced issue (build, boot or OS-level compatibility, not
 necessarily identified by coreboot.org facilities). Its commit message
 has to explain what change introduced the problem and the nature of
-the problem so that the emergency need becomes apparent. Avoid stating
-something like "fix build error" in the commit summary, describe what
-the commit does instead, just like any other commit. In addition, it is
-recommended to reference the commit that introduced the issue. The change
+the problem so that the emergency need becomes apparent. The change
 itself should be as limited in scope and impact as possible to make it
 simple to assess the impact. Such a change can be merged early with 3
 Code-Review+2. For emergency fixes that affect a single project (SoC,
@@ -127,54 +124,6 @@ those platforms. While it would be nice to update any other platforms, you
 must at least provide a path that will allow other platforms to continue
 working.
 
-Sign-off Procedure
-------------------
-The coreboot project employs a sign-off procedure similar to what is
-used by the Linux kernel. Each gerrit commit requires a sign-off line
-saying that the contributed code abides by the Developer's certificate
-of origin, below.
-```text
-Signed-off-by: Random J Developer <random@developer.example.org>
-```
-
-Using '-s' with 'git commit' will automatically add a Signed-off-by line
-to your commit message.  Patches without a Signed-off-by should not be
-pushed to gerrit, and will be rejected by coreboot's CI system.
-
-You must use a known identity in the Signed-off-by line. Anonymous
-contributions cannot be committed! This can be anything sufficient to
-identify and contact the source of a contribution, such as your name or
-an established alias/nickname. Refer to [this LKML thread] and the
-[SCO-Linux disputes] for the rationale behind the DCO.
-
-Developer's Certificate of Origin 1.1
-
-> By making a contribution to this project, I certify that:
->
-> (a) The contribution was created in whole or in part by me and I have
-> the right to submit it under the open source license indicated in the
-> file; or
->
-> (b) The contribution is based upon previous work that, to the best of
-> my knowledge, is covered under an appropriate open source license and
-> I have the right under that license to submit that work with
-> modifications, whether created in whole or in part by me, under the
-> same open source license (unless I am permitted to submit under a
-> different license), as indicated in the file; or
->
-> (c) The contribution was provided directly to me by some other person
-> who certified (a), (b) or (c) and I have not modified it; and
->
-> (d) In the case of each of (a), (b), or (c), I understand and agree
-> that this project and the contribution are public and that a record of
-> the contribution (including all personal information I submit with it,
-> including my sign-off) is maintained indefinitely and may be
-> redistributed consistent with this project or the open source license
-> indicated in the file.
-
-Note: The [Developer's Certificate of Origin 1.1] is licensed under the
-terms of the [Creative Commons Attribution-ShareAlike 2.5 License].
-
 
 Recommendations for gerrit activity
 -----------------------------------
@@ -221,10 +170,7 @@ This helps verify that the patch train won’t tie up the jenkins builders
 for no reason if there are failing patches in the train. For running
 parallel builds, you can specify the number of cores to use by setting the
 the CPUS environment variable. Example:
-
-```Bash
-make what-jenkins-does CPUS=8
-```
+        make what-jenkins-does CPUS=8
 
 * Use a topic when pushing a train of patches. This groups the commits
 together so people can easily see the connection at the top level of
@@ -232,10 +178,7 @@ gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
 commits with the i915-kernel-x60 set, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%topic=i915-kernel-x60
-```
+        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
@@ -245,28 +188,17 @@ Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
 mark the patch as not ready would be to give it a -1 or -2 review, but
 isn't as obvious as the commit message. These patches can also be pushed with
 the wip flag:
-
-```Bash
-git push origin HEAD:refs/for/master%wip
-```
+	git push origin HEAD:refs/for/master%wip
 
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
 private changes, so that only explicitly added reviewers will see them. These
-sorts of patches are frequently posted as ideas or RFCs for the community to
-look at. Note that private changes can still be fetched from Gerrit by anybody
-who knows their commit ID, so don't use this for sensitive changes. To push
-a private change, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%private
-```
+sorts of patches are frequently posted as ideas or RFCs for the community
+to look at. To push a private change, use the command:
+        git push origin HEAD:refs/for/master%private
 
 * Multiple push options can be combined:
-
-```Bash
-git push origin HEAD:refs/for/master%private,wip,topic=experiment
-```
+        git push origin HEAD:refs/for/master%private,wip,topic=experiment
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a
@@ -340,15 +272,13 @@ git/gerrit tags by prepending the lines with 'Original-'.  Marking
 the original text this way makes it much easier to tell what changes
 happened in which repository. This applies to these lines, not the actual
 commit message itself:
-
-	* Commit-Id:
-	* Change-Id:
-	* Signed-off-by:
-	* Reviewed-on:
-	* Tested-by:
-	* Reviewed-by:
-
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
+        Commit-Id:
+        Change-Id:
+        Signed-off-by:
+        Reviewed-on:
+        Tested-by:
+        Reviewed-by:
+The script 'util/gitconfig/rebase.sh' can be used to help automate this.
 Other tags such as 'Commit-Queue' can simply be removed.
 
 * Check if there's documentation that needs to be updated to remain current
@@ -390,51 +320,6 @@ is criticising your code, but the whole idea is to get better code into our
 codebase. Again, this also applies in the other direction: review code,
 criticize code, but don’t make it personal.
 
-Gerrit user roles
------------------
-There are a few relevant roles a user can have on Gerrit:
-
-- The anonymous user can check out source code.
-- A registered user can also comment and give "+1" and "-1" code reviews.
-- A reviewer can also give "+2" code reviews.
-- A core developer can also give "-2" (that is, blocking) code reviews
-  and submit changes.
-
-Anybody can register an account on our instance, using either an
-OpenID provider or OAuth through GitHub or Google.
-
-The reviewer group is still quite open: Any core developer can add
-registered users to that group and should do so once some activity
-(commits, code reviews, and so on) has demonstrated rough knowledge
-of how we handle things.
-
-A core developer should be sufficiently well established in the
-community so that they feel comfortable when submitting good patches,
-when asking for improvements to less good patches and reasonably
-uncomfortable when -2'ing patches. They're typically the go-to
-person for _some_ part of the coreboot tree and ideally listed as its
-maintainer in our MAINTAINERS registry. To become part of this group,
-a candidate developer who already demonstrated proficiency with the
-code base as a reviewer should be nominated, by themselves or others,
-at the regular [coreboot leadership meetings](../community/forums.md)
-where a decision is made.
-
-Core developers are expected to use their privileges for the good of the
-project, which includes any of their own coreboot development but also beyond
-that. They should make sure that [ready changes] don't linger around needlessly
-just because their authors aren't well-connected with core developers but
-submit them if they went through review and generally look reasonable. They're
-also expected to help clean-up breakage as a result of their submissions.
-
-Since the project expects some activity by core developers, long-term absence
-(as in "years") can lead to removal from the group, which can easily be
-reversed after they come back.
 
 Requests for clarification and suggestions for updates to these guidelines
 should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
-
-[ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergeable+label:All-Comments-Resolved%253Dok+label:Code-Review%253D2+-label:Code-Review%253C0+label:Verified%253D1+-label:Verified-1
-[Developer's Certificate of Origin 1.1]: https://developercertificate.org/
-[Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/
-[this LKML thread]: https://lkml.org/lkml/2004/5/23/10
-[SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes

Documentation/getting_started/gpio.md

@@ -115,44 +115,6 @@ variant's override table.
 This configuration is often hooked into the mainboard's `enable_dev` callback,
 defined in its `struct chip_operations`.
 
-## Unconnected and unused pads
-
-In digital electronics, it is generally recommended to tie unconnected GPIOs to
-a defined signal like VCC or GND by setting their direction to output, adding an
-external pull resistor or configuring an internal pull resistor. This is done to
-prevent floating of the pin state, which can cause various issues like EMI,
-higher power usage due to continuously switching logic, etc.
-
-On Intel PCHs from Sunrise Point onwards, termination of unconnected GPIOs is
-explicitly not required, when the input buffer is disabled by setting the bit
-`GPIORXDIS` which effectively disconnects the pad from the internal logic. All
-pads defaulting to GPIO mode have this bit set. However, in the mainboard's
-GPIO configuration the macro `PAD_NC(pad, NONE)` can be used to explicitly
-configure a pad as unconnected.
-
-In case there are no schematics available for a board and the vendor set a
-pad to something like `GPIORXDIS=1`, `GPIOTXDIS=1` with an internal pull
-resistor, an unconnected or otherwise unused pad can be assumed. In this case it
-is recommended to keep the pull resistor, because the external circuit might
-rely on it.
-
-Unconnected pads defaulting to a native function (input and output) usually
-don't need to be configured as GPIO with the `GPIORXDIS` bit set. For clarity
-and documentation purpose the macro may be used as well for them.
-
-Some pads configured as native input function explicitly require external
-pull-ups when being unused, according to the PDGs:
-- eDP_HPD
-- SMBCLK/SMBDATA
-- SML0CLK/SML0DATA/SML0ALERT
-- SATAGP*
-
-When the board was designed correctly, nothing needs to be done for them
-explicitly, while using `PAD_NC(pad, NONE)` can act as documentation. If such a
-pad is missing the external pull resistor due to bad board design, the pad
-should be configured with `PAD_NC(pad, NONE)` anyway to disconnect it
-internally.
-
 ## Potential issues (gotchas!)
 
 There are a couple of configurations that you need to especially careful about,
@@ -162,97 +124,8 @@ The first is configuring a pin as an output, when it was designed to be an
 input. There is a real risk in this case of short-circuiting a component which
 could cause catastrophic failures, up to and including your mainboard!
 
-### Intel SoCs
-
-As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register
-supports four different types of GPIO reset as:
-
-```eval_rst
-+------------------------+----------------+-------------+-------------+
-|                        |                |         PAD Reset ?       |
-+ PAD Reset Config       + Platform Reset +-------------+-------------+
-|                        |                |     GPP     |     GPD     |
-+========================+================+=============+=============+
-| | 00 - Power Good      |  Warm Reset    |     N       |    N        |
-| | (GPP: RSMRST,        +----------------+-------------+-------------+
-| | GPD: DSW_PWROK)      |  Cold Reset    |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| 01 - Deep              |  Warm Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Cold Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     N       |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| 10 - Host Reset/PLTRST |  Warm Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Cold Reset    |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     Y       |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     Y       |    Y        |
-+------------------------+----------------+-------------+-------------+
-| | 11 - Resume Reset    |  Warm Reset    |     n/a     |    N        |
-| | (GPP: Reserved,      +----------------+-------------+-------------+
-| | GPD: RSMRST)         |  Cold Reset    |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  S3/S4/S5      |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Global Reset  |     n/a     |    N        |
-|                        +----------------+-------------+-------------+
-|                        |  Deep Sx       |     n/a     |    Y        |
-|                        +----------------+-------------+-------------+
-|                        |  G3            |     n/a     |    Y        |
-+------------------------+----------------+-------------+-------------+
-```
-
-Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking
-specific register fields in the PAD configuration register.
-
-The Pad Config Lock registers reset type is default hardcoded to **Power Good** and
-it's **not** configurable by GPIO PAD DW0.PadRstCfg. Hence, it may appear that for a GPP,
-the Pad Reset Config (DW0 Bit 31) is configured differently from `Power Good`.
-
-This would create confusion where the Pad configuration is returned to its `default`
-value but remains `locked`, this would prevent software to reprogram the GPP.
-Additionally, this means software can't rely on GPIOs being reset by PLTRST# or Sx entry.
-
-Hence, as per GPIO BIOS Writers Guide (BWG) it's recommended to change the Pad Reset
-Configuration for lock GPP as `Power Good` so that pad configuration and lock bit are
-always in sync and can be reset at the same time.
-
-## Soft Straps
-
-Soft straps, that can be configured by the vendor in the Intel Flash Image Tool
-(FIT), can influence some pads' default mode. It is possible to select either a
-native function or GPIO mode for some pads on non-server SoCs, while on server
-SoCs most pads can be controlled. Thus, it is generally recommended to always
-configure all pads and don't just rely on the defaults mentioned in the
-datasheet(s) which might not reflect what the vendor configured.
-
-## Pad-related known issues and workarounds
-
-### LPC_CLKRUNB blocks S0ix states when board uses eSPI
-
-When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode.
-Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up
-enable/disable etc are ignored. Leaving this pin in native mode will keep the
-LPC Controller awake and prevent S0ix entry. This issues is know at least on
-Apollolake and Geminilake.
+The other configuration option to watch out for deals with unconnected GPIOs.
+If no pullup or pulldown is declared with these, they may end up "floating",
+i.e., not at logical high or logical low. This can cause problems such as
+unwanted power consumption or not reading the pin correctly, if it was intended
+to be strapped.

Documentation/getting_started/index.md

@@ -4,6 +4,7 @@
 * [Build System](build_system.md)
 * [Submodules](submodules.md)
 * [Kconfig](kconfig.md)
+* [Gerrit Guidelines](gerrit_guidelines.md)
+* [Documentation License](license.md)
 * [Writing Documentation](writing_documentation.md)
 * [Setting up GPIOs](gpio.md)
-* [Adding devices to a device tree](devicetree.md)

Documentation/getting_started/kconfig.md

@@ -55,6 +55,10 @@ command line.
 - savedefconfig - Creates a ‘defconfig’ file, stripping out all of the symbols
   that were left as default values.  This is very useful for debugging, and is
   how config files should be saved.
+- silentoldconfig - This evaluates the .config file the same way that the
+  oldconfig target does, but does not print out each question as it is
+  evaluated.  It still stops to query the user if an option with no answer in
+  the .config file is found.
 
 
 ### Targets not typically used in coreboot
@@ -603,7 +607,7 @@ int <expr> \[if <expr>\]
 
 
 ##### Example:
-    config PRE_GRAPHICS_DELAY_MS
+    config PRE_GRAPHICS_DELAY
         int "Graphics initialization delay in ms"
         default 0
         help
@@ -786,7 +790,7 @@ select <symbol> \[if <expr>\]
     config TPM
         bool
         default n
-        select MEMORY_MAPPED_TPM if ARCH_X86
+        select LPC_TPM if ARCH_X86
         select I2C_TPM if ARCH_ARM
         select I2C_TPM if ARCH_ARM64
         help
@@ -1188,7 +1192,7 @@ https://github.com/martinlroth/language-kconfig
 ## Syntax Checking:
 
 The Kconfig utility does some basic syntax checking on the Kconfig tree.
-Running "make oldconfig" will show any errors that the Kconfig utility
+Running "make silentoldconfig" will show any errors that the Kconfig utility
 sees.
 
 ### util/kconfig_lint

Documentation/getting_started/writing_documentation.md

@@ -6,7 +6,7 @@
 That said please always try to write documentation! One problem in the
 firmware development is the missing documentation. In this document
 you will get a brief introduction how to write, submit and publish
-documentation to coreboot.
+documenation to coreboot.
 
 ## Preparations
 
@@ -159,5 +159,5 @@ TOC tree.
 [guide]: http://www.sphinx-doc.org/en/stable/install.html
 [Sphinx]: http://www.sphinx-doc.org/en/master/
 [Markdown Guide]: https://www.markdownguide.org/
-[Gerrit Guidelines]: ../contributing/gerrit_guidelines.md
+[Gerrit Guidelines]: gerrit_guidelines.md
 [review.coreboot.org]: https://review.coreboot.org

Documentation/ifdtool/layout.md

@@ -2,7 +2,7 @@
 
 A coreboot image for an Intel SoC contains two separate definitions of the
 layout of the flash. The Intel Flash Descriptor (IFD) which defines offsets and
-sizes of various regions of flash and the [coreboot FMAP](../../lib/flashmap.md).
+sizes of various regions of flash and the [coreboot FMAP](../lib/flashmap.md).
 
 The FMAP should define all of the of the regions defined by the IFD to ensure
 that those regions are accounted for by coreboot and will not be accidentally
@@ -19,7 +19,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 | IFD Region | IFD Region name  | FMAP Name | Notes                                     |
 | index      |                  |           |                                           |
 +============+==================+===========+===========================================+
-| 0          | Flash Descriptor | SI_DESC   | Always the top 4 KiB of flash             |
+| 0          | Flash Descriptor | SI_DESC   | Always the top 4KB of flash               |
 +------------+------------------+-----------+-------------------------------------------+
 | 1          | BIOS             | SI_BIOS   | This is the region that contains coreboot |
 +------------+------------------+-----------+-------------------------------------------+
@@ -29,7 +29,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 +------------+------------------+-----------+-------------------------------------------+
 | 4          | Platform Data    | SI_PDR    |                                           |
 +------------+------------------+-----------+-------------------------------------------+
-| 8          | EC Firmware      | SI_EC     | Most ChromeOS devices do not use this     |
+| 8          | EC Firmware      | SI_EC     | Most Chrome OS devices do not use this    |
 |            |                  |           | region; EC firmware is stored in BIOS     |
 |            |                  |           | region of flash                           |
 +------------+------------------+-----------+-------------------------------------------+
@@ -40,9 +40,9 @@ way to categorize anything required by the SoC but not provided by coreboot.
 The ifdtool can be used to manipulate a firmware image with a IFD. This tool
 will not take into account the FMAP while modifying the image which can lead to
 unexpected and hard to debug issues with the firmware image. For example if the
-ME region is defined at 6 MiB in the IFD but the FMAP only allocates 4 MiB for
-the ME, then when the ME is added by the ifdtool 6 MiB will be written which
-could overwrite 2 MiB of the BIOS.
+ME region is defined at 6 MB in the IFD but the FMAP only allocates 4 MB for the
+ME, then when the ME is added by the ifdtool 6 MB will be written which could
+overwrite 2 MB of the BIOS.
 
 In order to validate that the FMAP and the IFD are compatible the ifdtool
 provides --validate (-t) option. `ifdtool -t` will read both the IFD and the
@@ -75,4 +75,4 @@ Region mismatch between pd and SI_PDR
  FMAP area SI_PDR:
   offset: 0x007fc000
   length: 0x00004000
-```
+```

Documentation/index.md

@@ -1,13 +1,9 @@
 # Welcome to the coreboot documentation
 
 This is the developer documentation for [coreboot](https://coreboot.org).
-It is built from Markdown files in the [Documentation] directory in the
-source code.
-
-## Spelling of coreboot
-
-The correct spelling of coreboot is completely in lower case characters and in
-one word without a space between the two parts.
+It is built from Markdown files in the
+[Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
+directory in the source code.
 
 ## Purpose of coreboot
 
@@ -25,7 +21,7 @@ initialization routines across many different use cases, no matter if
 they provide standard interfaces or entirely custom boot flows.
 
 Popular [payloads](payloads.md) in use with coreboot are SeaBIOS,
-which provides PCBIOS services, edk2, which provides UEFI services,
+which provides PCBIOS services, Tianocore, which provides UEFI services,
 GRUB2, the bootloader used by many Linux distributions, or depthcharge,
 a custom boot loader used on Chromebooks.
 
@@ -49,12 +45,6 @@ to the payload), but it's also a value that is deeply ingrained in the
 project. We fearlessly rip out parts of the architecture and remodel it
 when a better way of doing the same was identified.
 
-That said, since there are attempts to coerce coreboot to move in various
-directions by outside "standardization", long-established practices of
-coreboot as well as aligned projects can be documented as best practices,
-making them standards in their own right. However we reserve the right to
-retire them as the landscape shifts around us.
-
 ### One tree for everything
 
 Another difference to various other firmware projects is that we try
@@ -142,7 +132,7 @@ say hello!
 ## Getting the source code
 
 coreboot is primarily developed in the
-[git](https://review.coreboot.org/plugins/gitiles/coreboot) version control
+[git](https://review.coreboot.org/cgit/coreboot.git) version control
 system, using [Gerrit](https://review.coreboot.org) to manage
 contributions and code review.
 
@@ -172,8 +162,14 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Tutorial](tutorial/index.md)
-* [Contributing](contributing/index.md)
-* [Community](community/index.md)
+* [Coding Style](coding_style.md)
+* [Project Ideas](contributing/project_ideas.md)
+* [Documentation Ideas](contributing/documentation_ideas.md)
+* [Code of Conduct](community/code_of_conduct.md)
+* [Language style](community/language_style.md)
+* [Community forums](community/forums.md)
+* [Project services](community/services.md)
+* [coreboot at conferences](community/conferences.md)
 * [Payloads](payloads.md)
 * [Distributions](distributions.md)
 * [Technotes](technotes/index.md)
@@ -187,17 +183,9 @@ Contents:
 * [Mainboard](mainboard/index.md)
 * [Payloads](lib/payloads/index.md)
 * [Libraries](lib/index.md)
-* [Options](lib/option.md)
 * [Security](security/index.md)
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Software Bill of Materials](sbom/sbom.md)
-* [Project infrastructure & services](infrastructure/index.md)
-* [Boards supported in each release directory](releases/boards_supported_on_branches.md)
-* [Release notes](releases/index.md)
-* [Acronyms & Definitions](acronyms.md)
-* [External Resources](external_docs.md)
-* [Documentation License](documentation_license.md)
-
-[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Documentation/
+* [Release notes for past releases](releases/index.md)
+* [Flashing firmware tutorial](flash_tutorial/index.md)

Documentation/infrastructure/builders.md

@@ -1,420 +0,0 @@
-# Jenkins builder setup and configuration
-
-## How to set up a new jenkins builder
-
-### Contact a jenkins admin
-
-Let a jenkins admin know that you’re interested in setting up a jenkins
-build system.
-
-For a permanent build system, this should generally be a dedicated
-machine workstation or server class machine that is not generally being
-used for other purposes.  The coreboot builds are very intensive.
-
-It's also best to be aware that although we don't know of any security
-issues, the jenkins-node image is run with the privileged flag which
-gives the container root access to the build machine.  See
-[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-running-a-privileged-container-in-docker-is-a-bad-idea/)
-about why this is discouraged.
-
-It's recommended that you give an admin root access on your machine so
-that they can reset it in case of a failure.  This is not a requirement,
-as the system can just be disabled until someone is available to fix any
-issues.
-
-Currently active Jenkins admins:
-*   Patrick Georgi:
-    *   Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de)
-    *   IRC: pgeorgi
-*   Martin Roth:
-    *   Email: [gaumless@gmail.com](mailto:gaumless@gmail.com)
-    *   IRC: martinr
-
-### Build Machine requirements
-
-For a builder, we need a very fast system with lots of threads and
-plenty of RAM.  The builder builds and stores the git repos and output
-in tmpfs along with the ccache save area, so if there isn't enough
-memory, the builds will slow down because of smaller ccache areas and
-can run into "out of storage space" errors.
-
-#### Current Build Machines
-
-To give an idea of what a suitable build machine might be, currently the
-coreboot project has 6 active jenkins build machines.
-
-These times are taken from the week of Feb 21 - Feb 28, 2022
-
-* Congenialbuilder - 128 threads, 256GiB RAM
-  * Coverity Builds, Toolchain builds, Scanbuild-builds
-  * Fastest Passing coreboot gerrit build: 6 min, 47 sec
-  * Slowest Passing coreboot gerrit build: 14 min
-
-* Gleefulbuilder - 64 threads, 64GiB RAM
-  * Fastest Passing coreboot gerrit build: 10 min
-  * Slowest Passing coreboot gerrit build: 46 min
-
-* Fabulousbuilder - 64 threads, 64GiB RAM
-  * Fastest Passing coreboot gerrit build: 7 min, 56 sec
-  * Slowest Passing coreboot gerrit build: 56 min (No ccache)
-
-* Ultron (9elements) - 48 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 12 min
-  * Slowest Passing coreboot gerrit build: 58 min
-
-* Bob - 64 threads, 128GiB RAM
-  * Fastest Passing coreboot gerrit build: 7 min
-  * Slowest Passing coreboot gerrit build: 34 min
-
-* Pokeybuilder - 32 Threads, 96GiB RAM
-  * Runs coreboot-checkpatch and other lighter builds
-
-
-### Jenkins Builds
-
-There are a number of builds handled by the coreboot jenkins builders,
-for a number of different projects - coreboot, flashrom, memtest86+,
-em100, etc.  Many of these have builders for their current master branch
-as well as Gerrit and [Coverity](coverity.md) builds.
-
-
-#### Long builds - over 90 minutes on congenialbuilder
-There are a few builds that take a long time even on the fastest
-machines.  These tasks run overnight in the US timezones.
-* coreboot_coverity - 9 to 12 hours
-* coreboot_scanbuild - ~3 hours
-* coreboot_toolchain - ~1 hour 45 minutes
-
-
-#### All builds
-
-You can see all the builds in the main jenkins interface:
-[https://qa.coreboot.org/](https://qa.coreboot.org/)
-
-Most of the time on the builders is taken up by the coreboot master and
-coreboot gerrit builds.
-
-* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
-([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
-
-
-* [coreboot master build](https://qa.coreboot.org/job/coreboot/)
- ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
-
-
-### Stress test the machine
-
-Test the machine to make sure that building won't stress the hardware
-too much.  Install stress-ng, then run the stress test for at least an
-hour.
-
-On a system with 32 cores, it was tested with this command:
-
-```sh
-stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
-```
-
-You can watch the temperature with the sensors package or with ‘acpi -t’
-if your machine supports that.
-
-You can check for thermal throttling by running this command and seeing
-if the values go down on any of the cores after it's been running for a
-while.
-
-```sh
-while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
-```
-
-If the machine throttles or resets, you probably need to upgrade the
-cooling system.
-
-
-## jenkins-server docker installation
-
-
-### Manual Installation
-
-If you’ve met all the above requirements, and an admin has agreed to set
-up the builder in jenkins, you’re ready to go on to the next steps.
-
-
-### Set up your network so jenkins can talk to the container
-
-Expose a local port through any firewalls you might have on your router.
-This would generally be in the port forwarding section, and you'd just
-forward a port (typically 49151) from the internet directly to the
-builder’s IP address.
-
-You might also want to set up a port to forward to port 22 on your
-machine and set up openssh so you or the jenkins admins can manage
-the machine remotely (if you allow them).
-
-
-### Install and set up docker
-
-Install docker by following [the
-directions](https://docs.docker.com/engine/install/) on the docker site.
-These instructions keep changing, so just check the latest information.
-
-
-### Set up the system for the jenkins builder
-
-As a regular user - *Not root*, run:
-
-```sh
-sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
-sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR}
-wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar
-mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR}
-```
-
-
-#### Set up environment variables
-
-To make configuration and the later commands easier, these should go in
-your shell's .rc file.  Note that you only need to set them if you're
-using something other than the default.
-
-```sh
-# Set the port used on your machine to connect to jenkins.
-export COREBOOT_JENKINS_PORT=49151
-
-# Set the revision of the container from [docker hub](https://hub.docker.com/repository/docker/coreboot/coreboot-sdk)
-export DOCKER_COMMIT=2021-09-23_b0d87f753c
-
-# Set the location of where the jenkins cache directory will be.
-export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache"
-
-# Set the name of the container
-export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins"
-```
-
-Make sure any variables needed are set in your environment before
-continuing to the next step.
-
-
-### Using the Makefile for docker installation
-
-From the coreboot directory, run
-
-```sh
-make -C util/docker help
-```
-
-This will show you the available targets and variables needed:
-
-```text
-Commands for working with docker images:
-  coreboot-sdk                 - Build coreboot-sdk container
-  upload-coreboot-sdk          - Upload coreboot-sdk to hub.docker.com
-  coreboot-jenkins-node        - Build coreboot-jenkins-node container
-  upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com
-  doc.coreboot.org             - Build doc.coreboot.org container
-  clean-coreboot-containers    - Remove all docker coreboot containers
-  clean-coreboot-images        - Remove all docker coreboot images
-  docker-clean                 - Remove docker coreboot containers & images
-
-Commands for using docker images
-  docker-build-coreboot        - Build coreboot under coreboot-sdk
-      <BUILD_CMD=target>
-  docker-abuild                - Run abuild under coreboot-sdk
-      <ABUILD_ARGS='-a -B'>
-  docker-what-jenkins-does     - Run 'what-jenkins-does' target
-  docker-shell                 - Bash prompt in coreboot-jenkins-node
-      <USER=root or USER=coreboot>
-  docker-jenkins-server        - Run coreboot-jenkins-node image (for server)
-  docker-jenkins-attach        - Open shell in running jenkins server
-  docker-build-docs            - Build the documentation
-  docker-livehtml-docs         - Run sphinx-autobuild
-
-Variables:
-  COREBOOT_JENKINS_PORT=49151
-  COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache
-  COREBOOT_JENKINS_CONTAINER=coreboot_jenkins
-  COREBOOT_IMAGE_TAG=f2741aa632f
-  DOCKER_COMMIT=65718760fa
-```
-
-
-### Install the coreboot jenkins builder
-
-```sh
-make -C util/docker docker-jenkins-server
-```
-
-Your installation is complete on your side.
-
-### Tell the Admins that the machine is set up
-Let the admins know that the builder is set up so they can set up the
-machine profile on qa.coreboot.org.
-
-They need to know:
-*   Your external IP address or domain name.  If you don’t have a static
-    IP, make sure you have a dynamic dns hostname configured.
-*   The port on your machine and firewall that’s exposed for jenkins:
-    `$COREBOOT_JENKINS_PORT`
-*   The core count of the machine.
-*   How much memory is available on the machine.  This helps determine
-    the amount of memory used for ccache.
-
-
-### First build
-On the first build after a machine is reset, it will frequently take
-an hour to do the entire what-jenkins-does build while the ccache
-is getting filled up and the entire coreboot repo gets downloaded.  As
-the ccache gets populated, the build time will drop.
-
-
-## Additional Information
-
-
-### How to log in to the docker instance for debugging
-
-```sh
-make -C util/docker docker-jenkins-attach
-su coreboot
-cd ~/slave-root/workspace
-bash
-```
-
-
-WARNING: This should not be used to make changes to the build system,
-but just to debug issues. Changes to the build system image are highly
-discouraged as it leads to situations where patches can pass the build
-testing on one builder and fail on another builder. Any changes that are
-made in the image will be lost on the next update, so if you
-accidentally change something, you can remove the containers and images,
-then update to get a fresh installation.
-
-
-### How to download containers/images for a fresh installation and remove old containers
-
-To delete the old containers & images:
-
-```sh
-docker stop $COREBOOT_JENKINS_CONTAINER
-docker rm $COREBOOT_JENKINS_CONTAINER
-docker images # lists all existing images
-docker rmi XXXX # Use the image ID found in the above command.
-```
-
-To get and run the new coreboot-jenkins image, change the value in the
-`DOCKER_COMMIT` variable to the new image value.
-
-```sh
-make -C util/docker docker-jenkins-server
-```
-
-#### Getting ready to push the docker images
-
-Set up an account on hub.docker.com
-
-Get an admin to add the account to the coreboot team on hub.docker.com
-
-[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners)
-
-Make sure your credentials are configured on your host machine by
-running
-
-```sh
-docker login
-```
-
-This will prompt you for your docker username, password, and your email
-address, and write out to ~/.docker/config.json.  Without this file, you
-won’t be able to push the images.
-
-#### Updating the Dockerfiles
-
-The coreboot-sdk Dockerfile will need to be updated when any additional
-dependencies are added.  Both the coreboot-sdk and the
-coreboot-jenkins-node Dockerfiles will need to be updated to the new
-version number and git commit id anytime the toolchain is updated. Both
-files are stored in the coreboot repo under coreboot/util/docker.
-
-Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/)
-page before updating the files.
-
-#### Rebuilding the coreboot-sdk docker image to update the toolchain
-
-```sh
-make -C util/docker coreboot-sdk
-```
-
-This takes a relatively long time.
-
-#### Test the coreboot-sdk docker image
-
-There are two methods of running the docker image - interactively as a
-shell, or doing the build directly.  Running interactively as a shell is
-useful for early testing, because it allows you to update the image
-(without any changes getting saved) and re-test builds.  This saves the
-time of having to rebuild the image for every issue you find.
-
-#### Running the docker image interactively
-
-Run:
-
-```sh
-make -C util/docker docker-jenkins-server
-make -C util/docker docker-jenkins-attach
-```
-
-#### Running the build directly
-
-From the coreboot directory:
-
-```sh
-make -C util/docker docker-build-coreboot
-```
-
-You’ll also want to test building the other projects and payloads:
-ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo,
-nvramcui, tint...
-
-#### Pushing the coreboot-sdk image to hub.docker.com for use
-
-When you’re satisfied with the testing, push the coreboot-sdk image to
-the hub.docker.com
-
-```sh
-make -C util/docker upload-coreboot-sdk
-```
-
-#### Building and pushing the coreboot-jenkins-node docker image
-
-This docker image is pretty simple, so there’s not really any testing
-that needs to be done.
-
-```sh
-make -C util/docker coreboot-jenkins-node
-make -C util/docker upload-coreboot-jenkins-node
-```
-
-### Coverity Setup
-
-To run coverity jobs, the builder needs to have the tools available, and
-to be marked as a coverity builder.
-
-
-#### Set up the Coverity tools
-
-Download the Linux-64 coverity build tool and decompress it into your
-cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable
-on the jenkins server.
-
-[https://scan.coverity.com/download](https://scan.coverity.com/download)
-
-Rename the directory from its original name
-(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a
-symlink:
-
-```sh
-ln -s cov-analysis-linux64-7.7.0.4 coverity
-```
-
-
-Let the admins know that the ‘coverity’ label can be added to the
-builder.

Documentation/infrastructure/coverity.md

@@ -1,103 +0,0 @@
-# Coverity Scan for open source firmware
-
-## What’s Coverity and Coverity Scan?
-
-Coverity is a static analysis tool. It hooks into the build process
-and in addition to the compiler creating object files, Coverity collects
-information about the code. That data is then processed in a separate pass
-to identify common programming errors, like out of bounds accesses in C.
-
-Coverity Scan is an online service for Open Source projects providing this
-analysis for free. The analysis pass is done on their servers and issues
-can be handled in their [web UI](https://scan.coverity.com/).
-
-The Scan service has some quotas based on code size to avoid overloading
-the system, but even at one build per week, that’s usually good enough
-because the identified issues still need to be triaged and fixed or they
-will simply be re-identified next week.
-
-### Triage?
-
-The Web UI looks a bit like an issue tracker, even if it’s not a very
-good one. It’s possible to mark identified issues as valid or invalid,
-and annotate them with metadata which CLs fix them. The latter isn’t
-strictly necessary because Coverity Scan simply marks issues it can’t
-find anymore as fixed, but at times it helped identify issues that made
-a comeback.
-
-### Alternatives
-
-There’s also clang’s scan-build, which is fully open-source, and
-finds different issues. As such, it’s less of an alternative and more
-of a complement.
-
-There’s a regular run of that for coreboot but not for the other projects
-hosted at coreboot.org.
-
-One downside is that it emits a bunch of HTML to report on issues,
-but there’s no interactivity (e.g. marking issues solved), no way
-to merge multiple builds (e.g. multiple board builds of a single tree)
-or a simple way to extract burndown charts and the like from that.
-
-#### Looking for a project?
-
-On the upside, it can emit the data in a machine readable format, so if
-anybody needs a project, a scan-build web-frontend like Coverity Scan would
-be feasible without having to go through scan-build’s guts, just by parsing
-text files - plus all the stateful and web parts to build on top.
-
-## Logging into Coverity Scan
-
-Coverity Scan needs an account. It supports its own accounts and GitHub
-OAuth.
-
-Access to the dashboards needs approval: Request and you shall receive.
-
-## coreboot & friends and Coverity Scan
-
-coreboot, flashrom, Chromium EC and other projects of that family have
-been made Coverity aware, that is, their build systems support building
-with a custom compiler configuration passed in “just right” to enable
-Coverity to add its hooks.
-
-The public coreboot CI system at
-[https://qa.coreboot.org/](https://qa.coreboot.org/) regularly does
-builds with Coverity and sends them off to Coverity Scan.
-
-Specifically, it covers:
-
-* Chromium EC: [Coverity Scan site][crECCoverity] ([build job][crECBuildJob])
-* coreboot: [Coverity Scan site][corebootCoverity] ([build job][corebootBuildJob]), [scan-build output][corebootScanBuild] ([build job][corebootScanBuildJob])
-* em100: [Coverity Scan site][em100Coverity] ([build job][em100BuildJob])
-* fcode-utils: [Coverity Scan site][fcodeUtilsCoverity] ([build job][fcodeUtilsBuildJob])
-* flashrom: [Coverity Scan site][flashromCoverity] ([build job][flashromBuildJob])
-* memtest86+: [Coverity Scan site][memtestCoverity] ([build job][memtestBuildJob])
-* vboot: [Coverity Scan site][vbootCoverity] ([build job][vbootBuildJob])
-
-[crECCoverity]: https://scan.coverity.com/projects/chromium-ec
-[corebootCoverity]: https://scan.coverity.com/projects/coreboot
-[em100Coverity]: https://scan.coverity.com/projects/em100
-[fcodeUtilsCoverity]: https://scan.coverity.com/projects/fcode-utils
-[flashromCoverity]: https://scan.coverity.com/projects/flashrom
-[memtestCoverity]: https://scan.coverity.com/projects/memtest86
-[vbootCoverity]: https://scan.coverity.com/projects/vboot
-
-[corebootScanBuild]: https://www.coreboot.org/scan-build/
-
-[crECBuildJob]: https://qa.coreboot.org/view/coverity/job/ChromeEC-Coverity/
-[corebootBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot-coverity/
-[corebootScanBuildJob]: https://qa.coreboot.org/view/coverity/job/coreboot_scanbuild/
-[em100BuildJob]: https://qa.coreboot.org/view/coverity/job/em100-coverity/
-[fcodeUtilsBuildJob]: https://qa.coreboot.org/view/coverity/job/fcode-utils-coverity/
-[flashromBuildJob]: https://qa.coreboot.org/view/coverity/job/flashrom-coverity/
-[memtestBuildJob]: https://qa.coreboot.org/view/coverity/job/memtest86plus-coverity/
-[vbootBuildJob]: https://qa.coreboot.org/view/coverity/job/vboot-coverity/
-
-Some projects (e.g. Chromium EC) build a different subset of boards on
-each run, ensuring that everything is analyzed eventually. The downside
-is that coverity issues pop up and disappear somewhat randomly as they
-are discovered and go unnoticed in a later build.
-
-More projects that are hosted on review.coreboot.org (potentially as a
-mirror, like vboot and EC) could be served through that pipeline. Reach
-out to {stepan,patrick,martin}@coreboot.org.

Documentation/infrastructure/index.md

@@ -1,12 +0,0 @@
-# Project infrastructure & services
-
-This section contains documentation about our infrastructure
-
-## Services
-
-* [Project services](services.md)
-
-
-## Jenkins builders and builds
-* [Setting up Jenkins build machines](builders.md)
-* [Coverity Scan integration](coverity.md)

Documentation/infrastructure/services.md

@@ -1,60 +0,0 @@
-# Accounts on coreboot.org
-
-There are a number of places where you can benefit from creating an account
-in our community. Since there is no single sign-on system in place (at this
-time), they come with their own setup routines.
-
-## Gerrit code review
-We exchange and review patches to the code using our [Gerrit code review
-system](https://review.coreboot.org).
-
-It allows logging in with a Google or GitHub account using OAuth2 as well
-as with any OpenID provider that you may already use.
-
-On the [settings screen](https://review.coreboot.org/settings) you can register
-all your email addresses you intend to use in the context of coreboot
-development so that commits with your email address in them are associated with
-you properly.
-
-Below is a list of its SSH host keys and fingerprints.
-```Bash
-[review.coreboot.org]:29418 ssh-rsa AAAAB3NzaC1yc2EAAAABIwAAAQEAvNDn8qGHlWM/5ndFltStlg3QTc8xvGOgyjxxZByhMZx8LVE4cfgF38WP3euq0avyFy7gAJNghHorXpYKoOzuQPn2WNi5QhyGsUhg7ZJz9hC7Z2gqxxsZF3E7rku4Uj9sN7hWx9fBngxD4z2tP4y/18FTT5XTMcC3Q2sBCOLM0XVAO5R/nb2GO3d27avy+sanKAFEwJHnZ996IoTlU8JJFyi1Y6g30dC2K75oFgCtzntxf++wvrkkKPa+CFQub8fp20shat9WwX9kXjpRjt/Yv9LgqFCaI5ztJvWXicAmbgghGVzbzz4GoSjjF9cxxJF//KTmNb4iGQqmP3Olm27xuw==
-
-[review.coreboot.org]:29418 ecdsa-sha2-nistp256 AAAAE2VjZHNhLXNoYTItbmlzdHAyNTYAAAAIbmlzdHAyNTYAAABBBBzlwf/bFejt4EEz1QmbNOfK/HN1NtdcefrRs5Gs42uGnIvjxsff+vEF3//jCTvFPadoy3DrPsbQB3ioQAcYppk=
-
-[review.coreboot.org]:29418 ssh-ed25519 AAAAC3NzaC1lZDI1NTE5AAAAIOC3Z32gc+1rJXhKX+SW0vESlXR/h/mhcxd+62B1PWC2
-```
-
-```Bash
-2048 SHA256:WW5prF7YE3MTnkRIxLklr9Gxddj9s5BZKUqWJF5dnTg review.coreboot.org:29418 (RSA)
-256 SHA256:IuLv/DgrBtVn36eMP1zFD0ISAl3IxIoCeiRms6UDhZc review.coreboot.org:29418 (ECDSA)
-256 SHA256:QFZieVHy8dCRl9tDib6qiwELnfa7SVU4ZWJ5VrXoC8k review.coreboot.org:29418 (ED25519)
-```
-
-### https push access
-When using the https URLs to git repositories, you can push with the "HTTP
-Credentials" you can have Gerrit generate for you on that page. By default,
-git uses `$HOME/.netrc` for http authentication data, so add a line there
-stating:
-
-    machine review.coreboot.org login $your-user-name password $your-password
-
-### Gerrit user avatar
-To setup an avatar to show in Gerrit, clone the avatars repository at
-https://review.coreboot.org/gerrit-avatars.git and add a file named
-$your-user-ID.jpg (the user ID is a number shown on the [settings screen](https://review.coreboot.org/settings)).
-The image must be provided in JPEG format, must be square and have at most 50000
-bytes.
-
-After you push for review, the system will automatically verify your change
-and, if adhering to these constraints, approve it. You can then immediately
-submit it.
-
-## Issue tracker
-We have an [issue tracker](https://ticket.coreboot.org) that is used for
-coreboot and related code, such as libpayload, as well as for the project's
-infrastructure.
-
-It can be helpful to refer to issues we track there in commit messages:
-
-    Fixes: https://ticket.coreboot.org/issues/$id

Documentation/lib/flashmap.md

@@ -4,7 +4,7 @@
 
 [Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format to
 describe partitions in a flash chip. It was added to coreboot to support the
-requirements of ChromiumOS firmware but then was also used in other scenarios
+requirements of Chromium OS firmware but then was also used in other scenarios
 where precise placement of data in flash was necessary, or for data that is
 written to at runtime, as CBFS is considered too fragile for such situations.
 The Flashmap implementation inside coreboot is the de facto standard today.
@@ -17,8 +17,7 @@ something else) should have its own Flashmap section, and everything else should
 normally go into CBFS.
 
 The Flashmap itself starts with a header `struct fmap` and followed by a list of
-section descriptions in `struct fmap_area`. All fields in those structures are
-in little endian format.
+section descriptions in `struct fmap_area`.
 
 ### Header
 The header `struct fmap` has following fields:

Documentation/lib/fw_config.md

@@ -8,8 +8,8 @@ BIOS image to be used across a wide variety of devices which may have key differ
 otherwise similar enough to use the same coreboot build target.
 
 The initial implementation is designed to take advantage of a bitmask returned by the Embedded
-Controller on Google ChromeOS devices which allows the manufacturer to use the same firmware
-image across multiple devices by selecting various options at runtime.  See the ChromiumOS
+Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware
+image across multiple devices by selecting various options at runtime.  See the Chromium OS
 [Firmware Config][1] documentation for more information.
 
 This firmware configuration interface differs from the CMOS option interface in that this
@@ -91,7 +91,7 @@ file in CBFS use the value it contains when matching fields and options.
 
 ### Embedded Controller
 
-Google ChromeOS devices support an Embedded Controller interface for reading and writing the
+Google Chrome OS devices support an Embedded Controller interface for reading and writing the
 firmware configuration value, along with other board-specific information.  It is possible for
 coreboot to read this value at boot on systems that support this feature.
 
@@ -101,9 +101,9 @@ possible by enabling the CBFS source and coreboot will look in CBFS first for a
 before asking the embedded controller.
 
 It is also possible to adjust the value in the embedded controller *(after disabling write
-protection)* with the `ectool` command in a ChromeOS environment.
+protection)* with the `ectool` command in a Chrome OS environment.
 
-For more information on the firmware configuration field on ChromeOS devices see the Chromium
+For more information on the firmware configuration field on Chrome OS devices see the Chromium
 documentation for [Firmware Config][1] and [Board Info][2].
 
 [1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md
@@ -121,48 +121,12 @@ Each field is defined by providing the field name and the start and end bit mark
 location in the bitmask.  Field names must be at least three characters long in order to
 satisfy the sconfig parser requirements and they must be unique with non-overlapping masks.
 
-	field <name> <start-bit> <end-bit> [option...] end
+    field <name> <start-bit> <end-bit> [option...] end
 
 For single-bit fields only one number is needed:
 
 	field <name> <bit> [option...] end
 
-A field definition can also contain multiple sets of bit masks, which can be dis-contiguous.
-They are treated as if they are contiguous when defining option values.  This allows for
-extending fields even after the bits after its current masks are occupied.
-
-	field <name> <start-bit0> <end-bit0> | <start-bit1> <end-bit1> | ...
-
-For example, if more audio options need to be supported:
-
-	field AUDIO 3 3
-		option AUDIO_0  0
-		option AUDIO_1  1
-	end
-	field OTHER 4 4
-		...
-	end
-
-the following can be done:
-
-	field AUDIO 3 3 | 5 5
-		option AUDIO_FOO   0
-		option AUDIO_BLAH  1
-		option AUDIO_BAR   2
-		option AUDIO_BAZ   3
-	end
-	field OTHER 4 4
-		...
-	end
-
-In that case, the AUDIO masks are extended like so:
-
-	#define FW_CONFIG_FIELD_AUDIO_MASK						0x28
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE	0x0
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH_VALUE	0x8
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE	0x20
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAz_VALUE	0x28
-
 Each `field` definition starts a new block that can be composed of zero or more field options,
 and it is terminated with `end`.
 
@@ -383,7 +347,7 @@ training.  This example expects that the default value of this `register` is set
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
-	if (fw_config_probe(FW_CONFIG(FEATURE, DISABLED))
+	if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED))
 		mupd->ExampleFeature = false;
 }
 ```

Documentation/lib/option.md

@@ -1,31 +0,0 @@
-# Option API
-
-The option API around the `set_option(const char *name, void *val)` and
-`get_option(void *dest, const char *name)` functions deprecated in favor
-of a type-safe API.
-
-Historically, options were stored in RTC battery-backed CMOS RAM inside
-the chipset on PC platforms. Nowadays, options can also be stored in the
-same flash chip as the boot firmware or through some BMC interface.
-
-The new type-safe option framework can be used by calling
-`enum cb_err set_uint_option(const char *name, unsigned int value)` and
-`unsigned int get_uint_option(const char *name, const unsigned int fallback)`.
-
-The default setting is `OPTION_BACKEND_NONE`, which disables any runtime
-configurable options. If supported by a mainboard, the `USE_OPTION_TABLE`
-and `USE_MAINBOARD_SPECIFIC_OPTION_BACKEND` choices are visible, and can
-be selected to enable runtime configurability.
-
-# Mainboard-specific option backend
-
-Mainboards with a mainboard-specific (vendor-defined) method to access
-options can select `HAVE_MAINBOARD_SPECIFIC_OPTION_BACKEND` to provide
-implementations of the option API accessors. To allow choosing between
-multiple option backends, the mainboard-specific implementation should
-only be built when `USE_MAINBOARD_SPECIFIC_OPTION_BACKEND` is selected.
-
-Where possible, using a generic, mainboard-independent mechanism should
-be preferred over reinventing the wheel in mainboard-specific code. The
-mainboard-specific approach should only be used when the option storage
-mechanism has to satisfy externally-imposed, vendor-defined constraints.

Documentation/lib/payloads/fit.md

@@ -25,7 +25,7 @@ The section must be named in order to be found by the FIT parser:
 
 ## Architecture specifics
 
-The FIT parser needs architecture support.
+The FIT parser needs architecure support.
 
 ### aarch32
 The source code can be found in `src/arch/arm/fit_payload.c`.

Documentation/lib/timestamp.md

@@ -99,7 +99,7 @@ exist and an entry structure to hold variable number of entries.
 
 ### entries
 
-This field holds the details of each timestamp entry, up to a maximum
+This field holds the details of each timestamp entry, upto a maximum
 of `MAX_TIMESTAMP_CACHE` which is defined as 16 entries. Each entry is
 defined by:
 

Documentation/mainboard/acer/g43t-am3.md

@@ -1,177 +0,0 @@
-# Acer G43T-AM3
-
-The Acer G43T-AM3 is a microATX-sized desktop board. It was used for the
-Acer models Aspire M3800, Aspire M5800 and possibly more.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel G43 (called x4x in coreboot code)          |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel ICH10R (called i82801jx in coreboot code)  |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 775                                          |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1066                                    |
-+------------------+--------------------------------------------------+
-| SuperIO          | ITE IT8720F                                      |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82567V-2 Gigabit Ethernet                  |
-+------------------+--------------------------------------------------+
-```
-
-There is no serial port. Serial console output is possible by soldering
-to a point at the corresponding Super I/O pin and patching the
-mainboard-specific code accordingly.
-
-## Status
-
-### Working
-
-Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
-(linux-4.19.50).
-
-+ Intel Core 2 processors at up to FSB 1333
-+ All four DIMM slots at 1066 MHz (tested 2x2GB + 2x4GB)
-+ Integrated graphics (libgfxinit)
-+ HDMI and VGA ports
-+ Both PCI slots
-+ Both PCI-e slots
-+ USB (8 internal, 4 external)
-+ All six SATA ports
-+ Onboard Ethernet
-+ Onboard sound card with output on the rear stereo connector
-+ PS/2 mouse and keyboard
-    + With SeaBIOS, use CONFIG_SEABIOS_PS2_TIMEOUT, tested: 500
-    + With FILO it works without further settings
-+ Temperature readings from the Super I/O (including the CPU temperature
-  via PECI)
-+ Super I/O EC automatic fan control
-+ S3 suspend/resume
-+ Poweroff
-
-### Not working
-
-+ DDR3 memory with 512Mx8 chips (G43 limitation)
-+ 4x4GB of DDR3 memory (works, but showed a single bit error within one
-  pass of Memtest86+ 5.01)
-+ Super I/O voltage reading conversions
-
-### Untested
-
-+ Other audio jacks or the front panel header
-+ S/PDIF output
-+ On-board Firewire
-+ Wake-on-LAN
-
-## Flashing coreboot
-
-```eval_rst
-+-------------------+---------------------+
-| Type              | Value               |
-+===================+=====================+
-| Socketed flash    | No                  |
-+-------------------+---------------------+
-| Model             | Macronix MX25L1605D |
-+-------------------+---------------------+
-| Size              | 2 MiB               |
-+-------------------+---------------------+
-| Package           | 8-Pin SOP           |
-+-------------------+---------------------+
-| Write protection  | No                  |
-+-------------------+---------------------+
-| Dual BIOS feature | No                  |
-+-------------------+---------------------+
-| Internal flashing | Yes                 |
-+-------------------+---------------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-```
-00000000:00001fff fd
-00100000:001fffff bios
-00006000:000fffff me
-00002000:00005fff gbe
-```
-
-In general, flashing is possible internally and from an external header. It
-might be necessary to specify the chip type; `MX25L1605D/MX25L1608D/MX25L1673E`
-is the correct one, not `MX25L1605`.
-
-### Internal flashing
-
-Internal access to the flash chip is unrestricted. When installing coreboot,
-only the BIOS region should be updated by passing the `--ifd` and `-i bios`
-parameters to flashrom. A full backup is advisable.
-
-Here is an example:
-
-```
-$ sudo flashrom \
-  -p internal \
-  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
-  -r backup.rom
-$ sudo flashrom \
-  -p internal \
-  -c "MX25L1605D/MX25L1608D/MX25L1673E" \
-  --ifd -i bios \
-  -w coreboot.rom
-```
-
-```eval_rst
-In addition to the information here, please see the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-### External flashing
-
-The SPI flash chip on this board can be flashed externally through the
-SPI_ROM1 header while the board is off and disconnected from power. There
-seems to be a diode that prevents the external programmer from powering the
-whole board.
-
-The signal assignment on the header is identical to the pinout of the flash
-chip. The pinout diagram below is valid when the PCI slots are on the left
-and the CPU is on the right. Note that HOLD# and WP# must be pulled high
-(to VCC) to be able to flash the chip.
-
-                +---+---+
-     SPI_CSn <- | x | x | -> VCC
-                +---+---+
-    SPI_MISO <- | x | x | -> HOLDn
-                +---+---+
-         WPn <- | x | x | -> SPI_CLK
-                +---+---+
-         GND <- | x | x | -> SPI_MOSI
-                +---+---+
-
-## Intel Management Engine
-
-The Intel Management Engine (ME) can be disabled by setting the ME_DISABLE
-jumper on the board. It pulls GPIO33 on the ICH10 low, causing the "Flash
-Descriptor Security Override Strap" to be set. This disables the ME and also
-disables any read/write restrictions to the flash chip that may be set in the
-Intel Flash Descriptor (IFD) (none on this board). Note that changing this
-jumper only comes into effect when starting the board from a shutdown or
-suspend state, not during normal operation.
-
-To completely remove the ME blob from the flash image and to decrease the size
-of the ME region, thus increasing the size of the BIOS region, `me_cleaner` can
-be used with the `-t`, `-r` and `-S` options.
-
-## Fan control
-
-There are two fan connectors that can be controlled individually. CPU_FAN
-can only control a fan by a PWM signal and SYS_FAN only by voltage. See
-the mainboard's `devicetree.cb` file for how coreboot configures the Super
-I/O to control the fans.
-
-## Variants
-
-Various similar mainboards exist, like the Acer Q45T-AM. During a discussion
-in #coreboot on IRC, ECS was suspected to be the original designer of this
-series of mainboards. They have similar models such as the ECS G43T-WM.

Documentation/mainboard/amd/pademelon/pademelon.md

@@ -1,80 +0,0 @@
-# Pademelon board
-
-## Specs (with Merlin Falcon SOC)
-
-* Two 260-pin DDR4 SO-DIMM slots, 1.2V DDR4-1333/1600/1866/2133 SO-DIMMs
-  Supports 4GB, 8GB and 16GB DDR4 unbuffered ECC (Merlin Falcon)SO-DIMMs
-* Can use Prairie Falcon, Brown Falcon, Merlin Falcon, though coreboot
-  code is specific for Merlin Falcon SOC. Some specs will change if not
-  using Merlin Falcon.
-* One half mini PCI-Express slot on back side of mainboard
-* One PCI Express® 3.0 x8 slot
-* Two SATA3 ports with 6Gb/s data transfer rate
-* Two USB 2.0 ports at rear panel
-* Two USB 3.0 ports at rear panel
-* Dual Gigabit Ethernet from Realtek RTL8111F Gigabit controller
-* 6-channel High-Definition audio from Realtek ALC662 codec
-* One soldered down SPI flash with dediprog header
-
-## Mainboard
-
-![mainboard][pademelon]
-
-Three items are marked in this picture
-1. dediprog header
-2. memory dimms, address 0xA0 and 0xA4
-3. SATA cables connected to motherboard
-
-## Back panel
-
-![back panel][pademelon_io]
-
-* The lower serial port is UART A (debug serial)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+--------------------+
-| Type                | Value              |
-+=====================+====================+
-| Socketed flash      | no                 |
-+---------------------+--------------------+
-| Model               | Macronix MX256435E |
-+---------------------+--------------------+
-| Size                | 8 MiB              |
-+---------------------+--------------------+
-| Flash programming   | dediprog header    |
-+---------------------+--------------------+
-| Package             | SOIC-8             |
-+---------------------+--------------------+
-| Write protection    | No                 |
-+---------------------+--------------------+
-```
-
-## Technology
-
-```eval_rst
-+---------------+------------------------------+
-| Fan control   | Using fintek F81803A         |
-+---------------+------------------------------+
-| CPU           | Merlin Falcon (see reference)|
-+---------------+------------------------------+
-```
-
-## Description of pictures within this document
-
-```eval_rst
-+----------------------------+----------------------------------------+
-|pademelon.jpg               | Motherboard with components identified |
-+----------------------------+----------------------------------------+
-|pademelon_io.jpg            | Back panel picture                     |
-+----------------------------+----------------------------------------+
-```
-
-## Reference
-
-[Merlin Falcon BKDG][merlinfalcon]
-
-[merlinfalcon]: ../../../soc/amd/family15h.md
-[pademelon]: pademelon.jpg
-[pademelon_io]: pademelon_io.jpg