Fix peg for bonw15

Change-Id: Ifa62cdfd16cc0d246491fc2c8d4a11d8bfb71aa9

.gitmodules

@@ -1,67 +1,67 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 	branch = stable-1.1
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe
 [submodule "util/goswid"]
 	path = util/goswid
-	url = ../goswid
+	url = https://review.coreboot.org/goswid.git
 	branch = trunk

Documentation/Makefile

@@ -4,16 +4,15 @@
 # hacked together by Stefan Reinauer <stepan@openbios.org>
 #
 
-PDFLATEX  = pdflatex -t a4
-BUILDDIR ?= _build
+PDFLATEX=pdflatex -t a4
 
 FIGS=codeflow.pdf hypertransport.pdf
 
-all: sphinx corebootPortingGuide.pdf
+all: corebootPortingGuide.pdf
 
-SVG2PDF=$(shell command -v svg2pdf)
-INKSCAPE=$(shell command -v inkscape)
-CONVERT=$(shell command -v convert)
+SVG2PDF=$(shell which svg2pdf)
+INKSCAPE=$(shell which inkscape)
+CONVERT=$(shell which convert)
 
 codeflow.pdf: codeflow.svg
 ifneq ($(strip $(SVG2PDF)),)
@@ -33,9 +32,6 @@ else ifneq ($(strip $(CONVERT)),)
 	convert $< $@
 endif
 
-$(BUILDDIR):
-	mkdir -p $(BUILDDIR)
-
 corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 	# 2 times to make sure we have a current toc.
 	$(PDFLATEX) corebootBuildingGuide.tex
@@ -44,11 +40,11 @@ corebootPortingGuide.toc: $(FIGS) corebootBuildingGuide.tex
 corebootPortingGuide.pdf: $(FIGS) corebootBuildingGuide.tex corebootPortingGuide.toc
 	$(PDFLATEX) corebootBuildingGuide.tex
 
-sphinx: $(BUILDDIR)
-	$(MAKE) -f Makefile.sphinx html BUILDDIR="$(BUILDDIR)"
+sphinx:
+	$(MAKE) -f Makefile.sphinx html
 
 clean-sphinx:
-	$(MAKE) -f Makefile.sphinx clean BUILDDIR="$(BUILDDIR)"
+	$(MAKE) -f Makefile.sphinx clean
 
 clean: clean-sphinx
 	rm -f *.aux *.idx *.log *.toc *.out $(FIGS)
@@ -56,25 +52,5 @@ clean: clean-sphinx
 distclean: clean
 	rm -f corebootPortingGuide.pdf
 
-livesphinx: $(BUILDDIR)
-	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)" BUILDDIR="$(BUILDDIR)"
-
-test:
-	@echo "Test for logging purposes - Failing tests will not fail the build"
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx html
-	-$(MAKE) -f Makefile.sphinx clean && $(MAKE) -K -f Makefile.sphinx doctest
-
-help:
-	@echo "all            - Builds coreboot porting guide PDF (outdated)"
-	@echo "sphinx         - Builds html documentation in _build directory"
-	@echo "clean          - Cleans intermediate files"
-	@echo "clean-sphinx   - Removes sphinx output files"
-	@echo "distclean      - Removes PDF files as well"
-	@echo "test           - Runs documentation tests"
-	@echo
-	@echo "  Makefile.sphinx builds - run with $(MAKE) -f Makefile-sphinx [target]"
-	@echo
-	@$(MAKE) -s -f Makefile.sphinx help 2>/dev/null
-
-.phony: help livesphinx sphinx test
-.phony: distclean clean clean-sphinx
+livesphinx:
+	$(MAKE) -f Makefile.sphinx livehtml SPHINXOPTS="$(SPHINXOPTS)"

Documentation/acpi/index.md

@@ -10,13 +10,3 @@ upwards.
 ## GPIO
 
 - [GPIO toggling in ACPI AML](gpio.md)
-
-## Windows-specific ACPI documentation
-
-- [Windows-specific documentation](windows.md)
-
-##  ACPI specification - Useful links
-
-- [ACPI Specification 6.5](https://uefi.org/specs/ACPI/6.5/index.html)
-- [ASL 2.0 Syntax](https://uefi.org/specs/ACPI/6.5/19_ASL_Reference.html#asl-2-0-symbolic-operators-and-expressions)
-- [Predefined ACPI Names](https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#predefined-acpi-names)

Documentation/acpi/windows.md

@@ -1,9 +0,0 @@
-# Testing ACPI changes under Windows
-
-When testing ACPI changes in coreboot against Windows 8 or newer, beware that
-during a normal boot after a clean shutdown, Windows will use the fast startup
-mechanism which results in it not evaluating the changed ACPI code but instead
-using some cached version which won't include the changes that were supposed to
-be tested. In order for Windows to actually use the new ACPI tables, either
-disable the fast startup or just tell Windows to do a reboot which will make it
-read and use the ACPI tables in memory instead of an outdated cached version.

Documentation/acronyms.md

@@ -1,5 +1,7 @@
 # Firmware and Computer Acronyms, Initialisms and Definitions
 
+** Note that this document even more of a work in progress than most **
+** of the coreboot documentation **
 
 ## _0-9
 
@@ -18,25 +20,24 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   initialization that happens from the PSP.  Significantly, Memory
   Initialization.
 * AC - Electricity: [**Alternating Current**](https://en.wikipedia.org/wiki/Alternating_current)
-* Ack - Acknowledgment / Acknowledged
+* Ack - Acknowledgment
 * ACM – [**Authenticated Code Module**](https://doc.coreboot.org/security/intel/acm.html)
 * ACP - [**Average CPU power**](https://en.wikipedia.org/wiki/Thermal_design_power)
 * ACPI - The [**Advanced Configuration and Power
   Interface**](http://en.wikipedia.org/wiki/Advanced_Configuration_and_Power_Interface)
   is an industry standard for letting the OS control power management.
-  * [https://uefi.org/specifications](https://uefi.org/specifications)
+  * [http://www.acpi.info/](http://www.acpi.info/)
   * [http://kernelslacker.livejournal.com/88243.html](http://kernelslacker.livejournal.com/88243.html)
 * ADC - [**Analog-to-Digital Converter**](https://en.wikipedia.org/wiki/Analog-to-digital_converter)
 * ADL - Intel: [**Alder Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/alder_lake)
 * AES - [**Advanced Encryption Standard**](https://en.wikipedia.org/wiki/Advanced_Encryption_Standard)
-* AESKL - Intel: AES Key Locker
 * AGESA - [**AMD Generic Encapsulated Software Architecture**](https://en.wikipedia.org/wiki/AGESA_)
 * AGP - The [**Accelerated Graphics
-  Port**](https://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
+  Port**](http://en.wikipedia.org/wiki/Accelerated_Graphics_Port) is an
   older (1997-2004) point-to-point bus for video cards to communicate
   with the processor.
 * AHCI - The [**Advanced Host Controller
-  Interface**](https://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
+  Interface**](http://en.wikipedia.org/wiki/Advanced_Host_Controller_Interface)
   is a standard register set for communicating with a SATA controller.
   * [http://www.intel.com/technology/serialata/ahci.htm](http://www.intel.com/technology/serialata/ahci.htm)
   * [http://download.intel.com/technology/serialata/pdf/rev1_3.pdf](http://download.intel.com/technology/serialata/pdf/rev1_3.pdf)
@@ -50,11 +51,10 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   An open standard to connect and manage functional blocks in an SoC
   (System on a Chip)
 * AMD64 - Another name for [**x86-64**](https://en.wikipedia.org/wiki/X86-64)
-* AMD-Vi AMD: The AMD name for their IOMMU implementation
 * AMPL - AMD: [**Advanced Platform Management Link**](https://web.archive.org/web/20220509053546/https://developer.amd.com/wordpress/media/2012/10/419181.pdf) - Also referred to as
   SBI: Sideband Interface
 * AMT - Intel: [**Active Management Technology**](https://en.wikipedia.org/wiki/Intel_Active_Management_Technology)
-* ANSI - [**American National Standards Institute**](https://en.wikipedia.org/wiki/American_National_Standards_Institute)
+* ANSI - [**American National Standards Institute**](American_National_Standards_Institute)
 * AOAC - AMD: Always On, Always Connected
 * AP - Application processor - The main processor on the board (as
   opposed to the embedded controller or other processors that may be on
@@ -63,7 +63,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * APCB - AMD: AMD PSP Customization Block
 * API - [**Application Programming Interface**](https://en.wikipedia.org/wiki/API)
 * APIC - [**Advanced Programmable Interrupt
-  Controller**](https://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
+  Controller**](http://en.wikipedia.org/wiki/Advanced_Programmable_Interrupt_Controller)
   this is an advanced version of a PIC that can handle interrupts from
   and for multiple CPUs. Modern systems usually have several APICs:
   Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.
@@ -90,7 +90,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ASPM - PCI: [**Active State Power
   Management**](https://en.wikipedia.org/wiki/Active_State_Power_Management)
 * ATA - [**Advanced Technology Attachment**](https://en.wikipedia.org/wiki/Parallel_ATA)
-* ATS - PCIe: Address Translation Services
 * ATAPI - [**ATA Packet Interface**](https://en.wikipedia.org/wiki/Parallel_ATA#ATAPI)
 * ATX - [**Advanced Technology eXtended**](https://en.wikipedia.org/wiki/ATX)
 * AVX -  [**Advanced Vector Extensions**](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions)
@@ -98,7 +97,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## B
 
-* BAR - [**Base Address Register**](https://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
+* BAR - [**Base Address Register**](http://en.wikipedia.org/wiki/Base_Address_Register) This generally refers to one of the
   base address registers in the PCI config space of a PCI device
 * Baud - [**Baud**](https://en.wikipedia.org/wiki/Baud) - Not an acronym - Symbol rate unit of symbols per second, named
   after Émile Baudot
@@ -117,7 +116,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   the entire 4GiB of the 32-bit address space. Also known as flat mode
   or [**Unreal mode**](https://en.wikipedia.org/wiki/Unreal_mode).
 * BIOS - [**Basic Input/Output
-  System**](https://en.wikipedia.org/wiki/BIOS)
+  System**](http://en.wikipedia.org/wiki/BIOS)
 * BIST - The [**Built-in Self Test**](https://en.wikipedia.org/wiki/Built-in_self-test) is a test run by the processor on
   itself when it is first started. Usually, any nonzero value indicates
   that the selftest failed.
@@ -183,7 +182,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   generally used to describe a section of NVRAM (Non-volatile RAM), in
   this case a section battery-backed memory in the RTC (Real Time Clock)
   that is typically used to store BIOS settings.
-  *[https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](https://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
+  *[http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory](http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory)
 * CNL - Intel: [**Cannon Lake**](https://en.wikichip.org/wiki/intel/microarchitectures/cannon_lake) (formerly Skymont)
 * CNVi - Intel: [**Connectivity Integration**](https://en.wikipedia.org/wiki/CNVi)
 * CPL - x86: Current Privilege Level - Privilege levels range from 0-3; lower numbers are more privileged.
@@ -191,14 +190,14 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CPPC - AMD: Collaborative Processor Performance Controls
 * CPS - Characters Per Second
 * CPU - [**Central Processing
-  Unit**](https://en.wikipedia.org/wiki/Central_processing_unit)
+  Unit**](http://en.wikipedia.org/wiki/Central_processing_unit)
 * CPUID - x86: [**CPU Identification**](https://en.wikipedia.org/wiki/CPUID) opcode
 * Cr50 - Google: The first generation Google Security Chip (GSC) used on
   ChromeOS devices.
 * CRB - Customer Reference Board
 * CRLF - Carriage Return, Line Feed - \\r\\n - The standard window EOL
   (End-of-Line) marker.
-* crt0 - [**C Run Time 0**](https://en.wikipedia.org/wiki/Crt0)
+* crt0 - [**C Run Time 0**](http://en.wikipedia.org/wiki/Crt0)
 * crt0s - crt0 Source code
 * CRT - [**Cathode Ray Tube**](https://en.wikipedia.org/wiki/Cathode-ray_tube)
 * CSE - Intel: Converged Security Engine
@@ -207,7 +206,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * CSME - Intel: Converged Security and Management Engine
 * CTLE - Intel: Continuous Time Linear Equalization
 * CVE - [**Common Vulnerabilities and Exposures**](https://en.wikipedia.org/wiki/Common_Vulnerabilities_and_Exposures)
-* CXMT - ChangXin Memory Technologies
 * CZN - AMD: [**Cezanne**](https://en.wikichip.org/wiki/amd/cores/cezanne) - CPU Family 19h, Model 50h
 
 
@@ -226,9 +224,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   still has power.
 * D3 Cold - ACPI Device power state: Power is completely removed from
   the device.
-* DASH - [**Desktop and mobile Architecture for System Hardware**](https://en.wikipedia.org/wiki/Desktop_and_mobile_Architecture_for_System_Hardware)
+* DASH - [**Desktop and mobile Architecture for System Hardware**](Desktop_and_mobile_Architecture_for_System_Hardware)
 * DB - DaughterBoard
-* DbC - USB: Debug Capability on the USB host controller
 * DC - Electricity: Direct Current
 * DCP - Digital Content Protection
 * DCR - **Decode Control Register** This is a way of identifying the
@@ -237,14 +234,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DDI -  Intel: Digital Display Interface
 * DDR - [**Double Data Rate**](https://en.wikipedia.org/wiki/Double_data_rate)
 * DEVAPC - Mediatek: Device Access Permission Control
-* DF - Data Fabric
 * DFP - USB: Downstream Facing port
 * DHCP - [**Dynamic Host Configuration Protocol**](https://en.wikipedia.org/wiki/Dynamic_Host_Configuration_Protocol)
 * DID - Device Identifier
 * DIMM - [**Dual Inline Memory Module**](https://en.wikipedia.org/wiki/DIMM)
 * DIP - [**Dual inline package**](https://en.wikipedia.org/wiki/Dual_in-line_package)
 * DMA - [**Direct Memory
-  Access**](https://en.wikipedia.org/wiki/Direct_memory_access) Allows
+  Access**](http://en.wikipedia.org/wiki/Direct_memory_access) Allows
   certain hardware subsystems within a computer to access system memory
   for reading and/or writing independently of the main CPU. Examples of
   systems that use DMA: Hard Disk Controller, Disk Drive Controller,
@@ -252,7 +248,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   computers, as it allows devices of different speeds to communicate
   without subjecting the CPU to a massive interrupt load.
 * DMI - Direct Media Interface is a link/bus between CPU and PCH.
-* DMI - [**Desktop Management Interface**](https://en.wikipedia.org/wiki/Desktop_Management_Interface)
+* DMI - [**Desktop Management Interface**](Desktop_Management_Interface)
 * DMIC - Digital Microphone
 * DMTF - [**Distributed Management Task Force**](https://en.wikipedia.org/wiki/Distributed_Management_Task_Force)
 * DMZ - Demilitarized Zone
@@ -261,7 +257,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * DOS - Disk Operating System
 * DP - DisplayPort
 * DPM - Mediatek: DRAM Power Manager
-* DPTC - AMD: Dynamic Power and Thermal Control
 * DPTF - Intel: Dynamic Power and Thermal Framework
 * DRAM - Memory: [**Dynamic Random Access Memory**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory)
 * DRTM - Dynamic Root of Trust for Measurement
@@ -287,8 +282,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * dTPM - Discrete TPM (Trusted Platform Module) - A separate TPM chip,
   vs Integrated TPMs or fTPMs (Firmware TPMs).
 * DTS - U-Boot: Device Tree Source
-* DUT - Device Under Test
-* DvC - USB: Debug Capability on the USB Device (Device Capability)
 * DVFS - ARM: Dynamic Voltage and Frequency Scaling
 * DVI - [**Digital Video Interface**](https://en.wikipedia.org/wiki/Digital_Visual_Interface)
 * DVT - Production Timeline: Design Validation Test
@@ -301,13 +294,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 ## E
 
-* EAPD - Intel: [**External Amplifier Power Down**](https://web.archive.org/web/20210203194800/https://www.eeweb.com/hd-audio-eapd/)
 * EBDA - Extended BIOS Data Area
-* EBG - Intel: Emmitsburg PCH
 * ECC - [**Error Correction Code**](https://en.wikipedia.org/wiki/Error_correction_code) - Typically used to refer to a type of
   memory that can detect and correct memory errors.
 * EDID - [**Extended Display Identification Data**](https://en.wikipedia.org/wiki/Extended_Display_Identification_Data)
-* EDK2 - EFI Development Kit 2
+* edk2 - EFI Development Kit 2
 * EDO - Memory: [**Extended Data
   Out**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Extended_data_out_DRAM)
   - A DRAM standard introduced in 1994 that improved upon, but was
@@ -317,7 +308,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * EEPROM - [**Electrically Erasable Programmable ROM**](https://en.wikipedia.org/wiki/EEPROM) (common mistake:
   electrical erasable programmable ROM).
 * EFI - [**Extensible Firmware Interface**](https://en.wikipedia.org/wiki/Unified_Extensible_Firmware_Interface)
-* EFS - AMD: Embedded Firmware Structure: The data structure that AMD processors look for first in the boot ROM to start the boot process.
 * EHCI - [**Enhanced Host Controller Interface**](https://en.wikipedia.org/wiki/Host_controller_interface_%28USB%2C_Firewire%29#EHCI) - USB 2.0
 * EHL - Intel: [**Elkhart Lake**](https://en.wikichip.org/wiki/intel/cores/elkhart_lake)
 * EIDE - Enhanced Integrated Drive Electronics
@@ -329,7 +319,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * EOL - End of Life
 * EPP - Intel: Energy-Performance Preference
 * EPROM - Erasable Programmable Read-Only Memory
-* EROFS - Linux: [**Enhanced Read-Only File System**](https://en.wikipedia.org/wiki/EROFS)
 * ESD - Electrostatic discharge
 * eSPI - Enhanced System Peripheral Interface
 * EVT - Production Timeline: Engineering Validation Test
@@ -340,7 +329,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FADT - ACPI Table: Fixed ACPI Description Table
 * FAE - Field Application Engineer
 * FAT - File Allocation Table
-* FBVDDQ - Nvidia Power: Framebuffer Voltage
 * FCH - AMD: Firmware Control Hub
 * FCS - Production Timeline: First Customer Shipment
 * FDD - Floppy Disk Drive
@@ -358,7 +346,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPDT - ACPI: Firmware Performance Data Table
 * FPGA - [**Field-Programmable Gate Array**](https://en.wikipedia.org/wiki/Field-programmable_gate_array)
 * Framebuffer - The
-  [**framebuffer**](https://en.wikipedia.org/wiki/Framebuffer) is a part
+  [**framebuffer**](http://en.wikipedia.org/wiki/Framebuffer) is a part
   of RAM in a computer which is allocated to hold the graphics
   information for one frame or picture. This information typically
   consists of color values for every pixel on the screen. A framebuffer
@@ -370,15 +358,11 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * FPM - Memory: [**Fast Page Mode**](https://en.wikipedia.org/wiki/Dynamic_random-access_memory#Page_mode_DRAM) - A DRAM standard introduced in 1990.
 * FPU - [**Floating-Point Unit**](https://en.wikipedia.org/wiki/Floating-point_unit)
 * FSB - [**Front-Side Bus**](https://en.wikipedia.org/wiki/Front-side_bus)
-* FSM - Finite State Machine
 * FSP - Intel: Firmware Support Package
-* FSR - Intel: Firmware Status Register
 * FTP - Network Protocol: [**File Transfer Protocol**](https://en.wikipedia.org/wiki/File_Transfer_Protocol)
 * fTPM - Firmware TPM (Trusted Platform Module).  This is a TPM that is
   based in firmware instead of actual hardware.  It typically runs in
   some sort of TEE (Trusted Execution Environment).
-* FWCM Intel: firmware Connection Manager
-* FWID - Firmware Identifier
 
 
 ## G
@@ -399,10 +383,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GMA - Intel: [**Graphics Media
   Accelerator**](https://en.wikipedia.org/wiki/Intel_GMA)
 * GNB - Graphics NorthBridge
-* GND - Power: Ground
 * GNVS - Global Non-Volatile Storage
 * GPD - PCH GPIO in Deep Sleep well (D5 power)
-* GPE - ACPI: General Purpose Event
 * GPI - GPIOs: GPIO Input
 * GPIO - [**General Purpose Input/Output**](https://en.wikipedia.org/wiki/General-purpose_Input/Output) (Pin)
 * GPMR - Intel: General Purpose Memory Range
@@ -414,30 +396,21 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * GPU - [**Graphics Processing Unit**](https://en.wikipedia.org/wiki/Graphics_processing_unit)
 * GSoC - [**Google Summer of Code**](https://en.wikipedia.org/wiki/Google_Summer_of_Code)
 * GSC - Google Security Chip - Typically Cr50/Ti50, though could also refer to the titan chips
-* GSPI - Generic SPI - These are SPI controllers available for general
-  use, not dedicated to flash, for example.
-* GTDT - ACPI: Generic Timer Description Table
-* GTT - [**Graphics Translation Table**](https://en.wikipedia.org/wiki/Graphics_address_remapping_table)
 * GUID - UEFI: [**Globally Unique IDentifier**](https://en.wikipedia.org/wiki/Universally_unique_identifier)
 
 
 ## H
 
-* HBP - Graphics: [**Horizontal Back Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank area past the end of the scanline
 * HDA - [**High Definition Audio**](https://en.wikipedia.org/wiki/Intel_High_Definition_Audio)
 * HDCP - [**High-bandwidth Digital Content Protection**](https://en.wikipedia.org/wiki/High-bandwidth_Digital_Content_Protection)
 * HDD - Hard Disk Drive
 * HDMI - [**High-Definition Multimedia Interface**](https://en.wikipedia.org/wiki/HDMI)
 * HDR - [**High Dynamic Range**](https://en.wikipedia.org/wiki/High_dynamic_range)
 * HECI - Intel: [**Host Embedded Controller Interface**](https://en.wikipedia.org/wiki/Host_Embedded_Controller_Interface) (Replaced by MEI)
-* HFP - Graphics: [**Horizontal Front Porch**](https://en.wikipedia.org/wiki/Horizontal_blanking_interval) In the Horizontal blanking interval, this is the blank before the start of the next scanline.
 * HID - [**Human Interface
   Device**](https://en.wikipedia.org/wiki/Human_interface_device)
 * HOB - UEFI: Hand-Off Block
-* HPD - Hot-Plug Detect
 * HPET - [**High Precision Event Timer**](https://en.wikipedia.org/wiki/High_Precision_Event_Timer)
-* HSP - AMD: Hardware Security Processor
-* HSPHY - USB: USB3 High-Speed PHY
 * HSTI - Hardware Security Test Interface
 * HSW - Intel: Haswell
 * Hybrid S3 - System Power State:  This is where the operating system
@@ -446,7 +419,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   resume quickly from S3 if the system stays powered, and resume from
   the disk if power is lost.
 * Hypertransport - AMD: The
-  [**Hypertransport**](https://en.wikipedia.org/wiki/Hypertransport) bus
+  [**Hypertransport**](http://en.wikipedia.org/wiki/Hypertransport) bus
   is an older (2001-2017) high-speed electrical interconnection protocol
   specification between CPU, Memory, and (occasionally) peripheral
   devices.  This was originally called the Lightning Data Transport
@@ -467,7 +440,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   - Also known as SenseWire
 * IA - Intel Architecture
 * IA-64 - Intel Itanium 64-bit architecture
-* IAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus atomic instructions, single precision floating point instructions, and compressed instructions
 * IBB – Initial Boot Block
 * IBV - Independent BIOS Vendor
 * IC - Integrated Circuit
@@ -484,8 +456,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IF - AMD: [**Infinity
   Fabric**](https://en.wikipedia.org/wiki/HyperTransport#Infinity_Fabric)
   is a superset of AMD's earlier Hypertransport interconnect.
-* IFD - Intel: Intel Flash Descriptor
-* IMAFC - RISC-V: [**RISC-V Base Integer instruction set**](https://en.wikipedia.org/wiki/RISC-V), plus integer multiply & divide, atomic instructions, single precision floating point instructions, and compressed instructions
 * IMC - AMD: Integrated micro-controller - An 8051 microcontroller built
   into some AMD FCHs (Fusion Controller Hubs) and Southbridge chips.
   This never worked well for anything beyond fan control and caused
@@ -497,7 +467,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IoC - Security: Indicator of Compromise
 * IOC - Intel: I/O Cache
 * IOE - Intel: I/O Expander
-* IOHC - AMD: I/O Hub Controller
 * IOM - Intel: I/O Manager
 * IOMMU - [**I/O Memory Management Unit**](https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit)
 * IOMUX - AMD: The I/O Mux block controls how each GPIO is configured.
@@ -520,7 +489,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * IVHD - ACPI: I/O Virtualization Hardware Definition
 * IVMD - ACPI: I/O Virtualization Memory Definition
 * IVRS - I/O Virtualization Reporting Structure
-* IWYU - Include What you Use - A tool to help with include file use
 
 
 ## J
@@ -561,7 +529,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * LAPIC - Local APIC
 * LBA - Logical Block Address
 * LCD - Liquid Crystal Display
-* LCAP - PCIe: Link Capabilities
+* LCAP - PCIe:Link Capabilities
 * LED - Light Emitting Diode
 * LF - Line Feed - The standard Unix EOL (End-of-Line) marker.
 * LGTM - Looks Good To Me
@@ -574,7 +542,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   count**](http://www.intel.com/design/chipsets/industry/lpc.htm) bus
   was a replacement for the ISA bus, created by serializing a number of
   parallel signals to get rid of those connections.
-* LPM - USB: Link Power Management
 * LPT - Line Print Terminal, Local Print Terminal, or Line Printer. -
   The Parallel Port
 * LRU - Least Recently Used - a rule used in operating systems that
@@ -591,21 +558,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 
 * M.2 - An interface specification for small peripheral cards.
 * MAC Address - Media Access Control Address
-* MAFS - (eSPI) Master Attached Flash Sharing: Flash components are
-  attached to the controller device and may be accessed by by the
-  peripheral devices through the eSPI flash access channel.
-* MBP - Intel UEFI: ME-to-BIOS Payload
 * MBR - Master Boot Record
 * MCA - [**Machine Check Architecture**](https://en.wikipedia.org/wiki/Machine_Check_Architecture)
 * MCR - Machine Check Registers
-* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MCU - Memory Control Unit
 * MCU - [**MicroController
   Unit**](https://en.wikipedia.org/wiki/Microcontroller)
-* MCUPM - Mediatek: MCUPM is a hardware module which is used for MCUSYS Power Management. MCUPM firmware (mcupm.bin) is loaded into MCUPM SRAM at system initialization.
+* MCTP - [**Management Component Transport Protocol**](https://en.wikipedia.org/wiki/Management_Component_Transport_Protocol)
 * MDFIO - Intel: Multi-Die Fabric IO
 * MDN - AMD: Mendocino
-* mDP - Mini DisplayPort connector
 * ME - Intel: Management Engine
 * MEI - Intel: ME Interface (Previously known as HECI)
 * Memory training - the process of finding the best speeds, voltages,
@@ -622,7 +583,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MKBP - Matrix Keyboard Protocol
 * MMC - [**MultiMedia
   Card**](https://en.wikipedia.org/wiki/MultiMediaCard)
-* MMIO - [**Memory Mapped I/O**](https://en.wikipedia.org/wiki/MMIO)
+* MMIO - [**Memory Mapped I/O**](http://en.wikipedia.org/wiki/MMIO)
   allows peripherals' memory or registers to be accessed directly
   through the memory bus.  When the memory bus size was very small, this
   was initially done by hiding any memory at that address, effectively
@@ -649,23 +610,21 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * MSB - Most Significant Bit
 * MSI - Message Signaled Interrupt
 * MSR - Machine-Specific Register
-* MTS or MT/s - MegaTransfers per second
+* MT/s - MegaTransfers per second
 * MTL - Intel: Meteor Lake
 * MTL - ARM: MHU Transport Layer
-* MTRR - [**Memory Type and Range Register**](https://en.wikipedia.org/wiki/MTRR)
+* MTRR - [**Memory Type and Range Register**](http://en.wikipedia.org/wiki/MTRR)
   allows to set the cache behaviour on memory access in x86. Basically,
   it tells the CPU how to cache certain ranges of memory
   (e.g. write-through, write-combining, write-back...). Memory ranges
   are specified over physical address ranges. In Linux, they are visible
   over `/proc/mtrr` and they can be modified there. For further
   information, see the [**Linux documentation**](https://www.kernel.org/doc/html/v5.19/x86/pat.html).
-* MXM - PCIe: [**Mobile PCI Express Module**](https://en.wikipedia.org/wiki/Mobile_PCI_Express_Module)
 
 
 ## N
 
 * Nack - Negative Acknowledgement
-* NB - North Bridge
 * NBCI - Nvidia: NoteBook Common Interface
 * NC - GPIOs: No Connect
 * NDA - Non-Disclosure Agreement.
@@ -685,7 +644,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * NVME - Non-Volatile Memory Express - An SSD interface that allows
   access to the flash memory through a PCIe bus.
 * NVPCF - Nvidia Platform and Control Framework
-* NVVDD - Nvidia Power: Core voltage
 * NX - No Execute
 
 
@@ -731,23 +689,21 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PCD - UEFI: Platform Configuration Database
 * PCH - Intel: [**Platform Controller Hub**](https://en.wikipedia.org/wiki/Platform_Controller_Hub)
 * PCI - [**Peripheral Control
-  Interconnect**](https://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
+  Interconnect**](http://en.wikipedia.org/wiki/Peripheral_Component_Interconnect)
   - Replaced generally by PCIe (PCI Express)
 * PCI Configuration Space - The [**PCI Config
-  space**](https://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
+  space**](http://en.wikipedia.org/wiki/PCI_Configuration_Space) is an
   [address space](https://en.wikipedia.org/wiki/Address_space) for all
   PCI devices.  Originally, this address space was accessed through an
   index/data pair by writing the address that you wanted to read/write
   into the I/O address 0xCF8, then reading or writing I/O Address 0xCFC.
   This has been updated to an MMIO method which increases each PCI
   function's configuration space from 256 bytes to 4K.
-* PCIe - [**PCI Express**](https://en.wikipedia.org/wiki/Pci_express)
+* PCIe - [**PCI Express**](http://en.wikipedia.org/wiki/Pci_express)
 * PCMCIA: Personal Computer Memory Card International Association
 * PCO - AMD: [**Picasso**](https://en.wikichip.org/wiki/amd/cores/picasso)
 * PCR: TPM: Platform Configuration Register
-* PD - GPIOs: Pull-Down - Drives the pin to ground through a resistor.
-  The resistor allows the pin to be set to the reference voltage as
-  needed.
+* PD - GPIOs: Pull-Down - Setting the pin high drives it to the reference voltage.  Setting it low drives it to ground through a resistor.
 * PD - Power Delivery - This is a specification for communicating power
   needs and availability between two devices, typically over USB type C.
 * PEG - PCIe Graphics - A (typically) x16 PCIe slot connected to the CPU
@@ -755,9 +711,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PEI - UEFI: Pre-EFI Initialization
 * PEIM - UEFI: PEI Module
 * PEP - Intel: Power Engine Plug-in
-* PEXVDD - Nvidia Power: PCIExpress Voltage
-* PHX - AMD: Phoenix SoC
-* PHY - [**PHYsical layer**](https://en.wikipedia.org/wiki/PHY) - The
+* PHY - [**PHYsical layer**](http://en.wikipedia.org/wiki/PHY) - The
   hardware that implements the send/receive functionality of a
   communication protocol.
 * PI - Platform Initialization
@@ -776,7 +730,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * PIT - Generally refers to the 8253/8254 [**Programmable Interval
   Timer**](https://en.wikipedia.org/wiki/Programmable_interval_timer).
 * PLCC - [**Plastic leaded chip
-  carrier**](https://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
+  carrier**](http://en.wikipedia.org/wiki/Plastic_leaded_chip_carrier)
 * PLL - [**Phase-Locked
   Loop**](https://en.wikipedia.org/wiki/Phase-locked_loop)
 * PM - Platform Management
@@ -798,21 +752,15 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * POTS - [**Plain Old Telephone
   Service**](https://en.wikipedia.org/wiki/Plain_old_telephone_service)
 * PPI - UEFI: PEIM-to-PEIM Interface
-* PPR - Processor Programming Reference
+* PPR: Processor Programming Reference
 * PPT - AMD: Package Power Tracking
-* PROM - Programmable Read Only Memory
+* PROM: Programmable Read Only Memory
 * Proto - Production Timeline: The first initial production to test key
   concepts.
 * PSE - Page Size Extention
-* PSF - Intel: Primary Sideband Fabric
 * PSP - AMD: Platform Security Processor
 * PSPP - AMD: PCIE Speed Power Policy
-* PSR - Intel: Platform Service Record
-* PSR - Graphics: Panel Self-Refresh - This is a power-savings feature specified in eDP
-* PTT - Intel: Platform Trust Technology - Intel's firmware based TPM.
-* PU - GPIOs: Pull-Up - Drives the pin to reference voltage through a
-  resistor. The resistor allows the signal to still be set to ground
-  when needed.
+* PU - GPIOs: Pull-Up - Setting the pin low drives it to ground.  Setting it high drives it to the reference voltage through a resistor.
 * PVT - Production Timeline: (Production Validation Test
 * PWM - Pulse Width Modulation
 * PXE - Pre-boot Execution Environment
@@ -835,7 +783,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   a set of 3 or 4 GPIOs to allow 8 to 16 different memory chips to be
   used.
 * RAPL - Running Average Power Limit
-* RCB - PCIe: Read Completion Boundary - Sets the address alignment on which a read request may be serviced with multiple completions
 * RCS - [**Revision control
   system**](https://en.wikipedia.org/wiki/Revision_Control_System)
 * Real mode - The original 20-bit addressing mode of the 8086 & 8088
@@ -843,7 +790,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   Segment:Offset index pair.  In 2022, this is still the mode that
   x86-64 processors are in at the reset vector!
 * RDMA - [**Remote Direct Memory
-  Access**](https://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
+  Access**](http://en.wikipedia.org/wiki/Remote_Direct_Memory_Access) is
   a concept whereby two or more computers communicate via DMA directly
   from main memory of one system to the main memory of another.
 * RFC - Request for Comment
@@ -856,11 +803,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * ROM - Read Only Memory
 * RoT - Root of Trust
 * RPL - Intel: [**Raptor Lake**](https://en.wikipedia.org/wiki/Raptor_Lake)
-* RPP - Intel: Raptor Point PCH
 * RRG - AMD (ATI): Register Reference Guide
 * RSDP - Root System Description Pointer
 * RTC - Real Time Clock
-* RTD3 - Power State: Runtime D3
 * RTFM - Read the Fucking Manual
 * RTOS - Real-Time Operating System
 * RVP - Intel: Reference Validation Platform
@@ -896,11 +841,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   contents of memory.  Any critical processor state is restored.
 * S5 - ACPI System Power State: System is “completely powered off”, but
   still has power going to the board.
-* SAFS - (eSPI) Slave Attached Flash Sharing: Flash is attached to the
-  peripheral device.  Only valid for server platforms.
-* SAGV - Intel: System Agent Geyserville. The original internal name
-  for the feature eventually released as Speedstep which controls the
-  processor voltage and frequencies.
 * SAR - The [**Specific Absorption
   Rate**](https://en.wikipedia.org/wiki/Specific_absorption_rate) is the
   measurement for the amount of Radio Frequency (RF) energy absorbed by
@@ -924,7 +864,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   SAS (Serial Attached SCSI).  The initial version is now often referred
   to as Parallel SCSI.
 * SD - [**Secure Digital**](https://en.wikipedia.org/wiki/SD_card) card
-* SDHCI - SD Host Controller Interface
 * SDRAM - Synchronous DRAM
 * SDLE: AMD: Stardust Dynamic Load Emulator
 * SEEP - Serial EEPROM (Electrically Erasable Programmable Read-Only
@@ -948,7 +887,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SMBus -  [**System Management
   Bus**](https://en.wikipedia.org/wiki/System_Management_Bus)
   * [http://www.smbus.org/](http://www.smbus.org/)
-* SME - AMD: Secure Memory Encryption
 * SMI - System management interrupt
 * SMM - [**System management
   mode**](https://en.wikipedia.org/wiki/System_Management_Mode)
@@ -962,7 +900,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SO-DIMM: Small Outline Dual In-Line Memory Module
 * SoC - System on a Chip
 * SOIC - [**Small-Outline Integrated
-  Circuit**](https://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
+  Circuit**](http://en.wikipedia.org/wiki/Small-outline_integrated_circuit)
 * SPD - [**Serial Presence
   Detect**](https://en.wikipedia.org/wiki/Serial_presence_detect)
 * SPI - [**Serial Peripheral
@@ -970,7 +908,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SPL - AMD: Security Patch Level
 * SPM - Mediatek: System Power Manager
 * SPMI - MIPI: System Power Management Interface
-* SPR - Sapphire Rapids
 * SRAM - Static Random Access Memory
 * SSD - Solid State Drive
 * SSDT - Secondary System Descriptor Table - ACPI table
@@ -987,7 +924,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * SSI-TEB - Physical board format: [**SSI Thin Electronics
   Bay**](https://en.wikipedia.org/wiki/SSI_CEB)
 * SSP - [**Speech Signal Processor**](https://en.wikipedia.org/wiki/Speech_processing)
-* SSPHY - USB: USB3 Super-Speed PHY
 * STAPM - AMD: Skin Temperature Aware Power Management
 * STB - AMD: Smart Trace Buffer
 * SuperIO - The [**Super I/O**](https://en.wikipedia.org/wiki/Super_I/O)
@@ -995,16 +931,13 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   peripherals.  Most common are: A PS/2 Keyboard and mouse port, LPT
   Ports, UARTS, Watchdog Timers, Floppy drive Controllers, GPIOs, or any
   of a number of various other devices.
-* SVC - ARM: Supervisor Call
 * SVI2/3 - Serial VID (Voltage Identification) Interface 2.0 / 3.0
-* SWCM - Intel: Software Connection Manager
 
 
 ## T
 
 * TBT - Thunderbolt
 * TBT - Intel: Turbo Boost Technology
-* tBUF - I2C: The bus free time between a STOP and START condition
 * TCC - Intel: Thermal Control Circuit
 * TCP - Transmission Control Protocol
 * TCPC - Type C Port Controller
@@ -1028,8 +961,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * TOLUM - Top of Low Usable Memory
 * ToM - Top of Memory
 * TPM - Trusted Platform Module
-* TS - TimeStamp
-* TSN - Time-Sensitive Networking
+* TS - TimeStamp -
 * TSC - [**Time Stamp
   Counter**](https://en.wikipedia.org/wiki/Time_Stamp_Counter)
 * TSEG - TOM (Top of Memory) Segment
@@ -1046,9 +978,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * uCode - [**Microcode**](https://en.wikipedia.org/wiki/Microcode)
 * UDK - UEFI: UEFI Development Kit
 * UDP - User Datagram Protocol
-* UDMA - ATA: [**Ultra DMA**](https://en.wikipedia.org/wiki/UDMA) - The fastest transfer mode for ATA Hard Drives
 * UEFI - Unified Extensible Firmware Interface
-* UFC - User Facing Camera
 * UFP - USB: Upstream Facing Port
 * UFS - Universal Flash storage
 * UHCI - USB: [**Universal Host Controller
@@ -1064,7 +994,6 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * UPS - Uninterruptible Power Supply
 * USART - Universal Synchronous/Asynchronous Receiver/Transmitter
 * USB - Universal Serial Bus
-* USF - Intel: Universal Scalable Firmware
 
 
 ## V
@@ -1072,8 +1001,7 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VBIOS - Video BIOS
 * VBNV - Vboot Non-Volatile storage
 * VBT - [**Video BIOS
-  Table**](https://www.kernel.org/doc/html/latest/gpu/i915.html#video-bios-table-vbt)
-* VDDQ Memory/Power: The supply voltage to the output buffers of a memory chip.
+  Table**](https://01.org/linuxgraphics/gfx-docs/drm/ch04s02.html#id-1.4.3.4.16)
 * VESA - Video Electronics Standards Association
 * VGA: Video Graphics Array
 * VID: Vendor Identifier
@@ -1081,17 +1009,12 @@ Spec](https://uefi.org/specifications) for details, or run the tool
 * VLB - VESA Local Bus
 * VOIP - Voice over IP
 * Voodoo mode - a silly name for Big Real mode.
-* VMX - Intel: CPU flag for Hardware Virtualization
 * VPD - Vital Product Data
 * VPN - Virtual Private Network
-* VPU - Intel: Versatile Processor Unit
 * VR - Voltage Regulator
 * VRAM - Video Random Access Memory
-* VREF Memory/Power: Reference voltage for the input lines of a chip that determines the voltage level at which the threshold between a logical 1 and a logical 0 occurs. Usually 1/2 VDDQ.
 * VRM - Voltage Regulator Module
 * VT-d - Intel: Virtualization Technology for Directed I/O
-* VTT Memory/Power: Tracking Termination Voltage
-* vUART - Virtual UART
 
 
 ## W
@@ -1105,11 +1028,9 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   devices that open 360 degrees, or on the outside of the cover.  For
   tablets, it's on the the side away from the screen.
 * WDT - [**WatchDog Timer**](https://en.wikipedia.org/wiki/Watchdog_timer)
-* WFC - World Facing Camera
 * WLAN - Wireless LAN (Local Area Network)
 * WWAN - Telecommunication: Wireless WAN (Wide Area Network)
 * WP - Cache policy: [**Write-Protected**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
-* WPT - Intel: Wildcat Point - PCH for Broadwell
 * WO - Write-only
 * WOL - [**Wake-on-LAN**](https://en.wikipedia.org/wiki/Wake-on-LAN)
 * WT - Cache Policy: [**Write Through**](https://en.wikipedia.org/wiki/Cache_%28computing%29)
@@ -1130,9 +1051,8 @@ Spec](https://uefi.org/specifications) for details, or run the tool
   supporting 1.x, 2.0, and 3.x devices.
 
 
-## Y
 
-* YCC - Color Space: [**YCbCr**](https://en.wikipedia.org/wiki/YCbCr) - A family of color spaces used in video
+## Y
 
 
 ## Z

Documentation/community/code_of_conduct.md

@@ -95,17 +95,6 @@ If you feel you have been falsely or unfairly accused of violating this
 Code of Conduct, you should notify the arbitration team with a concise
 description of your grievance.
 
-## Legal action
-
-Threatening or starting legal action against the project, sibling
-projects hosted on coreboot.org infrastructure, project or infrastructure
-maintainers leads to an immediate ban from coreboot.org and related
-systems.
-
-The ban can be reconsidered, but it's the default action because the
-people who pour lots of time and money into the projects aren't interested
-in seeing their resources used against them.
-
 ## Scope
 
 We expect all community participants (contributors, paid or otherwise;

Documentation/community/forums.md

@@ -14,7 +14,7 @@ read its
 ## Real time chat
 
 We also have a real time chat room on [IRC](ircs://irc.libera.chat/#coreboot),
-also bridged to [Matrix](https://matrix.to/#/#coreboot:matrix.org) and a
+also bridged to [Matrix](https://matrix.to/#/#coreboot:libera.chat) and a
 [Discord](https://discord.gg/JqT8NM5Zbg) presence. You can also find us on
 [OSF Slack](https://osfw.slack.com/), which has channels on many open source
 firmware related topics. Slack requires that people come from specific domains

Documentation/conf.py

@@ -55,7 +55,7 @@ else:
 #
 # This is also used if you do content translation via gettext catalogs.
 # Usually you set "language" from the command line for these cases.
-language = 'en'
+language = None
 
 # List of patterns, relative to source directory, that match files and
 # directories to ignore when looking for source files.
@@ -87,9 +87,11 @@ html_theme = 'sphinx_rtd_theme'
 # so a file named "default.css" will overwrite the builtin "default.css".
 html_static_path = ['_static']
 
-html_css_files = [
-    'theme_overrides.css',  # override wide tables in RTD theme
-]
+html_context = {
+      'css_files': [
+        '_static/theme_overrides.css',  # override wide tables in RTD theme
+      ],
+}
 
 # Output file base name for HTML help builder.
 htmlhelp_basename = 'corebootdoc'

Documentation/contributing/gerrit_guidelines.md

@@ -41,7 +41,7 @@ project you're submitting the changes to. If you’re submitting code that
 you wrote that might be owned by your employer, make sure that your
 employer is aware and you are authorized to submit the code. For
 clarification, see the Developer's Certificate of Origin in the coreboot
-[Signed-off-by policy](#sign-off-procedure).
+[Signed-off-by policy](https://www.coreboot.org/Development_Guidelines#Sign-off_Procedure).
 
 * In general, patches should remain open for review for at least 24 hours
 since the last significant modification to the change. The purpose is to
@@ -127,54 +127,6 @@ those platforms. While it would be nice to update any other platforms, you
 must at least provide a path that will allow other platforms to continue
 working.
 
-Sign-off Procedure
-------------------
-The coreboot project employs a sign-off procedure similar to what is
-used by the Linux kernel. Each gerrit commit requires a sign-off line
-saying that the contributed code abides by the Developer's certificate
-of origin, below.
-```text
-Signed-off-by: Random J Developer <random@developer.example.org>
-```
-
-Using '-s' with 'git commit' will automatically add a Signed-off-by line
-to your commit message.  Patches without a Signed-off-by should not be
-pushed to gerrit, and will be rejected by coreboot's CI system.
-
-You must use a known identity in the Signed-off-by line. Anonymous
-contributions cannot be committed! This can be anything sufficient to
-identify and contact the source of a contribution, such as your name or
-an established alias/nickname. Refer to [this LKML thread] and the
-[SCO-Linux disputes] for the rationale behind the DCO.
-
-Developer's Certificate of Origin 1.1
-
-> By making a contribution to this project, I certify that:
->
-> (a) The contribution was created in whole or in part by me and I have
-> the right to submit it under the open source license indicated in the
-> file; or
->
-> (b) The contribution is based upon previous work that, to the best of
-> my knowledge, is covered under an appropriate open source license and
-> I have the right under that license to submit that work with
-> modifications, whether created in whole or in part by me, under the
-> same open source license (unless I am permitted to submit under a
-> different license), as indicated in the file; or
->
-> (c) The contribution was provided directly to me by some other person
-> who certified (a), (b) or (c) and I have not modified it; and
->
-> (d) In the case of each of (a), (b), or (c), I understand and agree
-> that this project and the contribution are public and that a record of
-> the contribution (including all personal information I submit with it,
-> including my sign-off) is maintained indefinitely and may be
-> redistributed consistent with this project or the open source license
-> indicated in the file.
-
-Note: The [Developer's Certificate of Origin 1.1] is licensed under the
-terms of the [Creative Commons Attribution-ShareAlike 2.5 License].
-
 
 Recommendations for gerrit activity
 -----------------------------------
@@ -221,10 +173,7 @@ This helps verify that the patch train won’t tie up the jenkins builders
 for no reason if there are failing patches in the train. For running
 parallel builds, you can specify the number of cores to use by setting the
 the CPUS environment variable. Example:
-
-```Bash
-make what-jenkins-does CPUS=8
-```
+        make what-jenkins-does CPUS=8
 
 * Use a topic when pushing a train of patches. This groups the commits
 together so people can easily see the connection at the top level of
@@ -232,10 +181,7 @@ gerrit. Topics can be set for individual patches in gerrit by going into
 the patch and clicking on the icon next to the topic line. Topics can also
 be set when you push the patches into gerrit. For example, to push a set of
 commits with the i915-kernel-x60 set, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%topic=i915-kernel-x60
-```
+        git push origin HEAD:refs/for/master%topic=i915-kernel-x60
 
 * If one of your patches isn't ready to be merged, make sure it's obvious
 that you don't feel it's ready for merge yet. The preferred way to show
@@ -245,10 +191,7 @@ Examples of this are "WIP: title" or "[NEEDS_TEST]: title".  Another way to
 mark the patch as not ready would be to give it a -1 or -2 review, but
 isn't as obvious as the commit message. These patches can also be pushed with
 the wip flag:
-
-```Bash
-git push origin HEAD:refs/for/master%wip
-```
+	git push origin HEAD:refs/for/master%wip
 
 * When pushing patches that are not for submission, these should be marked
 as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as
@@ -257,16 +200,10 @@ sorts of patches are frequently posted as ideas or RFCs for the community to
 look at. Note that private changes can still be fetched from Gerrit by anybody
 who knows their commit ID, so don't use this for sensitive changes. To push
 a private change, use the command:
-
-```Bash
-git push origin HEAD:refs/for/master%private
-```
+        git push origin HEAD:refs/for/master%private
 
 * Multiple push options can be combined:
-
-```Bash
-git push origin HEAD:refs/for/master%private,wip,topic=experiment
-```
+        git push origin HEAD:refs/for/master%private,wip,topic=experiment
 
 * Respond to anyone who has taken the time to review your patches, even if
 it's just to say that you disagree. While it may seem annoying to address a
@@ -340,15 +277,13 @@ git/gerrit tags by prepending the lines with 'Original-'.  Marking
 the original text this way makes it much easier to tell what changes
 happened in which repository. This applies to these lines, not the actual
 commit message itself:
-
-	* Commit-Id:
-	* Change-Id:
-	* Signed-off-by:
-	* Reviewed-on:
-	* Tested-by:
-	* Reviewed-by:
-
-The script `util/gitconfig/rebase.sh` can be used to help automate this.
+        Commit-Id:
+        Change-Id:
+        Signed-off-by:
+        Reviewed-on:
+        Tested-by:
+        Reviewed-by:
+The script 'util/gitconfig/rebase.sh' can be used to help automate this.
 Other tags such as 'Commit-Queue' can simply be removed.
 
 * Check if there's documentation that needs to be updated to remain current
@@ -434,7 +369,3 @@ Requests for clarification and suggestions for updates to these guidelines
 should be sent to the coreboot mailing list at <coreboot@coreboot.org>.
 
 [ready changes]: https://review.coreboot.org/q/age:1d+project:coreboot+status:open+is:mergeable+label:All-Comments-Resolved%253Dok+label:Code-Review%253D2+-label:Code-Review%253C0+label:Verified%253D1+-label:Verified-1
-[Developer's Certificate of Origin 1.1]: https://developercertificate.org/
-[Creative Commons Attribution-ShareAlike 2.5 License]: https://creativecommons.org/licenses/by-sa/2.5/
-[this LKML thread]: https://lkml.org/lkml/2004/5/23/10
-[SCO-Linux disputes]: https://en.wikipedia.org/wiki/SCO%E2%80%93Linux_disputes

Documentation/contributing/gsoc.md

@@ -1,16 +1,5 @@
 # Google Summer of Code
 
-## Organization admins
-
-The *organization admins* are managing the GSoC program for the coreboot
-organization.
-
-The organization admins are:
-
-  * Felix Singer (primary)
-  * Martin Roth
-  * David Hendricks
-
 
 ## Contacts
 
@@ -19,6 +8,9 @@ please have a look at our [community forums] and reach out to us. Working closel
 with the community is highly encouraged, as we've seen that our most successful
 contributors are generally very involved.
 
+Felix Singer, David Hendricks and Martin Roth are the coreboot GSoC admins for
+2022. Please feel free to reach out to them directly if you have any questions.
+
 
 ## Why work on coreboot for GSoC?
 
@@ -59,8 +51,6 @@ contributors are generally very involved.
 
   * [Glossary][GSoC Glossary]
 
-  * [Organization Admin Tips][GSoC Organization Admin Tips]
-
 
 ## Contributor requirements & commitments
 
@@ -101,7 +91,7 @@ amount of spare time. If this is not the case, then you should not apply.
       process and common issues.
 
     * Get signed up for Gerrit and push at least one patch to Gerrit for review.
-      Check the [small project list][Project ideas] or ask for simple tasks on
+      Check the [easy project list][Project ideas] or ask for simple tasks on
       the [mailing list] or on our other [community forums] if you need ideas.
 
 
@@ -283,4 +273,3 @@ questions.
 [GSoC FAQ]: https://developers.google.com/open-source/gsoc/faq
 [GSoC Rules]: https://summerofcode.withgoogle.com/rules
 [GSoC Glossary]: https://developers.google.com/open-source/gsoc/resources/glossary
-[GSoC Organization Admin Tips]: https://developers.google.com/open-source/gsoc/help/oa-tips

Documentation/contributing/project_ideas.md

@@ -20,12 +20,12 @@ doubt if you can bring yourself up to speed in a required time frame
 with the projects. We can then try together to figure out if you're a
 good match for a project, even when requirements might not all be met.
 
-## Small projects
+## Easy projects
 
 This is a collection of tasks which don't require deep knowledge on
 coreboot itself. If you are a beginner and want to get familiar with the
 the project and the code base, or if you just want to get your hands
-dirty with some small tasks, then these are for you.
+dirty with some easy tasks, then these are for you.
 
   * Resolve static analysis issues reported by [scan-build] and
     [Coverity scan]. More details on the page for
@@ -36,7 +36,7 @@ dirty with some small tasks, then these are for you.
 [scan-build]: https://coreboot.org/scan-build/
 [Coverity scan]: https://scan.coverity.com/projects/coreboot
 [Coverity scan integration]: ../infrastructure/coverity.md
-[Linter issues]: https://qa.coreboot.org/job/coreboot-untested-files/lastSuccessfulBuild/artifact/lint.txt
+[Linter issues]: https://qa.coreboot.org/job/untested-coreboot-files/lastSuccessfulBuild/artifact/lint.txt
 
 ## Provide toolchain binaries
 Our crossgcc subproject provides a uniform compiler environment for
@@ -63,6 +63,7 @@ non-Linux builds or Docker for different Linux distributions.
 * hardware requirements: Nothing special
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Support Power9/Power8 in coreboot
 There are some basic PPC64 stubs in coreboot, and there's open hardware
@@ -87,7 +88,7 @@ across architectures.
 While we have a rather big set of payloads for x86 based platforms, all other
 architectures are rather limited. Improve the situation by porting a payload
 to one of the platforms, for example GRUB2, U-Boot (the UI part), edk2,
-FILO, or Linux-as-Payload.
+yabits, FILO, or Linux-as-Payload.
 
 Since this is a bit of a catch-all idea, an application to GSoC should pick a
 combination of payload and architecture to support.
@@ -129,6 +130,7 @@ their bug reports.
   going on from the resulting logs.
 
 ### Mentors
+* Patrick Georgi <patrick@georgi.software>
 
 ## Extend Ghidra to support analysis of firmware images
 [Ghidra](https://ghidra-sre.org) is a recently released cross-platform

Documentation/distributions.md

@@ -71,8 +71,6 @@ focusing on clean and simple code, long-term maintenance, transparent
 validation, privacy-respecting implementation, liberty for the owners, and
 trustworthiness for all.
 
-Contributions are welcome,
-[this document](https://docs.dasharo.com/ways-you-can-help-us/).
 
 ### MrChromebox
 

Documentation/external_docs.md

@@ -24,33 +24,11 @@ Please add any helpful or informational links and sections as you see fit.
 
 * [OS Dev](https://wiki.osdev.org/Categorized_Main_Page)
 * [Interface BUS](http://www.interfacebus.com/)
+* Open course material for a variety of topics such as assembly, firmware,
+  security, debugging, and more.
+  * [Open Security Training](https://opensecuritytraining.info/Training.html),
+  * [Open Security Training 2](https://p.ost2.fyi/)
 
-## OpenSecurityTraining2
-
-OpenSecurityTraining2 is dedicated to sharing training material for any topic
-related to computer security, including coreboot.
-
-There are various ways to learn firmware, some are more efficient than others,
-depending on the people. Before going straight to practice and experimenting
-with hardware, it can be beneficial to learn the basics of computing. OST2
-focuses on conveying computer architecture and security information in the form
-of structured instructor-led classes, available to everyone for free.
-
-All material is licensed [CC BY-SA 4.0](http://creativecommons.org/licenses/by-sa/4.0/),
-allowing anyone to use the material however they see fit, so long as they share
-modified works back to the community.
-
-Below is a list of currently available courses that can help understand the
-inner workings of coreboot and other firmware-related topics:
-
-* [coreboot design principles and boot process](https://ost2.fyi/Arch4031)
-* [x86-64 Assembly](https://ost2.fyi/Arch1001)
-* [x86-64 OS Internals](https://ost2.fyi/Arch2001)
-* [x86-64 Intel Firmware Attack & Defense](https://ost2.fyi/Arch4001)
-
-There are [additional security courses](https://p.ost2.fyi/courses) at the site
-as well (such as
-[how to avoid writing exploitable code in C/C++](https://ost2.fyi/Vulns1001).)
 
 ## Firmware Specifications & Information
 

Documentation/getting_started/build_system.md

@@ -62,23 +62,6 @@ supported options are:
 
 `position` and `align` are mutually exclusive.
 
-### Adding Makefile fragments
-
-You can use the `add_intermediate` helper to add new post-processing steps for
-the final `coreboot.rom` image. For example you can add new files to CBFS by
-adding something like this to `site-local/Makefile.inc`
-
-```
-$(call add_intermediate, add_mrc_data)
-	$(CBFSTOOL) $< write -r RW_MRC_CACHE -f site-local/my-mrc-recording.bin
-```
-
-Note that the second line must start with a tab, not spaces.
-
-```eval_rst
-See also :doc:`../tutorial/managing_local_additions`.
-```
-
 #### FMAP region support
 With the addition of FMAP flash partitioning support to coreboot, there was a
 need to extend the specification of files to provide more precise control

Documentation/getting_started/devicetree.md

@@ -79,7 +79,7 @@ with no properties as a direct child of the SoC.
 ## Device drivers
 
 Platform independent device drivers are hooked up via entries in a devicetree.
-See [Driver Devicetree Entries](../drivers/dt_entries.md) for more info.
+See [Driver Devicetree Entries](drivers/dt_entries.md) for more info.
 
 ## Notes
 

Documentation/index.md

@@ -1,8 +1,9 @@
 # Welcome to the coreboot documentation
 
 This is the developer documentation for [coreboot](https://coreboot.org).
-It is built from Markdown files in the [Documentation] directory in the
-source code.
+It is built from Markdown files in the
+[Documentation](https://review.coreboot.org/cgit/coreboot.git/tree/Documentation)
+directory in the source code.
 
 ## Spelling of coreboot
 
@@ -142,7 +143,7 @@ say hello!
 ## Getting the source code
 
 coreboot is primarily developed in the
-[git](https://review.coreboot.org/plugins/gitiles/coreboot) version control
+[git](https://review.coreboot.org/cgit/coreboot.git) version control
 system, using [Gerrit](https://review.coreboot.org) to manage
 contributions and code review.
 
@@ -192,12 +193,9 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [Software Bill of Materials](sbom/sbom.md)
 * [Project infrastructure & services](infrastructure/index.md)
 * [Boards supported in each release directory](releases/boards_supported_on_branches.md)
 * [Release notes](releases/index.md)
 * [Acronyms & Definitions](acronyms.md)
 * [External Resources](external_docs.md)
 * [Documentation License](documentation_license.md)
-
-[Documentation]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/Documentation/

Documentation/mainboard/asrock/h77pro4-m.md

@@ -45,9 +45,7 @@ Tests were done with SeaBIOS 1.14.0 and slackware64-live from 2019-07-12
 - Rear eSATA connector (multiplexed with one ASM1061 port)
 - Gigabit Ethernet
 - Console output on the serial port
-- EDK II (MrChromebox's fork, at origin/uefipayload_202207) to boot
-Windows 10 (22H2) and Linux (5.19.17) via GRUB 2
-- SeaBIOS 1.16.1 to boot Windows 10 (needs VGA BIOS) and Linux via
+- SeaBIOS 1.14.0 and 1.15.0 to boot Windows 10 (needs VGA BIOS) and Linux via
 extlinux
 - Internal flashing with flashrom-1.2, see
 [Internal Programming](#internal-programming)

Documentation/mainboard/asus/p2b-ls.md

@@ -1,108 +0,0 @@
-# ASUS P2B-LS
-
-This page describes how to run coreboot on the ASUS P2B-LS mainboard.
-
-## Variants
-
-- P2B-LS
-- P2B-L (Same circuit board with SCSI components omitted)
-- P2B-S (Same circuit board with ethernet components omitted)
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | no                        |
-+---------------------+---------------------------+
-| Dual BIOS feature   | no                        |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-[flashrom] works out of the box since 0.9.2.
-Because of deficiency in vendor firmware, user needs to override the laptop
-warning as prompted. Once coreboot is in place there will be no further issue.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- Ethernet (-LS, -L; Intel 82558)
-- SCSI (-LS, -S; Adaptec AIC7890)
-- USB
-- ISA add-on cards
-- PCI add-on cards
-- AGP graphics card
-- Floppy
-- Serial ports 1 and 2
-- Reboot
-- Soft off
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted.
-  With SeaBIOS as payload, setting keyboard initialization timeout to
-  500ms may fix the issue.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-- Termination is enabled for all SCSI ports (if equipped). Support to
-  disable termination is pending. Note that the SCSI-68 port is
-  always terminated, even with vendor firmware.
-
-## Untested
-
-- Parallel port
-- EDO memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- S3 suspend to RAM
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel I440BX                                     |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p3b-f.md

@@ -1,106 +0,0 @@
-# ASUS P3B-F
-
-This page describes how to run coreboot on the ASUS P3B-F mainboard.
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------------+
-| Type                | Value                     |
-+=====================+===========================+
-| Model               | SST 39SF020A (or similar) |
-+---------------------+---------------------------+
-| Protocol            | Parallel                  |
-+---------------------+---------------------------+
-| Size                | 256 KiB                   |
-+---------------------+---------------------------+
-| Package             | DIP-32                    |
-+---------------------+---------------------------+
-| Socketed            | yes                       |
-+---------------------+---------------------------+
-| Write protection    | See below                 |
-+---------------------+---------------------------+
-| Internal flashing   | yes                       |
-+---------------------+---------------------------+
-```
-
-flashrom supports this mainboard since commit c7e9a6e15153684672bbadd1fc6baed8247ba0f6.
-If you are using older versions of flashrom, below has to be done (with ACPI disabled!)
-before flashrom can detect the flash chip:
-
-```bash
-  #  rmmod w83781d
-  #  modprobe i2c-dev
-  #  i2cset 0 0x48 0x80 0x80
-```
-
-Upon power up, flash chip is inaccessible until flashrom has been run once.
-Since flashrom does not support reversing board enabling steps,
-once it detects the flash chip, there will be no write protection until
-the next power cycle.
-
-### CPU microcode considerations
-
-By default, this board includes microcode updates for 5 families of Intel CPUs
-because of the wide variety of CPUs the board supports, directly or with an
-adapter. These take up a third of the total flash space leaving only 20kB free
-in the final cbfs image. It may be necessary to build a custom microcode update
-file by manually concatenating files in 3rdparty/intel-microcode/intel-ucode
-for only CPU models that the board will actually be run with.
-
-## Working
-
-- Slot 1 and Socket 370 CPUs and their L1/L2 caches
-- PS/2 keyboard with SeaBIOS (See [Known issues])
-- IDE hard drives
-- USB
-- PCI add-on cards
-- AGP graphics cards
-- Serial ports 1 and 2
-- Reboot
-
-## Known issues
-
-- PS/2 keyboard may not be usable until Linux has completely booted. With SeaBIOS
-  as payload, setting keyboard initialization timeout to 2500ms may help.
-
-- The coreboot+SeaBIOS combination boots so quickly some IDE hard drives are not
-  yet ready by the time SeaBIOS attempts to boot from them.
-
-- i440BX does not support 256Mbit RAM modules. If installed, coreboot
-  will attempt to initialize them at half their capacity anyway
-  whereas vendor firmware will not boot at all.
-
-- ECC memory can be used, but ECC support is still pending.
-
-## Untested
-
-- Floppy
-- Parallel port
-- EDO memory
-- ECC memory
-- Infrared
-- PC speaker
-
-## Not working
-
-- ACPI (Support is currently [under gerrit review](https://review.coreboot.org/c/coreboot/+/41098))
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel I440BX                                     |
-+------------------+--------------------------------------------------+
-| Southbridge      | i82371eb                                         |
-+------------------+--------------------------------------------------+
-| CPU              | P6 family for Slot 1 and Socket 370              |
-|                  | (all models from model_63x to model_6bx)         |
-+------------------+--------------------------------------------------+
-| Super I/O        | winbond/w83977tf                                 |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/asus/p8z77-m.md

@@ -1,137 +0,0 @@
-# ASUS P8Z77-M
-
-This page describes how to run coreboot on the [ASUS P8Z77-M].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+----------------+
-| Type                | Value          |
-+=====================+================+
-| Model               | W25Q64FVA1Q    |
-+---------------------+----------------+
-| Size                | 8 MiB          |
-+---------------------+----------------+
-| Package             | DIP-8          |
-+---------------------+----------------+
-| Socketed            | yes            |
-+---------------------+----------------+
-| Write protection    | yes            |
-+---------------------+----------------+
-| Dual BIOS feature   | no             |
-+---------------------+----------------+
-| Internal flashing   | yes            |
-+---------------------+----------------+
-```
-
-The flash chip is located between the blue SATA ports.
-
-The main SPI flash cannot be written internally because Asus disables BIOSWE and
-enables ``BLE/SMM_BWP`` flags in ``BIOS_CNTL`` for their latest bioses.
-To install coreboot for the first time, the flash chip must be removed and
-flashed with an external programmer; flashing in-circuit doesn't work.
-The flash chip is socketed, so it's easy to remove and reflash.
-
-## Working
-
-- All USB2 ports (mouse, keyboard and thumb drive)
-- USB3 ports on rear (Boots SystemRescue 6.0.3 off a Kingston DataTraveler G4 8GB)
-- Gigabit Ethernet (RTL8111F)
-- SATA3, SATA2 (all ports, hot-swap not tested)
-       (Blue SATA2)  (Blue SATA2)  (White SATA3)
-        port 5        port 3        port 1
-        port 6        port 4        port 2
-
-- CPU Temp sensors and hardware monitor (some values don't make sense)
-- Native and MRC memory initialization
-  (please see [Native raminit compatibility] and [MRC memory compatibility])
-
-- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM
-  (VGA/DVI-D/HDMI tested and working)
-- 16x PCIe GPU in PCIe-16x/4x slots (tested using nVidia Quadro 600 under SystemRescue 6.0.3
-  (Arch based))
-- Serial port
-- PCI slot
-  Rockwell HSF 56k PCI modem, Sound Blaster Live! CT4780 (cards detected, not function tested)
-  Promise SATA150 TX2plus (R/W OK to connected IDE hard drive, OpRom loaded, cannot boot from
-  SeaBIOS)
-- S3 suspend from Linux
-- 2-channel analog audio (WAV playback by mplayer via back panel line out port)
-- Windows 10 with libgfxinit high resolution framebuffer and VBT
-
-## Known issues
-
-- If you use MRC raminit, the NVRAM variable gfx_uma_size may be ignored as IGP's UMA could
-  be reconfigured by the blob.
-
-- If SeaBIOS is used for payload with libgfxinit, it must be brought in via coreboot's config.
-  Otherwise integrated graphics would fail with a black screen.
-
-- PCI POST card is not functional because the PCI bridge early init is not yet done.
-
-- The black PCIEX16_2 slot, although can physically fit an x16, only has physical contacts for
-  an x8, and is electrically an x4 only.
-
-## Untested
-
-- Wake-on-LAN
-- USB3 on header
-- TPM header
-- EHCI debugging (Debug port is on the 5-pin side of USB2_910 header)
-- HDMI and S/PDIF audio out
-
-## Not working
-
-- PS/2 keyboard or mouse
-- 4 and 6 channel analog audio out: Rear left and right audio is a muted
-  copy of front left and right audio, and the other two channels are silent.
-
-## Native (and MRC) raminit compatibility
-
-- OCZ OCZ3G1600LVAM 2x2GB kit works at DDR3-1066 instead of DDR3-1600.
-
-- GSkill F3-1600C9D-16GRSL 2x8GB SODIMM kit on adapter boots, but is highly unstable
-  with obvious pattern of bit errors during memtest86+ runs.
-
-- Samsung PC3-10600U 2x2GB kit works at full rated speed.
-
-- Kingston KTH9600B-4G 2x4GB kit works at full rated speed.
-
-## Extra onboard buttons
-
-The board has two onboard buttons, and each has a related LED nearby.
-What controls the LEDs and what the buttons control are unknown,
-therefore they currently do nothing under coreboot.
-
-- BIOS_FLBK
-  OEM firmware uses this button to facilitate a simple update mechanism
-  via a USB drive plugged into the bottom USB port of the USB/LAN stack.
-
-- MemOK!
-  OEM firmware uses this button for memory tuning related to overclocking.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton NCT6779D                                 |
-+------------------+--------------------------------------------------+
-| EC               | None                                             |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Extra resources
-
-- [Flash chip datasheet][W25Q64FVA1Q]
-
-[ASUS P8Z77-M]: https://www.asus.com/Motherboards/P8Z77M/
-[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/2170p.md

@@ -1,91 +0,0 @@
-# HP EliteBook 2170p
-
-This page is about the notebook [HP EliteBook 2170p].
-
-## Release status
-
-HP EliteBook 2170p was released in 2012 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-1. EC firmware
-2. Intel ME firmware
-
-EC firmware can be retrieved from the HP firmware update image, or the firmware
-backup of the laptop. EC Firmware is part of the coreboot build process.
-The guide on extracting EC firmware and using it to build coreboot is in
-document [HP Laptops with KBC1126 Embedded Controller](hp_kbc1126_laptops).
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-## Programming
-
-The flash chip is located between the memory slots, WWAN card and CPU,
-covered by the base enclosure, which needs to be removed according to
-the [Maintenance and Service Guide] to access the flash chip. Unlike
-other variants, the flash chip on 2170p is socketed, so it can be taken
-off and operated with an external programmer.
-
-Pin 1 of the flash chip is at the side near the CPU.
-
-![Flash Chip in 2170p](2170p_flash.jpg)
-
-For more details have a look at the general [flashing tutorial].
-
-## Debugging
-
-The board can be debugged with serial port on the dock or EHCI debug.
-The EHCI debug port is the left USB3 port.
-
-## Test status
-
-### Known issues
-
-- GRUB payload freezes if at_keyboard module is in the GRUB image
-  ([bug #141])
-
-### Untested
-
-- Fingerprint Reader
-- Dock: Parallel port, PS/2 mouse, S-Video port
-
-### Working
-
-- Integrated graphics init with libgfxinit
-- SATA
-- Audio: speaker and microphone
-- Ethernet
-- WLAN
-- WWAN
-- Bluetooth
-- SD Card Reader
-- SmartCard Reader
-- USB
-- DisplayPort
-- Keyboard, touchpad and trackpoint
-- EC ACPI support and thermal control
-- Dock: all USB ports, DVI-D, Serial debug, PS/2 keyboard
-- TPM
-- Internal flashing when IFD is unlocked
-- Using `me_cleaner`
-
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Sandy/Ivy Bridge (FCPGA988)                |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Panther Point QM77                         |
-+------------------+--------------------------------------------------+
-| EC               | SMSC KBC1126                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-[HP EliteBook 2170p]: https://support.hp.com/us-en/product/hp-elitebook-2170p-notebook-pc/5245427
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c03387961.pdf
-[flashing tutorial]: ../../tutorial/flashing_firmware/ext_power.md

Documentation/mainboard/hp/compaq_8200_sff.md

@@ -14,99 +14,30 @@ The following things are still missing from this coreboot port:
 ## Flashing coreboot
 
 ```eval_rst
-+---------------------+-------------------------+
-| Type                | Value                   |
-+=====================+=========================+
-| Socketed flash      | no                      |
-+---------------------+-------------------------+
-| Model               | MX25L6406E/MX25L6408E   |
-+---------------------+-------------------------+
-| Size                | 8 MiB                   |
-+---------------------+-------------------------+
-| In circuit flashing | yes                     |
-+---------------------+-------------------------+
-| Package             | SOIC-8                  |
-+---------------------+-------------------------+
-| Write protection    | bios region             |
-+---------------------+-------------------------+
-| Dual BIOS feature   | No                      |
-+---------------------+-------------------------+
-| Internal flashing   | yes                     |
-+---------------------+-------------------------+
-```
-
-### Flash layout
-The original layout of the flash should look like this:
-```
-00000000:00000fff fd
-00510000:007fffff bios
-00003000:0050ffff me
-00001000:00002fff gbe
++---------------------+------------+
+| Type                | Value      |
++=====================+============+
+| Socketed flash      | no         |
++---------------------+------------+
+| Model               | MX25L6406E |
++---------------------+------------+
+| Size                | 8 MiB      |
++---------------------+------------+
+| In circuit flashing | yes        |
++---------------------+------------+
+| Package             | SOIC-8     |
++---------------------+------------+
+| Write protection    | No         |
++---------------------+------------+
+| Dual BIOS feature   | No         |
++---------------------+------------+
+| Internal flashing   | yes        |
++---------------------+------------+
 ```
 
 ### Internal programming
 
 The SPI flash can be accessed using [flashrom].
-```console
-$ flashrom -p internal -c MX25L6406E/MX25L6408E -w coreboot.rom
-```
-
-After shorting the FDO jumper you gain access to the full flash, but you
-still cannot write in the bios region due to SPI protected ranges.
-
-**Position of FDO jumper close to the IO and second fan connector**
-![][compaq_8200_jumper]
-
-[compaq_8200_jumper]: compaq_8200_sff_jumper.jpg
-
-To write to the bios region you can use an [IFD Hack] originally developed
-for MacBooks, but with modified values described in this guide.
-You should read both guides before attempting the procedure.
-
-Since you can still write in the flash descriptor, you can shrink
-the ME and then move the bios region into where the ME originally was.
-coreboot does not by default restrict writing to any part of the flash, so
-you will first flash a small coreboot build and after it boots, flash
-the full one.
-
-The temporary flash layout with the neutered ME firmware should look like this:
-```
-00000000:00000fff fd
-00023000:001fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-00200000:007fffff pd
-```
-
-It is very important to use these exact numbers or you will need to fix it
-using external flashing, but you should already be familiar with the risks
-if you got this far.
-
-The temporary ROM chip size to set in menuconfig is 2 MB but the default
-CBFS size is too large for that, you can use up to about 0x1D0000.
-
-When building both the temporary and the permanent installation, don't forget
-to also add the gigabit ethernet configuration when adding the flash descriptor
-and ME firmware.
-
-You can pad the ROM to the required 8MB with zeros using:
-```console
-$ dd if=/dev/zero of=6M.bin bs=1024 count=6144
-$ cat coreboot.rom 6M.bin > coreboot8.rom
-```
-
-If you want to continue using the neutered ME firmware use this flash layout
-for stage 2:
-```
-00000000:00000fff fd
-00023000:007fffff bios
-00003000:00022fff me
-00001000:00002fff gbe
-```
-
-If you want to use the original ME firmware use the original flash layout.
-
-More about flashing internally and getting the flash layout [here](../../tutorial/flashing_firmware/index.md).
 
 ### External programming
 
@@ -143,7 +74,7 @@ as otherwise there's not enough space near the flash.
 | Coprocessor      | Intel ME                                         |
 +------------------+--------------------------------------------------+
 ```
-[IFD Hack]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/changes/70/38770/4/Documentation/flash_tutorial/int_macbook.md/
+
 [Compaq 8200 Elite SFF]: https://support.hp.com/us-en/document/c03414707
 [HP]: https://www.hp.com/
 [flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/hp/compaq_8300_usdt.md

@@ -1,65 +0,0 @@
-# HP Compaq Elite 8300 USDT
-
-This page describes how to run coreboot on the [Compaq Elite 8300 USDT] desktop
-from [HP].
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+-------------+
-| Type                | Value       |
-+=====================+=============+
-| Socketed flash      | no          |
-+---------------------+-------------+
-| Model               | W25Q128BVFG |
-+---------------------+-------------+
-| Size                | 16 MiB      |
-+---------------------+-------------+
-| In circuit flashing | yes         |
-+---------------------+-------------+
-| Package             | SOIC-16     |
-+---------------------+-------------+
-| Write protection    | No          |
-+---------------------+-------------+
-| Dual BIOS feature   | No          |
-+---------------------+-------------+
-```
-
-### Internal programming
-
-Internal programming is possible. Shorting the Flash Descriptor Override
-(FDO) jumper bypasses all write protections.
-
-### External programming
-
-Remove the lid. The flash chip can be found on the edge opposite to the CPU.
-There is a spot for a "ROM RCVRY" header next to the flash chip but it is
-unpopulated. If you don't feel like using a clip, you can easily solder
-a standard pin header there yourself and use it for programming.
-
-Programming powers some parts of the board. Programming when
-Wake on LAN is active works great.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | bd82x6x                                          |
-+------------------+--------------------------------------------------+
-| CPU              | model_206ax                                      |
-+------------------+--------------------------------------------------+
-| SuperIO          | NPCD379HAKFX                                     |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel ME                                         |
-+------------------+--------------------------------------------------+
-```
-
-### SuperIO
-
-This board has a Nuvoton NPCD379 SuperIO chip. Fan speed and PS/2 keyboard work
-fine using coreboot's existing code for :doc:`../../superio/nuvoton/npcd378`.
-
-[Compaq Elite 8300 USDT]: https://support.hp.com/gb-en/product/hp-compaq-elite-8300-ultra-slim-pc/5232866
-[HP]: https://www.hp.com/

Documentation/mainboard/hp/elitebook_820_g2.md

@@ -1,141 +0,0 @@
-# HP EliteBook 820 G2
-
-This page is about the notebook [HP EliteBook 820 G2].
-
-## Release status
-
-HP EliteBook 820 G2 was released in 2015 and is now end of life.
-It can be bought from a secondhand market like Taobao or eBay.
-
-## Required proprietary blobs
-
-The following blobs are required to operate the hardware:
-
-1. EC firmware
-2. Intel ME firmware
-3. Broadwell mrc.bin and refcode.elf
-
-HP EliteBook 820 G2 uses SMSC MEC1324 as its embedded controller.
-The EC firmware is stored in the flash chip, but we don't need to touch it
-or use it in the coreboot build process.
-
-Intel ME firmware is in the flash chip. It is not needed when building coreboot.
-
-The Broadwell memory reference code binary and reference code blob is needed
-when building coreboot. Read the document [Blobs used in Intel Broadwell boards]
-on how to get these blobs.
-
-## Programming
-
-Before flashing, remove the battery and the hard drive cover according to the
-[Maintenance and Service Guide] of this laptop.
-
-HP EliteBook 820 G2 has two flash chips, a 16MiB system flash, and a 2MiB
-private flash. To install coreboot, we need to program both flash chips.
-Read [HP Sure Start] for detailed information.
-
-![HP EliteBook 820 G2 flash chip](elitebook_820_g2_flash.jpg)
-
-To access the system flash, we need to connect the AC adapter to the machine,
-then clip on the flash chip with an SOIC-8 clip. An [STM32-based flash programmer]
-made with an STM32 development board is tested to work.
-
-To access the private flash chip, we can use a ch341a based flash programmer and
-flash the chip with the AC adapter disconnected.
-
-To flash coreboot on a board running OME firmware, create a backup for both flash
-chips, then do the following:
-
-1. Erase the private flash to disable the IFD protection
-2. Modify the IFD to shrink the BIOS region, so that we can put the firmware outside
-   the protected flash region
-
-To erase the private flash chip, attach it with the flash programmer via the SOIC-8 clip,
-then run:
-
-    flashrom -p <programmer> --erase
-
-To modify the IFD, write the following flash layout to a file:
-
-    00000000:00000fff fd
-    00001000:00002fff gbe
-    00003000:005fffff me
-    00600000:00bfffff bios
-    00eb5000:00ffffff pd
-
-Suppose the above layout file is ``layout.txt`` and the origin content of the system flash
-is in ``factory-sys.rom``, run:
-
-    ifdtool -n layout.txt factory-sys.rom
-
-Then a flash image with a new IFD will be in ``factory-sys.rom.new``.
-
-Flash the IFD of the system flash:
-
-    flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new
-
-Then flash the coreboot image:
-
-    # first extend the 12M coreboot.rom to 16M
-    fallocate -l 16M build/coreboot.rom
-    flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom
-
-After coreboot is installed, the coreboot firmware can be updated with internal flashing:
-
-    flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom
-
-## Debugging
-
-The board can be debugged with EHCI debug. The EHCI debug port is the USB port on the left.
-
-## Test status
-
-### Untested
-
-- NFC module
-- Fingerprint reader
-- Smart Card reader
-
-### Working
-
-- mainboards with i3-5010U, i5-5300U CPU, 16G+8G DDR3L memory
-- SATA and M.2 SATA disk
-- PCIe SSD
-- Webcam
-- Touch screen
-- Audio output from speaker and headphone jack
-- Intel GbE (needs a modified refcode documented in [Blobs used in Intel Broadwell boards])
-- WLAN
-- WWAN
-- SD card reader
-- Internal LCD, DisplayPort and VGA video outputs
-- Dock
-- USB
-- Keyboard and touchpad
-- EC ACPI
-- S3 resume
-- TPM
-- Arch Linux with Linux 5.11.16
-- Broadwell MRC version 2.6.0 Build 0 and refcode from Purism Librem 13 v1
-- Graphics initialization with libgfxinit
-- Payload: SeaBIOS 1.16.2
-- EC firmware: KBC Revision 96.54 from OEM firmware version 01.05
-- Internal flashing under coreboot
-
-## Technology
-
-```eval_rst
-+------------------+-----------------------------+
-| SoC              | Intel Broadwell             |
-+------------------+-----------------------------+
-| EC               | SMSC MEC1324                |
-+------------------+-----------------------------+
-| Coprocessor      | Intel Management Engine     |
-+------------------+-----------------------------+
-```
-
-[HP EliteBook 820 G2]: https://support.hp.com/us-en/product/HP-EliteBook-820-G2-Notebook-PC/7343192/
-[Blobs used in Intel Broadwell boards]: ../../soc/intel/broadwell/blobs.md
-[Maintenance and Service Guide]: http://h10032.www1.hp.com/ctg/Manual/c04775894.pdf
-[STM32-based flash programmer]: https://github.com/dword1511/stm32-vserprog
-[HP Sure Start]: hp_sure_start.md

Documentation/mainboard/index.md

@@ -23,14 +23,11 @@ This section contains documentation about coreboot on specific mainboards.
 
 - [A88XM-E](asus/a88xm-e.md)
 - [F2A85-M](asus/f2a85-m.md)
-- [P2B-LS](asus/p2b-ls.md)
-- [P3B-F](asus/p3b-f.md)
 - [P5Q](asus/p5q.md)
 - [P8C WS](asus/p8c_ws.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
 - [P8H77-V](asus/p8h77-v.md)
-- [P8Z77-M](asus/p8z77-m.md)
 - [P8Z77-M Pro](asus/p8z77-m_pro.md)
 - [P8Z77-V](asus/p8z77-v.md)
 - [wifigo_v1](asus/wifigo_v1.md)
@@ -75,23 +72,19 @@ The boards in this section are not real mainboards, but emulators.
 ## HP
 
 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
-- [Compaq Elite 8300 USDT](hp/compaq_8300_usdt.md)
 - [Z220 Workstation SFF](hp/z220_sff.md)
 
 ### EliteBook series
 
 - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md)
 - [HP Sure Start](hp/hp_sure_start.md)
-- [EliteBook 2170p](hp/2170p.md)
 - [EliteBook 2560p](hp/2560p.md)
 - [EliteBook 8760w](hp/8760w.md)
 - [EliteBook Folio 9480m](hp/folio_9480m.md)
-- [EliteBook 820 G2](hp/elitebook_820_g2.md)
 
 ## Intel
 
 - [DG43GT](intel/dg43gt.md)
-- [DQ67SW](intel/dq67sw.md)
 - [KBLRVP11](intel/kblrvp11.md)
 
 ## Kontron
@@ -125,7 +118,8 @@ The boards in this section are not real mainboards, but emulators.
 ### Ivy Bridge series
 
 - [T430](lenovo/t430.md)
-- [T530 / W530](lenovo/w530.md)
+- [T530](lenovo/w530.md)
+- [W530](lenovo/w530.md)
 - [T430 / T530 / X230 / W530 common](lenovo/Ivy_Bridge_series.md)
 - [T431s](lenovo/t431s.md)
 - [X230s](lenovo/x230s.md)
@@ -174,8 +168,6 @@ The boards in this section are not real mainboards, but emulators.
 
 - [FW2B / FW4B](protectli/fw2b_fw4b.md)
 - [FW6A / FW6B / FW6C](protectli/fw6.md)
-- [VP2420](protectli/vp2420.md)
-- [VP4630 / VP4650 / VP4670](protectli/vp46xx.md)
 
 ## Roda
 
@@ -206,33 +198,25 @@ The boards in this section are not real mainboards, but emulators.
 
 - [Adder Workstation 1](system76/addw1.md)
 - [Adder Workstation 2](system76/addw2.md)
-- [Adder Workstation 3](system76/addw3.md)
 - [Bonobo Workstation 14](system76/bonw14.md)
-- [Bonobo Workstation 15](system76/bonw15.md)
 - [Darter Pro 6](system76/darp6.md)
 - [Darter Pro 7](system76/darp7.md)
 - [Darter Pro 8](system76/darp8.md)
-- [Darter Pro 9](system76/darp9.md)
 - [Galago Pro 4](system76/galp4.md)
 - [Galago Pro 5](system76/galp5.md)
 - [Galago Pro 6](system76/galp6.md)
-- [Galago Pro 7](system76/galp7.md)
 - [Gazelle 15](system76/gaze15.md)
 - [Gazelle 16](system76/gaze16.md)
 - [Gazelle 17](system76/gaze17.md)
-- [Gazelle 18](system76/gaze18.md)
 - [Lemur Pro 9](system76/lemp9.md)
 - [Lemur Pro 10](system76/lemp10.md)
 - [Lemur Pro 11](system76/lemp11.md)
-- [Lemur Pro 12](system76/lemp12.md)
 - [Oryx Pro 5](system76/oryp5.md)
 - [Oryx Pro 6](system76/oryp6.md)
 - [Oryx Pro 7](system76/oryp7.md)
 - [Oryx Pro 8](system76/oryp8.md)
 - [Oryx Pro 9](system76/oryp9.md)
 - [Oryx Pro 10](system76/oryp10.md)
-- [Oryx Pro 11](system76/oryp11.md)
-- [Serval Workstation 13](system76/serw13.md)
 
 ## Texas Instruments
 

Documentation/mainboard/intel/dq67sw.md

@@ -1,170 +0,0 @@
-# Intel DQ67SW
-
-The Intel DQ67SW is a microATX-sized desktop board for Intel Sandy Bridge CPUs.
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel Q67 (bd82x6x)                              |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA 1155                                         |
-+------------------+--------------------------------------------------+
-| RAM              | 4 x DDR3-1333                                    |
-+------------------+--------------------------------------------------+
-| Super I/O        | Nuvoton/Winbond W83677HG-i                       |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888S                                  |
-+------------------+--------------------------------------------------+
-| Network          | Intel 82579LM Gigabit Ethernet                   |
-+------------------+--------------------------------------------------+
-| Serial           | Internal header                                  |
-+------------------+--------------------------------------------------+
-```
-
-## Status
-
-### Working
-
-- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
-- Native RAM initialization with four DIMMs
-- Integrated GPU with libgfxinit
-- PCIe graphics in the PEG slot
-- Additional PCIe slots
-- PCI slot
-- All rear (4x) and internal (8x) USB2 ports
-- Rear USB3 ports (2x)
-- All four internal SATA ports (two 6 Gb/s, two 3 Gb/s)
-- Two rear eSATA connectors (3 Gb/s)
-- SATA at 6 Gb/s
-- Gigabit Ethernet
-- SeaBIOS 1.16.1 + libgfxinit (legacy VGA) to boot slackware64 (Linux 5.15)
-- SeaBIOS 1.16.1 + extracted VGA BIOS to boot Windows 10 (21H2)
-- edk2 UefiPayload (uefipayload_202207) + libgfxinit (high-res) to boot:
-    - slackware64 (Linux 5.15)
-    - Windows 10 (22H2)
-- External in-circuit flashing with flashrom-1.2 and a Raspberry Pi 1
-- Poweroff
-- Resume from S3
-- Console output on the serial port
-
-### Not working
-
-- Automatic fan control. One can still use OS-based fan control programs,
-  such as fancontrol on Linux or SpeedFan on Windows.
-- Windows 10 booted from SeaBIOS + libgfxinit (high-res). The installation
-  works, but once Windows Update installs drivers, it crashes and enters a
-  bootloop.
-
-### Untested
-
-- Firewire (LSI L-FW3227-100)
-- EHCI debug
-- S/PDIF audio
-- Audio jacks other than the green one
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+------------+
-| Type                | Value      |
-+=====================+============+
-| Socketed flash      | no         |
-+---------------------+------------+
-| Model               | W25Q64.V   |
-+---------------------+------------+
-| Size                | 8 MiB      |
-+---------------------+------------+
-| Package             | SOIC-8     |
-+---------------------+------------+
-| Write protection    | yes        |
-+---------------------+------------+
-| Dual BIOS feature   | no         |
-+---------------------+------------+
-| Internal flashing   | see below  |
-+---------------------+------------+
-| In circuit flashing | see below  |
-+---------------------+------------+
-```
-
-The flash is divided into the following regions, as obtained with
-`ifdtool -f rom.layout backup.rom`:
-
-    00000000:00000fff fd
-    00580000:007fffff bios
-    00003000:0057ffff me
-    00001000:00002fff gbe
-
-Unfortunately the SPI interface to the chip is locked down by the vendor
-firmware. The BIOS Lock Enable (BLE) bit of the `BIOS_CNTL` register, part of
-the PCI configuration space of the LPC Interface Bridge, is set.
-
-It is possible to program the chip is to attach an external programmer
-with an SOIC-8 clip.
-
-```eval_rst
-Another way is to boot the vendor firmware in UEFI mode and exploit the
-unpatched S3 Boot Script vulnerability. See this page for a similar procedure:
-:doc:`../lenovo/ivb_internal_flashing`.
-```
-
-On this specific board it is possible to prevent the BLE bit from being set
-when it resumes from S3. One entry in the S3 Boot Script must be modified,
-e.g. with a patched version of [CHIPSEC](https://github.com/chipsec/chipsec)
-that supports this specific type of S3 Boot Script, for example from strobo5:
-
-    $ git clone -b headerless https://github.com/strobo5/chipsec.git
-    $ cd chipsec
-    $ python setup.py build_ext -i
-    $ sudo python chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xe00f80dc,0x00,1
-
-The boot script contains an entry that writes 0x02 to memory at address
-0xe00f80dc. This address points at the PCIe configuration register at offset
-0xdc for the PCIe device 0:1f.0, which is the BIOS Control Register of the LPC
-Interface Bridge [0][1]. The value 0x02 sets the BLE bit, and the modification
-prevents this by making it write a 0 instead.
-
-```eval_rst
-After suspending and resuming the board, the BIOS region can be flashed with
-a coreboot image, e.g. using flashrom. Note that the ME region is not readable,
-so the `--noverify-all` flag is necessary. Please refer to the
-:doc:`../../tutorial/flashing_firmware/index`.
-```
-
-## Hardware monitoring and fan control
-
-Currently there is no automatic, OS-independent fan control.
-
-## Serial port header
-
-Serial port 1, provided by the Super I/O, is exposed on a pin header. The
-RS-232 signals are assigned to the header so that its pin numbers map directly
-to the pin numbers of a DE-9 connector. If your serial port doesn't seem to
-work, check if your bracket expects a different assignment.
-
-Here is a top view of the serial port header found on this board:
-
-                 +---+---+
-             N/C |   | 9 | RI  -> pin 9
-                 +---+---+
-    Pin 8 <- CTS | 8 | 7 | RTS -> pin 7
-                 +---+---+
-    Pin 6 <- DSR | 6 | 5 | GND -> pin 5
-                 +---+---+
-    Pin 4 <- DTR | 4 | 3 | TxD -> pin 3
-                 +---+---+
-    Pin 2 <- RxD | 2 | 1 | DCD -> pin 1
-                 +---+---+
-
-## References
-
-[0]: Intel 6 Series Chipset and Intel C200 Series Chipset Datasheet,
-May 2011,
-Document number 324645-006
-
-[1]: Accessing PCI Express Configuration Registers Using Intel Chipsets,
-December 2008,
-Document number 321090
-

Documentation/mainboard/protectli/vp2420.md

@@ -1,87 +0,0 @@
-# Protectli Vault VP2420
-
-This page describes how to run coreboot on the [Protectli VP2420].
-
-![](VP2420_back.jpg)
-![](VP2420_front.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Elkhart Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. Firmware can be easily
-flashed with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is soldered in
-under RAM, easily accessed after taking out the memory. Specifically, it's a
-KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](VP2420_internal.jpg)
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 4 Ethernet ports
-- HDMI, DisplayPort
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector
-- SMBus (reading SPD from DIMMs)
-- Initialization with Elkhart Lake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Celeron J6412                              |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Elkhart Lake                               |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8613E                                      |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP2420 Hardware Overview](https://protectli.com/kb/vp2400-series-hardware-overview/)
-- [VP2420 Product Page](https://protectli.com/product/vp2420/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-- [MX25L12835F](https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf)
-- [flashrom](https://flashrom.org/Flashrom)

Documentation/mainboard/protectli/vp46xx.md

@@ -1,135 +0,0 @@
-# Protectli Vault VP46xx series
-
-This page describes how to run coreboot on the [Protectli VP46xx].
-
-![](vp46xx_front.jpg)
-![](vp46xx_back.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the Comet Lake FSP binary (done
-automatically by the coreboot build system and included into the image) from
-the `3rdparty/fsp` submodule. VP4630 and VP4650 use CometLake2 FSP and VP4670
-use CometLake1 FSP (see [variants](#variants) section), so be sure to select
-the correct board in the coreboot's menuconfig, otherwise the platform will not
-succeed on memory initialization.
-
-Microcode updates are automatically included into the coreboot image by build
-system from the `3rdparty/intel-microcode` submodule.
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. The first version
-supporting the chipset is flashrom v1.2. Firmware an be easily flashed
-with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB socketed SOIC-8 chip.
-This chip is located on the top side of the case (the lid side). One has to
-remove 4 top cover screws and lift up the lid. The flash chip is near the M.2
-WiFi slot connector. Remove the chip from socket and use a clip to program the
-chip. Specifically, it's a KH25L12835F (3.3V) which is a clone of Macronix
-MX25L12835F - [datasheet][MX25L12835F].
-
-![](vp46xx_flash.jpg)
-
-## Known issues
-
-- After flashing with external programmer it is always required to reset RTC
-  with a jumper or disconnect the coin cell temporarily. Only then the platform
-  will boot after flashing.
-
-## Working
-
-- USB 3.0 front ports (SeaBIOS, Tianocore UEFIPayload and Linux)
-- 6 Ethernet ports
-- HDMI, DisplayPort and USB-C Display Port with libgfxinit and FSP GOP
-- flashrom
-- M.2 WiFi
-- M.2 4G LTE
-- M.2 SATA and NVMe
-- 2.5'' SATA SSD
-- eMMC
-- Super I/O serial port 0 via front microUSB connector (Fintek F81232 USB to
-  UART adapter present on board)
-- SMBus (reading SPD from DIMMs)
-- Initialization with CometLake FSP 2.0
-- SeaBIOS payload (version rel-1.16.0)
-- TianoCore UEFIPayload
-- LPC TPM module (using Protectli custom-designed module with Infineon SLB9660)
-- Reset switch
-- Booting Debian, Ubuntu, FreeBSD
-
-## Variants
-
-There are 3 variants of VP46xx boards: VP4630, VP4650 and VP4670. They differ
-only in used SoC and some units may come with different Super I/O chips, either
-ITE IT8786E or IT8784E, but the configuration is the same on this platform.
-
-- VP4630:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i3-10110U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4650:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i5-10210U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-- VP4670:
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| CPU              | Intel Core i7-10810U                             |
-+------------------+--------------------------------------------------+
-| PCH              | Intel Comet Lake U Premium                       |
-+------------------+--------------------------------------------------+
-| Super I/O, EC    | ITE IT8786E/IT8784E                              |
-+------------------+--------------------------------------------------+
-| Coprocessor      | Intel Management Engine                          |
-+------------------+--------------------------------------------------+
-```
-
-## Useful links
-
-- [VP4600 Hardware Overview](https://protectli.com/kb/vp4600-hardware-overview/)
-- [VP4630 Product Page](https://protectli.com/product/vp4630/)
-- [Protectli TPM module](https://protectli.com/product/tpm-module/)
-
-[Protectli VP46xx]: https://protectli.com/vault-6-port/
-[MX25L12835F]: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8653/MX25L12835F,%203V,%20128Mb,%20v1.6.pdf
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/starlabs/labtop_cml.md

@@ -41,7 +41,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_cml` as config file.
 
 ## Flashing coreboot
 
@@ -63,6 +63,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/labtop_kbl.md

@@ -38,7 +38,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_labtop_kbl` as config file.
 
 ## Flashing coreboot
 
@@ -60,6 +60,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glk.md

@@ -37,7 +37,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glk` as config file.
 
 ## Flashing coreboot
 
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/lite_glkr.md

@@ -37,7 +37,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_lite_glkr` as config file.
 
 ## Flashing coreboot
 
@@ -59,6 +59,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_adl.md

@@ -5,8 +5,6 @@
 - CPU (full processor specs available at https://ark.intel.com)
     - Intel i7-1260P (Alder Lake)
     - Intel i3-1220P (Alder Lake)
-    - Intel i3-1315U (Raptor Lake)
-    - Intel i7-1360P (Raptor Lake)
 - EC
     - ITE IT5570E
     - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys
@@ -35,15 +33,14 @@
     - RTS5129 MicroSD card reader
 - USB
     - 1920x1080 CCD camera
-    - USB 3.1 Gen 2 (left) (Alder Lake)
-    - Thunderbolt 4.0 (left) (Raptor Lake)
+    - USB 3.1 Gen 2 (left)
     - USB 3.1 Gen 2 Type-A (left)
     - USB 3.1 Gen 1 Type-A (right)
     - USB 2.0 Type-A (right)
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file.
 
 ### Preliminaries
 
@@ -61,21 +58,12 @@ These files exist in the correct location in the StarLabsLtd/blobs repo on GitHu
 
 The following commands will build a working image:
 
-
-Alder Lake:
 ```bash
 make distclean
 make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_adl
 make
 ```
 
-Raptor Lake:
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_rpl
-make
-```
-
 ## Flashing coreboot
 
 ```eval_rst
@@ -96,6 +84,5 @@ make
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/starlabs/starbook_tgl.md

@@ -40,7 +40,7 @@
 
 ## Building coreboot
 
-Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
+Please follow the [Star Labs build instructions](../common/building.md) to build coreboot, using `config.starlabs_starbook_tgl` as config file.
 
 ## Flashing coreboot
 
@@ -62,6 +62,5 @@ Please follow the [Star Labs build instructions](common/building.md) to build co
 +---------------------+------------+
 | External flashing   | yes        |
 +---------------------+------------+
-```
 
-Please see [here](common/flashing.md) for instructions on how to flash with fwupd.
+Please see [here](../common/flashing.md) for instructions on how to flash with fwupd.

Documentation/mainboard/system76/addw3.md

@@ -1,71 +0,0 @@
-# System76 Adder Workstation 3 (addw3)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options
-    - NVIDIA GeForce RTX 4050
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - eDP displays
-    - 15.6" 1920x1080@144Hz LCD
-    - 17.3" 1920x1080@144Hz LCD
-  - External outputs
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-    - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 4800 MHz
-- Networking
-  - Intel I219-V gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6E AX210/AX211
-- Power
-  - 280W (20V, 14A) DC-in port
-    - Included: Chicony A18-280P1A
-  - 73Wh 4-cell Lithium-Ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 (PCIe NVMe Gen 4) SSDs
-  - MicroSD card reader
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 1x USB 3.2 Gen 1 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 2.71cm x 35.95cm x 23.8cm, 2.05kg
-  - 17": 2.82cm x 39.69cm x 26.2cm, 2.85kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U65) is above the battery connector.

Documentation/mainboard/system76/bonw15.md

@@ -1,65 +0,0 @@
-# System76 Bonobo Workstation 15 (bonw15)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4080
-    - NVIDIA GeForce RTX 4090
-  - eDP 17.3" 3840x2160@144Hz LCD (BOE NE173QUM-NY1)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 2x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
-- Networking
-  - Onboard Intel Killer Ethernet E3100X 2.5 GbE
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 330W (19.5V, 16.42A) AC adapter (Chicony A20-330P1A)
-    - Rectangular connector; not a barrel connector
-  - 99Wh 8-cell Lithium-ion battery
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 3x M.2 PCIe NVMe Gen 4 SSDs
-- USB
-  - 2x USB Type-C with Thunderbolt 4
-  - 2x USB 3.2 Gen 2 Type-A
-- Dimensions
-  - 2.49cm x 39.6cm x 27.8cm, 3.29kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U58) is next to the left M.2 port.

Documentation/mainboard/system76/darp9.md

@@ -1,62 +0,0 @@
-# Syste76 Darter Pro 9 (darp9)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1340P
-  - Intel Core i7-1360P
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 15.6" 1920x1080@60Hz LCD
-  - 1x HDMI
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
-- Networking
-  - Gigabit Ethernet (Realtek RTL8111H)
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6E AX210/211)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter
-  - USB-C charging, compatible with 65W+ chargers
-  - 73Wh 4-cell Lithium-ion battery (L140BAT-4)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSDs
-  - MicroSD card reader (OZ711LV2)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 35.7cm x 22.05cm x 1.99cm, 1.74kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U22) is above the left DIMM slot.

Documentation/mainboard/system76/galp7.md

@@ -1,58 +0,0 @@
-# System76 Galago Pro 7 (galp7)
-
-## Specs
-
-- CPU
-  - Intel Core i5-13500H
-  - Intel Core i7-13700H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.1" 1920x1080@144Hz LCD (Sharp LQ140M1JW49)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A)
-  - USB-C charging, compatible with 90W+ chargers
-  - 53Wh 4-cell Lithium-ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- USB
-  - 1x USB-C Type-C with Thunderbolt 4
-  - 1x USB 3.2 (Gen 2) Type-C
-  - 2x USB 3.2 (Gen 1) Type-A
-- Dimensions
-  - 32.49cm x 22.5cm x 1.82cm, 1.45kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U43) is left of the wireless card.

Documentation/mainboard/system76/gaze18.md

@@ -1,72 +0,0 @@
-# System76 Gazelle 18 (gaze18)
-
-## Specs
-
-- CPU
-  - Intel i9-13900H
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - NVIDIA GeForce RTX 3050 (70W TDP)
-  - Intel Irix Xe Graphics
-  - eDP displays
-    - 17.3" 1920x1080@144Hz LCD
-    - 15.6" 1920x1080@144Hz LCD
-  - External outputs
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Realtek RTL8111H gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6E AX210/AX211
-- Power
-  - 150W AC barrel adapter
-    - Included: LiteOn PA-1151-76, using a C5 power cord
-  - 54Wh 4-cell battery (NP50BAT-4-54)
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone/microphone jack
-  - Dedicated 3.5mm microphone jack
-  - HDMI, mDP audio
-- Storage
-  - 1x M.2 (PCIe NVMe Gen 4)
-  - 1x M.2 (PCIe NVMe Gen 3)
-  - MicroSD card reader
-    - Realtek RTS5227S
-- USB
-  - 2x USB 3.2 Gen 2 Type-C
-    - Does not support USB-C charging (USB-PD) or Thunderbolt
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 2.0 Type-A
-- Dimensions
-  - 15": 35.95cm x 23.8cm x 2.27cm, 1.99kg
-  - 17": 39.69cm x 26.2cm x 2.5cm, 2.41kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U24) is right of the M.2 SSD connectors.

Documentation/mainboard/system76/lemp12.md

@@ -1,62 +0,0 @@
-# System76 Lemur Pro 12 (lemp12)
-
-## Specs
-
-- CPU
-  - Intel Core i5-1335U
-  - Intel Core i7-1355U
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - Intel Iris Xe Graphics
-  - eDP 14.0" 1920x1080@60Hz LCD (Innolux N140HCE-EN2)
-  - 1x HDMI 2.1
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Channel 0: 8-GB onboard DDR5 (Samsung M425R1GB4BB0-CQKOD)
-  - Channel 1: 8/16/32-GB DDR5 SO-DIMM @ 4800 MHz
-- Networking
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 65W (19V, 3.42A) AC adapter (AcBel ADA012)
-  - USB-C charging, compatible with 65W+ charger
-  - 73Wh 4-cell Lithium-ion battery
-- Sound
-  - Realtek ALC256 codec
-  - Internal speakers and microphone
-  - Combined 3.5 mm headphone/microphone jack
-  - HDMI, USB-C DisplayPort audio
-- Storage
-  - 1x M.2 PCIe NVMe Gen 4 SSD
-  - 1x M.2 PCIe NVMe Gen 3 or SATA 3 SSD
-  - MicroSD card reader (RTS5227S)
-- USB
-  - 1x USB Type-C with Thudnerbolt 4
-  - 1x USB 3.2 Gen 2 Type-A
-  - 1x USB 3.2 Gen 1 Type-A
-- Dimensions
-  - 1.65cm x 32.2cm x 21.68cm, 1.15kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | Macronix            |
-+---------------------+---------------------+
-| Model               | MX25L25673G         |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U41) is left of the DIMM slot.

Documentation/mainboard/system76/oryp11.md

@@ -1,66 +0,0 @@
-# System76 Oryx Pro 11 (oryp11)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900H
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4050
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - 16" 1920x1200@165Hz LCD
-  - External outputs:
-    - 1x HDMI 2.1
-    - 1x Mini DisplayPort 1.4
-    - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5600 MHz
-- Networking
-  - Realtek RTL8125BG-CG 2.5G Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 180W (20V, 9A) AC barrel adapter (Lite-On PA-1181-86)
-  - 73Wh 4-cell Lithium-ion battery (NV40BAT-4-73)
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSD
-  - MicroSD card reader (Realtek RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 2x USB 2.1 Gen 1 Type-A
-- Dimensions
-  - 35.95cm x 27.3cm x 1.99cm, 2.7kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U61) is left of the memory slots.

Documentation/mainboard/system76/serw13.md

@@ -1,69 +0,0 @@
-# System76 Serval Workstation 13 (serw13)
-
-## Specs
-
-- CPU
-  - Intel Core i9-13900HX
-- Chipset
-  - Intel HM770
-- EC
-  - ITE IT5570E running [System76 EC](https://github.com/system76/ec)
-- Graphics
-  - dGPU options:
-    - NVIDIA GeForce RTX 4060
-    - NVIDIA GeForce RTX 4070
-  - eDP options:
-    - 15.6" 1920x1080@165Hz LCD (BOE NV156FHM-NY8)
-    - 17.6" 3840x2160@144Hz LCD (AUO B173ZAN03.0)
-  - 1x HDMI 2.1
-  - 1x Mini DisplayPort 1.4
-  - 1x DisplayPort 1.4 over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR5 SO-DIMMs @ 5200 Mhz
-- Networking
-  - Realtek RTL8125BG-CG 2.5G Ethernet
-  - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX210/211)
-- Power
-  - 280W (20V, 14A) AC adapter (Chicony A18-280P1A)
-  - 80Wh 6-cell Lithium-ion battery ()
-- Sound
-  - Realtek ALC1220 codec
-  - Realtek ALC1318 smart amp
-  - Internal speakers and microphone
-  - Combined 3.5mm headphone & microphone jack
-  - Combined 3.5mm microphone & S/PDIF jack
-  - HDMI, mDP, USB-C DP audio
-- Storage
-  - 2x M.2 PCIe NVMe Gen 4 SSDs
-  - MicroSD card reader (Realtek RTS5227S)
-- USB
-  - 1x USB Type-C with Thunderbolt 4
-  - 1x USB 3.2 Gen 2 Type-C
-  - 2x USB 3.2 Gen 1 Type-A
-- Dimensions
-  - 15": 2.49cm x 35.8cm x 24.0cm, 2.4kg
-  - 17": 2.49cm x 39.6cm x 26.2cm, 2.8kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25B256E           |
-+---------------------+---------------------+
-| Size                | 32 MiB              |
-+---------------------+---------------------+
-| Package             | WSON-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-The flash chip (U46) is left of the memory slots.

Documentation/releases/boards_supported_on_branches.md

@@ -12,9 +12,9 @@ desired.
 
 Currently, [jenkins](https://qa.coreboot.org), our continuous
 integration system is configured to build the 4.11, 4.12, 4.14, 4.15,
-4.16, 4.18, and 4.19 branches.  Builders for other branches can be
-added upon request.  Likewise, some releases are only marked with tags,
-and branches would need to be created to push new code.  These branches
+4.16, and 4.18 branches.  Builders for other branches can be created on
+request.  Likewise, some releases are only marked with tags, and
+branches would need to be created to push new code to.  These branches
 can also be created on request.
 
 Patches can be backported from the master branch to any of these other
@@ -23,17 +23,6 @@ critical security fixes, but other patches will need to handled by
 anyone using that release.
 
 
-## [4.19 Release](coreboot-4.19-relnotes.md)
-Branch created, builder configured
-
-```eval_rst
-+-------------------------------+------------------------+------------+-----------+
-| Vendor/Board                  | Processor              | Date added | Brd type  |
-+===============================+========================+============+===========+
-| intel/icelake_rvp             | INTEL_ICELAKE          | 2018-10-26 | eval      |
-+-------------------------------+------------------------+------------+-----------+
-```
-
 ## [4.18 Release](coreboot-4.18-relnotes.md)
 Branch created, builder configured
 
@@ -42,53 +31,29 @@ Branch created, builder configured
 | Vendor/Board                  | Processor              | Date added | Brd type  |
 +===============================+========================+============+===========+
 | amd/inagua                    | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/olivehill                 | AMD_FAMILY16_KB        | 2013-08-05 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/parmer                    | AMD_FAMILY15_TN        | 2012-07-22 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/persimmon                 | AMD_FAMILY14           | 2011-02-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/south_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/thatcher                  | AMD_FAMILY15_TN        | 2012-08-02 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | amd/union_station             | AMD_FAMILY14           | 2011-11-18 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | asrock/e350m1                 | AMD_FAMILY14           | 2011-02-24 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asrock/imb-a180               | AMD_FAMILY16_KB        | 2013-08-27 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asus/a88xm-e                  | AMD_FAMILY15_TN        | 2020-08-13 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | asus/am1i-a                   | AMD_FAMILY16_KB        | 2018-01-14 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | asus/f2a85-m                  | AMD_FAMILY15_TN        | 2013-03-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | bap/ode_e20XX                 | AMD_FAMILY16_KB        | 2015-05-27 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | biostar/a68n_5200             | AMD_FAMILY16_KB        | 2017-10-14 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | biostar/am1ml                 | AMD_FAMILY16_KB        | 2015-04-10 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | elmex/pcm205400               | AMD_FAMILY14           | 2016-09-29 | sbc       |
-+-------------------------------+------------------------+------------+-----------+
 | gizmosphere/gizmo2            | AMD_FAMILY16_KB        | 2014-12-09 | eval      |
-+-------------------------------+------------------------+------------+-----------+
 | gizmosphere/gizmo             | AMD_FAMILY14           | 2014-01-03 | half      |
-+-------------------------------+------------------------+------------+-----------+
 | hp/abm                        | AMD_FAMILY16_KB        | 2015-01-05 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | hp/pavilion_m6_1035dx         | AMD_FAMILY15_TN        | 2014-03-28 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
 | jetway/nf81-t56n-lf           | AMD_FAMILY14           | 2014-02-16 | mini      |
-+-------------------------------+------------------------+------------+-----------+
 | lenovo/g505s                  | AMD_FAMILY15_TN        | 2014-11-27 | laptop    |
-+-------------------------------+------------------------+------------+-----------+
 | lippert/frontrunner-af        | AMD_FAMILY14           | 2013-03-02 | half      |
-+-------------------------------+------------------------+------------+-----------+
 | msi/ms7721                    | AMD_FAMILY15_TN        | 2016-11-22 | desktop   |
-+-------------------------------+------------------------+------------+-----------+
 | pcengines/apu1                | AMD_FAMILY14           | 2015-02-23 | half      |
 +-------------------------------+------------------------+------------+-----------+
 ```

Documentation/releases/coreboot-4.19-relnotes.md

@@ -1,7 +1,7 @@
-coreboot 4.19 release
+Upcoming release - coreboot 4.19
 ========================================================================
 
-The 4.19 release was completed on the 16th of January 2023.
+The 4.19 release is planned for the 16th of January 2023.
 
 Since the last release, the coreboot project has merged over 1600
 commits from over 150 authors. Of those authors, around 25 were
@@ -15,10 +15,6 @@ It takes constant effort to just stay afloat, let alone improve the
 codebase. Thank you very much to everyone who has contributed, both in
 this release and in previous times.
 
-Note that the first set of tarballs posted for the 4.19 release had
-bad timestamps. This has been fixed. Hashes for all tarballs are at
-the bottom of this document.
-
 The 4.20 release is planned for the 20th of April, 2023.
 
 
@@ -221,47 +217,17 @@ Significant Known and Open Issues
 ---------------------------------
 
 Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
+
 | #   | Subject                                                         |
-+=====+=================================================================+
+|-----|-----------------------------------------------------------------|
 | 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
 | 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
 | 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
 | 445 | Thinkpad X200 wifi issue                                        |
-+-----+-----------------------------------------------------------------+
 | 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
 | 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
 | 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
 | 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
 | 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
 | 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
 | 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```
-
-Hashes for tarballs & signatures
---------------------------------
-
-Old tarballs:
-
-- a1f9ec1252a3cc19f0b4ba1a2b9d66ea9327499cbeecebd85377db7d5c68555d  coreboot-4.19.tar.xz
-- 6ceaa39429a2094d75e4c8a94615ae60664ddad7b4115570b65b9bb516cbd96d  coreboot-4.19.tar.xz.sig
-- 881a3477221d1b77e161759344df14eccda115086af3ef54e66485ae0eb2e5d9  coreboot-blobs-4.19.tar.xz
-- 16f4f1f7acc6203ce915ffea64edce8512bd9eb9e94e65db22a0cb5282a6e157  coreboot-blobs-4.19.tar.xz.sig
-
-New tarballs:
-
-- 65ccb2f46535b996e0066a1b76f81c8cf1ff3e27df84b3f97d8ad7b3e7cf0a43  coreboot-4.19.tar.xz
-- d3c52a209b8ccb49049960318f04f158dd47db52ebe6019d6a3dffe3196d9cbe  coreboot-4.19.tar.xz.sig
-- 30214caed07b25f11e47bec022ff6234841376e36689eb674de2330a3e980cbc  coreboot-blobs-4.19.tar.xz
-- 023d511d074703beab98c237c3e964dc7c598af86d5a0e2091195c68980b6c5d  coreboot-blobs-4.19.tar.xz.sig

Documentation/releases/coreboot-4.20-relnotes.md

@@ -0,0 +1,67 @@
+Upcoming release - coreboot 4.20
+========================================================================
+
+The 4.20 release is planned for the 20th of April 2023.
+
+
+The 4.21 release is planned for around the 17th of July, 2023
+
+
+Update this document with changes that should be in the release notes.
+
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
+* Note that all changes before the release are done are marked upcoming.
+  A final version of the notes are done after the release.
+
+* This document may also be edited at the google doc copy:
+  https://docs.google.com/document/d/1_0PeRxzT7ep8dIZobzIqG4n6Xwz3kkIDPVQURX7YTmM/edit
+
+Significant or interesting changes
+----------------------------------
+
+### Add changes that need a full description here
+
+
+
+Additional coreboot changes
+---------------------------
+
+The following are changes across a number of patches, or changes worth
+noting, but not needing a full description.
+
+* Changes that only need a line or two of description go here.
+
+
+
+
+Plans to move platform support to a branch
+------------------------------------------
+
+### Intel Quark SoC & Galileo mainboard
+
+The SoC Intel Quark is unmaintained and different efforts to revive it
+have so far failed.  The only user of this SoC ever was the Galileo
+board.
+
+Thus, to reduce the maintanence overhead for the community, support for
+the following components will be removed from the master branch and will
+be maintained on the release 4.20 branch.
+
+  * Intel Quark SoC
+  * Intel Galileo mainboard
+
+
+Statistics from the 4.19 to the 4.20 release
+--------------------------------------------
+
+* To be filled in immediately before the release by the release team
+
+
+Significant Known and Open Issues
+---------------------------------
+
+* To be filled in immediately before the release by the release team
+

Documentation/releases/coreboot-4.20.1-relnotes.md

@@ -1,265 +0,0 @@
-coreboot 4.20 release
-========================================================================
-
-The 4.20 release was done on May 15, 2023. Unfortunately, a licensing
-issues was found immediately after the release was completed, and it
-was decided to hold the release until that was fixed.
-
-Please do not use the 4.20 tag, and use the 4.20.1 git tag instead. The
-4.20_branch will contain all code for 4.20, 4.20.1, and any further
-changes required for this release.
-
-The coreboot community has done a tremendous amount of work on the
-codebase over the last three and a half months. We've had over 1600
-commits in that time period, doing ongoing cleanup and improvement.
-
-It can be hard to remember at times how much the codebase really has
-improved, but looking back at coreboot code from previous years, it's
-really impressive the changes that have happened. We'd like to thank
-everyone who has been involved in these changes. It's great to work
-with everyone involved, from the people who make the small cleanup
-patches and review all of the incoming changes to the people working
-on new chipsets and SoCs. We'd additionally like to thank all of those
-individuals who make the effort to become involved and report issues
-or push even a single patch to fix a bug that they've noticed.
-
-Many thanks to everyone involved!
-
-We plan to get the 4.21 release done in mid August, 2023.
-
-
-Significant or interesting changes
-----------------------------------
-
-
-### cpu/mp_init.c: Only enable CPUs once they execute code
-
-On some systems the BSP cannot know how many CPUs are present in the
-system. A typical use case is a multi socket system. Setting the enable
-flag only on CPUs that actually exist makes it more flexible.
-
-
-### cpu/x86/smm: Add PCI resource store functionality
-
-In certain cases data within protected memory areas like SMRAM could
-be leaked or modified if an attacker remaps PCI BARs to point within
-that area. Add support to the existing SMM runtime to allow storing
-PCI resources in SMRAM and then later retrieving them.
-
-This helps prevent moving BARs around to get SMM to access memory in
-areas that shouldn't be accessed.
-
-
-### acpi: Add SRAT x2APIC table support
-
-For platforms using X2APIC mode add SRAT x2APIC table
-generation. This allows the setup of proper SRAT tables.
-
-
-### drivers/usb/acpi: Add USB _DSM method to enable/disable USB LPM per port
-
-This patch supports projects to use _DSM to control USB3 U1/U2
-transition per port.
-
-More details can be found in
-https://web.archive.org/web/20230116084819/https://learn.microsoft.com/en-us/windows-hardware/drivers/bringup/usb-device-specific-method---dsm-
-
-The ACPI and USB driver of linux kernel need corresponding functions
-to support this feature. Please see
-https://git.kernel.org/pub/scm/linux/kernel/git/mnyman/xhci.git/log/?h=port_check_acpi_dsm
-
-
-### drivers/efi: Add EFI variable store option support
-
-Add a driver to read and write EFI variables stored in a region device.
-This is particularly useful for EDK2 as payload and allows it to reuse
-existing EFI tools to set/get options used by the firmware.
-
-The write implementation is fault tolerant and doesn't corrupt the
-variable store. A faulting write might result in using the old value
-even though a 'newer' had been completely written.
-
-Implemented basic unit tests for header corruption, writing existing
-data and append new data into the store.
-
-Initial firmware region state:
-Initially the variable store region isn't formatted. Usually this is
-done in the EDK2 payload when no valid firmware volume could be found.
-It might be useful to do this offline or in coreboot to have a working
-option store on the first boot or when it was corrupted.
-
-Performance improvements:
-Right now the code always checks if the firmware volume header is valid.
-This could be optimised by caching the test result in heap. For write
-operations it would be good to cache the end of the variable store in
-the heap as well, instead of walking the whole store. For read
-operations caching the entire store could be considered.
-
-Reclaiming memory:
-The EFI variable store is append write only. To update an existing
-variable, first a new is written to the end of the store and then the
-previous is marked invalid. This only works on PNOR flash that allow to
-clear set bits, but keep cleared bits state.
-This mechanisms allows a fault tolerant write, but it also requires to
-"clean" the variable store from time to time. This cleaning would remove
-variables that have been marked "deleted".
-Such cleaning mechanism in turn must be fault tolerant and thus must use
-a second partition in the SPI flash as backup/working region.
-For now, cleaning is done in coreboot.
-
-Fault checking:
-The driver should check if a previous write was successful and if not
-mark variables as deleted on the next operation.
-
-
-### drivers/ocp/ewl: Add EWL driver for EWL type 3 error handling
-
-Add EWL (Enhanced Warning Log) driver which handles Intel EWL HOB
-and prints EWL type 3 primarily associated with MRC training failures.
-
-
-### Toolchain updates
-
-* Upgrade MPC from version 1.2.1 to 1.3.1
-* Upgrade MPFR from version 4.1.1 to 4.2.0
-* Upgrade CMake from version 3.25.0 to 3.26.3
-* Upgrade LLVM from version 15.0.6 to 15.0.7
-* Upgrade GCC from version 11.2.0 to 11.3.0
-* Upgrade binutils from version 2.37 to 2.40
-
-
-Additional coreboot changes
----------------------------
-
-* Remove Yabits payload. Yabits is deprecated and archived.
-* Add DDR2 support to Intel GM45 code.
-* Fix superiotool compilation issues when using musl-libc.
-* Drop the Python 2 package from the coreboot-sdk.
-* Drop the Zephyr SDK from coreboot-sdk since the packaged version
-  was quite old and wasn’t really used.
-* Add inteltool support for the Intel "Emmitsburg" PCH.
-* Work to improve cache hit percentage when rebuilding using ccache.
-* Adding Sound-Open-Firmware drivers to chromebooks to enable audio on
-  non-chrome operating systems.
-* Improve and expand ACPI generation code.
-* Fix some issues for the RISC-V code.
-* Continue upstreaming the POWER9 architecture.
-* Add documentation for SBOM (Software Bill of Materials).
-* Add SimNow console logging support for AMD.
-* Do initial work on Xeon SPR
-* CMOS defaults greater than 128 bytes long now extend to bank 1.
-
-
-New Mainboards
---------------
-
-* Asrock: B75M-ITX
-* Dell: Latitude E6400
-* Google: Aurash
-* Google: Boxy
-* Google: Constitution
-* Google: Gothrax
-* Google: Hades
-* Google: Myst
-* Google: Screebo
-* Google: Starmie
-* Google: Taranza
-* Google: Uldren
-* Google: Yavilla
-* HP: EliteBook 2170p
-* Intel: Archer City CRB
-* Intel: DQ67SW
-* Protectli: VP2420
-* Protectli: VP4630/VP4650
-* Protectli: VP4670
-* Siemens: MC EHL4
-* Siemens: MC EHL5
-* System76: lemp11
-* System76: oryp10
-* System76: oryp9
-
-
-Removed Mainboards
-------------------
-
-* Intel Icelake U DDR4/LPDDR4 RVP
-* Intel Icelake Y LPDDR4 RVP
-* Scaleway TAGADA
-
-
-Updated SoCs
-------------
-
-* Removed soc/intel/icelake
-
-
-Plans to move platform support to a branch
-------------------------------------------
-
-### Intel Quark SoC & Galileo mainboard
-
-The SoC Intel Quark is unmaintained and different efforts to revive it
-have so far failed.  The only user of this SoC ever was the Galileo
-board.
-
-Thus, to reduce the maintenance overhead for the community, support for
-the following components will be removed from the master branch and will
-be maintained on the release 4.20 branch.
-
-  * Intel Quark SoC
-  * Intel Galileo mainboard
-
-
-Statistics from the 4.19 to the 4.20 release
---------------------------------------------
-
-Total Commits: 1630
-Average Commits per day: 13.72
-Total lines added: 102592
-Average lines added per commit: 62.94
-Number of patches adding more than 100 lines: 128
-Average lines added per small commit: 37.99
-Total lines removed: 34824
-Average lines removed per commit: 21.36
-Total difference between added and removed: 67768
-Total authors: ~170
-New authors: ~35
-
-
-Significant Known and Open Issues
----------------------------------
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```

Documentation/releases/coreboot-4.21-relnotes.md

@@ -1,407 +0,0 @@
-Upcoming release - coreboot 4.21
-========================================================================
-
-The 4.21 release is scheduled for August 21st, 2023
-
-In the past quarter year, the coreboot project has gotten over 1200 new
-patches from around 140 authors, 20 of whom contributed for the first
-time.
-
-Thank you to all of our donors, the code contributors, the people who
-take time to review all of those patches and all of the people who care
-about the coreboot project. There have been a number of new companies
-starting to use coreboot recently, and we appreciate all of the
-contributions and support.
-
-### Upcoming switch from master branch to main branch
-
-Historically, the initial branch that was created in a new git
-repository was named ‘master’. In line with many other projects,
-coreboot has decided to switch away from this name and use the name
-‘main’ instead. You can read about the initial reasoning on the SFC’s
-website: https://sfconservancy.org/news/2020/jun/23/gitbranchname/
-
-At some point before the 4.22 release, coreboot will be switching from
-the master branch to the main branch. This shouldn’t be a difficult
-change for most people, as everyone will just have to rebase on top of
-a different branch name.
-
-We’ve already created the main branch, and it is currently synced with
-the master branch. Please update any scripts to point to main instead
-of master.
-
-At the point of the changeover, we will move all patches in gerrit to
-the main branch and disable pushes to the master branch.
-
-After the switch, we will sync the main branch to the master branch for
-a while to give people a little more time to update any scripts that
-are currently pointed at the master branch. Note that this update will
-probably be done just once per day, and the frequency of updates will
-be decreased over time. We plan to stop updating the master branch
-following the 4.22 release.
-
-Significant or interesting changes
-----------------------------------
-
-### lib: Support localized text of memory_training_desc in ux_locales.c
-
-Most of the text in coreboot is for logging, and does not use
-localization. There are however, some bits of text that can be
-presented to the user, and this patch supplies a method to localize
-them.
-
-To support the localized text, we need to get the locale id by vboot
-APIs and read raw string content file: preram_locales located at either
-RO or RW.
-
-The preram_locales file follows the format:
-
-    [PRERAM_LOCALES_VERSION_BYTE (\x01)]
-    [string_name_1] [\x00]
-    [locale_id_1] [\x00] [localized_string_1] [\x00]
-    [locale_id_2] [\x00] [localized_string_2] …
-    [\x01]
-    [string_name_2] [\x00] ...
-
-This code will search for the correct localized string that its string
-name is `memory_training_desc` and its locale ID matches the ID vb2api
-returns. If no valid string found, we will try to display in English
-(locale ID 0).
-
-
-### Improved the bootsplash support
-
-The JPEG decoder, that was added many years ago to display a bootsplash
-in coreboot, has a few quirks. People used to do some voodoo with GIMP
-to convert images to the right format, but we can also achieve the same
-with ImageMagick's `convert`. The currently known constraints are:
-
-* The framebuffer's color format is ignored,
-* only YCC 4:2:0 color sampling is supported, and
-* width and height have to be a multiple of 16 pixels.
-
-Beside that, we can only display the bootsplash if it completely fits
-into the framebuffer. As the latter's size is often decided at runtime,
-we can't do much more than offering an option to set a specific size.
-
-The build system has been extended so that the necessary adjustments to
-the picture can be done by it and several options have been added to
-Kconfig.
-
-
-### libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
-
-This is a complete rewrite of the UHCI root-hub driver, based on the
-xHCI one. We are doing things by the book as far as possible. One
-special case is uhci_rh_reset_port() which does the reset sequencing
-that usually the hardware would do.
-
-This abandons some quirks of the old driver:
-* Ports are not disabled/re-enabled for every attachment anymore.
-* We solely rely on the Connect Status Change bit to track changes.
-* Further status changes are now deferred to the next polling round.
-
-
-### linux_trampoline: Handle coreboot framebuffer & 64-bit addresses
-
-Translate the coreboot framebuffer info from coreboot tables to the
-Linux zero page.
-
-To support full 64-bit addresses, there is a new field `ext_lfb_base`
-since Linux 4.1. It is unclear, however, how a loader is supposed to
-know if the kernel is compatible with this. Filling these previously
-reserved bits doesn't hurt, but an old kernel would probably ignore
-them and not know that it's handling a clipped, invalid address. So we
-play safe, and only allow 64-bit addresses for kernels after the 2.15
-version bump of the boot protocol.
-
-
-### arch/x86: Don't allow hw floating point operations
-
-Even though coreboot does not allow floating point operations, some
-compilers like clang generate code using hw floating point registers,
-e.g. SSE %XMMx registers on 64bit code by default. Floating point
-operations need to be enabled in hardware for this to work (CR4). Also
-in SMM we explicitly need to save and restore floating point registers
-for this reason. If we instruct the compiler to not generate code with
-FPU ops, this simplifies our code as we can skip that step.
-
-With clang this reduces the binary size a bit. For instance ramstage
-for emulation/qemu-q35 drops by 4 kB from from 216600 bytes
-decompressed to 212768 bytes.
-
-Since we now explicitly compile both ramstage and smihandler code
-without floating point operations and associated registers we don't
-need to save/restore floating point registers in SMM.
-
-The EFER MSR is in the SMM save state and RSM properly restores it.
-Returning to 32bit mode was only done so that fxsave was done in the
-same mode as fxrstor, but this is no longer done.
-
-
-### Caching of PCIe 5.0 HSPHY firmware in SPI flash
-
-This adds the ability to cache the PCIe 5.0 HSPHY firmware in the SPI
-flash. A new flashmap region is created for that purpose. The goal of
-caching is to reduce the dependency on the CSME (Converged Security and
-Management Engine) and the HECI (Host Embedded Controller Interface) IP
-LOAD command which may fail when the CSME is disabled, e.g. soft
-disabled by HECI command or HAP (High Assurance Platform mode). By
-caching that firmware, this allows the PCIe 5.0 root ports to keep
-functioning even if CSME/HECI is not functional.
-
-
-### Extracting of TPM logs using cbmem tool
-
-CBMEM can contain logs in different forms (at most one is present):
- * coreboot-specific format (CBMEM_ID_TPM_CB_LOG exported as
-   LB_TAG_TPM_CB_LOG)
- * TPM1.2 format (CBMEM_ID_TCPA_TCG_LOG)
- * TPM2 format (CBMEM_ID_TPM2_TCG_LOG)
-
-The last two follow specifications by Trusted Computing Group, but
-until now cbmem couldn't print them.
-
-These changes make the cbmem utility check for existence of TPM1.2/TPM2
-logs in CBMEM and add code necessary for parsing and printing of their
-entries.
-
-`cbmem -L` for CONFIG_TPM1=y case
-
-```
-TCPA log:
-	Specification: 1.21
-	Platform class: PC Client
-TCPA log entry 1:
-	PCR: 2
-	Event type: Action
-	Digest: 5622416ea417186aa1ac32b32c527ac09009fb5e
-	Event data: FMAP: FMAP
-```
-
-`cbmem -L` for CONFIG_TPM2=y case
-
-```
-TPM2 log:
-	Specification: 2.00
-	Platform class: PC Client
-TPM2 log entry 1:
-	PCR: 2
-	Event type: Action
-	Digests:
-		 SHA256: 68d27f08cb261463a6d004524333ac5db1a3c2166721785a6061327b6538657c
-	Event data: FMAP: FMAP
-```
-
-
-### soc/amd: read domain resource window configuration from hardware
-
-Read the MMIO and IO decode windows for the PCI root complex and the
-PCI bus number range decoded to the PCI root complex from the data
-fabric registers and pass the information to the resource allocator so
-it has the correct constraints to do its job. Also generate the
-corresponding ACPI resource producers in the SSDT so that the OS knows
-about this too. This is required for the upcoming USB 4 support.
-
-
-Additional coreboot changes
----------------------------
-
-* Added SPDX headers to more files to help automated license checking.
-  The linter has been enabled to check the Makefiles as well.
-* Cleaned up Kconfig files and source code.
-* Enabled acpigen to generate tables for SPCR (Serial Port Console
-  Redirection) and GTDT (Generic Timer Description Table).
-* The resource allocation above the 4GiB boundary has been improved.
-* Most of the code has been adjusted to make use of C99 flexible arrays
-  instead of one-element or zero-length arrays.
-* Additional Dockerfiles based on Arch and Alpine Linux have been added
-  to build-test with alternate build environments, including musl-libc.
-  They are very basic at the moment and not equal to the coreboot-sdk.
-  They will be extended in the future.
-* Added support for ITE IT8784E to superiotool.
-* Added support for Intel 700 chipset series to inteltool and a build
-  issue with musl–libc has been fixed.
-* Added support for Intel 800 chipset series to ifdtool.
-* The coreboot-sdk container has been extended so that it allows
-  extracting the MRC binary from Haswell-based ChromeOS firmware images.
-* From now on POST code preprocessor macros should have a POSTCODE
-  prefix following the name of the POST code.
-* The NASM compiler provided by the coreboot toolchain wasn’t properly
-  integrated into xcompile and thus it wasn’t used by the build system.
-  Instead, it was required to install NASM on the host in order to use
-  it. This has been fixed.
-* The time measurement done in abuild got improved and also an issue
-  has been fixed when the variant name contains hyphens.
-* The RISC-V code was enabled to build with Clang.
-* Initial work has been done to transform Camelcase options to
-  Snakecase.
-* The buildgcc script is now able to just fetch the tarballs if desired,
-  which is needed for reproducible build environments for example.
-
-
-
-Changes to external resources
------------------------------
-
-### Toolchain
-
-* binutils
-  * Added binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch
-* Upgrade IASL from 20221020 to 20230628
-* Upgrade LLVM from 15.0.7 to 16.0.6
-* Upgrade NASM from 2.15.05 to 2.16.01
-  * Added nasm-2.16.01_handle_warning_files_while_building_in_a_directory.patch
-* Upgrade CMake from 3.26.3 to 3.26.4
-* Upgrade GCC from 11.3.0 to 11.4.0
-  * Added gcc-11.4.0_rv32iafc.patch
-
-
-### Git submodule pointers
-
-#### /3rdparty
-* amd_blobs: Update from commit id 1cd6ea5cc5 to 6a1e1457af (5 commits)
-* arm-trusted-firmware: Update from commit id 4c985e8674 to 37366af8d4
-(851 commits)
-* blobs: Update from commit id 01ba15667f to a8db7dfe82 (14 commits)
-* fsp: Update from commit id 6f2f17f3d3 to 3beceb01f9 (24 commits)
-* intel-microcode: Update from commit id 2be47edc99 to 6f36ebde45 (5
-commits)
-* libgfxinit: Update from commit id 066e52eeaa to a4be8a21b0 (18
-commits)
-* libhwbase: Update from commit id 8be5a82b85 to 584629b9f4 (2 commits)
-* qc_blobs: Update from commit id 33cc4f2fd8 to a252198ec6 (4 commits)
-* vboot: Update from commit id 35f50c3154 to 0c11187c75 (83 commits)
-
-#### /util
-* goswid: Update from commit id bdd55e4202 to 567a1c99b0 (5 commits)
-* nvidia/cbootimage: Update from commit id 65a6d94dd5 to 80c499ebbe (1
-commit)
-
-
-### External payloads
-
-* Update the depthcharge payload from commit ID 902681db13 to c48613a71c
-* Upgrade EDK2-MrChromebox from version 202304 to version 202306
-* Upgrade SeaBIOS from version 1.16.1 to version 1.16.2
-* Update tint from version 0.05 to version 0.07
-* Update U-Boot from version 2021.07 to version v2023.07
-
-
-Added mainboards:
------------------
-* ByteDance ByteDance bd_egs
-* Google: Craaskov
-* Google: Expresso
-* Google: Karis
-* Google: Karis4ES
-* Google: Pirrha
-* Google: Ponyta
-* Google: Screebo4ES
-* Google: Ovis
-* Google: Ovis4ES
-* Google: Rex EC ISH
-* Google: Rex4ES
-* HP Compaq Elite 8300 USDT
-* HP EliteBook 820 G2
-* IBM SBP1
-* Intel Raptorlake silicon with Alderlake-P RVP
-* Inventec Transformers
-* MSI PRO Z790-P (WIFI)
-* MSI PRO Z790-P (WIFI) DDR4
-* Star Labs Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
-* System76 addw3
-* System76 bonw15
-* System76 darp9
-* System76 galp7
-* System76 gaze17 3050
-* System76 gaze17 3060-b
-* System76 gaze18
-* System76 lemp12
-* System76 oryp11
-* System76 serw13
-
-
-Removed Mainboards
-------------------
-
-* Intel Galileo
-
-
-Updated SoCs
-------------
-
-* Removed src/soc/intel/quark
-
-
-Statistics from the 4.20 to the 4.21 release
---------------------------------------------
-
-* Total Commits: 1252
-* Average Commits per day: 12.59
-* Total lines added: 317734
-* Average lines added per commit: 253.78
-* Number of patches adding more than 100 lines: 86
-* Average lines added per small commit: 36.22
-* Total lines removed: 261063
-* Average lines removed per commit: 208.52
-* Total difference between added and removed: 56671
-
-* Total authors: 143
-* New authors: 21
-
-
-Significant Known and Open Issues
----------------------------------
-
-
-Issues from the coreboot bugtracker: https://ticket.coreboot.org/
-```eval_rst
-+-----+-----------------------------------------------------------------+
-| #   | Subject                                                         |
-+=====+=================================================================+
-| 499 | edk2 boot fails with RESOURCE_ALLOCATION_TOP_DOWN enabled       |
-+-----+-----------------------------------------------------------------+
-| 495 | Stoney chromebooks not booting PSPSecureOS                      |
-+-----+-----------------------------------------------------------------+
-| 478 | X200 booting Linux takes a long time with TSC                   |
-+-----+-----------------------------------------------------------------+
-| 474 | X200s crashes after graphic init with 8GB RAM                   |
-+-----+-----------------------------------------------------------------+
-| 457 | Haswell (t440p): CAR mem region conflicts with CBFS_SIZE > 8mb  |
-+-----+-----------------------------------------------------------------+
-| 453 | Intel HDMI / DP Audio device not showing up after libgfxinit    |
-+-----+-----------------------------------------------------------------+
-| 449 | ThinkPad T440p fail to start, continuous beeping & LED blinking |
-+-----+-----------------------------------------------------------------+
-| 448 | Thinkpad T440P ACPI Battery Value Issues                        |
-+-----+-----------------------------------------------------------------+
-| 446 | Optiplex 9010 No Post                                           |
-+-----+-----------------------------------------------------------------+
-| 439 | Lenovo X201 Turbo Boost not working (stuck on 2,4GHz)           |
-+-----+-----------------------------------------------------------------+
-| 427 | x200: Two battery charging issues                               |
-+-----+-----------------------------------------------------------------+
-| 414 | X9SAE-V: No USB keyboard init on SeaBIOS using Radeon RX 6800XT |
-+-----+-----------------------------------------------------------------+
-| 412 | x230 reboots on suspend                                         |
-+-----+-----------------------------------------------------------------+
-| 393 | T500 restarts rather than waking up from suspend                |
-+-----+-----------------------------------------------------------------+
-| 350 | I225 PCIe device not detected on Harcuvar                       |
-+-----+-----------------------------------------------------------------+
-| 327 | OperationRegion (OPRG, SystemMemory, ASLS, 0x2000) causes BSOD  |
-+-----+-----------------------------------------------------------------+
-```
-
-
-coreboot Links and Contact Information
---------------------------------------
-
-* Main Web site: https://www.coreboot.org
-* IRC: https://web.libera.chat/#coreboot
-* Downloads: https://coreboot.org/downloads.html
-* Source control: https://review.coreboot.org
-* Documentation: https://doc.coreboot.org
-* Issue tracker: https://ticket.coreboot.org/projects/coreboot
-* Donations: https://coreboot.org/donate.html

Documentation/releases/coreboot-4.22-relnotes.md

@@ -1,48 +0,0 @@
-Upcoming release - coreboot 4.22
-========================================================================
-
-The 4.22 release is planned for mid-November, 2023
-
-Update this document with changes that should be in the release notes.
-
-* Please use Markdown.
-* See the past few release notes for the general format.
-* The chip and board additions and removals will be updated right
-  before the release, so those do not need to be added.
-* Note that all changes before the release are done are marked upcoming.
-  A final version of the notes are done after the release.
-
-### Significant or interesting changes
-
-* Add changes that need a full description here
-
-* This section should have full descriptions and can or should have
-  a link to the referenced commits.
-
-### Toolchain updates
-
-* To be filled in immediately before the release by the release team
-
-### Additional coreboot changes
-
-The following are changes across a number of patches, or changes worth
-noting, but not needing a full description.
-
-* Changes that only need a line or two of description go here.
-
-### Platform Updates
-
-* To be filled in immediately before the release by the release team
-
-### Plans to move platform support to a branch
-
-* Section to be filled in or removed after discussion
-
-### Statistics from the 4.21 to the 4.22 release
-
-* To be filled in immediately before the release by the release team
-
-
-### Significant Known and Open Issues
-
-* To be filled in immediately before the release by the release team

Documentation/releases/index.md

@@ -3,7 +3,7 @@
 ## Upcoming release
 
 Please add to the release notes as changes are added:
-* [4.22 - November 2023](coreboot-4.22-relnotes.md)
+* [4.20 - April 2023](coreboot-4.20-relnotes.md)
 
 The [checklist] contains instructions to ensure that a release covers all
 important things and provides a reliable format for tarballs, branch
@@ -15,27 +15,25 @@ important is taken care of.
 
 ## Previous releases
 
-* [4.21   - August 2023](coreboot-4.21-relnotes.md)
-* [4.20.1 - May 2023](coreboot-4.20.1-relnotes.md)
-* [4.19   - January 2023](coreboot-4.19-relnotes.md)
-* [4.18   - October 2022](coreboot-4.18-relnotes.md)
-* [4.17   - May 2022](coreboot-4.17-relnotes.md)
-* [4.16   - February 2022](coreboot-4.16-relnotes.md)
-* [4.15   - November 2021](coreboot-4.15-relnotes.md)
-* [4.14   - May 2021](coreboot-4.14-relnotes.md)
-* [4.13   - November 2020](coreboot-4.13-relnotes.md)
-* [4.12   - May 2020](coreboot-4.12-relnotes.md)
-* [4.11   - November 2019](coreboot-4.11-relnotes.md)
-* [4.10   - July 2019](coreboot-4.10-relnotes.md)
-* [4.9    - December 2018](coreboot-4.9-relnotes.md)
-* [4.8.1  - May 2018](coreboot-4.8.1-relnotes.md)
-* [4.7    - January 2018](coreboot-4.7-relnotes.md)
-* [4.6    - April 2017](coreboot-4.6-relnotes.md)
-* [4.5    - October 2016](coreboot-4.5-relnotes.md)
-* [4.4    - May 2016](coreboot-4.4-relnotes.md)
-* [4.3    - January 2016](coreboot-4.3-relnotes.md)
-* [4.2    - October 2015](coreboot-4.2-relnotes.md)
-* [4.1    - July 2015](coreboot-4.1-relnotes.md)
+* [4.19 - January 2023](coreboot-4.19-relnotes.md)
+* [4.18 - October 2022](coreboot-4.18-relnotes.md)
+* [4.17 - May 2022](coreboot-4.17-relnotes.md)
+* [4.16 - February 2022](coreboot-4.16-relnotes.md)
+* [4.15 - November 2021](coreboot-4.15-relnotes.md)
+* [4.14 - May 2021](coreboot-4.14-relnotes.md)
+* [4.13 - November 2020](coreboot-4.13-relnotes.md)
+* [4.12 - May 2020](coreboot-4.12-relnotes.md)
+* [4.11 - November 2019](coreboot-4.11-relnotes.md)
+* [4.10 - July 2019](coreboot-4.10-relnotes.md)
+* [4.9 - December 2018](coreboot-4.9-relnotes.md)
+* [4.8 - May 2018](coreboot-4.8.1-relnotes.md)
+* [4.7 - January 2018](coreboot-4.7-relnotes.md)
+* [4.6 - April 2017](coreboot-4.6-relnotes.md)
+* [4.5 - October 2016](coreboot-4.5-relnotes.md)
+* [4.4 - May 2016](coreboot-4.4-relnotes.md)
+* [4.3 - January 2016](coreboot-4.3-relnotes.md)
+* [4.2 - October 2015](coreboot-4.2-relnotes.md)
+* [4.1 - July 2015](coreboot-4.1-relnotes.md)
 
 
 [checklist]: checklist.md

Documentation/sbom/sbom.md

@@ -1,156 +0,0 @@
-# Software Bill of Materials (SBOM)
-
-SBOM is a collection of information of each software component
-you are supplying/building. Similar to a package manager on Linux
-based systems, it holds information of as many software parts as
-possible. This information can be a version, name of the software, URL,
-license information and more. A SBOM can be saved in various formats.
-In coreboot it's saved as "uSWID" file. uSWID is not a standard or
-specification but it doesn't need to be, since it's basically just an
-array/list of CoSWID (Concise Software Identification) files which in
-turn are specified by a RFC specification. CoSWID files are saved in a
-CBOR format. CBOR is like JSON if JSON were a binary format. Similar
-to a package manager the CoSWID format can link multiple softwares
-together. For example on most modern Intel systems FSP is included as
-a dependency of coreboot. That kind of relationship between software
-components (among others) can be expressed in an uSWID file. That makes
-firmware/software much more transparent. One could for example create a
-software that takes a coreboot firmware image as input and
-automatically creates a graph with all software components the coreboot
-image contains and their relationship to each other.
-
-
-## SWID/CoSWID
-
-SWID is a standard hidden behind an ISO paywall.
-It generally identifies/describes Software components. Since SWID files
-are written in XML, they can get too large for devices with network and
-storage constraints. CoSWID is basically SWID but in CBOR binary
-format, which makes it far smaller compared to its big brother. Also,
-CoSWID is a RFC specification (so publicly accessible). Therefore
-CoSWID is the standard used in coreboot SBOM. But one CoSWID file/tag
-can only describe one single software, but since software is usually
-composed of multiple parts (especially in firmware with many binary
-blobs) uSWID was born as a container format to hold multiple CoSWID
-files. It also has a magic value, that makes software capable of
-extracting uSWID/CoSWID data without the need to understand the
-underlying format of the binary (in coreboot it's the CBFS and in EDK2
-it's the COFF). To get a simple overview of how a SWID/CoSWID file
-looks like, just take a look at the various "templates" in src/sbom/.
-There are of course other SBOM specifications out there, but most of
-them are rather blown up and don't support a binary format at all.
-
-
-## coreboot implementation
-
-Quick overview of how things are generated:
-
-![Generation of an SBOM File in coreboot][sbom_generation]
-
-[sbom_generation]: sbom_generation.svg
-
-After all SBOM data has been fetched from all the software components,
-the 'goswid' tool links them all together into one sbom.uswid file.
-Therefore the goswid tool is basically a linker that takes multiple
-CoSWID/SWID files and converts them into one uSWID file. Although the
-image shows only Files in JSON format it is also possible to supply
-them in XML or CBOR format.
-
-The final SBOM file is located inside the CBFS.
-For each software component in coreboot SBOM, there is an option in
-Kconfig (usually called `CONFIG_INCLUDE_[software-name]_SBOM`) to either
-include or not include SBOM metadata for the specified software.
-Furthermore there is a `CONFIG_SBOM_[software-name]_PATH` option which
-contains a path to a SWID/CoSWID file in a format of choice
-(being either JSON, XML or CBOR). `CONFIG_SBOM_[software-name]_PATH`
-option usually defaults to a very generic CoSWID file in JSON format
-(which are stored in src/sbom/). That at least gives minimal
-information like the name of the software and maybe a version.
-But it is always preferred, that the `CONFIG_SBOM_[software-name]_PATH`
-is set to a custom CoSWID/SWID file that contains much more information
-(like version/commit-hash, license, URL, dependencies, ...).
-Therefore using the defaults is by any means to be avoided, since they
-hold very little information or even worse wrong information.
-Furthermore some of these Kconfig options have a suboption
-(usually called `CONFIG_SBOM_[software-name]_GENERATE`) to generate
-some basic SBOM data for the specified software component, in order to
-get at least some bit of information about it by analyzing the binary
-(for binary blobs) or querying information via git (for open source
-projects). This is for example currently done for all payloads. For
-each payload the commit hash used in the build is taken and put into
-the SBOM file. For open-source projects (like all payloads) crucial
-information like the current commit-hash of the payload can easily be
-put into the SBOM file. Extracting information out of binary blobs is a
-bit trickier for obvious reasons. For closed source binary blobs it is
-therefore recommended that vendors and software-engineers create a SBOM
-file as part of their build process and add a path to that SBOM file
-via Kconfig options in coreboot (`CONFIG_SBOM_[software-name]_PATH`).
-That way the final SBOM has much more useful and correct data.
-
-
-## Build coreboot with SBOM
-
-Directly under the 'General setup' Kconfig menu is a
-'Software Bill of Materials (SBOM)' submenu where all options are to
-enable/disable SBOM integration in to the corebeoot build.
-Therefore one can just enable/disable them via `make menuconfig`.
-
-
-## What to do as Developer of a binary blob (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID File in either JSON, XML or CBOR Format
-as part of your software build process
-
-2. Supply that generated File along with your binary blob (preferably
-not inside the blob)
-
-3. To build coreboot: Add `CONFIG_SBOM_[software-name]_PATH` to your
-defconfig pointing to your [software-name] generated File.
-
-
-## What to do as Developer of an open source project (which is used in coreboot)
-
-1. Generate a SWID/CoSWID/uSWID file in either JSON, XML or CBOR format
-as part of your software's build process. For example in form of a
-Makefile target.
-
-2. Change src/sbom/Makefile.inc (in order to know where to find the
-CoSWID/SWID/uSWID file) as well as the Makefile in coreboot which
-builds said software. For example for GRUB2 that could mean to add a
-Makefile target in payloads/external/GRUB2/Makefile.
-
-
-## Problems
-
-What to do if the binary blob that is included in coreboot's build
-already has a SBOM file embedded in the binary? One could supply the
-path of the software binary itself (e.g. me.bin) as SBOM file path for
-the software in question. Which would basically mean to set
-`CONFIG_SBOM_[software-name]_PATH=/path/to/me.bin`. This is possible
-since the 'goswid' tooling is able to extract uSWID information out of
-an unknown binary format because of uSWIDs magic value. But even if
-coreboot can extract the uSWID data there is still the question of what
-to do next. One can do one of the following:
-
-  - Do not include the Software's SBOM data in the final SBOM of
-    coreboot. Data would not be duplicated, but therefore not included
-    in coreboot SBOM file.
-
-  - Extract the uSWID/CoSWID information from the binary and also
-    include it in the coreboot SBOM. That would mean, that SBOM data
-    is duplicated.
-
-The first solution should in general be preferred, since its no
-problem if SBOM data is located at multiple locations/binaries if they
-don't have a direct dependency on each other. It would be good if
-software that cannot run on its own only supplies the SBOM data along
-with it as kind of extra file instead of embedded in an unknown binary
-blob. coreboot can then just take it and include it in its own SBOM
-file. If on the other hand the binary can function on its own (e.g. EC
-or BMC binary), it is generally preferred that the software supplies
-its own SBOM data and coreboot just simply doesn't include it in its
-own SBOM file. That would make a more or less clear distinction and
-avoids duplication in case the BMC or EC is updated (without updating
-coreboot). The distinction is not always easy and this problem is
-currently not considered in the implementation, since none of the
-software components currently create a SBOM file on their own.

Documentation/sbom/sbom_generation.plantuml

@@ -1,61 +0,0 @@
-@startuml
-
-map "src/sbom/compiler-gcc.json" as gcc {
-    software-name => GCC
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/intel-me.json" as me {
-    software-name => Intel Mangement Engine
-    ... => ...
-}
-map "src/sbom/intel-microcode.json" as ucode {
-    software-name => Intel Microcode
-    ... => ...
-}
-map "src/sbom/generic-ec.json" as ec {
-    software-name => ecxyz
-    ... => ...
-}
-map "src/sbom/generic-fsp.json" as fsp {
-    software-name => Firmware Support Package
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/payload-[...].json" as payload {
-    software-name => ...
-    version => x.y.z
-    ... => ...
-}
-map "src/sbom/coreboot.json" as coreboot {
-    software-name => coreboot
-    version => x.y.z
-    url => coreboot.rocks
-    ... => ...
-}
-object "sbom.uswid" as uswid {
-    merged SBOM data in binary format
-}
-object goswid {
-    # ./goswid
-        --compiler gcc.json
-        --parent coreboot.json
-        --requires fsp.json,payload.json
-        intel-me.json
-        intel-ec.json
-        intel-ucode.json
-        --output sbom.uswid
-}
-
-left to right direction
-gcc --> goswid
-me --> goswid
-ucode --> goswid
-goswid <-- ec
-goswid <-- fsp
-goswid <-- payload
-
-coreboot -up> goswid
-goswid -up> uswid
-
-@enduml

Documentation/security/vboot/list_vboot.md

@@ -36,37 +36,16 @@
 - Agah
 - Anahera
 - Anahera4ES
-- Aurash
-- Banshee
 - Brask
 - Brya 0
-- Craask
-- Craaskov
-- Constitution
-- Crota
 - Felwinter
-- Gaelin
 - Gimble
 - Gimble4ES
-- Gladios
-- Gothrax
-- Hades
 - Kano
-- Kinox
-- Kuldax
-- Joxer
-- Lisbon
-- Marasov
-- Mithrax
-- Moli
 - Nivviks
 - Nereid
-- Omnigul
-- Osiris
-- Pirrha
 - Primus
 - Primus4ES
-- Pujjo
 - Redrix
 - Redrix4ES
 - Skolas
@@ -74,13 +53,26 @@
 - Taeko
 - Taeko4ES
 - Taniks
-- Uldren
 - Vell
 - Volmar
+- Banshee
+- Crota
+- Moli
+- Kinox
+- Craask
+- Osiris
+- Mithrax
+- Kuldax
+- Joxer
+- Pujjo
 - Xivu
+- Gaelin
 - Yaviks
-- Yavilla
+- Lisbon
 - Zydron
+- Gladios
+- Marasov
+- Omnigul
 - Butterfly (HP Pavilion Chromebook 14)
 - Cherry
 - Dojo
@@ -88,11 +80,9 @@
 - Kingler
 - Steelix
 - Voltorb
-- Ponyta
 - Krabby
 - Tentacruel
 - Magikarp
-- Starmie
 - Banon (Acer Chromebook 15 (CB3-532))
 - Celes (Samsung Chromebook 3)
 - Cyan (Acer Chromebook R11 (C738T))
@@ -180,7 +170,6 @@
 - Pico
 - Link (Google Chromebook Pixel (2013))
 - Mistral
-- Myst
 - Nyan
 - Nyan Big (Acer Chromebook 13 (CB5-311))
 - Nyan Blaze (HP Chromebook 14 G3)
@@ -214,14 +203,6 @@
 - Snappy (HP Chromebook x360 11 G1 EE)
 - Coral
 - Rex 0
-- Screebo
-- Screebo4ES
-- Karis
-- Karis4ES
-- Rex EC ISH
-- Ovis
-- Ovis4ES
-- Rex4ES
 - Arcada (Latitude 5300 2-in-1 Chromebook Enterprise)
 - Sarien (Dell Latitude 5400 Chromebook Enterprise)
 - Skyrim
@@ -256,25 +237,25 @@
 - Veyron_Speedy (ASUS C201 Chromebook)
 - Veyron_Mickey (Asus Chromebit CS10)
 - Veyron_Rialto
-- Chronicler (FMV Chromebook 14F)
-- Collis (Asus Chromebook Flip CX3)
-- Copano (ASUS Chromebook Flip CX5400)
 - Delbin (ASUS Chromebook Flip CX5)
-- Drobit (ASUS Chromebook CX9400)
-- Eldrid (HP Chromebook x360 14c)
-- Elemi (HP Pro c640 G2 Chromebook)
+- Eldrid
 - Halvor
-- Lindar (Lenovo 5i-14/Slim 5 Chromebook)
+- Lindar
 - Malefor
 - Terrador
 - Todor
 - Trondo
-- Voema (Acer Chromebook Spin 514)
-- Volet (Acer Chromebook 515)
 - Volteer
 - Volteer2
 - Volteer2_Ti50
 - Voxel (Acer Chromebook Spin 713 (CP713-3W))
+- Elemi (HP Pro c640 G2 Chromebook)
+- Voema
+- Drobit (ASUS Chromebook CX9400)
+- Copano (ASUS Chromebook Flip CX5400)
+- Collis
+- Volet
+- Chronicler
 - Dalboz
 - Vilboz (Lenovo 100e/300e Gen3 AMD)
 - Ezkinil (Acer Chromebook Spin 514)
@@ -298,7 +279,6 @@
 - Alderlake-M RVP with Chrome EC
 - Alderlake-N RVP
 - Alderlake-N RVP with Chrome EC
-- Raptorlake silicon with Alderlake-P RVP
 - Raptorlake silicon with Alderlake-P RVP and Chrome EC
 - Basking Ridge CRB
 - Coffeelake U SO-DIMM DDR4 RVP
@@ -307,6 +287,8 @@
 - Coffeelake S U-DIMM DDR4 RVP8
 - Cometlake U DDR4 RVP
 - Elkhartlake LPDDR4x CRB
+- Emerald Lake 2 CRB
+- Galileo
 - Glkrvp
 - Jasperlake DDR4/LPDDR4 RVP
 - Jasperlake DDR4/LPDDR4 RVP with Chrome EC
@@ -317,7 +299,6 @@
 - Kunimitsu
 - Meteorlake-P RVP
 - Meteorlake-P RVP with Chrome EC
-- Meteorlake-P RVP with Microchip EC
 - shadowmountain
 - Strago
 - Tigerlake UP3 RVP
@@ -358,17 +339,10 @@
 ## MSI
 - PRO Z690-A (WIFI) DDR4
 - PRO Z690-A (WIFI)
-- PRO Z790-P (WIFI) DDR4
-- PRO Z790-P (WIFI)
 
 ## OpenCellular
 - Elgon (GBCv2)
 
-## Protectli
-- VP4630/VP4650
-- VP4670
-- VP2420
-
 ## SAMSUNG
 - Lumpy
 - Stumpy
@@ -385,11 +359,6 @@
 ## Star Labs
 - Star Labs Lite Mk III (N5000)
 - Star Labs Lite Mk IV (N5030)
-- Star Labs LabTop Mk III (i7-8550u)
-- Star Labs LabTop Mk IV (i3-10110U and i7-10710U)
-- Star Labs StarBook Mk V (i3-1115G4 and i7-1165G7)
-- Star Labs StarBook Mk VI (i3-1220P and i7-1260P)
-- Star Labs StarBook Mk VI (i3-1315U and i7-1360P)
 
 ## Supermicro
 - X11SSH-TF

Documentation/security/vboot/measured_boot.md

@@ -1,52 +1,16 @@
 # Measured Boot
-Measured boot feature was initially implemented as an extension of Google
-Verified Boot. However, the two features were decoupled since then and use of
-measured boot no longer requires enabling vboot.
-
-In most cases TPM eventlog is initialized during bootblock before TPM gets set
-up, hence digests are not measured into TPM immediately, but are only cached in
-the event log. Later, as part of TPM setup, the cached events are applied onto
-TPM device. The behaviour is different if TPM_MEASURED_BOOT_INIT_BOOTBLOCK
-kconfig is set, which moves TPM initialization into bootblock.
-
-## SRTM
-A measured-based trust chain is one that begins with an initial entity that
-takes the first measurement, referred to as the "Core Root of Trust for
-Measurement" (CRTM), before control is granted to the measured entity. This
-process of measurement and then passing control is referred to as a transitive
-trust. When the CRTM can only ever be executed once during the power life-cycle
-of the system, it is referred to as a "Static CRTM" (S-CRTM). Thus the trust
-chain constructed from the S-CRTM is referred to as the Static Root of Trust for
-Measurement (SRTM) trust chain. The theory is that as long as a proper
-transitive trust is conducted as more code is allowed to execute, a trustworthy
-record showing the provenance of the executing system may be provided to
-establish the trustworthiness of the system.
+coreboot measured boot is implemented as Google Verified Boot extension. This
+means in order to use it, vboot needs to be available for your platform. The
+goal of this implementation is to implement an easy to understand and
+transparent measured boot mechanism.
 
 ## IBB/CRTM
-The "Initial Boot Block" (IBB) is a one-time executed code block loaded at the
-reset vector. Under measured boot mode, the IBB measures itself before measuring
-the next code block making it an S-CRTM for the measured boot trust chain, an
-SRTM trust chain. Since the IBB measures itself and executes out of DRAM, it is
-said to have a "Root of Trust" (RoT) that is rooted in software.
-
-## S-CRTM Hardening
-To address attacks that took advantage of the IBB being self-referential with
-both the "Root of Trust for Verification" (RTV) and "Root of Trust for
-Measurement" (RTM) being rooted in software, hardening was implemented by CPU
-manufactures. This was accomplished by introducing RoT, typically an RTV, to an
-external entity provided by the manufacture that could be validated by the CPU
-at boot. Examples of this are Intel's BootGuard and AMD's Hardware Validated
-Boot (also known as Platform Secure Boot). These solutions work by having the
-IBB invoke the manufacture provided RoT as early as possible, for which the CPU
-has already validated or validates when invoked. The RoT will then validate the
-IBB, thus moving the root for the respective trust chain, typically the
-verification trust chain, into hardware.
-
-It should be noted that when Intel BootGuard was originally designed, it
-provided a measurement mode that resulted in the ACM (Authenticated Code
-Module) becoming the S-CRTM for the SRTM trust chain. Unfortunately, this was
-never deployed and thus relying on "Root of Trust for Verification" (RTV)
-signature check as the only assertion rooted in hardware.
+The "Initial Boot Block" or "Core Root of Trust for Measurement" is the first
+code block loaded at reset vector and measured by a DRTM solution.
+In case SRTM mode is active, the IBB measures itself before measuring the next
+code block. In coreboot, cbfs files which are part of the IBB are identified
+by a metadata tag. This makes it possible to have platform specific IBB
+measurements without hardcoding them.
 
 ## Known Limitations
 At the moment measuring IBB dynamically and FMAP partitions are not possible but
@@ -55,59 +19,43 @@ will be added later to the implementation.
 Also SoCs making use of VBOOT_RETURN_FROM_VERSTAGE are not able to use the
 measured boot extension because of platform constraints.
 
+## SRTM Mode
+The "Static Root of Trust for Measurement" is the easiest way doing measurements
+by measuring code before it is loaded.
+
 ### Measurements
-To construct the coreboot SRTM trust chain, the CBFS files which are part of the
-IBB, are identified by a metadata tag. This makes it possible to have platform
-specific IBB measurements without hard-coding them.
+SRTM mode measurements are done starting with the IBB as root of trust.
+Only CBFS contents are measured at the moment.
 
 #### CBFS files (stages, blobs)
 * CBFS data is measured as raw data before decompression happens.
 * CBFS header is excluded from measurements.
-* Measurements are stored in PCR 2 (by default, use PCR_SRTM kconfig option to
-  change).
+* Measurements are stored in PCR 2.
 
 #### Runtime Data
 * CBFS data which changes by external input dynamically. Never stays the same.
 * It is identified by VBOOT_MEASURED_BOOT_RUNTIME_DATA kconfig option and
-  measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default)
-  in order to avoid PCR pre-calculation issues.
+  measured into a different PCR 3 in order to avoid PCR pre-calculation issues.
 
 ![][srtm]
 
 [srtm]: srtm.png
 
-### TPM eventlog
-There are three supported formats of event logs:
-* coreboot-specific format.
-* [TPM1.2 Specification][TPM12] (chapter 11).
-* [TPM2.0 Specification][TPM20] (chapter 10).
+### TCPA eventlog
+coreboot makes use of its own TCPA log implementation. Normally the eventlog
+specification can be found via the TCG homepage:
 
-#### coreboot-specific format
-```c
-struct tcpa_entry {
-	uint32_t pcr;           /* PCR number. */
-	char digest_type[10];   /* Hash algorithm name. */
-	uint8_t digest[64];     /* Digest (tail can be unused). */
-	uint32_t digest_length; /* Number of digest bytes used. */
-	char name[50];          /* Description of what was hashed. */
-} __packed;
+[UEFI Specification](https://trustedcomputinggroup.org/resource/tcg-efi-platform-specification/)
 
-struct tcpa_table {
-	uint16_t max_entries;
-	uint16_t num_entries;
-	struct tcpa_entry entries[0];
-} __packed;
-```
+[BIOS Specification](https://www.trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf)
 
-Single hash per PCR. No magic number or any other way of recognizing it.
-Endianness isn't specified.
+Both of them are not representing firmware measurements in a generalized way.
+Therefore we have to implement our own solution.
 
-In principle can hold any hash with 512 bits or less. In practice,
-SHA-1 (for TPM1) and SHA-256 (TPM2) are used.
+We decided to provide an easy to understand TCPA log which can be read out
+from the operating system and firmware itself.
 
-Can be parsed by `cbmem`.
-
-##### Console dump format
+#### Table Format
 The first column describes the PCR index used for measurement.
 The second column is the hash of the raw data. The third column contains
 the hash algorithm used in the operation. The last column provides
@@ -115,53 +63,6 @@ information about what is measured. First the namespace from where the data
 came from, CBFS or FMAP, then the name used to look up the data
 (region or file name).
 
-#### TPM 1.2 format
-Single hash per PCR (always SHA-1). First entry serves as a header, provides
-ID and version. Always little endian. Event data describes what is being hashed
-as a NUL-terminated string instead of providing the actual raw data.
-
-Can be parsed by at least `cbmem` and Linux (exports in both text and binary
-forms).
-
-Packed data in vendor info section of the header:
-```c
-uint8_t reserved;      /* 0 */
-uint8_t version_major; /* 1 */
-uint8_t version_minor; /* 0 */
-uint32_t magic;        /* 0x31544243 ("CBT1" in LE) */
-uint16_t max_entries;
-uint16_t num_entries;
-uint32_t entry_size;
-```
-All fields are little endian.
-
-#### TPM 2.0 format
-One or more hashes per PCR, but implementation is limited to single hash (SHA-1,
-SHA-256, SHA-384 or SHA-512). First entry is overall compatible with TPM 1.2 and
-serves as a header with ID, version and number of hashing algorithms used.
-Always little endian. Event data describes what is being hashed as a
-NUL-terminated string instead of providing the actual raw data.
-
-By default SHA-1 is used for TPM1 and SHA-256 for TPM2. Other options are
-selectable via kconfig menu.
-
-Can be parsed by at least `cbmem`, Linux (exports only binary form) and
-[Skiboot][skiboot].
-
-[skiboot]: https://github.com/open-power/skiboot/
-
-Packed data in vendor info section of the header:
-```c
-uint8_t reserved;      /* 0 */
-uint8_t version_major; /* 1 */
-uint8_t version_minor; /* 0 */
-uint32_t magic;        /* 0x32544243 ("CBT2" in LE) */
-uint16_t max_entries;
-uint16_t num_entries;
-uint32_t entry_size;
-```
-All fields are little endian.
-
 #### Example:
 ```bash
 PCR-2 e8f2b57c9ec5ea06d1bbd3240a753974d4c3e7c8cd305c20a8ea26eed906dc89 SHA256 [FMAP: COREBOOT CBFS: bootblock]
@@ -186,7 +87,7 @@ PCR-2 178561f046e2adbc621b12b47d65be82756128e2a1fe5116b53ef3637da700e8 SHA256 [F
 PCR-2 091706f5fce3eb123dd9b96c15a9dcc459a694f5e5a86e7bf6064b819a8575c7 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/payload]
 ```
 
-#### Dump TPM eventlog in the OS:
+#### Dump TCPA eventlog in the OS:
 ```bash
 cbmem -L
 ```
@@ -201,64 +102,38 @@ cbfstool coreboot.rom extract -r COREBOOT -n fallback/romstage -U -f /dev/stdout
 cbfstool coreboot.rom read -n SI_ME -f /dev/stdout | sha256sum
 ```
 
-## DRTM
-Certain hardware platforms, for example those with Intel TXT or AMD-V, provide
-a mechanism to dynamically execute a CRTM, referred to as the "Dynamic
-CRTM" (D-CRTM), at any point and repeatedly during a single power life-cycle of
-a system. The trust chain constructed by this D-CRTM is referred to as the
-"Dynamic Root of Trust for Measurement" (DRTM) trust chain. On platforms with
-Intel TXT and AMD-V, the D-CRTM is the CPU itself, which is the reason for these
-capabilities being referred to as having a "Root of Trust" (RoT) rooted in
-hardware.
+## DRTM Mode
+The "Dynamic Root of Trust for Measurement" is realised by platform features
+like Intel TXT or Boot Guard. The features provide a way of loading a signed
+"Authenticated Code Module" aka signed blob. Most of these features are also
+a "Trusted Execution Environment", e.g. Intel TXT.
 
-To provide as an authority assertion and for the DRTM trust chain attestations
-to co-exist with the SRTM trust chain, the TPM provides localities, localities
-1 - 4, which restrict access to a subset of the Platform Configuration
-Registers (PCR), specifically the DRTM PCRs 17 - 22. The mechanism to assert
-authority for access to these localities is platform specific, though the
-intention was for it to be a hardware mechanism. On Intel x86 platforms this is
-controlled through communication between the CPU and the PCH to determine if
-the "Dynamic Launch" instruction, `GETSEC[SENTER]`, was executed and that the
-CPU is in SMX mode. For AMD x86 platforms, this controlled with the APU with a
-similar enforcement that the "Dynamic Launch" instruction, `SKINIT`, was
-executed.
+DRTM gives you the ability of measuring the IBB from a higher Root of Trust
+instead of doing it yourself without any hardware support.
 
-## Platform Configuration Registers
-PCRs are allocated as follows:
-* PCRs 0-15 are SRTM PCRs.
-  - PCRs 0-7 are reserved for firmware usage.
-* PCR 16 is the debug PCR.
-* PCRs 17-22 are DRTM PCRs (PCR 22 is resettable from locality 1).
-* PCR 23 is the application/user PCR and is resettable from locality 0.
+## Platform Configuration Register
+Normally PCR 0-7 are reserved for firmware usage. In coreboot we use just 4 PCR
+banks in order to store the measurements. coreboot uses the SHA-1 or SHA-256
+hash algorithm depending on the TPM specification for measurements. PCR-4 to
+PCR-7 are left empty.
 
-coreboot uses 3 or 4 PCRs in order to store the measurements. PCRs 4-7 are left
-empty.
+### PCR-0
+_Hash:_ SHA1
 
-The firmware computes the hash and passes it to TPM.
+_Description:_ Google vboot GBB flags.
 
-The bank used by the TPM depends on the selected eventlog format. CBFS hashes
-use the same algorithm as the bank. However, GBB flags are always hashed by
-SHA-1 and GBB HWID by SHA-256. This results in these hashes being truncated or
-extended with zeroes in eventlog and on passing them to TPM.
+### PCR-1
+_Hash:_ SHA1/SHA256
 
-### If CHROMEOS kconfig option is set
-vboot-specific (non-standard) PCR usage.
+_Description:_ Google vboot GBB HWID.
 
-* PCR-0 - SHA1 of Google vboot GBB flags.
-* PCR-1 - SHA256 of Google vboot GBB HWID.
-* PCR-2 - Hash of Root of Trust for Measurement which includes all stages,
-          data and blobs.
-* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache.
+### PCR-2
+_Hash:_ SHA1/SHA256
 
-### If CHROMEOS kconfig option is NOT set
-See [TPM1.2 Specification][TPM12] (section 3.3.3) and
-[TPM2.0 Specification][TPM20] (section 3.3.4) for PCR assignment information.
+_Description:_ Core Root of Trust for Measurement which includes all stages,
+data and blobs.
 
-* PCR-0 - Unused.
-* PCR-1 - SHA1 of Google vboot GBB flags, SHA256 of Google vboot GBB HWID.
-* PCR-2 - Hash of Root of Trust for Measurement which includes all stages,
-          data and blobs.
-* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache.
+### PCR-3
+_Hash:_ SHA1/SHA256
 
-[TPM12]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf
-[TPM20]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_v23_pub.pdf
+_Description:_ Runtime data like hwinfo.hex or MRC cache.

Documentation/soc/amd/psp_integration.md

@@ -127,11 +127,11 @@ implementations currently use combo tables.
 +--------------+---------------+------------------+----------------------------+
 | Address Mode | 0x0F[7:6]     | 2                | 00: x86 Physical address   |
 |              |               |                  | 01: offset from start of   |
-|              |               |                  | BIOS (flash offset)        |
+|              |               |                  |     BIOS (flash offset)    |
 |              |               |                  | 02: offset from start of   |
-|              |               |                  | directory header           |
+|              |               |                  |     directory header       |
 |              |               |                  | 03: offset from start of   |
-|              |               |                  | partition                  |
+|              |               |                  |     partition              |
 +--------------+---------------+------------------+----------------------------+
 
 ```

Documentation/soc/intel/broadwell/blobs.md

@@ -29,25 +29,6 @@ field. For boards with an Intel GbE device, a modification of `refcode` is neede
 otherwise `refcode` will disable the Intel GbE device and the OS cannot find it
 in the list of PCI devices.
 
-For the refcode binary extracted from Purism Librem 13 v1 (SHA256:
-8a919ffece61ba21664b1028b0ebbfabcd727d90c1ae2f72b48152b8774323a4,
-.program section starts at file offset 0x2040), we can see the
-following code sequence:
-
-    1e06b:       c6 43 0c 00             movb   $0x0,0xc(%ebx)
-    1e06f:       c6 83 7e 03 00 00 00    movb   $0x0,0x37e(%ebx)
-    1e076:       c6 83 70 03 00 00 01    movb   $0x1,0x370(%ebx)
-    1e07d:       66 89 43 0a             mov    %ax,0xa(%ebx)
-    1e081:       c6 83 da 01 00 00 01    movb   $0x1,0x1da(%ebx)
-    1e088:       c6 83 86 03 00 00 01    movb   $0x1,0x386(%ebx)
-
-The code at 0x1e06f sets the field that is to enable the GbE to the
-hardcoded 0 value. Change the byte at 0x1e075 (file offset 0x200b5)
-to 0x01 to make the refcode support Intel GbE:
-
-    cp refcode.elf refcode_gbe.elf
-    printf '\x01' | dd of=refcode_gbe.elf bs=1 seek=131253 count=1 conv=notrunc
-
 ## Use Broadwell SoC code for Haswell ULT boards
 
 Haswell ULT boards can use Broadwell SoC code. To use Broadwell code for Haswell ULT

Documentation/technotes/console.md

@@ -27,7 +27,7 @@ This feature has been tested on the following platforms:
 | Tested platforms                   |
 +====================================+
 | GA-H61M-S2PV + Intel Ivy Bridge    |
-+------------------------------------+
++---------------------+---------------
 ```
 
 A minimal DDR3 DIMM breakout board PCB design with only the

Documentation/tutorial/part1.md

@@ -6,19 +6,6 @@ coreboot toolchain. In same cases you will find specific instructions
 for Debian (apt-get), Fedora (dnf) and Arch Linux (pacman) based package
 management systems. Use the instructions according to your system.
 
-To test the toolchain and make sure it works, we will build coreboot for
-an emulated system provided by QEMU. This allows you to get familiar
-with the general process of configuring and building coreboot without
-needing to flash any hardware.
-
-**IMPORTANT:**
-**Do not attempt to flash the coreboot ROM built here to a real board**
-
-coreboot is board specific, so a ROM built for one board model (such as
-the QEMU emulation boards) cannot be expected to work on a different
-board. You must reconfigure coreboot for your board and rebuild the ROM
-before flashing it to a physical system.
-
 **Note: Summaries of each of the steps are at the end of the document.**
 
 
@@ -69,7 +56,7 @@ make crossgcc-riscv CPUS=$(nproc)      # build RISC-V toolchain
 ```
 
 Note that the i386 toolchain is currently used for all x86 platforms,
-including x86_64. For this tutorial we only need the i386 toolchain.
+including x86_64.
 
 Also note that you can possibly use your system toolchain, but the
 results are not reproducible, and may have issues, so this is not
@@ -116,8 +103,8 @@ select < Exit >
 
 ```Text
 select 'Payload' menu
-select 'Payload to add (SeaBIOS) --->'
-choose 'An ELF executable payload'
+select 'Add a Payload'
+choose 'An Elf executable payload'
 select 'Payload path and filename'
 enter 'payloads/coreinfo/build/coreinfo.elf'
 select < Exit >
@@ -132,26 +119,15 @@ make savedefconfig
 cat defconfig
 ```
 
-There should only be 9 lines (or 10 if you're using the system
+There should only be two lines (or 3 if you're using the system
 toolchain):
 
 ```Text
-CONFIG_CBFS_SIZE=0x00400000
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402
-CONFIG_POST_IO_PORT=0x80
 CONFIG_PAYLOAD_ELF=y
 CONFIG_PAYLOAD_FILE="payloads/coreinfo/build/coreinfo.elf"
 ```
 
-Note that this may differ depending on the revision of the coreboot
-source you are building from and should not be taken as the required
-contents of defconfig. 
-
-### Step 6 - Build coreboot
+### Step 6 - build coreboot
 
 ```Bash
 make
@@ -159,10 +135,10 @@ make
 
 At the end of the build, you should see:
 
-`Built emulation/qemu-i440fx (QEMU x86 i440fx/piix4)`
+`Build emulation/qemu-i440fx (QEMU x86 i440fx/piix4)``
 
 This means your build was successful. The output from the build is in
-the `build` directory. `build/coreboot.rom` is the full rom file.
+the build directory. build/coreboot.rom is the full rom file.
 
 
 Test the image using QEMU
@@ -171,7 +147,7 @@ Test the image using QEMU
 
 ### Step 7 - Install QEMU
 
-* Debian: `sudo apt-get install -y qemu-system`
+* Debian: `sudo apt-get install -y qemu`
 * Arch: `sudo pacman -S qemu`
 * Redhat: `sudo dnf install qemu`
 
@@ -246,19 +222,6 @@ coreinfo, a small demonstration payload that allows the user to look at
 various things such as memory and the contents of the coreboot file
 system (CBFS) - the pieces that make up the coreboot rom.
 
-Usually, the coreboot build system automatically builds the payload
-selected in the "Payload to add" menu and sets it as the default payload
-(also known as the "primary payload"). Such payloads are able to boot an
-operating system and may be able to load another payload. Although
-coreinfo can be found in the "Secondary Payloads" menu, in which case it
-would be handled automatically, it is not available as a primary payload
-since it cannot load an OS or another payload. Secondary payloads must
-be loaded from other primary or secondary payloads and will not be run
-when coreboot hands off execution after initializing hardware. Thus, to
-get coreinfo to run as if it were a primary payload, it must be manually
-built and explicitly set as the primary payload using the "ELF
-executable payload" option.
-
 
 ### Step 5 summary - Configure the build
 

Documentation/tutorial/part3.md

@@ -1,20 +1,20 @@
 # Writing unit tests for coreboot
 
 ## Introduction
-General thoughts about unit testing coreboot can be found in
-[Unit-testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
+General thoughts about unit testing coreboot can be found in [Unit
+testing coreboot](../technotes/2020-03-unit-testing-coreboot.md).
 Additionally, [code coverage](../technotes/2021-05-code-coverage.md)
 support is available for unit tests.
 
 This document aims to guide developers through the process of adding and
 writing unit tests for coreboot modules.
 
-As an example of unit-under-test, `src/device/i2c.c` (referred hereafter
+As an example of unit under test, `src/device/i2c.c` (referred hereafter
 as UUT "Unit Under Test") will be used. This is simple module, thus it
 should be easy for the reader to focus solely on the testing logic,
 without the need to spend too much time on digging deeply into the
 source code details and flow of operations. That being said, a good
-understanding of what the unit-under-test is doing is crucial for
+understanding of what the unit under test is doing is crucial for
 writing unit tests.
 
 This tutorial should also be helpful for developers who want to follow
@@ -23,7 +23,7 @@ though TDD has a different work flow of building tests first, followed
 by the code that satisfies them, the process of writing tests and adding
 them to the tree is the same.
 
-## Analysis of unit-under-test
+## Analysis of unit under test
 First of all, it is necessary to precisely establish what we want to
 test in a particular module. Usually this will be an externally exposed
 API, which can be used by other modules.
@@ -69,7 +69,7 @@ UUT and not on the other modules. While some software dependencies may
 be hard to be mock (for example due to complicated dependencies) and
 thus should be simply linked into the test binaries, all hardware
 dependencies need to be mocked out, since in the user-space host
-environment, target hardware is not available.
+environment, targets hardware is not available.
 
 ```eval_rst
 .. admonition:: i2c-test example
@@ -142,12 +142,12 @@ for coreboot `make unit-tests`.
      make unit-tests
 ```
 
-When trying to build test binary, one can often see the linker complaining
-about `undefined reference` for a couple of symbols. This is one of the
+When trying to build test binary, one can often see linker complains
+about `undefined reference` to couple of symbols. This is one of
 solutions to determine all external dependencies of UUT - iteratively
 build test and resolve errors one by one. At this step, developer should
 decide either it's better to add an extra module to provide necessary
-definitions or rather mock such dependency. A quick guide about adding
+definitions or rather mock such dependency. Quick guide through adding
 mocks is provided later in this doc.
 
 ## Writing new tests
@@ -324,8 +324,8 @@ a described range.
 .. admonition:: i2c-test example
 
    In our example, we may want to check that `platform_i2c_transfer` is
-   fed with a number of segments bigger than 0, each segment has flags
-   which are in the supported range and each segment has a buf which is
+   fed with number of segments bigger than 0, each segment has flags
+   which are in supported range and each segment has buf which is
    non-NULL. We are expecting such values for _every_ call, thus the
    last parameter in `expect*` macros is -1.
 
@@ -375,16 +375,16 @@ API documentation.
 
 ### Test runner
 Finally, the developer needs to implement the test `main()` function.
-All tests should be registered there and the cmocka test runner invoked.
-All methods for invoking Cmocka test are described
+All tests should be registered there and cmocka test runner invoked. All
+methods for invoking Cmocka test are described
 [here](https://api.cmocka.org/group__cmocka__exec.html).
 
 ```eval_rst
 .. admonition:: i2c-test example
 
    We don't need any extra setup and teardown functions for i2c-test, so
-   let's simply register the test for `i2c_read_field` and return from
-   main the output of Cmocka's runner (it returns number of tests
+   let's simply register test for `i2c_read_field` and return from main
+   value which is output of Cmocka's runner (it returns number of tests
    that failed).
 
    .. code-block:: c

Documentation/util.md

@@ -49,8 +49,8 @@ file `Python`
 * __cbmem__ - CBMEM parser to read e.g. timestamps and console log `C`
 * __chromeos__ - These scripts can be used to access ChromeOS
 resources, for example to extract System Agent reference code and other
-blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS recovery
-image. `C`
+blobs (e.g. mrc.bin, refcode, VGA option roms) from a ChromeOS
+recovery image. `C`
 * __crossgcc__ - A cross toolchain builder for -elf toolchains (ie. no
 libc support) `Bash`
 * __docker__ - Dockerfiles for _coreboot-sdk_, _coreboot-jenkins-node_,
@@ -88,7 +88,7 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
 embedded controller and insert them to the firmware image. `C`
 * __kconfig__ - Build system `Make`
 * __lint__ - Source linter and linting rules `Shell`
-* __nixos__ - A script and NixOS configuration files to create an ISO
+* __liveiso__ - A script and NixOS configuration files to create an ISO
 image for testing purposes and for working on firmware. `Bash`
 * __mainboard__ - mainboard specific scripts
 	* _google_ - Directory for google mainboard specific scripts
@@ -138,10 +138,6 @@ for the files modified in a patch or for a file `Perl`
 license headers `Shell`
 	* _parse-maintainers.pl_ - Script to alphabetize MAINTAINERS
 file `Perl`
-	* _rm_unused_code_ - Remove all code not used for a platform
-from the local git repository for auditing or release `Bash`
-	* _show_platforms.sh_ - Makes a list of platforms in the tree.
-Does not show variants. `Shell`
 	* _ucode_h_to_bin.sh_ - Microcode conversion tool `Bash`
 	* _update_submodules_ - Check all submodules for updates `Bash`
 * __showdevicetree__ - Compile and dump the device tree `C`
@@ -166,9 +162,9 @@ the documentation `Bash`
 * __x86__ - Generates 32-bit PAE page tables based on a CSV input file.
 `Go`
 * __xcompile__ - Cross compile setup `Bash`
+
 ## In depth documentation
 
-* [abuild](util/abuild/index.md)
 * [cbfstool](util/cbfstool/index.md)
 * [ifdtool](util/ifdtool/index.md)
 * [intelp2m](util/intelp2m/index.md)

Documentation/util/abuild/index.md

@@ -1,260 +0,0 @@
-abuild
-======
-
-This utility is a great tool to check whether your coreboot tree
-compiles for one or all targets. It compiles the 'default' build for a
-mainboard. This is roughly equivalent to removing the .config file,
-running `make menuconfig`, selecting the manufacturer and mainboard,
-then saving the config without making any other changes.
-
-It is run on all patches submitted via gerrit as part of the process.
-Before submitting a patch, it is a very good idea to run abuild first
-to make sure your patch compiles cleanly for all.
-
-Note that abuild is a tool to do a simple build test, and binaries it
-produces may well not boot if flashed to a system.
-
-### Basic usage
-
-abuild needs to be run from the coreboot directory. If you cd into the
-coreboot/util/abuild directory and try to run it from there, it will
-not run correctly.
-
-If you invoke abuild with no parameters, it will build all boards
-automatically.
-
-You can also specify a single board to build with the -t option. For
-example, to build the Lenovo X230 target, run:
-
-```bash
-$ util/abuild/abuild -t lenovo/x230
-```
-
-### Where builds and logs are stored
-
-The resulting images and logs are stored in directory coreboot-builds/
-under your current directory. This can be overridden with --outdir:
-
-```bash
-$ util/abuild/abuild --outdir /mnt/portable/coreboot-builds
-```
-
-This is useful if you want to divert the build to an external hard
-drive, e.g. to keep the solid-state drive holding the coreboot tree
-young.
-
-(We will still refer to this directory as "coreboot-builds" below.)
-
-After running the X230 build above, the build log will be in
-coreboot-builds/LENOVO_X230/make.log.
-
-For an overview of what passed and what failed, look at
-coreboot-builds/passing_boards and coreboot-builds/failing_boards.
-**These logs are overwritten with each abuild run.** Save them elsewhere
-if you feel a need to reference the results later.
-
-### Payloads
-
-You can also specify a payload directory with -p:
-
-```bash
-mkdir payloads
-cp /somewhere/filo.elf payloads
-```
-
-Then add a file payloads/payload.sh which prints the name of the
-payload to use (and takes the mainboard as a parameter) such as:
-
-```bash
-echo "`dirname $0`/build/filo.elf"
-```
-
-Then you can build an image with payload by specifying:
-
-```bash
-util/abuild/abuild -t lenovo/x230 -p ./payloads
-```
-
-You can also tell abuild not to use a payload:
-
-```bash
-util/abuild/abuild -t lenovo/x230 -p none
-```
-
-### Build non-default configurations
-
-Sometimes you do need to build test a custom, non-default configuration.
-This can be accomplished by placing a config file in configs/.
-
-First, clean your slate with `make distclean` or `rm .config`.
-
-Then run `make menuconfig`, select the manufacturer and mainboard, and
-configure the options you need to test building for.
-
-Then save a minimal config file omitting options that did not change
-from default:
-
-```bash
-make savedefconfig
-```
-
-This file is saved as `defconfig` and can be edited further.
-
-Now this file can be saved in configs/ which will form the basis of a
-custom configuration included in an abuild. However, it needs to be
-named in a specific way for abuild to pick it up:
-
-```
-config.<board>_<suffix>
-```
-
-<board> is effectively the BOARD\_xxx Kconfig option without "BOARD\_".
-<suffix> is a free form description of the configuration being built.
-
-For example, a config for ASUS P8Z77-M PRO that tests building with MRC
-raminit code (as opposed to the default native raminit) would be named
-`config.asus_p8z77_m_pro_mrc_bin` and contains:
-
-```
-CONFIG_VENDOR_ASUS=y
-CONFIG_BOARD_ASUS_P8Z77_M_PRO=y
-# CONFIG_USE_NATIVE_RAMINIT is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
-# CONFIG_BOOTBLOCK_CONSOLE is not set
-# CONFIG_POSTCAR_CONSOLE is not set
-```
-
-For what we are trying to do, not setting USE_NATIVE_RAMINIT is the
-important part. The other three optional changes are meant to speed
-things up. All these options can be selected during `make menuconfig`.
-
-Path to MRC binary blob remains default and thus not included here.
-
-Custom configurations can also be put in a file and applied to an entire
-abuild run using -K. Assume for example you are not interested in
-the postcar stage at all and just want it to shut up, you can create
-a file named `myconfig` with this line:
-
-```
-# CONFIG_POSTCAR_CONSOLE is not set
-```
-
-and run `abuild -K myconfig` to build everything with a silent postcar
-stage.
-
-### Selectively build certain targets only (also config file naming caveats)
-
-The P8Z77-M PRO example above would fail for P8Z77-M, because the
-config file name is ambiguous. `abuild` would pick up this config when
-building for P8Z77-M, but fails when it sees that this config isn't
-meant for P8Z77-M (but for P8Z77-M PRO). To avoid this error, you have
-to skip this config using --skip_set:
-
-```bash
-util/abuild/abuild --skip_set BOARD_ASUS_P8Z77_M_PRO
-```
-
-To complete the test, run abuild again specifically for this board
-variant (see next section).
-
-You can skip building other targets based on other Kconfigs. To skip
-building targets without a Kconfig set, use --skip_unset:
-
-```bash
-util/abuild/abuild --skip_unset USE_NATIVE_RAMINIT
-```
-This example skips building configs not using (Sandy/Ivy Bridge) native
-RAM init.
-
-### Additional Examples
-
-Many boards have multiple variants. You can build for a specific
-variant of a board:
-
-```bash
-util/abuild/abuild -t asus/p8x7x-series -b p8z77-m_pro -p none
-```
-
-Many of the boards need files from the 'blobs' repository, which will
-be initialized by the -B option. If the blobs repo has already been
-initialized in your local tree, it won't hurt to add the -B.
-
-```bash
-util/abuild/abuild -B -t lenovo/x230 -p none
-```
-
-Adding ccache to your system and telling abuild to use it with the -y
-option will speed things up a bit:
-
-```bash
-util/abuild/abuild -B -y -t lenovo/x230 -p none
-```
-
-Telling abuild to use multiple cores with the -c option helps speed
-things up as well:
-
-```bash
-util/abuild/abuild -B -y -c 8 -t lenovo/x230 -p none
-```
-
-Of course, the real power of abuild is in testing multiple boards.
-
-```bash
-util/abuild/abuild -B -y -c 8 -p none
-```
-
-### Full options list
-
-```text
-coreboot autobuild v0.11.01 (Feb 3, 2023)
-[...]
-Usage: util/abuild/abuild [options]
-       util/abuild/abuild [-V|--version]
-       util/abuild/abuild [-h|--help]
-
-Options:
-    [-a|--all]                    Build previously succeeded ports as well
-    [-A|--any-toolchain]          Use any toolchain
-    [-b|--board-variant <name>]   Build specific board variant under the
-                                  given target.
-    [-B|--blobs]                  Allow using binary files
-    [--checksum <path/basefile>]  Store checksums at path/basefile
-    [-c|--cpus <numcpus>]         Build on <numcpus> at the same time
-    [-C|--config]                 Configure-only mode
-    [-d|--dir <dir>]              Directory containing config files
-    [-e|--exitcode]               Exit with a non-zero errorlevel on failure
-    [-J|--junit]                  Write JUnit formatted xml log file
-    [-K|--kconfig <name>]         Prepend file to generated Kconfig
-    [-l|--loglevel <num>]         Set loglevel
-    [-L|--clang]                  Use clang on supported arch
-    [-n|--name]                   Set build name - also sets xmlfile if not
-                                  already set
-    [-o|--outdir <path>]          Store build results in path
-                                  (defaults to coreboot-builds)
-    [-p|--payloads <dir>]         Use payloads in <dir> to build images
-    [-P|--prefix <name>]          File name prefix in CBFS
-    [-q|--quiet]                  Print fewer messages
-    [-r|--remove]                 Remove output dir after build
-    [-R|--root <path>]            Absolute path to coreboot sources
-                                  (defaults to /usr/src/coreboot)
-    [--scan-build]                Use clang's static analyzer
-    [--skip_set <value>]          Skip building boards with this Kconfig set
-    [--skip_unset <value>]        Skip building boards with this Kconfig not set
-    [--timeless]                  Generate timeless builds
-    [-t|--target <vendor/board>]  Attempt to build target vendor/board only
-    [-T|--test]                   Submit image(s) to automated test system
-    [-u|--update]                 Update existing image
-    [-v|--verbose]                Print more messages
-    [-x|--chromeos]               Build with CHROMEOS enabled
-                                  Skip boards without ChromeOS support
-    [-X|--xmlfile <name>]         Set JUnit XML log file filename
-                                  (defaults to /usr/src/coreboot/abuild.xml)
-    [-y|--ccache]                 Use ccache
-    [-z|--clean]                  Remove build results when finished
-    [-Z|--clean-somewhat]         Remove build but keep coreboot.rom + config
-
-    [-V|--version]                Print version number and exit
-    [-h|--help]                   Print this help and exit
-
-    [-s|--silent]                 obsolete
-```

MAINTAINERS

@@ -177,11 +177,6 @@ F:	src/mainboard/apple/
 
 
 
-ASROCK B75M-ITX MAINBOARD
-M:	Kevin Keijzer <kevin@quietlife.nl>
-S:	Maintained
-F:	src/mainboard/asrock/b75m-itx/
-
 ASROCK B85M PRO4 MAINBOARD
 M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
@@ -270,10 +265,6 @@ DELL MAINBOARDS
 S:	Orphan
 F:	src/mainboard/dell/
 
-DELL E6400 MAINBOARD
-M:	Nicholas Chin <nic.c3.14@gmail.com>
-S:	Maintained
-F:	src/mainboard/dell/e6400/
 
 
 ELMEX MAINBOARDS
@@ -340,22 +331,18 @@ F:	src/mainboard/gizmosphere/
 
 GOOGLE REX MAINBOARDS
 M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <tstuli@gmail.com>
+M:	Tarun Tuli <taruntuli@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
-M:	Jakub Czapiga <jacz@semihalf.com>
-M:	Eran Mitrani <mitrani@google.com>
 S:	Maintained
 F:	src/mainboard/google/rex/
 
 GOOGLE BRYA MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Tarun Tuli <taruntuli@google.com>
 S:	Maintained
 F:	src/mainboard/google/brya/
 
 GOOGLE HATCH MAINBOARDS
-M:	Subrata Banik <subratabanik@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Tarun Tuli <taruntuli@google.com>
 S:	Maintained
 F:	src/mainboard/google/hatch/
 
@@ -388,18 +375,6 @@ F:	src/mainboard/google/zork/
 F:	src/mainboard/google/guybrush/
 F:	src/mainboard/google/skyrim/
 
-GOOGLE MEDIATEK-BASED MAINBOARDS
-M:	Hung-Te Lin <hungte@chromium.org>
-M:	Yu-Ping Wu <yupingso@google.com>
-M:	Yidi Lin <yidilin@google.com>
-S:	Supported
-F:	src/mainboard/google/asurada/
-F:	src/mainboard/google/cherry/
-F:	src/mainboard/google/corsola/
-F:	src/mainboard/google/geralt/
-F:	src/mainboard/google/kukui/
-F:	src/mainboard/google/oak/
-
 
 
 HP 280 G2 MAINBOARD
@@ -421,10 +396,7 @@ M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
 S:	Maintained
 F:	src/mainboard/intel/harcuvar/
 
-INVENTEC MAINBOARDS
-M:	Annie Chen <Chen.AnnieET@inventec.com>
-S:	Maintained
-F:	src/mainboard/inventec/
+
 
 JETWAY MAINBOARDS
 S:	Orphan
@@ -711,12 +683,6 @@ M:	Caveh Jalali <caveh@chromium.org>
 S:	Maintained
 F:	src/ec/google/
 
-DELL SMSC MEC5035 EC
-M:	Nicholas Chin <nic.c3.14@gmail.com>
-W:	https://github.com/nic3-14159/E6400-EC-research
-S:	Maintained
-F:	src/ec/dell/mec5035/
-
 LENOVO EC
 M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
@@ -868,16 +834,14 @@ F:	src/soc/amd/stoneyridge/
 
 INTEL METEORLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
-M:	Tarun Tuli <tstuli@gmail.com>
+M:	Tarun Tuli <taruntuli@google.com>
 M:	Kapil Porwal <kapilporwal@google.com>
-M:	Jakub Czapiga <jacz@semihalf.com>
-M:	Eran Mitrani <mitrani@google.com>
 S:	Maintained
 F:	src/soc/intel/meteorlake/
 
 INTEL ALDERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Tarun Tuli <taruntuli@google.com>
 S:	Maintained
 F:	src/soc/intel/alderlake/
 
@@ -894,10 +858,6 @@ S:	Maintained
 F:	/src/soc/intel/braswell/
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
 
-INTEL CANNONLAKE SOC
-S:	Orphan
-F:	src/soc/intel/cannonlake/
-
 INTEL DENVERTON-NS SOC
 M:	Jeff Daly <jeffd@silicom-usa.com>
 M:	Vanessa Eusebio <vanessa.f.eusebio@intel.com>
@@ -912,7 +872,7 @@ F:	src/soc/intel/elkhartlake/
 
 INTEL TIGERLAKE SOC
 M:	Subrata Banik <subratabanik@google.com>
-M:	Nick Vaccaro <nvaccaro@chromium.org>
+M:	Tarun Tuli <taruntuli@google.com>
 S:	Maintained
 F:	src/soc/intel/tigerlake/
 
@@ -929,8 +889,6 @@ F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
 
 MEDIATEK SOCS
 M:	Hung-Te Lin <hungte@chromium.org>
-M:	Yu-Ping Wu <yupingso@google.com>
-M:	Yidi Lin <yidilin@google.com>
 S:	Supported
 F:	src/soc/mediatek/
 
@@ -968,26 +926,12 @@ M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
 M:	Martin Roth <gaumless@gmail.com>
 F:	payloads/external/
 
-COREDOOM PAYLOAD INTEGRATION
-M:	Nicholas Chin <nic.c3.14@gmail.com>
-W:	https://github.com/nic3-14159/coreDOOM
-S:	Maintained
-F:	payloads/external/coreDOOM/
-
 LINUXBOOT PAYLOAD INTEGRATION
 M:	Christian Walter <christian.walter@9elements.com>
 M:	Marcello Sylvester Bauer <info@marcellobauer.com>
 S:	Supported
 F:	payloads/external/LinuxBoot/
 
-EDK2 PAYLOAD INTEGRATION
-M:	Benjamin Doron <benjamin.doron00@gmail.com>
-M:	Matt DeVillier <matt.devillier@gmail.com>
-M:	Sean Rhodes <sean@starlabs.systems>
-M:	Lean Sheng Tan <sheng.tan@9elements.com>
-S:	Supported
-F:	payloads/external/edk2/
-
 ################################################################################
 # Utilities
 ################################################################################
@@ -1020,7 +964,6 @@ F:	util/crossgcc/
 
 DOCKER
 M:	Martin Roth <gaumless@gmail.com>
-M:	Felix Singer <felixsinger@posteo.net>
 S:	Supported
 F:	util/docker/
 
@@ -1133,7 +1076,8 @@ F:	src/drivers/*/tpm/
 F:	src/security/tpm/
 
 SUPERIOS & SUPERIOTOOL
-S:	Orphan
+M:	Felix Held <felix-coreboot@felixheld.de>
+S:	Odd Fixes
 F:	src/superio/
 F:	util/superiotool/
 

Makefile

@@ -85,7 +85,7 @@ help_coreboot help::
 	@echo  '  clean                 - Remove coreboot build artifacts'
 	@echo  '  distclean             - Remove build artifacts and config files'
 	@echo  '  sphinx                - Build sphinx documentation for coreboot'
-	@echo  '  sphinx-lint           - Build sphinx documentation for coreboot with warnings as errors'
+	@echo  '  sphinx-lint           - Build sphinx documenttion for coreboot with warnings as errors'
 	@echo  '  filelist              - Show files used in current build'
 	@echo  '  printall              - print makefile info for debugging'
 	@echo  '  gitconfig             - set up git to submit patches to coreboot'
@@ -190,6 +190,10 @@ endif
 # are reproducible
 export LANG LC_ALL TZ SOURCE_DATE_EPOCH
 
+ifneq ($(CONFIG_MMX),y)
+CFLAGS_x86_32 += -mno-mmx
+endif
+
 ifneq ($(UNIT_TEST),1)
 include toolchain.inc
 endif
@@ -197,10 +201,6 @@ endif
 strip_quotes = $(strip $(subst ",,$(subst \",,$(1))))
 # fix makefile syntax highlighting after strip macro \" "))
 
-ifneq ($(NOCOMPILE),1)
-$(shell rm -f $(CCACHE_STATSLOG))
-endif
-
 # The primary target needs to be here before we include the
 # other files
 
@@ -273,18 +273,17 @@ src-to-ali=\
 # Add paths to files in X-y to X-srcs
 # Add subdirs-y to subdirs
 includemakefiles= \
-	$(if $(wildcard $(1)), \
-		$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
-		$(eval -include $(1)) \
-		$(foreach class,$(classes-y), $(call add-class,$(class))) \
-		$(foreach special,$(special-classes), \
-			$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
-		$(foreach class,$(classes), \
-			$(eval $(class)-srcs+= \
-				$$(subst $(absobj)/,$(obj)/, \
-				$$(subst $(top)/,, \
-				$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
-		$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))))
+	$(foreach class,classes subdirs $(classes) $(special-classes), $(eval $(class)-y:=)) \
+	$(eval -include $(1)) \
+	$(foreach class,$(classes-y), $(call add-class,$(class))) \
+	$(foreach special,$(special-classes), \
+		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
+	$(foreach class,$(classes), \
+		$(eval $(class)-srcs+= \
+			$$(subst $(absobj)/,$(obj)/, \
+			$$(subst $(top)/,, \
+			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y)))))))) \
+	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(wildcard $$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y))))))
 
 # For each path in $(subdirs) call includemakefiles
 # Repeat until subdirs is empty
@@ -316,11 +315,6 @@ $(eval $(postinclude-hooks))
 # Eliminate duplicate mentions of source files in a class
 $(foreach class,$(classes),$(eval $(class)-srcs:=$(sort $($(class)-srcs))))
 
-ifeq ($(CONFIG_IWYU),y)
-MAKEFLAGS += -k
-SAVE_IWYU_OUTPUT := 2>&1 | grep "should\|\#include\|---\|include-list\|^[[:blank:]]\?\'" | tee -a $$(obj)/iwyu.txt
-endif
-
 # Build Kconfig .ads if necessary
 ifeq ($(CONFIG_ROMSTAGE_ADA),y)
 romstage-srcs += $(obj)/romstage/$(notdir $(KCONFIG_AUTOADS))
@@ -387,7 +381,7 @@ $$(call src-to-obj,$1,$$(1).$2): $$(1).$2 $(KCONFIG_AUTOHEADER) $(4)
 	@printf "    CC         $$$$(subst $$$$(obj)/,,$$$$(@))\n"
 	$(CC_$(1)) \
 		-MMD $$$$(CPPFLAGS_$(1)) $$$$(CFLAGS_$(1)) -MT $$$$(@) \
-		$(3) -c -o $$$$@ $$$$< $(SAVE_IWYU_OUTPUT)
+		$(3) -c -o $$$$@ $$$$<
 end$(EMPTY)if
 en$(EMPTY)def
 end$(EMPTY)if
@@ -448,7 +442,7 @@ $(obj)/project_filelist.txt:
 		echo "*** Error: Project must be built before generating file list ***"; \
 		exit 1; \
 	fi
-	find $(obj) -path "$(obj)/util" -prune -o -path "$(obj)/external" -prune -o -name "*.d" -exec cat {} \; | \
+	find $(obj) -path "$(obj)/util" -prune -o -name "*.d" -exec cat {} \; | \
 	  sed "s|$(top)/||" | sed 's/[:\\]/ /g' | sed 's/ /\n/g' | sort | uniq | \
 	  grep -v '\.o$$' > $(obj)/project_filelist.txt
 
@@ -468,10 +462,10 @@ cscope:
 	cscope -bR
 
 sphinx:
-	$(MAKE) -C Documentation sphinx
+	$(MAKE) -C Documentation -f Makefile.sphinx html
 
 sphinx-lint:
-	$(MAKE) SPHINXOPTS=-W -C Documentation sphinx
+	$(MAKE) SPHINXOPTS=-W -C Documentation -f Makefile.sphinx html
 
 symlink:
 	@echo "Creating Symbolic Links.."; \

Makefile.inc

@@ -23,7 +23,7 @@ ifeq ($(BUILD_TIMELESS),1)
 KERNELVERSION := -TIMELESS--LESSTIME-
 else
 KERNELVERSION := $(strip $(if $(GIT),\
-	$(shell git describe --abbrev=12 --dirty --always || git describe),\
+	$(shell git describe --dirty --always || git describe),\
 	$(if $(wildcard $(top)/.coreboot-version),\
 		$(shell cat $(top)/.coreboot-version),\
 		coreboot-unknown$(KERNELREVISION))))
@@ -66,11 +66,8 @@ coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool $(
 # targets after the build completes by creating a Makefile.inc in the
 # site-local directory with a target named 'build_complete::'
 build_complete:: coreboot
-	printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) $(CONFIG_MAINBOARD_PART_NUMBER)
-	if [ -f "$(CCACHE_STATSLOG)" ]; then \
-		printf "\nccache statistics\n"; \
-		$(CCACHE) --show-log-stats -v; \
-	fi
+	printf "\nBuilt %s (%s)\n" $(MAINBOARDDIR) \
+		$(CONFIG_MAINBOARD_PART_NUMBER)
 
 # This target can be used to run rules after all files were added to CBFS,
 # for example to process FMAP regions or the entire image.
@@ -110,9 +107,6 @@ classes-y := ramstage romstage bootblock decompressor postcar smm smmstub cpu_mi
 $(call add-special-class,all)
 all-handler = $(foreach class,bootblock verstage romstage postcar ramstage,$(eval $(class)-y += $(2)))
 
-$(call add-special-class,all_x86)
-all_x86-handler = $(foreach class,bootblock verstage_x86 romstage postcar ramstage,$(eval $(class)-y += $(2)))
-
 $(call add-special-class,verstage_x86)
 ifeq ($(CONFIG_ARCH_VERSTAGE_X86_32)$(CONFIG_ARCH_VERSTAGE_X86_64),y)
 verstage_x86-handler = $(eval verstage-y += $(2))
@@ -146,9 +140,7 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \
 # tolower:        returns the value in all lowercase
 # toupper:        returns the value in all uppercase
 # ws_to_under:    returns the value with any whitespace changed to underscores
-# get_fmap_value  returns the value of a given FMAP field from fmap_config.h
 _toint=$(shell printf "%d" $1)
-_tohex=$(shell printf 0x"%x" $1)
 _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2))
 int-add=$(if $(filter 1,$(words $1)),$(strip $1),$(call int-add,$(call _int-add2,$(word 1,$1),$(word 2,$1)) $(wordlist 3,$(words $1),$1)))
 int-subtract=$(if $(filter 1,$(words $1)),$(strip $1),$(shell expr $(call _toint,$(word 1,$1)) - $(call _toint,$(word 2,$1))))
@@ -166,7 +158,6 @@ file-size=$(strip $(shell wc -c "$1" | cut -f 1 -d ' '))
 tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]')
 toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]')
 ws_to_under=$(shell echo '$1' | tr ' \t' '_')
-get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h)
 
 #######################################################################
 # Helper functions for ramstage postprocess
@@ -319,7 +310,7 @@ cbfs-files-processor-nvramtool= \
 # arg1: input
 # arg2: output
 define cbfs-files-processor-config
-	$(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \
+	$(eval $(2): $(1) $(obj)/build.h; \
 		+printf "    CREATE     $(2) (from $(1))\n"; \
 		printf "# This image was built using coreboot " > $(2).tmp && \
 		grep "\<COREBOOT_VERSION\>" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \
@@ -331,19 +322,6 @@ define cbfs-files-processor-config
 		mv -f $(2).tmp $(2))
 endef
 
-#######################################################################
-# Add a file to CBFS with just type and compression values
-# arg1: name in CBFS
-# arg2: filename and path
-# arg3: type in CBFS
-# arg4: compression type
-define add-cbfs-file-simple
-	$(eval cbfs-files-y += $(1))
-	$(eval $(1)-file := $(2))
-	$(eval $(1)-type := $(3))
-	$(eval $(1)-compression := $(4))
-endef
-
 #######################################################################
 # Compile a C file with a bare struct definition into binary
 # arg1: C source file
@@ -356,41 +334,6 @@ cbfs-files-processor-struct= \
 		rm -f $(2).tmp) \
 	$(eval DEPENDENCIES += $(2).d)
 
-#######################################################################
-# Convert image to YCC 4:2:0 JPEG
-#
-# In two steps:
-# 1. Convert to RGB colors, optionally resize and store as BMP.
-# 2. Round final size to multiples of 16, optionally swap colors,
-#    convert (back) to sRGB and store as JPEG.
-# The split is necessary because we don't know the exact, scaled
-# size due to aspect-ratio. Note: IM v7 would allow us to do the
-# calculations in one command using %[fx:...] syntax.
-#
-# arg1: image input file
-# arg2: output jpg
-cbfs-files-processor-jpg420= \
-	$(eval $(2): $(1) $(KCONFIG_AUTOCONFIG);				\
-		printf "    CONVERT    $$<\n";					\
-		res=$(CONFIG_BOOTSPLASH_CONVERT_RESOLUTION);			\
-		res=$$$$(convert $$<						\
-			-colorspace RGB						\
-			$$(BOOTSPLASH_RESIZE-y)					\
-			-format '%wx%h' -write info:				\
-			bmp:$$@);						\
-		convert $$@							\
-			$$(BOOTSPLASH_ROUND16)					\
-			$$(BOOTSPLASH_COLORSWAP-y)				\
-			-colorspace sRGB					\
-			-quality $$(CONFIG_BOOTSPLASH_CONVERT_QUALITY)%		\
-			-interlace none -colorspace YCC -sampling-factor 4:2:0	\
-			jpg:$$@)
-BOOTSPLASH_FLOOR = $$(($${res%%x*} & ~15))x$$(($${res\#\#*x} & ~15))
-BOOTSPLASH_RESIZE-$(CONFIG_BOOTSPLASH_CONVERT_RESIZE) = -resize $(BOOTSPLASH_FLOOR)
-BOOTSPLASH_CEIL = $$((($${res%%x*} + 15) & ~15))x$$((($${res\#\#*x} + 15) & ~15))
-BOOTSPLASH_ROUND16 = -background black -gravity center -extent $(BOOTSPLASH_CEIL)
-BOOTSPLASH_COLORSWAP-$(CONFIG_BOOTSPLASH_CONVERT_COLORSWAP) := -channel-fx 'red<=>blue'
-
 #######################################################################
 # Add handler for arbitrary files in CBFS
 $(call add-special-class,cbfs-files)
@@ -480,7 +423,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
 CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla -Wold-style-definition
-CFLAGS_common += -Wdangling-else -Wmissing-include-dirs
+CFLAGS_common += -Wdangling-else
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
@@ -488,8 +431,10 @@ ifeq ($(CONFIG_COMPILER_GCC),y)
 ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
-CFLAGS_common += -Wnull-dereference
+CFLAGS_common += -Wnull-dereference -Wreturn-type
 CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wno-array-compare
+# cf. commit f69a99db (coreboot: x86: enable gc-sections)
+CFLAGS_common += -Wno-unused-but-set-variable
 endif
 endif
 
@@ -650,8 +595,6 @@ APCB_EDIT_TOOL:=$(top)/util/apcb/apcb_edit.py
 
 APCB_V3_EDIT_TOOL:=$(top)/util/apcb/apcb_v3_edit.py
 
-APCB_V3A_EDIT_TOOL:=$(top)/util/apcb/apcb_v3a_edit.py
-
 CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage
 
 FUTILITY?=$(objutil)/futility/futility
@@ -709,14 +652,6 @@ bootblock-c-deps+=$(DEVICETREE_STATIC_C)
 postcar-c-deps+=$(DEVICETREE_STATIC_C)
 smm-c-deps+=$(DEVICETREE_STATIC_C)
 
-# Ensure fmap_config.h are created before any objects are compiled
-ramstage-c-deps+=$(obj)/fmap_config.h
-romstage-c-deps+=$(obj)/fmap_config.h
-verstage-c-deps+=$(obj)/fmap_config.h
-bootblock-c-deps+=$(obj)/fmap_config.h
-postcar-c-deps+=$(obj)/fmap_config.h
-smm-c-deps+=$(obj)/fmap_config.h
-
 .PHONY: devicetree
 devicetree: $(DEVICETREE_STATIC_C)
 
@@ -866,7 +801,7 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(objcbfs)/%.map
 #                mma, efi, deleted, null
 # 4 - Compression type      [$(FILENAME)-compression]
 #                      none, LZMA
-# 5 - Base address          [$(FILENAME)-position]
+# 5 - Base address          [$(FILANAME)-position]
 # 6 - Alignment             [$(FILENAME)-align]
 # 7 - cbfstool flags        [$(FILENAME)-options]
 #
@@ -887,7 +822,7 @@ extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-)
 #
 # This is the default implementation. When using a boot strategy employing
 # multiple CBFSes in fmap regions, override it.
-regions-for-file ?= $(if $(value regions-for-file-$(1)), $(regions-for-file-$(1)), COREBOOT)
+regions-for-file ?= COREBOOT
 
 ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y)
 	cbfs-autogen-attributes=-g
@@ -990,22 +925,11 @@ prebuild-files = $(foreach region,$(all-regions), \
 		$(call sort-files,$(call placed-files-in-region,$(region))), \
 		$(call cbfs-add-cmd,$(file),$(region),$(CONFIG_UPDATE_IMAGE))))
 
-# If no FMD file (Flashmap) is supplied by mainboard, fall back to a default
 ifeq ($(CONFIG_FMDFILE),)
-
+# For a description of the flash layout described by these variables, check
+# the $(DEFAULT_FLASHMAP) .fmd files.
 ifeq ($(CONFIG_ARCH_X86),y)
-
 DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default-x86.fmd
-# check if IFD_CHIPSET is set and if yes generate a FMAP template from IFD descriptor
-ifneq ($(CONFIG_IFD_CHIPSET),)
-ifeq ($(CONFIG_HAVE_IFD_BIN),y)
-DEFAULT_FLASHMAP:=$(obj)/fmap-template.fmd
-$(DEFAULT_FLASHMAP): $(call strip_quotes,$(CONFIG_IFD_BIN_PATH)) $(IFDTOOL)
-	echo "    IFDTOOL    -p $(CONFIG_IFD_CHIPSET) -F $@ $<"
-	$(IFDTOOL) -p $(CONFIG_IFD_CHIPSET) -F $@ $<
-endif # ifeq($(CONFIG_HAVE_IFD_BIN),y)
-endif # ifneq($(CONFIG_IFD_CHIPSET),)
-
 # entire flash
 FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_ROM_SIZE))
 FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE)
@@ -1068,15 +992,6 @@ else
 FMAP_VPD_ENTRY :=
 endif
 
-ifeq ($(CONFIG_INCLUDE_HSPHY_IN_FMAP),y)
-FMAP_HSPHY_FW_BASE := $(call int-align, $(FMAP_CURRENT_BASE), 0x1000)
-FMAP_HSPHY_FW_SIZE := $(CONFIG_HSPHY_FW_MAX_SIZE)
-FMAP_HSPHY_FW_ENTRY := HSPHY_FW@$(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE)
-FMAP_CURRENT_BASE := $(call int-add, $(FMAP_HSPHY_FW_BASE) $(FMAP_HSPHY_FW_SIZE))
-else
-FMAP_HSPHY_FW_ENTRY :=
-endif
-
 #
 # X86 FMAP region
 #
@@ -1155,7 +1070,6 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h
 	    -e "s,##SMMSTORE_ENTRY##,$(FMAP_SMMSTORE_ENTRY)," \
 	    -e "s,##SPD_CACHE_ENTRY##,$(FMAP_SPD_CACHE_ENTRY)," \
 	    -e "s,##VPD_ENTRY##,$(FMAP_VPD_ENTRY)," \
-	    -e "s,##HSPHY_FW_ENTRY##,$(FMAP_HSPHY_FW_ENTRY)," \
 	    -e "s,##CBFS_BASE##,$(FMAP_CBFS_BASE)," \
 	    -e "s,##CBFS_SIZE##,$(FMAP_CBFS_SIZE)," \
 		$(DEFAULT_FLASHMAP) > $@.tmp
@@ -1316,19 +1230,10 @@ cbfs-files-y += build_info
 build_info-file := $(obj)/build_info
 build_info-type := raw
 
-ifeq ($(CONFIG_BOOTSPLASH_CONVERT),y)
-ifeq ($(shell command -v convert),)
-$(error CONFIG_BOOTSPLASH_CONVERT requires the convert program (part of ImageMagick))
-endif
-cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash.jpg
-bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)):jpg420
-bootsplash.jpg-type := bootsplash
-else
 BOOTSPLASH_SUFFIX=$(suffix $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE)))
 cbfs-files-$(CONFIG_BOOTSPLASH_IMAGE) += bootsplash$(BOOTSPLASH_SUFFIX)
 bootsplash$(BOOTSPLASH_SUFFIX)-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
 bootsplash$(BOOTSPLASH_SUFFIX)-type := bootsplash
-endif
 
 # Ensure that no payload segment overlaps with memory regions used by ramstage
 # (not for x86 since it can relocate itself in that case)

configs/builder/config.intel.crb.ac

@@ -1,23 +0,0 @@
-# Intel ArcherCity CRB is a dual socket CRB based on Intel
-# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
-#
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
-
-CONFIG_VENDOR_INTEL=y
-CONFIG_BOARD_INTEL_ARCHERCITY_CRB=y
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-CONFIG_PAYLOAD_LINUX=y
-CONFIG_PAYLOAD_FILE="site-local/archercity/linuxboot_bzImage"
-CONFIG_HAVE_ME_BIN=y
-CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd"
-CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd"
-CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd"
-CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin"
-CONFIG_ME_BIN_PATH="site-local/archercity/me.bin"
-CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb"
-CONFIG_VALIDATE_INTEL_DESCRIPTOR=y

configs/builder/config.ocp.tiogapass

@@ -2,7 +2,6 @@
 #   make defconfig KBUILD_DEFCONFIG=configs/builder/config.ocp.tiogapass
 
 CONFIG_VENDOR_OCP=y
-CONFIG_BOARD_OCP_TIOGAPASS=y
 CONFIG_HAVE_IFD_BIN=y
 CONFIG_HAVE_ME_BIN=y
 CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION=y

configs/builder/config.transformers

@@ -1,16 +0,0 @@
-# Inventec Transformers coreboot is modified from Intel ArcherCity CRB
-# Inventec Transformers is a dual socket CRB based on Intel.
-# Sapphire Rapids Scalable Processor (SPR-SP) chipset.
-#
-# Type this in coreboot root directory to get a working .config:
-#   make defconfig KBUILD_DEFCONFIG=configs/builder/config.intel.crb.ac
-
-CONFIG_VENDOR_INVENTEC=y
-CONFIG_BOARD_INVENTEC_TRANSFORMERS=y
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_LINUX_COMMAND_LINE="loglevel=7 earlyprintk=serial,ttyS0,115200 console=ttyS0,115200"
-CONFIG_PAYLOAD_LINUX=y
-CONFIG_PAYLOAD_FILE="site-local/transformers/linuxboot_bzImage"
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y
-CONFIG_CPU_UCODE_BINARIES="3rdparty/intel-microcode/intel-ucode/06-55-04"

configs/config.facebook_fbg1701.sbom

@@ -1,6 +1,6 @@
-CONFIG_SBOM=y
-CONFIG_SBOM_PAYLOAD=y
-CONFIG_SBOM_ME=y
-CONFIG_SBOM_MICROCODE=y
+CONFIG_INCLUDE_COREBOOT_SBOM=y
+CONFIG_INCLUDE_PAYLOAD_SBOM=y
+CONFIG_INCLUDE_ME_SBOM=y
+CONFIG_INCLUDE_MICROCODE_SBOM=y
 CONFIG_VENDOR_FACEBOOK=y
 CONFIG_BOARD_FACEBOOK_FBG1701=y

configs/config.intel_galileo_gen1

@@ -0,0 +1,10 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_GALILEO_GEN2 is not set
+# CONFIG_FSP_DEBUG_ALL is not set
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_460800=y

configs/config.intel_galileo_gen2

@@ -0,0 +1,9 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.debug

@@ -0,0 +1,13 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_DISPLAY_MTRRS=y
+CONFIG_DISPLAY_ESRAM_LAYOUT=y
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+CONFIG_VERIFY_HOBS=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.fsp2.0

@@ -0,0 +1,8 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.sd

@@ -0,0 +1,18 @@
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_COMMONLIB_STORAGE_MMC=y
+CONFIG_STORAGE_ERASE=y
+CONFIG_STORAGE_EARLY_ERASE=y
+CONFIG_STORAGE_WRITE=y
+CONFIG_STORAGE_EARLY_WRITE=y
+CONFIG_SD_MMC_DEBUG=y
+CONFIG_SD_MMC_TRACE=y
+CONFIG_SDHC_TRACE=y
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.intel_galileo_gen2.vboot

@@ -0,0 +1,9 @@
+CONFIG_VENDOR_INTEL=y
+CONFIG_BOARD_INTEL_GALILEO=y
+# CONFIG_FSP_DEBUG_ALL is not set
+CONFIG_VBOOT_WITH_CRYPTO_SHIELD=y
+# CONFIG_ENABLE_SD_TESTING is not set
+CONFIG_BOOTBLOCK_NORMAL=y
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_SERIAL_921600=y

configs/config.lenovo_t400_vboot_and_debug

@@ -13,4 +13,3 @@ CONFIG_DEBUG_ADA_CODE=y
 CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW=y
 CONFIG_VBOOT=y
 CONFIG_USE_EXP_X86_64_SUPPORT=y
-CONFIG_ARCH_X86_64_PGTBL_LOC=0xfffe8000

configs/config.msi_ms7e06_ddr4

@@ -1,11 +0,0 @@
-CONFIG_VENDOR_MSI=y
-CONFIG_VBOOT=y
-CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-CONFIG_TPM2=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_CBMEM_LOGGING=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

configs/config.msi_ms7e06_ddr5

@@ -1,11 +0,0 @@
-CONFIG_VENDOR_MSI=y
-CONFIG_VBOOT=y
-CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-CONFIG_TPM2=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_CBMEM_LOGGING=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y

configs/config.protectli_vp2420

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_CBFS_SIZE=0x900000
-CONFIG_ONBOARD_VGA_IS_PRIMARY=y
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_BOARD_PROTECTLI_VP2420=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.protectli_vp4630_vp4650

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP4630_VP4650=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_TPM2=y
-CONFIG_POST_IO_PORT=0x80
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.protectli_vp4670

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_PROTECTLI=y
-CONFIG_BOARD_PROTECTLI_VP4670=y
-CONFIG_TPM_MEASURED_BOOT=y
-CONFIG_SMMSTORE_SIZE=0x40000
-CONFIG_TPM2=y
-CONFIG_POST_IO_PORT=0x80
-CONFIG_PAYLOAD_EDK2=y
-CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
-CONFIG_EDK2_BOOT_TIMEOUT=6
-CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
-# CONFIG_EDK2_FULL_SCREEN_SETUP is not set
-CONFIG_EDK2_SD_MMC_TIMEOUT=10
-CONFIG_EDK2_SERIAL_SUPPORT=y

configs/config.scaleway_tagada

@@ -0,0 +1,15 @@
+CONFIG_VENDOR_SCALEWAY=y
+CONFIG_BOARD_SCALEWAY_TAGADA=y
+CONFIG_CBFS_SIZE=0x400000
+CONFIG_CONSOLE_POST=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+# CONFIG_IQAT_ENABLE is not set
+CONFIG_LEGACY_UART_MODE=y
+CONFIG_USE_DENVERTON_NS_FSP_CAR=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+CONFIG_PAYLOAD_ELF=y
+CONFIG_PAYLOAD_FILE="UEFIPAYLOAD.fd"
+CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
+CONFIG_DISPLAY_FSP_HEADER=y
+CONFIG_DEBUG_CBFS=y
+CONFIG_DEBUG_BOOT_STATE=y