Fix peg for bonw15

Change-Id: Ifa62cdfd16cc0d246491fc2c8d4a11d8bfb71aa9

src/drivers/smmstore/ramstage.c

@@ -57,22 +57,18 @@ static void init_store(void *unused)
 
 	printk(BIOS_INFO, "SMMSTORE: Setting up SMI handler\n");
 
-	for (int retries = 0; retries < 3; retries++) {
-		/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
-		__asm__ __volatile__ (
-			"outb %%al, %%dx"
-			: "=a" (eax)
-			: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
-			  "b" (ebx),
-			  "d" (APM_CNT)
-			: "memory");
+	/* Issue SMI using APM to update the com buffer and to lock the SMMSTORE */
+	__asm__ __volatile__ (
+		"outb %%al, %%dx"
+		: "=a" (eax)
+		: "a" ((SMMSTORE_CMD_INIT << 8) | APM_CNT_SMMSTORE),
+		  "b" (ebx),
+		  "d" (APM_CNT)
+		: "memory");
 
-		if (eax == SMMSTORE_RET_SUCCESS) {
-			printk(BIOS_INFO, "SMMSTORE: Installed com buffer\n");
-			break;
-		}
-
-		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer: 0x%x\n", eax);
+	if (eax != SMMSTORE_RET_SUCCESS) {
+		printk(BIOS_ERR, "SMMSTORE: Failed to install com buffer\n");
+		return;
 	}
 }
 

src/mainboard/system76/adl/Kconfig

@@ -1,7 +1,6 @@
 config BOARD_SYSTEM76_ADL_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
-	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID
@@ -108,10 +107,6 @@ config MAINBOARD_VERSION
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
 
-config CMOS_DEFAULT_FILE
-	default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
-	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
-
 config CONSOLE_POST
 	default y
 

src/mainboard/system76/adl/cmos-csme.default

@@ -1,3 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-me_state=Enable

src/mainboard/system76/adl/ramstage.c

@@ -23,9 +23,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13
 
 	params->SataPortsSolidStateDrive[1] = 1;
-
-	// Enable reporting CPU C10 state over eSPI
-	params->PchEspiHostC10ReportEnable = 1;
 }
 
 static void mainboard_init(void *chip_info)

src/mainboard/system76/adl/variants/darp8/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/alderlake
-	register "s0ix_enable" = "1"
-
 	register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 56,
@@ -153,6 +151,12 @@ chip soc/intel/alderlake
 				.clk_req = 4,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
+				register "srcclk_pin" = "4" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux

src/mainboard/system76/adl/variants/gaze17-3050/overridetree.cb

@@ -103,6 +103,14 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to 3.3VS?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "disable_l23" = "true"
+				register "srcclk_pin" = "1" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp9 on
 			# PCIe RP#9 x1, Clock 6 (GLAN)
@@ -111,6 +119,13 @@ chip soc/intel/alderlake
 				.clk_req = 6,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp10 on
 			# PCIe RP#10 x1, Clock 2 (WLAN)
@@ -119,6 +134,12 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp11 on
 			# PCIe RP#11 x1, Clock 5 (CARD)
@@ -127,6 +148,13 @@ chip soc/intel/alderlake
 				.clk_req = 5,
 				.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to 3.3VS?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B7)" # CARD_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # CARD_CLKREQ#
+				device generic 0 on end
+			end
 		end
 	end
 end

src/mainboard/system76/adl/variants/gaze17-3060-b/overridetree.cb

@@ -109,6 +109,12 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp6 on
 			# PCIe root port #6 x1, Clock 5 (CARD)
@@ -117,6 +123,12 @@ chip soc/intel/alderlake
 				.clk_req = 5,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: No enable_gpio = no D3cold?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # CARD_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp7 on
 			# PCIe root port #7 x1, Clock 6 (GLAN)
@@ -135,6 +147,14 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable tied to 3.3VS?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # SATA_M2_PWR_EN1
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "disable_l23" = "true" # Fixes suspend on WD drives
+				register "srcclk_pin" = "1" # SSD_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref gbe on end
 	end

src/mainboard/system76/adl/variants/lemp11/overridetree.cb

@@ -137,6 +137,12 @@ chip soc/intel/alderlake
 				.clk_req = 1,
 				.flags = PCIE_RP_LTR,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST#
+				register "srcclk_pin" = "1" # SSD1_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux

src/mainboard/system76/adl/variants/oryp10/overridetree.cb

@@ -150,6 +150,12 @@ chip soc/intel/alderlake
 				.clk_req = 2,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "2" # WLAN_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp6 on
 			# PCIe RP#6 x1, Clock 6 (CARD)
@@ -158,6 +164,12 @@ chip soc/intel/alderlake
 				.clk_req = 6,
 				.flags = PCIE_RP_HOTPLUG | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to 3.3VS?
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "6" # CARD_CLKREQ#
+				device generic 0 on end
+			end
 		end
 		device ref pcie_rp8 on
 			# PCIe RP#8 x1, Clock 5 (GLAN)
@@ -166,7 +178,15 @@ chip soc/intel/alderlake
 				.clk_req = 5,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
+			chip soc/intel/common/block/pcie/rtd3
+				# XXX: Enable connected directly to VDD3?
+				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "srcclk_pin" = "5" # GLAN_CLKREQ#
+				device generic 0 on end
+			end
 		end
+
 		device ref pmc hidden
 			chip drivers/intel/pmc_mux
 				device generic 0 on

src/mainboard/system76/cml-u/Makefile.inc

@@ -3,8 +3,6 @@ CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 bootblock-y += bootblock.c
 bootblock-y += gpio_early.c
 
-romstage-y += variants/$(VARIANT_DIR)/romstage.c
-
 ramstage-y += ramstage.c
 ramstage-y += variants/$(VARIANT_DIR)/gpio.c
 ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c

src/mainboard/system76/rpl/Kconfig

@@ -1,7 +1,6 @@
 config BOARD_SYSTEM76_RPL_COMMON
 	def_bool n
 	select BOARD_ROMSIZE_KB_32768
-	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_I2C_HID
@@ -133,10 +132,6 @@ config MAINBOARD_VERSION
 	default "oryp11" if BOARD_SYSTEM76_ORYP11
 	default "serw13" if BOARD_SYSTEM76_SERW13
 
-config CMOS_DEFAULT_FILE
-	default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9
-	default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
-
 config CONSOLE_POST
 	default y
 

src/mainboard/system76/rpl/acpi/mainboard.asl

@@ -14,7 +14,11 @@ Scope (\_SB) {
 		#include "backlight.asl"
 
 #if CONFIG(DRIVERS_GFX_NVIDIA)
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(BOARD_SYSTEM76_BONW15)
+#if CONFIG(BOARD_SYSTEM76_BONW15)
+		Scope (PEG2) {
+			#include "../variants/bonw15/acpi/gpu.asl"
+		}
+#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_P)
 		Scope (PEG2) {
 			#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
 		}

src/mainboard/system76/rpl/cmos-csme.default

@@ -1,3 +0,0 @@
-boot_option=Fallback
-debug_level=Debug
-me_state=Enable

src/mainboard/system76/rpl/variants/addw3/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
-	# Support 5600 MT/s memory
-	register "max_dram_speed_mts" = "5600"
+	# Support 5200 MT/s memory
+	register "max_dram_speed_mts" = "5200"
 
 	device domain 0 on
 		subsystemid 0x1558 0xa671 inherit

src/mainboard/system76/rpl/variants/bonw15/acpi/dsm.asl

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NV_ERROR_SUCCESS 0x0
+#define NV_ERROR_UNSPECIFIED 0x80000001
+#define NV_ERROR_UNSUPPORTED 0x80000002
+
+#include "gps.asl"
+
+Method (_DSM, 4, Serialized) {
+	Printf("GPU _DSM")
+	If (Arg0 == ToUUID (GPS_DSM_GUID)) {
+		If (ToInteger(Arg1) == GPS_REVISION_ID) {
+			Return (GPS(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported GPS revision: %o", SFST(Arg1))
+			Return (NV_ERROR_UNSUPPORTED)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return (NV_ERROR_UNSPECIFIED)
+	}
+}

src/mainboard/system76/rpl/variants/bonw15/acpi/gps.asl

@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define GPS_DSM_GUID "A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID 0x00000200
+#define GPS_FUNC_SUPPORT 0x00000000
+#define GPS_FUNC_PSHARESTATUS 0x00000020
+#define GPS_FUNC_PSHAREPARAMS 0x0000002A
+
+Method(GPS, 2, Serialized) {
+	Printf("  GPU GPS")
+	Switch(ToInteger(Arg0)) {
+		Case(GPS_FUNC_SUPPORT) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << GPS_FUNC_SUPPORT) |
+				(1 << GPS_FUNC_PSHARESTATUS) |
+				(1 << GPS_FUNC_PSHAREPARAMS)
+			))
+		}
+		Case(GPS_FUNC_PSHARESTATUS) {
+			Printf("    Power Share Status")
+			Return(ITOB(0))
+		}
+		Case(GPS_FUNC_PSHAREPARAMS) {
+			Printf("    Power Share Parameters")
+
+			CreateField(Arg1, 0, 4, QTYP) // Query type
+
+			Name(GPSP, Buffer(36) { 0x00 })
+			CreateDWordField(GPSP, 0, RSTS) // Response status
+			CreateDWordField(GPSP, 4, VERS) // Version
+
+			// Set query type of response
+			RSTS = QTYP
+			// Set version of response
+			VERS = 0x00010000
+
+			Switch(ToInteger(QTYP)) {
+				Case(0) {
+					Printf("      Request Current Information")
+					// No required information
+					Return(GPSP)
+				}
+				Case(1) {
+					Printf("      Request Supported Fields")
+					// Support GPU temperature field
+					RSTS |= (1 << 8)
+					Return(GPSP)
+				}
+				Case(2) {
+					Printf("      Request Current Limits")
+					// No required limits
+					Return(GPSP)
+				}
+				Default {
+					Printf("      Unknown Query: %o", SFST(QTYP))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NV_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/mainboard/system76/rpl/variants/bonw15/acpi/gpu.asl

@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device (DEV0) {
+	Name(_ADR, 0x00000000)
+
+	#include "utility.asl"
+	#include "dsm.asl"
+}
+
+#if CONFIG(DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST)
+Scope (\_SB) {
+	Device(NPCF) {
+		#include "utility.asl"
+		#include "nvpcf.asl"
+	}
+}
+#endif

src/mainboard/system76/rpl/variants/bonw15/acpi/nvpcf.asl

@@ -0,0 +1,111 @@
+#define NVPCF_DSM_GUID "36b49710-2483-11e7-9598-0800200c9a66"
+#define NVPCF_REVISION_ID 0x00000200
+#define NVPCF_ERROR_SUCCESS 0x0
+#define NVPCF_ERROR_GENERIC 0x80000001
+#define NVPCF_ERROR_UNSUPPORTED 0x80000002
+#define NVPCF_FUNC_GET_SUPPORTED 0x00000000
+#define NVPCF_FUNC_GET_STATIC_CONFIG_TABLES 0x00000001
+#define NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS 0x00000002
+
+Name(_HID, "NVDA0820")
+
+Name(_UID, "NPCF")
+
+Method(_DSM, 4, Serialized) {
+	Printf("NVPCF _DSM")
+	If (Arg0 == ToUUID(NVPCF_DSM_GUID)) {
+		If (ToInteger(Arg1) == NVPCF_REVISION_ID) {
+			Return(NPCF(Arg2, Arg3))
+		} Else {
+			Printf("  Unsupported NVPCF revision: %o", SFST(Arg1))
+			Return(NVPCF_ERROR_GENERIC)
+		}
+	} Else {
+		Printf("  Unsupported GUID: %o", IDST(Arg0))
+		Return(NVPCF_ERROR_GENERIC)
+	}
+}
+
+Method(NPCF, 2, Serialized) {
+	Printf("  NVPCF NPCF")
+	Switch(ToInteger(Arg0)) {
+		Case(NVPCF_FUNC_GET_SUPPORTED) {
+			Printf("    Supported Functions")
+			Return(ITOB(
+				(1 << NVPCF_FUNC_GET_SUPPORTED) |
+				(1 << NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) |
+				(1 << NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS)
+			))
+		}
+		Case(NVPCF_FUNC_GET_STATIC_CONFIG_TABLES) {
+			Printf("    Get Static Config")
+			Return(Buffer(14) {
+				// Device table header
+				0x20, 0x03, 0x01,
+				// Intel + NVIDIA
+				0x00,
+				// Controller table header
+				0x23, 0x04, 0x05, 0x01,
+				// Dynamic boost controller
+				0x01,
+				// Supports DC
+				0x01,
+				// Reserved
+				0x00, 0x00, 0x00,
+				// Checksum
+				0xAD
+			})
+		}
+		Case(NVPCF_FUNC_UPDATE_DYNAMIC_PARAMS) {
+			Printf("    Update Dynamic Boost")
+
+			CreateField(Arg1, 0x28, 2, ICMD) // Input command
+
+			Name(PCFP, Buffer(49) {
+				// Table version
+				0x23,
+				// Table header size
+				0x05,
+				// Size of common status in bytes
+				0x10,
+				// Size of controller entry in bytes
+				0x1C,
+				// Other fields filled in later
+			})
+			CreateByteField(PCFP, 0x04, CCNT) // Controller count
+			CreateWordField(PCFP, 0x19, ATPP) // AC TPP offset
+			CreateWordField(PCFP, 0x1D, AMXP) // AC maximum TGP offset
+			CreateWordField(PCFP, 0x21, AMNP) // AC minimum TGP offset
+
+			Switch(ToInteger(ICMD)) {
+				Case(0) {
+					Printf("      Get Controller Params")
+					// Number of controllers
+					CCNT = 1
+					// AC total processor power offset from default TGP in 1/8 watt units
+					ATPP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP << 3)
+					// AC maximum TGP offset from default TGP in 1/8 watt units
+					AMXP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX << 3)
+					// AC minimum TGP offset from default TGP in 1/8 watt units
+					AMNP = (CONFIG_DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MIN << 3)
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Case(1) {
+					Printf("      Set Controller Status")
+					//TODO
+					Printf("PCFP: %o", SFST(PCFP))
+					Return(PCFP)
+				}
+				Default {
+					Printf("      Unknown Input Command: %o", SFST(ICMD))
+					Return(NV_ERROR_UNSUPPORTED)
+				}
+			}
+		}
+		Default {
+			Printf("    Unsupported function: %o", SFST(Arg0))
+			Return(NVPCF_ERROR_UNSUPPORTED)
+		}
+	}
+}

src/mainboard/system76/rpl/variants/bonw15/acpi/utility.asl

@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Convert a byte to a hex string, trimming extra parts
+Method (BHEX, 1) {
+	Local0 = ToHexString(Arg0)
+	Return (Mid(Local0, SizeOf(Local0) - 2, 2))
+}
+
+// UUID to string
+Method (IDST, 1) {
+	Local0 = ""
+	Fprintf(
+		Local0,
+		"%o%o%o%o-%o%o-%o%o-%o%o-%o%o%o%o%o%o",
+		BHEX(DerefOf(Arg0[3])),
+		BHEX(DerefOf(Arg0[2])),
+		BHEX(DerefOf(Arg0[1])),
+		BHEX(DerefOf(Arg0[0])),
+		BHEX(DerefOf(Arg0[5])),
+		BHEX(DerefOf(Arg0[4])),
+		BHEX(DerefOf(Arg0[7])),
+		BHEX(DerefOf(Arg0[6])),
+		BHEX(DerefOf(Arg0[8])),
+		BHEX(DerefOf(Arg0[9])),
+		BHEX(DerefOf(Arg0[10])),
+		BHEX(DerefOf(Arg0[11])),
+		BHEX(DerefOf(Arg0[12])),
+		BHEX(DerefOf(Arg0[13])),
+		BHEX(DerefOf(Arg0[14])),
+		BHEX(DerefOf(Arg0[15]))
+	)
+	Return (Local0)
+}
+
+// Safe hex conversion, checks type first
+Method (SFST, 1) {
+	Local0 = ObjectType(Arg0)
+	If (Local0 == 1 || Local0 == 2 || Local0 == 3) {
+		Return (ToHexString(Arg0))
+	} Else {
+		Return (Concatenate("Type: ", Arg0))
+	}
+}
+
+// Convert from 4-byte buffer to 32-bit integer
+Method (BTOI, 1) {
+	Return(
+		DerefOf(Arg0[0]) |
+		(DerefOf(Arg0[1]) << 8) |
+		(DerefOf(Arg0[2]) << 16) |
+		(DerefOf(Arg0[3]) << 24)
+	)
+}
+
+// Convert from 32-bit integer to 4-byte buffer
+Method (ITOB, 1) {
+	Local0 = Buffer(4) { 0, 0, 0, 0 }
+	Local0[0] = Arg0 & 0xFF
+	Local0[1] = (Arg0 >> 8) & 0xFF
+	Local0[2] = (Arg0 >> 16) & 0xFF
+	Local0[3] = (Arg0 >> 24) & 0xFF
+	Return (Local0)
+}

src/mainboard/system76/rpl/variants/bonw15/hda_verb.c

@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
 	0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
 	0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
 	0x02050027, 0x02040010, 0x02050028, 0x02040000,
-	0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
+	0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
 	0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
 	0x02050028, 0x02040000, 0x02050029, 0x0204c206,
 	0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,

src/mainboard/system76/rpl/variants/bonw15/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
-	# Support 5600 MT/s memory
-	register "max_dram_speed_mts" = "5600"
+	# Support 5200 MT/s memory
+	register "max_dram_speed_mts" = "5200"
 
 	device domain 0 on
 		subsystemid 0x1558 0x3702 inherit

src/mainboard/system76/rpl/variants/darp9/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/alderlake
-	register "s0ix_enable" = "1"
-
 	register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
 		.tdp_pl1_override = 20,
 		.tdp_pl2_override = 56,
@@ -16,11 +14,6 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST#
-				register "srcclk_pin" = "0" # SSD2_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref pcie4_1 on
 			# CPU RP#3 x4, Clock 4 (SSD1)
@@ -29,11 +22,6 @@ chip soc/intel/alderlake
 				.clk_req = 4,
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
-				register "srcclk_pin" = "4" # SSD1_CLKREQ#
-				device generic 0 on end
-			end
 		end
 		device ref tbt_pcie_rp0 on end
 		device ref tcss_xhci on

src/mainboard/system76/rpl/variants/oryp11/hda_verb.c

@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
 	0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
 	0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
 	0x02050027, 0x02040010, 0x02050028, 0x02040000,
-	0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
+	0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
 	0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
 	0x02050028, 0x02040000, 0x02050029, 0x0204c206,
 	0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,

src/mainboard/system76/rpl/variants/serw13/overridetree.cb

@@ -1,6 +1,6 @@
 chip soc/intel/alderlake
-	# Support 5600 MT/s memory
-	register "max_dram_speed_mts" = "5600"
+	# Support 5200 MT/s memory
+	register "max_dram_speed_mts" = "5200"
 
 	device domain 0 on
 		subsystemid 0x1558 0xd502 inherit

src/mainboard/system76/tgl-h/Kconfig

@@ -3,7 +3,6 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
-	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_GFX_NVIDIA

src/mainboard/system76/tgl-h/devicetree.cb

@@ -68,6 +68,9 @@ chip soc/intel/tigerlake
 	# rdmsr --bitfield 31:24 --decimal 0x1A2
 	register "tcc_offset" = "8"
 
+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
 # PM Util (soc/intel/tigerlake/pmutil.c)
 	# GPE configuration
 	register "pmc_gpe0_dw0" = "PMC_GPP_R"
@@ -100,8 +103,6 @@ chip soc/intel/tigerlake
 		# From PCH EDS(615985)
 		device ref shared_ram on end
 		device ref cnvi_wifi on
-			register "CnviBtCore" = true
-			register "CnviBtAudioOffload" = true
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end

src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c

@@ -18,7 +18,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	// Remap PEG2 as PEG1
 	params->CpuPcieRpFunctionSwap = 1;
-
-	// Enable reporting CPU C10 state over ESPI
-	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c

@@ -15,7 +15,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 	params->CpuPcieRpAdvancedErrorReporting[1] = 0;
 	params->CpuPcieRpLtrEnable[1] = 1;
 	params->CpuPcieRpPtmEnabled[1] = 0;
-
-	// Enable reporting CPU C10 state over ESPI
-	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-h/variants/oryp8/ramstage.c

@@ -21,7 +21,4 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params)
 
 	// Low latency legacy I/O
 	params->PchLegacyIoLowLatency = 1;
-
-	// Enable reporting CPU C10 state over ESPI
-	params->PchEspiHostC10ReportEnable = 1;
 }

src/mainboard/system76/tgl-u/Kconfig

@@ -3,7 +3,6 @@ if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
-	select DRIVERS_GENERIC_BAYHUB_LV2
 	select DRIVERS_GENERIC_CBFS_SERIAL
 	select DRIVERS_GENERIC_CBFS_UUID
 	select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5

src/mainboard/system76/tgl-u/devicetree.cb

@@ -62,6 +62,9 @@ chip soc/intel/tigerlake
 	# Thermal
 	register "tcc_offset" = "12"
 
+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
 # Actual device tree
 	device cpu_cluster 0 on
 		device lapic 0 on end
@@ -87,8 +90,6 @@ chip soc/intel/tigerlake
 		device ref gna on end
 		device ref shared_ram on end
 		device ref cnvi_wifi on
-			register "CnviBtCore" = true
-			register "CnviBtAudioOffload" = true
 			chip drivers/wifi/generic
 				register "wake" = "GPE0_PME_B0"
 				device generic 0 on end

src/soc/intel/alderlake/cpu.c

@@ -301,10 +301,10 @@ uint8_t get_supported_lpm_mask(void)
 	case ADL_M: /* fallthrough */
 	case ADL_N:
 	case ADL_P:
+	case RPL_HX:
 	case RPL_P:
 		return LPM_S0i2_0 | LPM_S0i3_0;
 	case ADL_S:
-	case RPL_HX:
 		return LPM_S0i2_0 | LPM_S0i2_1;
 	default:
 		printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type);

src/soc/intel/alderlake/include/soc/gpio.h

@@ -5,13 +5,8 @@
 
 #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
 #include <soc/gpio_defs_pch_s.h>
-#if CONFIG(SOC_INTEL_RAPTORLAKE)
-#define CROS_GPIO_NAME		"INTC1085"
-#define CROS_GPIO_DEVICE_NAME	"INTC1085:00"
-#else
 #define CROS_GPIO_NAME		"INTC1056"
 #define CROS_GPIO_DEVICE_NAME	"INTC1056:00"
-#endif
 #elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
 #include <soc/gpio_defs.h>
 #define CROS_GPIO_NAME		"INTC1057"

src/soc/intel/alderlake/include/soc/iomap.h

@@ -20,14 +20,8 @@
 #define PCH_TRACE_HUB_BASE_SIZE	0x00800000
 #endif
 
-/* Hack to include SBREG in PCH_RESERVED region on ADL-S/RPL-S */
-#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
-#define PCH_PRESERVED_BASE_ADDRESS	0xe0000000
-#define PCH_PRESERVED_BASE_SIZE		0x1e800000
-#else
 #define PCH_PRESERVED_BASE_ADDRESS	0xfc800000
 #define PCH_PRESERVED_BASE_SIZE		0x02000000
-#endif
 
 #define UART_BASE_SIZE		0x1000