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Author SHA1 Message Date
Tim Crawford
70a16fed07 mb/system76/adl: galp6: Fix GLAN RTD3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I9d5cf318dcbbe4bda916b1a17469e1ad6b6b58e4
2023-10-12 11:45:09 -06:00
11 changed files with 8 additions and 36 deletions

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@@ -108,10 +108,6 @@ config MAINBOARD_VERSION
default "oryp9" if BOARD_SYSTEM76_ORYP9
default "oryp10" if BOARD_SYSTEM76_ORYP10
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP8
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
config CONSOLE_POST
default y

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@@ -1,3 +0,0 @@
boot_option=Fallback
debug_level=Debug
me_state=Enable

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@@ -1,6 +1,4 @@
chip soc/intel/alderlake
register "s0ix_enable" = "1"
register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 56,

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@@ -7,7 +7,7 @@ static const struct pad_config gpio_table[] = {
/* ------- GPIO Group GPD ------- */
PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP#
PAD_NC(GPD2, NONE),
PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
@@ -16,7 +16,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN#
PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE#
PAD_NC(GPD11, NONE),
/* ------- GPIO Group GPP_A ------- */
PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
@@ -41,7 +41,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R
PAD_NC(GPP_A20, NONE),
PAD_NC(GPP_A21, NONE),
PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN
PAD_NC(GPP_A22, NONE),
PAD_NC(GPP_A23, NONE),
/* ------- GPIO Group GPP_B ------- */
@@ -76,7 +76,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap
PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
PAD_CFG_GPO(GPP_C5, 1, PLTRST), // ESPI OR EC LESS strap
PAD_CFG_GPO(GPP_C5, 1, PLTRST), // GPIO_LANRTD3
PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL
PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA
// GPP_C8 missing
@@ -152,7 +152,7 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
// GPP_F5 (CNVI_CLKREQ) programmed by FSP
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST#
PAD_CFG_GPO(GPP_F7, 1, PLTRST), // LAN_PLT_RST#
// GPP_F8 missing
PAD_NC(GPP_F9, NONE),
PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST#

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@@ -165,6 +165,7 @@ chip soc/intel/alderlake
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C5)" # GPIO_LANRTD3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST#
register "srcclk_pin" = "6" # LAN_CLKREQ#
device generic 0 on end

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@@ -133,10 +133,6 @@ config MAINBOARD_VERSION
default "oryp11" if BOARD_SYSTEM76_ORYP11
default "serw13" if BOARD_SYSTEM76_SERW13
config CMOS_DEFAULT_FILE
default "src/mainboard/\$(MAINBOARDDIR)/cmos-csme.default" if BOARD_SYSTEM76_DARP9
default "src/mainboard/\$(MAINBOARDDIR)/cmos.default"
config CONSOLE_POST
default y

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@@ -1,3 +0,0 @@
boot_option=Fallback
debug_level=Debug
me_state=Enable

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@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c206,
0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,

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@@ -1,6 +1,4 @@
chip soc/intel/alderlake
register "s0ix_enable" = "1"
register "power_limits_config[RPL_P_682_482_282_28W_CORE]" = "{
.tdp_pl1_override = 20,
.tdp_pl2_override = 56,
@@ -16,11 +14,6 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD2_RST#
register "srcclk_pin" = "0" # SSD2_CLKREQ#
device generic 0 on end
end
end
device ref pcie4_1 on
# CPU RP#3 x4, Clock 4 (SSD1)
@@ -29,11 +22,6 @@ chip soc/intel/alderlake
.clk_req = 4,
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST#
register "srcclk_pin" = "4" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref tbt_pcie_rp0 on end
device ref tcss_xhci on

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@@ -126,7 +126,7 @@ const u32 cim_verb_data[] = {
0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
0x02050027, 0x02040010, 0x02050028, 0x02040000,
0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
0x02050029, 0x0204c203, 0x0205002b, 0x02040084,
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
0x02050028, 0x02040000, 0x02050029, 0x0204c206,
0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,

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@@ -3,7 +3,6 @@ if BOARD_SYSTEM76_DARP7 || BOARD_SYSTEM76_GALP5 || BOARD_SYSTEM76_LEMP10
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select DRIVERS_GENERIC_BAYHUB_LV2
select DRIVERS_GENERIC_CBFS_SERIAL
select DRIVERS_GENERIC_CBFS_UUID
select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_GALP5