mb/system76/gaze16: 3060: Add variant for I219-V GbE

Some models use Intel I219-V instead of the Realtek RTL8111 controller.
Introduce a new variant so the IFD of the Realtek board does not have
the onboard LAN enabled when it is not connected.

Change-Id: I1961a7a8fac2dc6e81ebae013ff62cd491fba43c
Signed-off-by: Tim Crawford <tcrawford@system76.com>

.checkpatch.conf

@@ -20,8 +20,6 @@
 --ignore SPDX_LICENSE_TAG
 --ignore UNDOCUMENTED_DT_STRING
 --ignore PRINTK_WITHOUT_KERN_LEVEL
---ignore ASSIGN_IN_IF
---ignore UNNECESSARY_ELSE
 
 # FILE_PATH_CHANGES seems to not be working correctly. It will
 # choke on added / deleted files even if the MAINTAINERS file
@@ -32,8 +30,5 @@
 # some commits unnecessarily.
 --ignore EXECUTE_PERMISSIONS
 
-# Exclude vendorcode directories that don't follow coreboot's coding style.
---exclude src/vendorcode/amd
---exclude src/vendorcode/cavium
---exclude src/vendorcode/intel
---exclude src/vendorcode/mediatek
+# Exclude the vendorcode directory
+--exclude src/vendorcode

.gitmodules

@@ -1,61 +1,60 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
-	branch = main
+	url = https://review.coreboot.org/vboot.git
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

Documentation/RFC/intel-gpio-cleanup.md

@@ -1,98 +0,0 @@
-# Background
-
-CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is
-done") introduced a workaround in coreboot for `soc/intel/cannonlake`
-platforms to save and restore GPIO configuration performed by
-mainboard across call to FSP Silicon Init (FSP-S). This workaround was
-required because FSP-S was configuring GPIOs differently than
-mainboard resulting in boot and runtime issues because of
-misconfigured GPIOs. This issue was observed on `google/hatch`
-mainboard and was raised with Intel to get the FSP behavior
-fixed. Until the fix in FSP was available, this workaround was used to
-ensure that the mainboards can operate correctly and were not impacted
-by the GPIO misconfiguration in FSP-S.
-
-The issues observed on `google/hatch` mainboard were fixed by adding
-(if required) and initializing appropriate FSP UPDs. This UPD
-initialization ensured that FSP did not configure any GPIOs
-differently than the mainboard configuration. Fixes included:
- * CB:31375 ("soc/intel/cannonlake: Configure serial debug uart")
- * CB:31520 ("soc/intel/cannonlake: Assign FSP UPDs for HPD and Data/CLK of DDI ports")
- * CB:32176 ("mb/google/hatch: Update GPIO settings for SD card and SPI1 Chip select")
- * CB:34900 ("soc/intel/cnl: Add provision to configure SD controller write protect pin")
-
-With the above changes merged, it was verified on `google/hatch`
-mainboard that the workaround for GPIO reconfiguration was not
-needed. However, at the time, we missed dropping the workaround in
-'soc/intel/cannonlake`. Currently, this workaround is used by the
-following mainboards:
- * `google/drallion`
- * `google/sarien`
- * `purism/librem_cnl`
- * `system76/lemp9`
-
-As verified on `google/hatch`, FSP v1263 included all UPD additions
-that were required for addressing this issue.
-
-# Proposal
-
-* The workaround can be safely dropped from `soc/intel/cannonlake`
-  only after the above mainboards have verified that FSP-S does not
-  configure any pads differently than the mainboard in coreboot. Since
-  the fix included initialization of FSP UPDs correctly, the above
-  mainboards can use the following diff to check what pads change
-  after FSP-S has run:
-
-```
-diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c
-index 28e78fb366..0cce41b316 100644
---- a/src/soc/intel/common/block/gpio/gpio.c
-+++ b/src/soc/intel/common/block/gpio/gpio.c
-@@ -303,10 +303,10 @@ static void gpio_configure_pad(const struct pad_config *cfg)
-                /* Patch GPIO settings for SoC specifically */
-                soc_pad_conf = soc_gpio_pad_config_fixup(cfg, i, soc_pad_conf);
- 
--               if (CONFIG(DEBUG_GPIO))
-+               if (soc_pad_conf != pad_conf)
-                        printk(BIOS_DEBUG,
--                       "gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
--                       " : 0x%08x]\n",
-+                       "%d: gpio_padcfg [0x%02x, %02zd] DW%d [0x%08x : 0x%08x"
-+                       " : 0x%08x]\n", cfg->pad,
-                        comm->port, relative_pad_in_comm(comm, cfg->pad), i,
-                        pad_conf,/* old value */
-                        cfg->pad_config[i],/* value passed from gpio table */
-```
-
-Depending upon the pads that are misconfigured by FSP-S, these
-mainboards will have to set UPDs appropriately. Once this is verified
-by the above mainboards, the workaround implemented in CB:31250 can be
-dropped.
-
-* The fix implemented in FSP/coreboot for `soc/intel/cannonlake`
-  platforms is not really the right long term solution for the
-  problem. Ideally, FSP should not be touching any GPIO configuration
-  and letting coreboot configure the pads as per mainboard
-  design. This recommendation was accepted and implemented by Intel
-  starting with Jasper Lake and Tiger Lake platforms using a single
-  UPD `GpioOverride` that coreboot can set so that FSP does not change
-  any GPIO configuration. However, this implementation is not
-  backported to any older platforms. Given the issues that we have
-  observed across different platforms, the second proposal is to:
-
-  - Add a Kconfig `CHECK_GPIO_CONFIG_CHANGES` that enables checks
-    in coreboot to stash GPIO pad configuration before various calls
-    to FSP and compares the configuration on return from FSP.
-  - This will have to be implemented as part of
-    drivers/intel/fsp/fsp2_0/ to check for the above config selection
-    and make callbacks `gpio_snapshot()` and `gpio_verify_snapshot()`
-    to identify and print information about pads that have changed
-    configuration after calls to FSP.
-  - This config can be kept disabled by default and mainboard
-    developers can enable them as and when required for debug.
-  - This will be helpful not just for the `soc/intel/cannonlake`
-    platforms that want to get rid of the above workaround, but also
-    for all future platforms using FSP to identify and catch any GPIO
-    misconfigurations that might slip in to any platforms (in case the
-    `GpioOverride` UPD is not honored by any code path within FSP).
-

Documentation/acpi/devicetree.md

@@ -30,7 +30,7 @@ device pci 15.0 on
 	chip drivers/i2c/generic
 		register "hid" = ""ELAN0000""
 		register "desc" = ""ELAN Touchpad""
-		register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+		register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
 		register "wake" = "GPE0_DW0_21"
 		device i2c 15 on end
 	end
@@ -60,12 +60,12 @@ Scope (\_SB.PCI0.I2C0)
             I2cSerialBusV2 (0x0015, ControllerInitiated, 400000,
                 AddressingMode7Bit, "\\_SB.PCI0.I2C0",
                 0x00, ResourceConsumer, , Exclusive, )
-            Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+            Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
             {
                 0x0000002D,
             }
         })
-        Name (_S0W, ACPI_DEVICE_SLEEP_D3_HOT)  // _S0W: S0 Device Wake State
+        Name (_S0W, 0x04)  // _S0W: S0 Device Wake State
         Name (_PRW, Package (0x02)  // _PRW: Power Resources for Wake
         {
             0x15, // GPE #21
@@ -136,7 +136,7 @@ corresponds to **const char *desc** and in ASL:
 It also adds the interrupt,
 
 ```
-    Interrupt (ResourceConsumer, Level, ActiveLow, ExclusiveAndWake, ,, )
+    Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, ,, )
     {
         0x0000002D,
     }
@@ -145,15 +145,15 @@ It also adds the interrupt,
 which comes from:
 
 ```
-    register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A21_IRQ)"
+    register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)"
 ```
 
-The GPIO pin IRQ settings control the "Level", "ActiveLow", and
-"ExclusiveAndWake" settings seen above (level means it is a level-triggered
-interrupt as opposed to edge-triggered; active low means the interrupt is
-triggered when the signal is low).
+The GPIO pin IRQ settings control the "Edge", "ActiveLow", and
+"ExclusiveAndWake" settings seen above (edge means it is an edge-triggered
+interrupt as opposed to level-triggered; active low means the interrupt is
+triggered on a falling edge).
 
-Note that the ACPI_IRQ_WAKE_LEVEL_LOW macro informs the platform that the GPIO
+Note that the ACPI_IRQ_WAKE_EDGE_LOW macro informs the platform that the GPIO
 will be routed through SCI (ACPI's System Control Interrupt) for use as a wake
 source.  Also note that the IRQ names are SoC-specific, and you will need to
 find the names in your SoC's header file.  The ACPI_* macros are defined in
@@ -196,7 +196,7 @@ for more details on ACPI methods)
 
 ### _S0W (S0 Device Wake State)
 _S0W indicates the deepest S0 sleep state this device can wake itself from,
-which in this case is ACPI_DEVICE_SLEEP_D3_HOT, representing _D3hot_.
+which in this case is 4, representing _D3cold_.
 
 ### _PRW (Power Resources for Wake)
 _PRW indicates the power resources and events required for wake.  There are no

Documentation/acpi/gpio.md

@@ -159,6 +159,7 @@ for the GPIO.
 	 */
 	acpigen_write_if_and(Local5, TX_BIT);
 	acpigen_write_store_args(ONE_OP, LOCAL0_OP);
+	acpigen_pop_len();
 	acpigen_write_else();
 	acpigen_write_store_args(ZERO_OP, LOCAL0_OP);
 	acpigen_pop_len();

Documentation/coding_style.md

@@ -5,26 +5,12 @@ coreboot project. It is in many ways exactly the same as the Linux
 kernel coding style. In fact, most of this document has been copied from
 the [Linux kernel coding style](http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/plain/Documentation/CodingStyle?id=HEAD)
 
-The guidelines in this file should be seen as a strong suggestion, and
-should overrule personal preference. But they may be ignored in
-individual instances when there are good practical reasons to do so, and
-reviewers are in agreement.
+Please at least consider the points made here.
 
-Any style questions that are not mentioned in here should be decided
-between the author and reviewers on a case-by-case basis. When modifying
-existing files, authors should try to match the prevalent style in that
-file -- otherwise, they should try to match similar existing files in
-coreboot.
+First off, I'd suggest printing out a copy of the GNU coding standards,
+and NOT read it. Burn them, it's a great symbolic gesture.
 
-Bulk style changes to existing code ("cleanup patches") should avoid
-changing existing style choices unless they actually violate this style
-guide, or there is broad consensus that the new version is an
-improvement. By default the style choices of the original author should
-be honored. (Note that `checkpatch.pl` is not part of this style guide,
-and neither is `clang-format`. These tools can be useful to find
-potential issues or simplify formatting in new submissions, but they
-were not designed to directly match this guide and may have false
-positives. They should not be bulk-applied to change existing code.)
+Anyway, here goes:
 
 ## Indentation
 
@@ -544,7 +530,7 @@ than desirable (in fact, they are worse than random typing - an infinite
 number of monkeys typing into GNU emacs would never make a good program).
 
 So, you can either get rid of GNU emacs, or change it to use saner values.
-To do the latter, you can stick the following in your .emacs file:
+To do the latter, you can stick the following in your .emacs file: 
 
 ```lisp
 (defun c-lineup-arglist-tabs-only (ignored)
@@ -848,53 +834,22 @@ subject to this rule. Generally they indicate failure by returning some
 out-of-range result. Typical examples would be functions that return
 pointers; they use NULL or the ERR_PTR mechanism to report failure.
 
-Headers and includes
----------------
+Don't re-invent the kernel macros
+----------------------------------
 
-Headers should always be included at the top of the file. Includes should
-always use the `#include <file.h>` notation, except for rare cases where a file
-in the same directory that is not part of a normal include path gets included
-(e.g. local headers in mainboard directories), which should use `#include
-"file.h"`. Local "file.h" includes should always come separately after all
-<file.h> includes.  Headers that can be included from both assembly files and
-.c files should keep all C code wrapped in `#ifndef __ASSEMBLER__` blocks,
-including includes to other headers that don't follow that provision. Where a
-specific include order is required for technical reasons, it should be clearly
-documented with comments.
-
-Files should generally include every header they need a definition from
-directly (and not include any unnecessary extra headers). Excepted from
-this are certain headers that intentionally chain-include other headers
-which logically belong to them and are just factored out into a separate
-location for implementation or organizatory reasons. This could be
-because part of the definitions is generic and part SoC-specific (e.g.
-`<gpio.h>` chain-including `<soc/gpio.h>`), architecture-specific (e.g.
-`<device/mmio.h>` chain-including `<arch/mmio.h>`), separated out into
-commonlib[/bsd] for sharing/license reasons (e.g. `<cbfs.h>`
-chain-including `<commonlib/bsd/cbfs_serialized.h>`) or just split out
-to make organizing subunits of a larger header easier. This can also
-happen when certain definitions need to be in a specific header for
-legacy POSIX reasons but we would like to logically group them together
-(e.g. `uintptr_t` is in `<stdint.h>` and `size_t` in `<stddef.h>`, but
-it's nicer to be able to just include `<types.h>` and get all the common
-type and helper function stuff we need everywhere).
-
-The headers `<kconfig.h>`, `<rules.h>` and `<commonlib/bsd/compiler.h>`
-are always automatically included in all compilation units by the build
-system and should not be included manually.
-
-Don't re-invent common macros
------------------------------
-
-The header file `src/commonlib/bsd/include/commonlib/bsd/helpers.h`
-contains a number of macros that you should use, rather than explicitly
-coding some variant of them yourself. For example, if you need to
-calculate the length of an array, take advantage of the macro
+The header file include/linux/kernel.h contains a number of macros that
+you should use, rather than explicitly coding some variant of them
+yourself. For example, if you need to calculate the length of an array,
+take advantage of the macro
 
 ```c
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 ```
 
+There are also min() and max() macros that do strict type checking if
+you need them. Feel free to peruse that header file to see what else is
+already defined that you shouldn't reproduce in your code.
+
 Editor modelines and other cruft
 --------------------------------
 

Documentation/community/forums.md

@@ -16,20 +16,3 @@ read its
 We also have a
 [real time chat](https://webchat.freenode.net?channels=%23coreboot)
 on the Freenode IRC network's #coreboot channel.
-
-## Fortnightly coreboot leadership meeting
-
-There's a leadership meeting held every 14 days (currently every other
-Wednesday at 10am Pacific Time, usually 18:00 UTC with some deviation
-possible due to daylight saving time related shifts). The meeting
-is open to everyone and provides a forum to discuss general coreboot
-topics, including community and technical matters that benefit from
-an official decision.
-
-We tried a whole lot of different tools, but so far the meetings worked
-best with [Google Meet](https://meet.google.com/syn-toap-agu),
-using [Google Docs](https://docs.google.com/document/d/1NRXqXcLBp5pFkHiJbrLdv3Spqh1Hu086HYkKrgKjeDQ/edit)
-for the agenda and meeting minutes. Neither the video conference nor
-the document require a Google account to participate, although editing
-access to the document is limited to adding comments - any desired
-agenda item added that way will be approved in time before the meeting.

Documentation/getting_started/gerrit_guidelines.md

@@ -320,35 +320,6 @@ is criticising your code, but the whole idea is to get better code into our
 codebase. Again, this also applies in the other direction: review code,
 criticize code, but don’t make it personal.
 
-Gerrit user roles
------------------
-There are a few relevant roles a user can have on Gerrit:
-
-- The anonymous user can check out source code.
-- A registered user can also comment and give "+1" and "-1" code reviews.
-- A reviewer can also give "+2" code reviews.
-- A core developer can also give "-2" (that is, blocking) code reviews
-  and submit changes.
-
-Anybody can register an account on our instance, using either an
-OpenID provider or OAuth through GitHub or Google.
-
-The reviewer group is still quite open: Any core developer can add
-registered users to that group and should do so once some activity
-(commits, code reviews, and so on) has demonstrated rough knowledge
-of how we handle things.
-
-A core developer should be sufficiently well established in the
-community so that they feel comfortable when submitting good patches,
-when asking for improvements to less good patches and reasonably
-uncomfortable when -2'ing patches. They're typically the go-to
-person for _some_ part of the coreboot tree and ideally listed as its
-maintainer in our MAINTAINERS registry. To become part of this group,
-a candidate developer who already demonstrated proficiency with the
-code base as a reviewer should be nominated, by themselves or others,
-at the regular [coreboot leadership meetings](../community/forums.md)
-where a decision is made.
-
 
 Requests for clarification and suggestions for updates to these guidelines
 should be sent to the coreboot mailing list at <coreboot@coreboot.org>.

Documentation/getting_started/gpio.md

@@ -129,13 +129,3 @@ If no pullup or pulldown is declared with these, they may end up "floating",
 i.e., not at logical high or logical low. This can cause problems such as
 unwanted power consumption or not reading the pin correctly, if it was intended
 to be strapped.
-
-## Pad-related known issues and workarounds
-
-### LPC_CLKRUNB blocks S0ix states when board uses eSPI
-
-When using eSPI, the pad implementing `LPC_CLKRUNB` must be set to GPIO mode.
-Other pin settings i.e. Rx path enable/disable, Tx path enable/disable, pull up
-enable/disable etc are ignored. Leaving this pin in native mode will keep the
-LPC Controller awake and prevent S0ix entry. This issues is know at least on
-Apollolake and Geminilake.

Documentation/getting_started/kconfig.md

@@ -607,7 +607,7 @@ int <expr> \[if <expr>\]
 
 
 ##### Example:
-    config PRE_GRAPHICS_DELAY_MS
+    config PRE_GRAPHICS_DELAY
         int "Graphics initialization delay in ms"
         default 0
         help

Documentation/ifdtool/layout.md

@@ -19,7 +19,7 @@ way to categorize anything required by the SoC but not provided by coreboot.
 | IFD Region | IFD Region name  | FMAP Name | Notes                                     |
 | index      |                  |           |                                           |
 +============+==================+===========+===========================================+
-| 0          | Flash Descriptor | SI_DESC   | Always the top 4 KiB of flash             |
+| 0          | Flash Descriptor | SI_DESC   | Always the top 4KB of flash               |
 +------------+------------------+-----------+-------------------------------------------+
 | 1          | BIOS             | SI_BIOS   | This is the region that contains coreboot |
 +------------+------------------+-----------+-------------------------------------------+
@@ -40,9 +40,9 @@ way to categorize anything required by the SoC but not provided by coreboot.
 The ifdtool can be used to manipulate a firmware image with a IFD. This tool
 will not take into account the FMAP while modifying the image which can lead to
 unexpected and hard to debug issues with the firmware image. For example if the
-ME region is defined at 6 MiB in the IFD but the FMAP only allocates 4 MiB for
-the ME, then when the ME is added by the ifdtool 6 MiB will be written which
-could overwrite 2 MiB of the BIOS.
+ME region is defined at 6 MB in the IFD but the FMAP only allocates 4 MB for the
+ME, then when the ME is added by the ifdtool 6 MB will be written which could
+overwrite 2 MB of the BIOS.
 
 In order to validate that the FMAP and the IFD are compatible the ifdtool
 provides --validate (-t) option. `ifdtool -t` will read both the IFD and the
@@ -75,4 +75,4 @@ Region mismatch between pd and SI_PDR
  FMAP area SI_PDR:
   offset: 0x007fc000
   length: 0x00004000
-```
+```

Documentation/index.md

@@ -162,7 +162,7 @@ Contents:
 
 * [Getting Started](getting_started/index.md)
 * [Tutorial](tutorial/index.md)
-* [Coding Style](contributing/coding_style.md)
+* [Coding Style](coding_style.md)
 * [Project Ideas](contributing/project_ideas.md)
 * [Documentation Ideas](contributing/documentation_ideas.md)
 * [Code of Conduct](community/code_of_conduct.md)
@@ -187,6 +187,5 @@ Contents:
 * [SuperIO](superio/index.md)
 * [Vendorcode](vendorcode/index.md)
 * [Utilities](util.md)
-* [coreboot infrastructure](infrastructure/index.md)
 * [Release notes for past releases](releases/index.md)
 * [Flashing firmware tutorial](flash_tutorial/index.md)

Documentation/infrastructure/builders.md

@@ -1,392 +0,0 @@
-# Jenkins builder setup and configuration
-
-## How to set up a new jenkins builder
-
-### Contact a jenkins admin
-
-Let a jenkins admin know that you’re interested in setting up a jenkins
-build system.
-
-For a permanent build system, this should generally be a dedicated
-machine that is not generally being used for other purposes.  The
-coreboot builds are very intensive.
-
-It's also best to be aware that although we don't know of any security
-issues, the jenkins-node image is run with the privileged flag which
-gives the container root access to the build machine.  See
-[this article](https://blog.trendmicro.com/trendlabs-security-intelligence/why-running-a-privileged-container-in-docker-is-a-bad-idea/)
-about why this is discouraged.
-
-It's recommended that you give an admin root access on your machine so
-that they can reset it in case of a failure.  This is not a requirement,
-as the system can just be disabled until someone is available to fix any
-issues.
-
-Currently active Jenkins admins:
-*   Patrick Georgi:
-    *   Email: [patrick@georgi-clan.de](mailto:patrick@georgi-clan.de)
-    *   IRC: pgeorgi
-
-
-### Build Machine requirements
-
-For a builder, we need a fast system with lots of threads and plenty of
-RAM.  The builder builds and stores the git repos and output in tmpfs
-along with the ccache save area, so if there isn't enough memory, the
-builds will slow down because of smaller ccache areas and can run into
-"out of storage space" errors.
-
-#### Current Build Machines
-
-To give an idea of what a suitable build machine might be, currently the
-coreboot project has 3 active jenkins build machines.
-
-* Congenialbuilder - 128 threads, 256GiB RAM
-  *  Fastest Passing coreboot gerrit build: 4 min, 30 sec
-  *  Slowest Passing coreboot gerrit build: 9 min, 56 sec
-
-
-* Gleeful builder - 64 thread, 64GiB RAM
-  *  Fastest Passing coreboot gerrit build: 6 min, 6 sec
-  *  Slowest Passing coreboot gerrit build, 34 min
-
-
-* Ultron (9elements) - 48 threads, 128GiB RAM
-  *  Fastest Passing coreboot gerrit build: 6 min, 32 sec
-  *  Slowest Passing coreboot gerrit build: 44 min
-
-
-### Jenkins Builds
-
-There are a number of builds handled by the coreboot jenkins builders,
-for a number of different projects - coreboot, flashrom, memtest86+,
-em100, etc.  Many of these have builders for their current master branch
-as well as gerrit and coverity builds.
-
-You can see all the builds here:
-[https://qa.coreboot.org/](https://qa.coreboot.org/)
-
-Most of the time on the builders is taken up by the coreboot master and
-gerrit builds.
-
-* [coreboot gerrit build](https://qa.coreboot.org/job/coreboot-gerrit/)
-([Time trend](https://qa.coreboot.org/job/coreboot-gerrit/buildTimeTrend))
-
-
-* [coreboot master build](https://qa.coreboot.org/job/coreboot/)
- ([Time trend](https://qa.coreboot.org/job/coreboot/buildTimeTrend))
-
-
-### Stress test the machine
-
-Test the machine to make sure that building won't stress the hardware
-too much.  Install stress-ng, then run the stress test for at least an
-hour.
-
-On a system with 32 cores, it was tested with this command:
-
-```
-$ stress-ng --cpu 20 --io 6 --vm 6 --vm-bytes 1G --verify --metrics-brief -t 60m
-```
-
-You can watch the temperature with the sensors package or with ‘acpi -t’
-if your machine supports that.
-
-You can check for thermal throttling by running this command and seeing
-if the values go down on any of the cores after it's been running for a
-while.
-
-```
-$ while [ true ]; do clear; cat /proc/cpuinfo | grep 'cpu MHz' ; sleep 1; done
-```
-
-If the machine throttles or resets, you probably need to upgrade the
-cooling system.
-
-
-## jenkins-server docker installation
-
-
-### Manual Installation
-
-If you’ve met all the above requirements, and an admin has agreed to set
-up the builder in jenkins, you’re ready to go on to the next steps.
-
-
-### Set up your network so jenkins can talk to the container
-
-Expose a local port through any firewalls you might have on your router.
-This would generally be in the port forwarding section, and you'd just
-forward a port (typically 49151) from the internet directly to the
-builder’s IP address.
-
-You might also want to set up a port to forward to port 22 on your
-machine and set up openssh so you or the jenkins admins can manage
-the machine remotely (if you allow them).
-
-
-### Install and set up docker
-
-Install docker by following the
-[directions](https://docs.docker.com/engine/install/) on the docker
-site.  These instructions keep changing, so just check the latest
-information.
-
-
-#### Set up environment variables
-
-To make configuration and the later commands easier, these should go in
-your shell's .rc file.  Note that you only need to set them if you're
-using something other than the default.
-
-```
-# Set the port used on your machine to connect to jenkins.
-export COREBOOT_JENKINS_PORT=49151
-
-# Set the revision of the container from docker hub
-export DOCKER_COMMIT=65718760fa
-
-# Set the location of where the jenkins cache directory will be.
-export COREBOOT_JENKINS_CACHE_DIR="/srv/docker/coreboot-builder/cache"
-
-# Set the name of the container
-export COREBOOT_JENKINS_CONTAINER="coreboot_jenkins"
-```
-
-Make sure any variables needed are set in your environment before
-continuing to the next step.
-
-
-### Using the Makefile for docker installation
-
-From the coreboot directory, run
-
-```
-make -C util/docker help
-```
-
-This will show you the available targets and variables needed:
-
-```
-Commands for working with docker images:
-  coreboot-sdk                 - Build coreboot-sdk container
-  upload-coreboot-sdk          - Upload coreboot-sdk to hub.docker.com
-  coreboot-jenkins-node        - Build coreboot-jenkins-node container
-  upload-coreboot-jenkins-node - Upload coreboot-jenkins-node to hub.docker.com
-  doc.coreboot.org             - Build doc.coreboot.org container
-  clean-coreboot-containers    - Remove all docker coreboot containers
-  clean-coreboot-images        - Remove all docker coreboot images
-  docker-clean                 - Remove docker coreboot containers & images
-
-Commands for using docker images
-  docker-build-coreboot        - Build coreboot under coreboot-sdk
-      <BUILD_CMD=target>
-  docker-abuild                - Run abuild under coreboot-sdk
-      <ABUILD_ARGS='-a -B'>
-  docker-what-jenkins-does     - Run 'what-jenkins-does' target
-  docker-shell                 - Bash prompt in coreboot-jenkins-node
-      <USER=root or USER=coreboot>
-  docker-jenkins-server        - Run coreboot-jenkins-node image (for server)
-  docker-jenkins-attach        - Open shell in running jenkins server
-  docker-build-docs            - Build the documentation
-  docker-livehtml-docs         - Run sphinx-autobuild
-
-Variables:
-  COREBOOT_JENKINS_PORT=49151
-  COREBOOT_JENKINS_CACHE_DIR=/srv/docker/coreboot-builder/cache
-  COREBOOT_JENKINS_CONTAINER=coreboot_jenkins
-  COREBOOT_IMAGE_TAG=f2741aa632f
-  DOCKER_COMMIT=65718760fa
-```
-
-### Set up the system for the jenkins builder
-
-As a regular user - *Not root*, run:
-
-```
-sudo mkdir -p ${COREBOOT_JENKINS_CACHE_DIR}
-sudo mkdir -p ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CCACHE_DIR}
-sudo chown $(whoami):$(whoami) ${COREBOOT_JENKINS_CACHE_DIR}
-wget http://www.dediprog.com/save/78.rar/to/EM100Pro.rar
-mv EM100Pro.rar ${COREBOOT_JENKINS_CACHE_DIR}
-```
-
-### Install the coreboot jenkins builder
-
-```
-make -C util/docker docker-jenkins-server
-```
-
-Your installation is complete on your side.
-
-### Tell the Admins that the machine is set up
-Let the admins know that the builder is set up so they can set up the
-machine profile on qa.coreboot.org.
-
-They need to know:
-*   Your external IP address or domain name.  If you don’t have a static
-IP, make sure you have a dynamic dns hostname configured.
-*   The port on your machine and firewall that’s exposed for jenkins:
-`$COREBOOT_JENKINS_PORT`
-*   The core count of the machine.
-*   How much memory is available on the machine.  This helps determine
-the amount of memory used for ccache.
-
-
-### First build
-On the first build after a machine is reset, it will frequently take
-20-25 minutes to do the entire what-jenkins-does build while the ccache
-is getting filled up and the entire coreboot repo gets downloaded.  As
-the ccache gets populated, the build time will drop.
-
-
-## Additional Information
-
-
-### How to log in to the docker instance for debugging
-```
-    $ make -C util/docker docker-jenkins-attach
-    $ su coreboot
-    $ cd ~/slave-root/workspace
-    $ bash
-```
-
-
-WARNING: This should not be used to make changes to the build system,
-but just to debug issues. Changes to the build system are highly
-discouraged as it leads to situations where patches can pass the build
-testing on one builder and fail on another builder. Any changes that are
-made in the image will be lost on the next update, so if you
-accidentally change something, you can remove the containers and images
-and update to get a fresh installation.
-
-
-### How to download containers/images for a fresh installation and remove old containers
-
-To delete the old containers & images:
-
-```
-$ docker stop $COREBOOT_JENKINS_CONTAINER
-$ docker rm $COREBOOT_JENKINS_CONTAINER
-$ docker images # lists all existing images
-$ docker rmi XXXX # Use the image ID found in the above command.
-```
-
-To get and run the new coreboot-jenkins image, change the value in the
-`DOCKER_COMMIT` variable to the new image value.
-
-```
-$ make -C util/docker docker-jenkins-server
-```
-
-#### Getting ready to push the docker images
-
-Set up an account on hub.docker.com
-
-Get an admin to add the account to the coreboot team on hub.docker.com
-
-[https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners](https://hub.docker.com/u/coreboot/dashboard/teams/?team=owners)
-
-Make sure your credentials are configured on your host machine by
-running
-
-```
-$ docker login
-```
-
-This will prompt you for your docker username, password, and your email
-address, and write out to ~/.docker/config.json.  Without this file, you
-won’t be able to push the images.
-
-#### Updating the Dockerfiles:
-
-The coreboot-sdk Dockerfile will need to be updated when any additional
-dependencies are added.  Both the coreboot-sdk and the
-coreboot-jenkins-node Dockerfiles will need to be updated to the new
-version number and git commit id anytime the toolchain is updated. Both
-files are stored in the coreboot repo under coreboot/util/docker.
-
-Read the [dockerfile best practices](https://docs.docker.com/v1.8/articles/dockerfile_best-practices/)
-page before updating the files.
-
-#### Rebuilding the coreboot-sdk docker image to update the toolchain:
-
-```
-$ make -C util/docker coreboot-sdk
-```
-
-This takes a relatively long time.
-
-#### Test the coreboot-sdk docker image:
-
-There are two methods of running the docker image - interactively as a
-shell, or doing the build directly.  Running interactively as a shell is
-useful for early testing, because it allows you to update the image
-(without any changes getting saved) and re-test builds.  This saves the
-time of having to rebuild the image for every issue you find.
-
-#### Running the docker image interactively:
-
-Run:
-
-```
-$ make -C util/docker docker-jenkins-server
-$ make -C util/docker docker-jenkins-attach
-```
-
-#### Running the build directly:
-
-From the coreboot directory:
-
-```
-$ make -C util/docker docker-build-coreboot
-```
-
-You’ll also want to test building the other projects and payloads:
-ChromeEC, flashrom, memtest86+, em100, Grub2, SeaBIOS, iPXE, coreinfo,
-nvramcui, tint...
-
-#### Pushing the coreboot-sdk image to hub.docker.com for use:
-
-When you’re satisfied with the testing, push the coreboot-sdk image to
-the hub.docker.com
-
-```
-$ make -C util/docker upload-coreboot-sdk
-```
-
-#### Building and pushing the coreboot-jenkins-node docker image:
-
-This docker image is pretty simple, so there’s not really any testing
-that needs to be done.
-
-```
-$ make -C util/docker coreboot-jenkins-node
-$ make -C util/docker upload-coreboot-jenkins-node
-```
-
-### Coverity Setup
-
-To run coverity jobs, the builder needs to have the tools available, and
-to be marked as a coverity builder.
-
-
-#### Set up the Coverity tools
-
-Download the Linux-64 coverity build tool and decompress it into your
-cache directory as defined by the `$COREBOOT_JENKINS_CACHE_DIR` variable
-
-[https://scan.coverity.com/download](https://scan.coverity.com/download)
-
-Rename the directory from its original name
-(cov-analysis-linux64-7.7.0.4) to ‘coverity’, or better, create a
-symlink:
-
-```
-ln -s cov-analysis-linux64-7.7.0.4 coverity
-```
-
-
-Let the admins know that the ‘coverity’ label can be added to the
-builder.

Documentation/infrastructure/index.md

@@ -1,6 +0,0 @@
-# coreboot infrastructure
-
-This section contains documentation about coreboot infrastructure
-
-## Jenkins builders and builds
-[Setting up Jenkins build machines](builders.md)

Documentation/lib/fw_config.md

@@ -121,48 +121,12 @@ Each field is defined by providing the field name and the start and end bit mark
 location in the bitmask.  Field names must be at least three characters long in order to
 satisfy the sconfig parser requirements and they must be unique with non-overlapping masks.
 
-	field <name> <start-bit> <end-bit> [option...] end
+    field <name> <start-bit> <end-bit> [option...] end
 
 For single-bit fields only one number is needed:
 
 	field <name> <bit> [option...] end
 
-A field definition can also contain multiple sets of bit masks, which can be dis-contiguous.
-They are treated as if they are contiguous when defining option values.  This allows for
-extending fields even after the bits after its current masks are occupied.
-
-	field <name> <start-bit0> <end-bit0> | <start-bit1> <end-bit1> | ...
-
-For example, if more audio options need to be supported:
-
-	field AUDIO 3 3
-		option AUDIO_0  0
-		option AUDIO_1  1
-	end
-	field OTHER 4 4
-		...
-	end
-
-the following can be done:
-
-	field AUDIO 3 3 | 5 5
-		option AUDIO_FOO   0
-		option AUDIO_BLAH  1
-		option AUDIO_BAR   2
-		option AUDIO_BAZ   3
-	end
-	field OTHER 4 4
-		...
-	end
-
-In that case, the AUDIO masks are extended like so:
-
-	#define FW_CONFIG_FIELD_AUDIO_MASK						0x28
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_FOO_VALUE	0x0
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BLAH_VALUE	0x8
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAR_VALUE	0x20
-	#define FW_CONFIG_FIELD_AUDIO_OPTION_AUDIO_BAz_VALUE	0x28
-
 Each `field` definition starts a new block that can be composed of zero or more field options,
 and it is terminated with `end`.
 

Documentation/mainboard/asus/p5q.md

@@ -2,7 +2,9 @@
 
 This page describes how to run coreboot on the [ASUS P5Q] desktop board.
 
-## Working
+## TODO
+
+The following things are working in this coreboot port:
 
 + PCI slots
 + PCI-e slots
@@ -13,21 +15,20 @@ This page describes how to run coreboot on the [ASUS P5Q] desktop board.
 + All 4 DIMM slots
 + S3 suspend and resume
 + Red SATA ports
-+ Fan control through the W83667HG chip
-+ FireWire
 
-## Not working
+The following things are still missing from this coreboot port:
 
 + PS/2 mouse support
 + PATA aka IDE (because of buggy IDE controller)
-+ Fan profiles with Q-Fan
++ Fan control (will be working on 100% power)
 + TPM module (support not implemented)
 
-## Untested
+The following things are untested on this coreboot port:
 
 + S/PDIF
 + CD Audio In
 + Floppy disk drive
++ FireWire: PCI device shows up and driver loads, no further test
 
 
 ## Flashing coreboot
@@ -72,63 +73,5 @@ You can flash coreboot into your motherboard using [this guide].
 +------------------+---------------------------------------------------+
 ```
 
-## Controlling fans
-
-With vendor firmware, the P5Q uses the ATK0110 ACPI device to control its fans
-according to the parameters configured in the BIOS setup menu. With coreboot,
-one can instead control the Super I/O directly as described in the
-[kernel docs]:
-
-+ pwm1 controls fan1 (CHA_FAN1) and fan4 (CHA_FAN2)
-+ pwm2 controls fan2 (CPU_FAN)
-+ fan3 (PWR_FAN) cannot be controlled
-+ temp1 (board) can be used to control fan1 and fan4
-+ temp2 (CPU) can be used to control fan2
-
-### Manual fan speed
-
-These commands set the chassis fans to a constant speed:
-
-    # Use PWM output
-    echo 1 >/sys/class/hwmon/hwmon2/pwm1_mode
-    # Set to manual mode
-    echo 1 >/sys/class/hwmon/hwmon2/pwm1_enable
-    # Set relative speed: 0 (stop) to 255 (full)
-    echo 150 >/sys/class/hwmon/hwmon2/pwm1
-
-### Automatic fan speed
-
-The W83667HG can adjust fan speeds when things get too warm. These settings will
-control the chassis fans:
-
-    # Set to "Thermal Cruise" mode
-    echo 2 >/sys/class/hwmon/hwmon2/pwm1_enable
-    # Target temperature: 60°C
-    echo 60000 >/sys/class/hwmon/hwmon2/pwm1_target
-    # Minimum fan speed when spinning up
-    echo 135 >/sys/class/hwmon/hwmon2/pwm1_start_output
-    # Minimum fan speed when spinning down
-    echo 135 >/sys/class/hwmon/hwmon2/pwm1_stop_output
-    # Tolerance: 2°C
-    echo 2000 >/sys/class/hwmon/hwmon2/pwm1_tolerance
-    # Turn fans off after 600 seconds when below defined range
-    echo 600000 >/sys/class/hwmon/hwmon2/pwm1_stop_time
-
-You can also control the CPU fan with similar rules:
-
-    # Switch to "Thermal Cruise" mode
-    echo 2 >/sys/class/hwmon/hwmon2/pwm2_enable
-    # Target temperature: 55°C
-    echo 55000 >/sys/class/hwmon/hwmon2/pwm2_target
-    # Minimum fan speed when spinning down
-    echo 50 >/sys/class/hwmon/hwmon2/pwm2_stop_output
-    # Rate of fan speed change
-    echo 50 >/sys/class/hwmon/hwmon2/pwm2_step_output
-    # Maximum fan speed
-    echo 200 >/sys/class/hwmon/hwmon2/pwm2_max_output
-    # Tolerance: 2°C
-    echo 2000 >/sys/class/hwmon/hwmon2/pwm1_tolerance
-
 [ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
 [this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
-[kernel docs]: https://www.kernel.org/doc/Documentation/hwmon/w83627ehf.rst

Documentation/mainboard/facebook/monolith.md

@@ -41,8 +41,8 @@ These can be extracted from the original flash image as follows:
 00003000:006FFFFF me
 00001000:00002fff gbe
 ```
-3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6 MiB
-   to 9 MiB, this is required to create sufficient space for LinuxBoot.
+3) Use `ifdtool -n <layout_file> <flash_image>` to resize the *bios* region from the default 6MB
+   to 9 MB, this is required to create sufficient space for LinuxBoot.
    NOTE: Please make sure only the firmware descriptor (*fd*) region is changed. Older versions
    	 of the ifdtool corrupt the *me* region.
 4) Use `ifdtool -x <resized_flash_image>` to extract the components.

Documentation/mainboard/gigabyte/ga-g41m-es2l.md

@@ -1,283 +0,0 @@
-# Gigabyte GA-G41M-ES2L rev 1.1
-
-This page describes how to use coreboot on the [Gigabyte GA-G41M-ES2L rev 1.1](https://www.gigabyte.com/Motherboard/GA-G41M-ES2L-rev-11) mainboard.
-
-This motherboard [also works with Libreboot](https://libreboot.org/docs/install/ga-g41m-es2l.html).
-
-## Technology
-
-```eval_rst
-+------------------+--------------------------------------------------+
-| Type             | Value                                            |
-+==================+==================================================+
-| BIOS flash chips | 2 x SST25VF080B (8 Mbit SPI) (DUAL BIOS)         |
-+------------------+--------------------------------------------------+
-| Northbridge      | Intel G41                                        |
-+------------------+--------------------------------------------------+
-| Southbridge      | Intel ICH7                                       |
-+------------------+--------------------------------------------------+
-| CPU socket       | LGA775                                           |
-+------------------+--------------------------------------------------+
-| RAM              | 2 x DDR2 800, max. 8 GiB                         |
-+------------------+--------------------------------------------------+
-| SuperIO          | ITE IT8718F-S                                    |
-+------------------+--------------------------------------------------+
-| Audio            | Realtek ALC888B                                  |
-+------------------+--------------------------------------------------+
-| Network          | Realtek RTL8111C PCIe Gigabit Ethernet           |
-+------------------+--------------------------------------------------+
-```
-
-## Preparation
-
-```eval_rst
-For more datails how to get sources and build the toolchain, see :doc:`../../tutorial/part1`.
-```
-
-### Devuan 4 Chimaera
-
-This probably works also for any fresh Debian/Ubuntu-based distros.
-
-Install tools and libraries needed for coreboot:
-
-```shell
-sudo apt-get -V install bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev wget python2 python-is-python2 flashrom
-```
-
-### Get sources
-
-You need about 700 MB disk space for sources only and ~2GB disk space for sources + build results
-
-```shell
-git clone --recursive https://review.coreboot.org/coreboot.git
-```
-
-### Build toolchain
-
-Your system compilers can be different with versions, tested by coreboot developers.
-So, it is recommended to build cross-compilers with special versions, which were tested with coreboot.
-
-It is possible to skip this time-consuming part and use `ANY_TOOLCHAIN=y`, but this not recommended.
-
-You can build them for all platforms: `make crossgcc CPUS=2` but this takes ~2 hours with Intel core2duo E8400.
-
-The best way, probably, is to build cross-compilers for your platform (this takes ~20 minutes with Intel core2duo E8400):
-
-```shell
-make crossgcc-i386 CPUS=2
-```
-
-### Save MAC-address of internal LAN
-
-Run `ip -c link show`, you will find MAC-address like 6c:f0:49:xx:xx:xx
-
-```
-1: lo: <LOOPBACK,UP,LOWER_UP> mtu 65536 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000
-    link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00
-2: eth0: <BROADCAST,MULTICAST,UP,LOWER_UP> mtu 1500 qdisc pfifo_fast state UP mode DEFAULT group default qlen 1000
-    link/ether 6c:f0:49:xx:xx:xx brd ff:ff:ff:ff:ff:ff
-```
-
-## Configure
-
-Create file `payloads/external/SeaBIOS/.config_seabios`:
-
-```shell
-CONFIG_COREBOOT=y
-CONFIG_ATA_DMA=y
-CONFIG_VGA_COREBOOT=y
-```
-
-Edit file `configs/config.gigabyte_ga-g41m-es2l`, replace `CONFIG_REALTEK_8168_MACADDRESS` value with your MAC-address.
-
-Run
-
-```shell
-make defconfig KBUILD_DEFCONFIG="configs/config.gigabyte_ga-g41m-es2l"
-```
-
-## Build
-
-Just execute:
-
-```shell
-make
-```
-
-It takes ~2 minutes with Intel core2duo E8400.
-
-Example of last part in the output:
-
-```
-    CBFSPRINT  coreboot.rom
-
-FMAP REGION: COREBOOT
-Name                           Offset     Type           Size   Comp
-cbfs master header             0x0        cbfs header        32 none
-fallback/romstage              0x80       stage           62316 none
-cpu_microcode_blob.bin         0xf480     microcode      180224 none
-fallback/ramstage              0x3b500    stage           98745 none
-vgaroms/seavgabios.bin         0x53700    raw             28672 none
-config                         0x5a740    raw               301 none
-revision                       0x5a8c0    raw               675 none
-build_info                     0x5abc0    raw               103 none
-fallback/dsdt.aml              0x5ac80    raw              8447 none
-rt8168-macaddress              0x5cdc0    raw                17 none
-vbt.bin                        0x5ce40    raw               802 LZMA (1899 decompressed)
-cmos.default                   0x5d1c0    cmos_default      256 none
-cmos_layout.bin                0x5d300    cmos_layout      1040 none
-fallback/postcar               0x5d740    stage           20844 none
-fallback/payload               0x62900    simple elf      70270 none
-payload_config                 0x73bc0    raw              1699 none
-payload_revision               0x742c0    raw               237 none
-(empty)                        0x74400    null           482904 none
-bootblock                      0xea280    bootblock       23360 none
-    HOSTCC     cbfstool/ifwitool.o
-    HOSTCC     cbfstool/ifwitool (link)
-
-Built gigabyte/ga-g41m-es2l (GA-G41M-ES2L)
-```
-
-## Flashing coreboot
-
-```eval_rst
-In addition to the information here, please see the
-:doc:`../../flash_tutorial/index`.
-```
-
-### Do backup
-
-The above commands read the SPI flash chip(s), write into file and then verify content again with the chip:
-
-```shell
-sudo flashrom -p internal:dualbiosindex=0 -r m_bios.rom
-sudo flashrom -p internal:dualbiosindex=0 -v m_bios.rom
-sudo flashrom -p internal:dualbiosindex=1 -r b_bios.rom
-sudo flashrom -p internal:dualbiosindex=1 -v b_bios.rom
-```
-
-If access error appeared, then add `iomem=relaxed` to Linux kernel parameters and restart your Linux system.
-
-You can also repeat backup and compare checksums manually.
-
-Backup file should be stored elsewhere, so that in case the coreboot build is faulty, some external procedure can be used without having to extract the backup from the target device first.
-
-### Write new flash image
-
-Let's write new image into SPI flash chip, verify checksum again and erase second flash chip:
-
-```shell
-sudo flashrom -p internal:dualbiosindex=0 -w build/coreboot.rom
-sudo flashrom -p internal:dualbiosindex=0 -v build/coreboot.rom
-sudo flashrom -p internal:dualbiosindex=1 -E
-```
-
-## Set text mode for GRUB
-
-Update your `/etc/default/grub` with:
-
-```shell
-GRUB_TERMINAL=console
-```
-
-And recreate GRUB configuration `/boot/grub/grub.cfg` by command
-
-```shell
-sudo update-grub
-```
-
-## Boot with new firmware
-
-Restart your system:
-
-```shell
-sudo shutdown -r now
-```
-
-If it is needed, use <kbd>Esc</kbd> key to choose boot device.
-
-Remove `iomem=relaxed` from Linux kernel parameters.
-
-Enjoy!
-
-## Status
-
-```
-+-----------------------+--------------------------+--------+-------------------------------+
-| coreboot version      | Date of sources checkout | Status | Comment                       |
-+-----------------------+--------------------------+--------+-------------------------------+
-| 4.13-1531-g2fae1c0494 | 2021-01-28               | Good   |                               |
-+-----------------------+--------------------------+--------+-------------------------------+
-| 4.13-2182-g6410a0002f | 2021-02-18               | Good   |                               |
-+-----------------------+--------------------------+--------+-------------------------------+
-```
-
-### Known issues
-
-Lm-sensors shows wrong values from it87:
-
-```
-coretemp-isa-0000
-Adapter: ISA adapter
-Core 0:       +27.0°C  (high = +80.0°C, crit = +100.0°C)
-Core 1:       +31.0°C  (high = +80.0°C, crit = +100.0°C)
-
-it8718-isa-0290
-Adapter: ISA adapter
-in0:           1.06 V  (min =  +0.00 V, max =  +4.08 V)
-in1:           1.90 V  (min =  +0.00 V, max =  +4.08 V)
-in2:           3.34 V  (min =  +0.00 V, max =  +4.08 V)
-+5V:           2.96 V  (min =  +0.00 V, max =  +4.08 V)
-in4:         224.00 mV (min =  +0.00 V, max =  +4.08 V)
-in5:           4.08 V  (min =  +0.00 V, max =  +4.08 V)  ALARM
-in6:           4.08 V  (min =  +0.00 V, max =  +4.08 V)  ALARM
-in7:           3.09 V  (min =  +0.00 V, max =  +4.08 V)
-Vbat:          2.82 V
-fan1:        1290 RPM  (min =    0 RPM)
-fan2:           0 RPM  (min =    0 RPM)
-temp1:        -54.0°C  (low  =  +0.0°C, high = +127.0°C)  sensor = thermistor
-temp2:         -1.0°C  (low  =  +0.0°C, high = +127.0°C)  sensor = thermistor
-temp3:        +44.0°C  (low  =  +0.0°C, high = +127.0°C)  sensor = thermal diode
-cpu0_vid:    +1.100 V
-intrusion0:  ALARM
-```
-
-### Working
-
-- RAM 1,2x1GiB DDR2 PC2-6400 Kingston KTC1G-UDIMM (1.8V, 2Rx8 ?)
-- RAM 1x1GiB DDR2 PC2-5300 Brooktree AU1G08E32-667P005 / Apogee AU1G082-667P005 CL6 (1.8V, 2Rx8 ?)
-- CPU E8400
-- ACPI
-- CPU frequency scaling
-- flashrom under coreboot
-- Gigabit Ethernet
-- Hardware monitoring
-- Integrated graphics
-- SATA
-- PCI POST card
-
-### Not working
-
-- SuperIO based fan control: PWM fan speed is not changing in depend of CPU temperature
-- RAM 1,2x4GiB DDR2 PC2-6400 Samsung M378T5263AZ3-CF7 (2Rx4 PC2-6400U-666-12-E3)
-
-### Not tested
-
-- KVM virtualization
-- Onboard audio
-- PCI
-- PCIe
-- PS/2 keyboard mouse (during payload, bootloader)
-- Serial port
-- USB (disabling XHCI controller makes to work as fallback USB2.0 ports)
-- IOMMU
-
-## Interesting facts
-
-`lshw` output is different for BIOS and coreboot.
-
-```shell
-diff --side-by-side --ignore-all-space --strip-trailing-cr \
-     Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt \
-     Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt
-```

Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_after_coreboot.txt

@@ -1,306 +0,0 @@
-my-desktop
-    description: Desktop Computer
-    product: GA-G41M-ES2L
-    vendor: GIGABYTE
-    version: 1.0
-    serial: 123456789
-    width: 64 bits
-    capabilities: smbios-3.0.0 dmi-3.0.0 smp vsyscall32
-    configuration: boot=normal chassis=desktop
-  *-core
-       description: Motherboard
-       product: GA-G41M-ES2L
-       vendor: GIGABYTE
-       physical id: 0
-       version: 1.0
-       serial: 123456789
-     *-firmware
-          description: BIOS
-          vendor: coreboot
-          physical id: 0
-          version: 4.13-1531-g2fae1c0494
-          date: 01/29/2021
-          size: 1MiB
-          capacity: 1MiB
-          capabilities: pci pcmcia upgrade bootselect acpi
-     *-cpu
-          description: CPU
-          product: Intel(R) Core(TM)2 Duo CPU     E8400  @ 3.00GHz
-          vendor: Intel Corp.
-          physical id: 4
-          bus info: cpu@0
-          version: Intel(R) Core(TM)2 Duo CPU     E8400  @ 3.00GHz
-          slot: CPU0
-          size: 2943MHz
-          capacity: 3GHz
-          width: 64 bits
-          capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority vpid dtherm cpufreq
-        *-cache
-             description: L2 cache
-             physical id: 7
-             slot: CACHE2
-             size: 6MiB
-             capacity: 6MiB
-             capabilities: internal unified
-             configuration: level=2
-     *-memory
-          description: System memory
-          physical id: 1
-          size: 2GiB
-     *-pci
-          description: Host bridge
-          product: 4 Series Chipset DRAM Controller
-          vendor: Intel Corporation
-          physical id: 100
-          bus info: pci@0000:00:00.0
-          version: 03
-          width: 32 bits
-          clock: 33MHz
-        *-pci:0
-             description: PCI bridge
-             product: 4 Series Chipset PCI Express Root Port
-             vendor: Intel Corporation
-             physical id: 1
-             bus info: pci@0000:00:01.0
-             version: 03
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci pm msi pciexpress normal_decode bus_master cap_list
-             configuration: driver=pcieport
-             resources: irq:24
-        *-display:0
-             description: VGA compatible controller
-             product: 4 Series Chipset Integrated Graphics Controller
-             vendor: Intel Corporation
-             physical id: 2
-             bus info: pci@0000:00:02.0
-             version: 03
-             width: 64 bits
-             clock: 33MHz
-             capabilities: msi pm vga_controller bus_master cap_list rom
-             configuration: driver=i915 latency=0
-             resources: irq:16 memory:90000000-903fffff memory:80000000-8fffffff ioport:20a0(size=8) memory:c0000-dffff
-        *-display:1 UNCLAIMED
-             description: Display controller
-             product: 4 Series Chipset Integrated Graphics Controller
-             vendor: Intel Corporation
-             physical id: 2.1
-             bus info: pci@0000:00:02.1
-             version: 03
-             width: 64 bits
-             clock: 33MHz
-             capabilities: pm cap_list
-             configuration: latency=0
-             resources: memory:90400000-904fffff
-        *-multimedia
-             description: Audio device
-             product: NM10/ICH7 Family High Definition Audio Controller
-             vendor: Intel Corporation
-             physical id: 1b
-             bus info: pci@0000:00:1b.0
-             version: 01
-             width: 64 bits
-             clock: 33MHz
-             capabilities: pm msi pciexpress bus_master cap_list
-             configuration: driver=snd_hda_intel latency=0
-             resources: irq:28 memory:90700000-90703fff
-        *-pci:1
-             description: PCI bridge
-             product: NM10/ICH7 Family PCI Express Port 1
-             vendor: Intel Corporation
-             physical id: 1c
-             bus info: pci@0000:00:1c.0
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
-             configuration: driver=pcieport
-             resources: irq:25
-        *-pci:2
-             description: PCI bridge
-             product: NM10/ICH7 Family PCI Express Port 2
-             vendor: Intel Corporation
-             physical id: 1c.1
-             bus info: pci@0000:00:1c.1
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
-             configuration: driver=pcieport
-             resources: irq:26 ioport:1000(size=4096) memory:90600000-906fffff ioport:90500000(size=1048576)
-           *-network
-                description: Ethernet interface
-                product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
-                vendor: Realtek Semiconductor Co., Ltd.
-                physical id: 0
-                bus info: pci@0000:03:00.0
-                logical name: eth0
-                version: 02
-                serial: 6c:f0:49:a3:e3:d5
-                size: 1Gbit/s
-                capacity: 1Gbit/s
-                width: 64 bits
-                clock: 33MHz
-                capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation
-                configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=5.10.0-2-amd64 duplex=full ip=192.168.155.136 latency=0 link=yes multicast=yes port=MII speed=1Gbit/s
-                resources: irq:17 ioport:1000(size=256) memory:90510000-90510fff memory:90500000-9050ffff memory:90600000-9060ffff
-        *-usb:0
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #1
-             vendor: Intel Corporation
-             physical id: 1d
-             bus info: pci@0000:00:1d.0
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:23 ioport:2000(size=32)
-        *-usb:1
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #2
-             vendor: Intel Corporation
-             physical id: 1d.1
-             bus info: pci@0000:00:1d.1
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:19 ioport:2020(size=32)
-        *-usb:2
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #3
-             vendor: Intel Corporation
-             physical id: 1d.2
-             bus info: pci@0000:00:1d.2
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:18 ioport:2040(size=32)
-        *-usb:3
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #4
-             vendor: Intel Corporation
-             physical id: 1d.3
-             bus info: pci@0000:00:1d.3
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:16 ioport:2060(size=32)
-        *-usb:4
-             description: USB controller
-             product: NM10/ICH7 Family USB2 EHCI Controller
-             vendor: Intel Corporation
-             physical id: 1d.7
-             bus info: pci@0000:00:1d.7
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pm debug ehci bus_master cap_list
-             configuration: driver=ehci-pci latency=0
-             resources: irq:23 memory:90704000-907043ff
-        *-pci:3
-             description: PCI bridge
-             product: 82801 PCI Bridge
-             vendor: Intel Corporation
-             physical id: 1e
-             bus info: pci@0000:00:1e.0
-             version: e1
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci subtractive_decode bus_master cap_list
-        *-isa
-             description: ISA bridge
-             product: 82801GB/GR (ICH7 Family) LPC Interface Bridge
-             vendor: Intel Corporation
-             physical id: 1f
-             bus info: pci@0000:00:1f.0
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: isa bus_master cap_list
-             configuration: driver=lpc_ich latency=0
-             resources: irq:0
-        *-ide:0
-             description: IDE interface
-             product: 82801G (ICH7 Family) IDE Controller
-             vendor: Intel Corporation
-             physical id: 1f.1
-             bus info: pci@0000:00:1f.1
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: ide isa_compat_mode pci_native_mode bus_master
-             configuration: driver=ata_piix latency=0
-             resources: irq:18 ioport:1f0(size=8) ioport:3f6 ioport:170(size=8) ioport:376 ioport:2080(size=16)
-        *-ide:1
-             description: IDE interface
-             product: NM10/ICH7 Family SATA Controller [IDE mode]
-             vendor: Intel Corporation
-             physical id: 1f.2
-             bus info: pci@0000:00:1f.2
-             logical name: scsi2
-             version: 01
-             width: 32 bits
-             clock: 66MHz
-             capabilities: ide pm isa_compat_mode pci_native_mode bus_master cap_list emulated
-             configuration: driver=ata_piix latency=0
-             resources: irq:19 ioport:20b8(size=8) ioport:20d0(size=4) ioport:20c0(size=8) ioport:20d4(size=4) ioport:2090(size=16)
-           *-disk
-                description: ATA Disk
-                product: WDC WD5000BPVT-2
-                vendor: Western Digital
-                physical id: 0.0.0
-                bus info: scsi@2:0.0.0
-                logical name: /dev/sda
-                version: 1A03
-                serial: WD-WXD1E71MYND4
-                size: 465GiB (500GB)
-                capabilities: gpt-1.00 partitioned partitioned:gpt
-                configuration: ansiversion=5 guid=868a1c85-f309-4f3d-8282-6b5c4c373275 logicalsectorsize=512 sectorsize=4096
-        *-serial
-             description: SMBus
-             product: NM10/ICH7 Family SMBus Controller
-             vendor: Intel Corporation
-             physical id: 1f.3
-             bus info: pci@0000:00:1f.3
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             configuration: driver=i801_smbus latency=0
-             resources: irq:19 ioport:400(size=32)
-     *-pnp00:00
-          product: PnP device PNP0c02
-          physical id: 2
-          capabilities: pnp
-          configuration: driver=system
-     *-pnp00:01
-          product: PnP device PNP0103
-          physical id: 3
-          capabilities: pnp
-          configuration: driver=system
-     *-pnp00:02
-          product: PnP device PNP0c02
-          physical id: 5
-          capabilities: pnp
-          configuration: driver=system
-     *-pnp00:03
-          product: PnP device PNP0b00
-          physical id: 6
-          capabilities: pnp
-          configuration: driver=rtc_cmos
-     *-pnp00:04
-          product: PnP device PNP0303
-          physical id: 7
-          capabilities: pnp
-          configuration: driver=i8042 kbd
-     *-pnp00:05
-          product: PnP device PNP0f13
-          physical id: 8
-          capabilities: pnp
-          configuration: driver=i8042 aux

Documentation/mainboard/gigabyte/ga-g41m-es2l_lshw_before_coreboot.txt

@@ -1,304 +0,0 @@
-my-desktop
-    description: Desktop Computer
-    product: G41M-ES2L
-    vendor: Gigabyte Technology Co., Ltd.
-    width: 64 bits
-    capabilities: smbios-2.4 dmi-2.4 smp vsyscall32
-    configuration: boot=normal chassis=desktop uuid=00000000-0000-0000-0000-6CF049A3E3D5
-  *-core
-       description: Motherboard
-       product: G41M-ES2L
-       vendor: Gigabyte Technology Co., Ltd.
-       physical id: 0
-     *-firmware
-          description: BIOS
-          vendor: Award Software International, Inc.
-          physical id: 0
-          version: F9
-          date: 06/21/2010
-          size: 128KiB
-          capacity: 1MiB
-          capabilities: pci pnp apm upgrade shadowing cdboot bootselect edd int13floppy360 int13floppy1200 int13floppy720 int13floppy2880 int5printscreen int9keyboard int14serial int17printer int10video acpi usb ls120boot zipboot biosbootspecification
-     *-cpu
-          description: CPU
-          product: Intel(R) Core(TM)2 Duo CPU     E8400  @ 3.00GHz
-          vendor: Intel Corp.
-          physical id: 4
-          bus info: cpu@0
-          version: Intel(R) Core(TM)2 Duo CPU
-          slot: Socket 775
-          size: 2631MHz
-          capacity: 4GHz
-          width: 64 bits
-          clock: 333MHz
-          capabilities: fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ht tm pbe syscall nx x86-64 constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority vpid dtherm cpufreq
-        *-cache:0
-             description: L1 cache
-             physical id: a
-             slot: Internal Cache
-             size: 64KiB
-             capacity: 64KiB
-             capabilities: synchronous internal write-back
-             configuration: level=1
-        *-cache:1
-             description: L2 cache
-             physical id: b
-             slot: External Cache
-             size: 6MiB
-             capabilities: synchronous internal write-back
-             configuration: level=2
-     *-memory
-          description: System Memory
-          physical id: 19
-          slot: System board or motherboard
-          size: 2GiB
-        *-bank:0
-             description: DIMM 800 MHz (1.2 ns)
-             physical id: 0
-             slot: A0
-             size: 1GiB
-             width: 64 bits
-             clock: 800MHz (1.2ns)
-        *-bank:1
-             description: DIMM [empty]
-             physical id: 1
-             slot: A1
-        *-bank:2
-             description: DIMM 800 MHz (1.2 ns)
-             physical id: 2
-             slot: A2
-             size: 1GiB
-             width: 64 bits
-             clock: 800MHz (1.2ns)
-        *-bank:3
-             description: DIMM [empty]
-             physical id: 3
-             slot: A3
-     *-pci
-          description: Host bridge
-          product: 4 Series Chipset DRAM Controller
-          vendor: Intel Corporation
-          physical id: 100
-          bus info: pci@0000:00:00.0
-          version: 03
-          width: 32 bits
-          clock: 33MHz
-        *-display
-             description: VGA compatible controller
-             product: 4 Series Chipset Integrated Graphics Controller
-             vendor: Intel Corporation
-             physical id: 2
-             bus info: pci@0000:00:02.0
-             version: 03
-             width: 64 bits
-             clock: 33MHz
-             capabilities: msi pm vga_controller bus_master cap_list rom
-             configuration: driver=i915 latency=0
-             resources: irq:16 memory:fd800000-fdbfffff memory:d0000000-dfffffff ioport:ff00(size=8) memory:c0000-dffff
-        *-multimedia
-             description: Audio device
-             product: NM10/ICH7 Family High Definition Audio Controller
-             vendor: Intel Corporation
-             physical id: 1b
-             bus info: pci@0000:00:1b.0
-             version: 01
-             width: 64 bits
-             clock: 33MHz
-             capabilities: pm msi pciexpress bus_master cap_list
-             configuration: driver=snd_hda_intel latency=0
-             resources: irq:27 memory:fdff8000-fdffbfff
-        *-pci:0
-             description: PCI bridge
-             product: NM10/ICH7 Family PCI Express Port 1
-             vendor: Intel Corporation
-             physical id: 1c
-             bus info: pci@0000:00:1c.0
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
-             configuration: driver=pcieport
-             resources: irq:24 ioport:1000(size=4096) memory:7dd00000-7defffff ioport:80000000(size=2097152)
-        *-pci:1
-             description: PCI bridge
-             product: NM10/ICH7 Family PCI Express Port 2
-             vendor: Intel Corporation
-             physical id: 1c.1
-             bus info: pci@0000:00:1c.1
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci pciexpress msi pm normal_decode bus_master cap_list
-             configuration: driver=pcieport
-             resources: irq:25 ioport:d000(size=4096) memory:fdd00000-fddfffff ioport:fde00000(size=1048576)
-           *-network
-                description: Ethernet interface
-                product: RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
-                vendor: Realtek Semiconductor Co., Ltd.
-                physical id: 0
-                bus info: pci@0000:02:00.0
-                logical name: eth0
-                version: 02
-                serial: 6c:f0:49:a3:e3:d5
-                size: 1Gbit/s
-                capacity: 1Gbit/s
-                width: 64 bits
-                clock: 33MHz
-                capabilities: pm msi pciexpress msix vpd bus_master cap_list rom ethernet physical tp mii 10bt 10bt-fd 100bt 100bt-fd 1000bt 1000bt-fd autonegotiation
-                configuration: autonegotiation=on broadcast=yes driver=r8169 driverversion=5.10.0-2-amd64 duplex=full ip=192.168.155.137 latency=0 link=yes multicast=yes port=MII speed=1Gbit/s
-                resources: irq:17 ioport:de00(size=256) memory:fdeff000-fdefffff memory:fdee0000-fdeeffff memory:fdd00000-fdd0ffff
-        *-usb:0
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #1
-             vendor: Intel Corporation
-             physical id: 1d
-             bus info: pci@0000:00:1d.0
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:23 ioport:fe00(size=32)
-        *-usb:1
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #2
-             vendor: Intel Corporation
-             physical id: 1d.1
-             bus info: pci@0000:00:1d.1
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:19 ioport:fd00(size=32)
-        *-usb:2
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #3
-             vendor: Intel Corporation
-             physical id: 1d.2
-             bus info: pci@0000:00:1d.2
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:18 ioport:fc00(size=32)
-        *-usb:3
-             description: USB controller
-             product: NM10/ICH7 Family USB UHCI Controller #4
-             vendor: Intel Corporation
-             physical id: 1d.3
-             bus info: pci@0000:00:1d.3
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: uhci bus_master
-             configuration: driver=uhci_hcd latency=0
-             resources: irq:16 ioport:fb00(size=32)
-        *-usb:4
-             description: USB controller
-             product: NM10/ICH7 Family USB2 EHCI Controller
-             vendor: Intel Corporation
-             physical id: 1d.7
-             bus info: pci@0000:00:1d.7
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pm ehci bus_master cap_list
-             configuration: driver=ehci-pci latency=0
-             resources: irq:23 memory:fdfff000-fdfff3ff
-        *-pci:2
-             description: PCI bridge
-             product: 82801 PCI Bridge
-             vendor: Intel Corporation
-             physical id: 1e
-             bus info: pci@0000:00:1e.0
-             version: e1
-             width: 32 bits
-             clock: 33MHz
-             capabilities: pci subtractive_decode cap_list
-        *-isa
-             description: ISA bridge
-             product: 82801GB/GR (ICH7 Family) LPC Interface Bridge
-             vendor: Intel Corporation
-             physical id: 1f
-             bus info: pci@0000:00:1f.0
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: isa bus_master cap_list
-             configuration: driver=lpc_ich latency=0
-             resources: irq:0
-        *-ide:0
-             description: IDE interface
-             product: 82801G (ICH7 Family) IDE Controller
-             vendor: Intel Corporation
-             physical id: 1f.1
-             bus info: pci@0000:00:1f.1
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             capabilities: ide isa_compat_mode pci_native_mode bus_master
-             configuration: driver=ata_piix latency=0
-             resources: irq:18 ioport:1f0(size=8) ioport:3f6 ioport:170(size=8) ioport:376 ioport:f800(size=16)
-        *-ide:1
-             description: IDE interface
-             product: NM10/ICH7 Family SATA Controller [IDE mode]
-             vendor: Intel Corporation
-             physical id: 1f.2
-             bus info: pci@0000:00:1f.2
-             logical name: scsi2
-             version: 01
-             width: 32 bits
-             clock: 66MHz
-             capabilities: ide pm isa_compat_mode pci_native_mode bus_master cap_list emulated
-             configuration: driver=ata_piix latency=0
-             resources: irq:19 ioport:f700(size=8) ioport:f600(size=4) ioport:f500(size=8) ioport:f400(size=4) ioport:f300(size=16)
-           *-disk
-                description: ATA Disk
-                product: WDC WD5000BPVT-2
-                vendor: Western Digital
-                physical id: 0.0.0
-                bus info: scsi@2:0.0.0
-                logical name: /dev/sda
-                version: 1A03
-                serial: WD-WXD1E71MYND4
-                size: 465GiB (500GB)
-                capabilities: gpt-1.00 partitioned partitioned:gpt
-                configuration: ansiversion=5 guid=868a1c85-f309-4f3d-8282-6b5c4c373275 logicalsectorsize=512 sectorsize=4096
-        *-serial
-             description: SMBus
-             product: NM10/ICH7 Family SMBus Controller
-             vendor: Intel Corporation
-             physical id: 1f.3
-             bus info: pci@0000:00:1f.3
-             version: 01
-             width: 32 bits
-             clock: 33MHz
-             configuration: driver=i801_smbus latency=0
-             resources: irq:19 ioport:500(size=32)
-     *-pnp00:00
-          product: PnP device PNP0c02
-          physical id: 1
-          capabilities: pnp
-          configuration: driver=system
-     *-pnp00:01
-          product: PnP device PNP0b00
-          physical id: 2
-          capabilities: pnp
-          configuration: driver=rtc_cmos
-     *-pnp00:02
-          product: PnP device PNP0c02
-          physical id: 3
-          capabilities: pnp
-          configuration: driver=system
-     *-pnp00:03
-          product: PnP device PNP0c02
-          physical id: 5
-          capabilities: pnp
-          configuration: driver=system
-     *-pnp00:04
-          product: PnP device PNP0c01
-          physical id: 6
-          capabilities: pnp
-          configuration: driver=system

Documentation/mainboard/hp/8760w.md

@@ -36,7 +36,7 @@ checkout the [code on gerrit] to build coreboot for the laptop.
 
 ## Flashing instructions
 
-HP EliteBook 8760w has an 8 MiB SOIC-8 flash chip on the bottom of the
+HP EliteBook 8760w has an 8MB SOIC-8 flash chip on the bottom of the
 mainboard. You just need to remove the service cover, and use an SOIC-8
 clip to read and flash the chip.
 

Documentation/mainboard/index.md

@@ -56,7 +56,6 @@ The boards in this section are not real mainboards, but emulators.
 
 ## Gigabyte
 
-- [GA-G41M-ES2L](gigabyte/ga-g41m-es2l.md)
 - [GA-H61M-S2PV](gigabyte/ga-h61m-s2pv.md)
 
 ## HP
@@ -176,10 +175,7 @@ The boards in this section are not real mainboards, but emulators.
 
 ## System76
 
-- [Gazelle 15](system76/gaze15.md)
 - [Lemur Pro](system76/lemp9.md)
-- [Oryx Pro 5](system76/oryp5.md)
-- [Oryx Pro 6](system76/oryp6.md)
 
 ## Texas Instruments
 

Documentation/mainboard/intel/kblrvp11.md

@@ -60,7 +60,7 @@ $ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all
 2. Make sure power supply is disconnected from board.
 3. Connect Dediprog SF600 to header at J7H1.
 4. Ensure that "currently working on" is in "application memory chip 1"
-5. Go to "file" and select the .rom file (16 MiB) to program chip1.
+5. Go to "file" and select the .rom file (16 MB) to program chip1.
 6. Execute the batch operation to erase and program the chip.
 
 ## Technology

Documentation/mainboard/lenovo/Ivy_Bridge_series.md

@@ -25,7 +25,7 @@ This information is valid for all supported models, except T430s, [T431s](t431s.
 
 ## Installation instructions
 * Update the EC firmware, as there's no support for EC updates in coreboot.
-* Do **NOT** accidentally swap pins or power on the board while a SPI flasher
+* Do **NOT** accidently swap pins or power on the board while a SPI flasher
   is connected. It will permanently brick your device.
 * It's recommended to only flash the BIOS region. In that case you don't
   need to extract blobs from vendor firmware.

Documentation/mainboard/lenovo/Sandy_Bridge_series.md

@@ -22,12 +22,8 @@
 ```
 
 ## Installation instructions
-
-Flashing coreboot for the first time needs to be done using an external
-programmer, because vendor firmware prevents rewriting the BIOS region.
-
 * Update the EC firmware, as there's no support for EC updates in coreboot.
-* Do **NOT** accidentally swap pins or power on the board while a SPI flasher
+* Do **NOT** accidently swap pins or power on the board while a SPI flasher
   is connected. It will destroy your device.
 * It's recommended to only flash the BIOS region. In that case you don't
   need to extract blobs from vendor firmware.

Documentation/mainboard/lenovo/montevina_series.md

@@ -44,7 +44,7 @@ $ ifdtool -x backup.rom
 
 Now you need to patch the flash descriptor. You can either [modify the one from
 your backup with **ifdtool**](#modifying-flash-descriptor-using-ifdtool), or
-[use one from the coreboot repository](#using-checked-in-flash-descriptor-via-bincfg).
+[generate a completely new one with **bincfg**](#creating-a-new-flash-descriptor-using-bincfg).
 
 #### Modifying flash descriptor using ifdtool
 
@@ -53,13 +53,13 @@ the `new_layout.txt` file:
 
 ```eval_rst
 +---------------------------+---------------------------+---------------------------+
-| 4 MiB chip                | 8 MiB chip                | 16 MiB chip               |
+| 4 MB chip                 | 8 MB chip                 | 16 MB chip                |
 +===========================+===========================+===========================+
 | .. code-block:: none      | .. code-block:: none      | .. code-block:: none      |
 |                           |                           |                           |
 |    00000000:00000fff fd   |    00000000:00000fff fd   |    00000000:00000fff fd   |
 |    00001000:00002fff gbe  |    00001000:00002fff gbe  |    00001000:00002fff gbe  |
-|    00003000:003fffff bios |    00003000:007fffff bios |    00003000:00ffffff bios |
+|    00003000:003fffff bios |    00003000:007fffff bios |    00003000:01ffffff bios |
 |    00fff000:00000fff pd   |    00fff000:00000fff pd   |    00fff000:00000fff pd   |
 |    00fff000:00000fff me   |    00fff000:00000fff me   |    00fff000:00000fff me   |
 +---------------------------+---------------------------+---------------------------+
@@ -88,37 +88,33 @@ $ mv flashregion_0_flashdescriptor.bin.new.new flashregion_0_flashdescriptor.bin
 
 Continue to the [Configuring coreboot](#configuring-coreboot) section.
 
-#### Using checked-in flash descriptor via bincfg
+#### Creating a new flash descriptor using bincfg
 
-There is a copy of an X200's flash descriptor checked into the coreboot
-repository. It is supposed to work for the T400/T500 as well. The descriptor
-can be converted back to its binary form using a tool called **bincfg**. Go
-to `util/bincfg` and build it:
+There is a tool to generate a modified flash descriptor called **bincfg**. Go to
+`util/bincfg` and build it:
 ```console
 $ cd util/bincfg
 $ make
 ```
 
-If your flash is not 8 MiB, you need to change values of `flcomp_density1` and
+If your flash is not 8 MB, you need to change values of `flcomp_density1` and
 `flreg1_limit` in the `ifd-x200.set` file according to following table:
 
 ```eval_rst
 +-----------------+-------+-------+--------+
-|                 | 4 MiB | 8 MiB | 16 MiB |
+|                 | 4 MB  | 8 MB  | 16 MB  |
 +=================+=======+=======+========+
 | flcomp_density1 | 0x3   | 0x4   | 0x5    |
 +-----------------+-------+-------+--------+
-| flreg1_limit    | 0x3ff | 0x7ff | 0xfff  |
+| flreg1_limit    | 0x3ff | 0x7ff | 0x1fff |
 +-----------------+-------+-------+--------+
 ```
 
-Then convert the flash descriptor:
+Then create the flash descriptor:
 ```console
-$ make gen-ifd-x200
+$ ./bincfg ifd-x200.spec ifd-x200.set ifd.bin
 ```
 
-It will be saved to the `flashregion_0_fd.bin` file.
-
 #### Configuring coreboot
 
 Now configure coreboot. You need to select correct chip size and specify paths
@@ -127,11 +123,11 @@ to flash descriptor and gbe dump.
 ```
 Mainboard --->
     ROM chip size (8192 KB (8 MB)) # According to your chip
-    (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MiB chip / 0xffd000 for 16 MiB chip
+    (0x7fd000) Size of CBFS filesystem in ROM # or 0x3fd000 for 4 MB chip / 0x1ffd000 for 16 MB chip
 
 Chipset --->
     [*] Add Intel descriptor.bin file
-    # Note: if you used bincfg, specify path to generated util/bincfg/flashregion_0_fd.bin
+    # Note: if you used bincfg, specify path to generated util/bincfg/ifd.bin
     (/path/to/flashregion_0_flashdescriptor.bin) Path and filename of the descriptor.bin file
 
     [*] Add gigabit ethernet configuration
@@ -146,7 +142,7 @@ The flash layouts of the OEM firmware are as follows:
 
 ```eval_rst
 +---------------------------------+---------------------------------+
-| 4 MiB chip                      | 8 MiB chip                      |
+| 4 MB chip                       | 8 MB chip                       |
 +=================================+=================================+
 | .. code-block:: none            | .. code-block:: none            |
 |                                 |                                 |
@@ -163,6 +159,6 @@ The flash layouts of the OEM firmware are as follows:
 On each boot of vendor BIOS `ec` area in flash is checked for having firmware
 there, and if there is one, it proceedes to update firmware on H8S/2116 (when
 both external power and main battery are attached). Once update is performed,
-first 64 KiB of `ec` area is erased. Visit
+first 64 KB of `ec` area is erased. Visit
 [thinkpad-ec repository](https://github.com/hamishcoleman/thinkpad-ec) to learn
 more about how to extract EC firmware from vendor updates.

Documentation/mainboard/lenovo/t420.md

@@ -18,40 +18,6 @@ the general [flashing tutorial].
 
 Steps to access the flash IC are described here [T4xx series].
 
-## Working
- * CPU: Sandy Bridge i5-2520M, i7-2670QM
- * RAM module combinations of 2G+0, 2G+2G, 4G+0
- * mSATA
- * USB
- * Video (Intel integrated)
- * Sound (integrated speakers, integrated mic, external headphones, external mic)
- * LAN
- * Mini-PCIe slots (WLAN)
- * Bluetooth
- * Linux
- * Windows 10 (through SeaBIOS as payload, using a VGA BIOS)
- * DVD-ROM drive
- * SD card slot
- * TrackPoint
- * Touchpad
- * Webcam
- * Fn hotkeys (backlight control, thinklight)
- * Thinklight
- * Mute button (Speaker only)
- * Mini Jack audio (headphones)
- * Suspend (Linux)
-
-## Not tested
- * DSub (VGA) out
- * DisplayPort out
- * eSATA
- * ExpressCard
- * WWAN
-
-## Not working/TODOs
- * Mutemic button doesn't mute
- * Suspend (Windows 10)
-
 [T4xx series]: t4xx_series.md
 [flashing tutorial]: ../../flash_tutorial/ext_power.md
 [T420 / T520 / X220 / T420s / W520 common]: Sandy_Bridge_series.md

Documentation/mainboard/lenovo/t440p.md

@@ -8,15 +8,15 @@ Please see [mrc.bin](../../northbridge/intel/haswell/mrc.bin).
 
 ## Flashing instructions
 
-T440p has two flash chips, an 8 MiB W25Q64FV and a 4 MiB W25Q32FV. To flash
+T440p has two flash chips, an 8MB W25Q64FV and a 4MB W25Q32FV. To flash
 coreboot, you just need to remove the big door according to the T440
-[Hardware Maintenance Manual] and flash the 4 MiB chip.
+[Hardware Maintenance Manual] and flash the 4MB chip.
 
 ![T440p flash chip](t440p_flash_chip.jpg)
 
-To access the 8 MiB chip, you need to remove the base cover.
+To access the 8MB chip, you need to remove the base cover.
 
-![T440p 8 MiB flash chip](t440p_all_flash_chips.jpg)
+![T440p 8MB flash chip](t440p_all_flash_chips.jpg)
 
 The flash layout of the OEM firmware is as follows:
 

Documentation/mainboard/msi/ms7707/ms7707.md

@@ -2,7 +2,7 @@
 
 * MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555)
 * SandyBridge Intel P67 (BD82x6x)
-* Winbond 25Q32BV (4 MiB)
+* Winbond 25Q32BV (4MB)
 * Fintek F71808A SuperIO
 * Intel 82579V Gigabit
 * NEC uPD720200 USB 3.0 Host Controller

Documentation/mainboard/ocp/deltalake.md

@@ -1,7 +1,8 @@
 # OCP Delta Lake
 
 This page describes coreboot support status for the [OCP] (Open Compute Project)
-Delta Lake server platform.
+Delta Lake server platform. This page is updated following each 4-weeks
+build/test/release cycle.
 
 ## Introduction
 
@@ -11,23 +12,22 @@ Yosemite-V3. Both were announced by Facebook and Intel in [OCP virtual summit 20
 Delta Lake server is a single socket Cooper Lake Scalable Processor (CPX-SP) server.
 
 Yosemite-V3 has multiple configurations. Depending on configurations, it may
-host up to 4 Delta Lake servers (blades) in one sled.
+host up to 4 Delta Lake servers in one sled.
 
-The Yosemite-V3 system is in mass production. Facebook, Intel and partners
-jointly develop Open System Firmware (OSF) solution on Delta Lake as an alternative
-solution. The OSF solution is based on FSP/coreboot/LinuxBoot stack. The
-OSF solution reached DVT exit equivalent status.
+The Yosemite-V3 program is in PVT phase. Facebook, Intel and partners
+jointly develop FSP/coreboot/LinuxBoot stack on Delta Lake as an alternative
+solution. This development reached EVT exit equivalent status.
 
 ## Required blobs
 
-Delta Lake server OSF solution requires:
+This board currently requires:
 - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package)
-  is not yet available to the public. It will be made public soon by Intel 
-  with redistributable license.
+  is not yet available to the public. It will be made public some time after the MP
+  (Mass Production) of CPX-SP.
 - Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git.
-- ME binary: Ignition binary will be made public soon by Intel with
-  redistributable license.
-- ACM binaries: only required for CBnT enablement. Available under NDA with Intel.
+- ME binary: Ignition binary will be made public some time after the MP
+  of CPX-SP.
+- ACM binaries: only required for CBnT enablement.
 
 ## Payload
 - LinuxBoot: This is necessary only if you use LinuxBoot as coreboot payload.
@@ -58,16 +58,11 @@ values.
 VPD variables supported are:
 - firmware_version: This variable holds overall firmware version. coreboot
   uses that value to populate smbios type 1 version field.
-- bmc_bootorder_override: When it's set to 1 IPMI OEM command can override boot
-  order. The boot order override is done in the u-root LinuxBoot payload.
-- systemboot_log_level: u-root package systemboot log levels, would be mapped to
-  quiet/verbose in systemboot as that is all we have for now. 5 to 8 would be
-  mapped to verbose, 0 to 4 and 9 would be mapped to quiet.
-- VPDs affecting coreboot are listed/documented in src/mainboard/ocp/deltalake/vpd.h.
+- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h.
 
 ## Working features
-The solution is developed using LinuxBoot payload with Linux kernel 5.2.9,
-and [u-root] as initramfs.
+The solution is developed using LinuxBoot payload with Linux kernel 5.2.9, and [u-root]
+as initramfs.
 - SMBIOS:
     - Type 0 -- BIOS Information
     - Type 1 -- System Information
@@ -96,14 +91,11 @@ and [u-root] as initramfs.
     - TPM
     - Bootguard profile 0T
     - TXT
-    - SRTM
-    - DRTM (verified through tboot)
-		- unsigned KM/BPM generation
-		- KM/BPM signing
-		- memory secret clearance upon ungraceful shutdown
+    - SRTM (verified through tboot)
+    - memory secret clearance upon ungraceful shutdown
 - Early serial output
 - port 80h direct to GPIO
-- ACPI tables: APIC/DMAR/DSDT/EINJ/FACP/FACS/HEST/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
+- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT
 - Skipping memory training upon subsequent reboots by using MRC cache
 - BMC crash dump
 - Error injection through ITP
@@ -112,13 +104,13 @@ and [u-root] as initramfs.
     - Check Microcode version: cat /proc/cpuinfo | grep microcode
 - Devices:
     - Boot drive
-    - All 5 data drives
     - NIC card
+    - All 5 data drives
 - Power button
 - localboot
 - netboot from IPv6
-- basic memory hardware error injection/detection (SMI handlers not upstreamed)
-- basic PCIe hardware error injection/detection (SMI handlers not upstreamed)
+- basic memory hardware error injection/detection (SMI handler not upstreamed)
+- basic PCIe hardware error injection/detection (SMI handler not upstreamed)
 
 ## Stress/performance tests passed
 - OS warm reboot (1000 cycles)
@@ -128,32 +120,27 @@ and [u-root] as initramfs.
 - StressAppTest (6 hours)
 - Ptugen (6 hours)
 
-## Performance on par with traditional firmware
+## Performance tests on par with traditional firmware
 - coremark
-- FIO
-- Iperf(IPv6)
-- Linpack
-- Intel MLC (memory latency and bandwidth)
 - SpecCPU
-- stream
+- Linkpack
+- Iperf(IPv6)
+- FIO
 
 ## Other tests passed
 - Power
 - Thermal
-- coreboot address sanitizer (both romstage and ramstage)
-- Intel selftest tool (all errors analyzed; applicable errors clean)
 
 ## Known issues
+- MLC (Intel Memory Latency Check) and stream performance issue
 - HECI access at OS run time:
     - spsInfoLinux64 command fail to return ME version
     - ptugen command fail to get memory power
-- CLTT (Closed Loop Thermal Throttling, eg. thermal protection for DIMMs)
-- ProcHot (thermal protection for processors)
 
 ## Feature gaps
 - flashrom command not able to update ME region
-- ACPI BERT table
-- PCIe hotplug through VPP (Virtual Pin Ports)
+- ACPI APEI tables
+- PCIe hotplug, Virtual Pin Ports
 - PCIe Live Error Recovery
 - RO_VPD region as well as other RO regions are not write protected
 - Not able to selectively enable/disable core

Documentation/mainboard/purism/librem_14.md

@@ -1,113 +0,0 @@
-# Purism Librem 14
-
-This page describes how to run coreboot on the [Purism Librem 14].
-
-```eval_rst
-+------------------+------------------------------------------------------+
-| CPU              | Intel Core i7-10710U                                 |
-+------------------+------------------------------------------------------+
-| PCH              | Comet Lake LP Premium (Comet Lake-U)                 |
-+------------------+------------------------------------------------------+
-| EC               | ITE IT8528E                                          |
-+------------------+------------------------------------------------------+
-| Coprocessor      | Intel Management Engine (CSME 14.x)                  |
-+------------------+------------------------------------------------------+
-```
-
-![](librem_14.webp)
-![](librem_14_flash.jpg)
-![](librem_14_ec_flash.jpg)
-
-## Required proprietary blobs
-
-To build a minimal working coreboot image some blobs are required (assuming
-only the BIOS region is being modified).
-
-```eval_rst
-+-----------------+---------------------------------+---------------------+
-| Binary file     | Apply                           | Required / Optional |
-+=================+=================================+=====================+
-| FSP-M, FSP-S    | Intel Firmware Support Package  | Required            |
-+-----------------+---------------------------------+---------------------+
-| microcode       | CPU microcode                   | Required            |
-+-----------------+---------------------------------+---------------------+
-```
-
-FSP-M and FSP-S are obtained after splitting the CometLake1 FSP binary
-(done automatically by the coreboot build system and included into the
-image) from the `3rdparty/fsp` submodule.
-
-Microcode updates are automatically included into the coreboot image by the
-build system from the `3rdparty/intel-microcode` submodule. Official Purism
-release images may include newer microcode, which is instead pulled from
-Purism's [purism-blobs] repository.
-
-A VGA Option ROM is not required to boot, as the Librem 14 uses libgfxinit.
-
-## Intel Management Engine
-
-The Librem 14 uses version 14.x of the Intel Management Engine (ME) /
-Converged Security Engine (CSE). The ME/CSE is disabled using the High
-Assurance Platform (HAP) bit, which puts the ME into a disabled state after
-platform bring-up (BUP) and disables all PCI/HECI interfaces.
-This can be verified checking the coreboot console log, using coreboot’s
-cbmem utility:
-
-    `sudo ./cbmem -1 | grep 'ME:'`
-
-provided coreboot has been patched to output the ME status even when the
-PCI device is not visible/active (as it is in Purism's release builds).
-
-## Flashing coreboot
-
-### Internal programming
-
-The main SPI flash can be accessed using [flashrom]. No official flashrom
-release supports the CometLake-U SoC yet, so it must be built from source.
-Version v1.2-107-gb1f858f or later is needed. Firmware an be easily
-flashed with internal programmer (either BIOS region or full image).
-
-### External programming
-
-The system has an internal flash chip which is a 16 MiB soldered SOIC-8
-chip, and has a diode attached to the VCC line for in-system programming.
-This chip is located on the bottom side of the board, in between the CPU
-heatsink and the left cooling fan, just above the left SO-DIMM slot.
-
-One has to remove all 9 screws from the bottom cover, then disconnect the
-battery from the mainboard (bottom left of mainboard). Use a SOIC-8 chip
-clip to program the chip (a Gigadevice GD25Q127C (3.3V) - [datasheet][GD25Q127C]).
-
-The EC firmware is stored on a separate SOIC-8 chip (a Gigadevices GD25Q80C),
-located underneath the Wi-Fi module, below the left cooling fan.
-
-## Known issues
-
- * Automatic detection of external audio input/output via the 3.5mm jack
-   does not currently work.
- * PL1/PL2 limited to 15W/20W by charger and battery discharge capability,
-   not SoC or thermal design.
-
-## Working
-
- * Internal display with libgfxinit, VGA option ROM, or FSP/GOP init
- * External displays via HDMI, USB-C Alt-Mode
- * SeaBIOS (1.14), Tianocore (CorebootPayloadPkg), and Heads payloads
- * Ethernet, m.2 2230 Wi-Fi
- * System firmware updates via flashrom
- * M.2 storage (NVMe, SATA III)
- * Built-in audio (speakers, microphone)
- * SMBus (reading SPD from DIMMs)
- * Initialization with FSP 2.0 (CometLake1)
- * S3 Suspend/Resume
- * Booting PureOS 10.x, Debian 11.x, Qubes 4.0.4, Windows 10 20H2
-
-## Not working / untested
-
- * N/A
-
-
-[Purism Librem 14]: https://puri.sm/products/librem-14/
-[purism-blobs]: https://source.puri.sm/coreboot/purism-blobs
-[GD25Q127C]: https://www.gigadevice.com/datasheet/gd25q127c/
-[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/supermicro/flashing_on_vendorbmc.md

@@ -30,15 +30,3 @@ You can use the *SMCIPMITool* to remotely flash the BIOS:
 
 Make sure that the ME isn't in recovery mode, otherwise you get an error
 message on updating the BIOS.
-
-## Flashing with disabled ME
-
-If ME is disabled via `me_cleaner` or the ME recovery jumper, it is still
-possible to flash remotely with the [`Supermicro Update Manager`](SUM) (`SUM`).
-
-```sh
-./sum -i <remote BMC IP> -u <user> -p <password> -c UpdateBios --reboot \
-  --force_update --file build/coreboot.rom
-```
-
-[SUM]: https://www.supermicro.com/SwDownload/SwSelect_Free.aspx?cat=SUM

Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md

@@ -7,7 +7,7 @@ Controller etc.
 ## Supported boards
 
 - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md)
-- [X11SSH-F/LN4F](x11ssh-f/x11ssh-f.md)
+- [X11SSH-F](x11ssh-f/x11ssh-f.md)
 - [X11SSM-F](x11ssm-f/x11ssm-f.md)
 
 ## Required proprietary blobs
@@ -18,7 +18,7 @@ Controller etc.
 ## De-blobbing
 
 - [Intel FSP2.0] can not be removed as long as there is no free replacement
-- Intel ME can be cleaned using me_cleaner (~4.5 MiB more free space)
+- Intel ME can be cleaned using me_cleaner (~4.5 MB more free space)
 - Intel Ethernet Controller Firmware can be removed when it's extended functionality is not
   needed. For more details refer to the respective datasheet (e.g 333016-008 for I210).
 - Boards with [AST2400] BMC/IPMI: Firmware can be replaced by [OpenBMC]

Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-f/x11ssh-f.md

@@ -1,6 +1,6 @@
-# Supermicro X11SSH-F/X11SSH-LN4F
+# Supermicro X11SSH-F
 
-This section details how to run coreboot on the [Supermicro X11SSH-F] or [Supermicro X11SSH-LN4F].
+This section details how to run coreboot on the [Supermicro X11SSH-F].
 
 ## Flashing coreboot
 
@@ -43,11 +43,6 @@ tasks, or for offloading graphics rendering via "muxless" [vga_witcheroo].
 - S3 resume not working (vendor and coreboot)
 - SeaBIOS cannot make use of VGA on Aspeed (even if IGD is disabled)
 
-## Difference between X11SSH-F and X11SSH-LN4F
-
-The PCB is identical. The X11SSH-F has 2 NICs, the X11SSH-LN4F has 4 NICs.
-So the X11SSH-F just doesn't have 2 NICs populated.
-
 ## ToDo
 
 - Fix known issues
@@ -65,8 +60,7 @@ So the X11SSH-F just doesn't have 2 NICs populated.
 +------------------+--------------------------------------------------+
 | Super I/O        | ASPEED AST2400                                   |
 +------------------+--------------------------------------------------+
-| Ethernet         | 2x Intel I210-AT 1 GbE (for X11SSH-F)            |
-|                  | 4x Intel I210-AT 1 GbE (for X11SSH-LN4F)         |
+| Ethernet         | 2x Intel I210-AT 1 GbE                           |
 |                  | 1x dedicated BMC                                 |
 +------------------+--------------------------------------------------+
 | PCIe slots       | 1x 3.0 x8                                        |
@@ -101,7 +95,6 @@ So the X11SSH-F just doesn't have 2 NICs populated.
 - [Board manual]
 
 [Supermicro X11SSH-F]: https://www.supermicro.com/en/products/motherboard/X11SSH-F
-[Supermicro X11SSH-LN4F]: https://www.supermicro.com/en/products/motherboard/X11SSH-LN4F
 [Board manual]: https://www.supermicro.com/manuals/motherboard/C236/MNL-1778.pdf
 [AST2400]: https://www.aspeedtech.com/products.php?fPath=20&rId=376
 [IPMI]: ../../../../drivers/ipmi_kcs.md

Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md

@@ -4,14 +4,9 @@ This section details how to run coreboot on the [Supermicro X11SSM-F].
 
 ## Flashing coreboot
 
-The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4.
-
-The board can be flashed externally with a SOIC test clip or probes. Since
-there is no diode between VCC3.3 and the flash chip, so VCC must **not** be
-connected. Instead, the flash chip is powered from VCC3.3, which is always-on
-(even in S5). WP# and HOLD# have pull-ups and don't need to be connected.
-
-FTDI FT2232H and FT232H based programmers worked.
+The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. For this,
+one needs to add a diode between VCC and the flash chip. The flash IC [MX25L12873F] can be found
+near PCH PCIe Slot 4.
 
 Flashing is also possible through the BMC web interface, when a valid license was entered.
 

Documentation/mainboard/system76/gaze15.md

@@ -1,72 +0,0 @@
-# System76 Gazelle 15 (gaze15)
-
-## Specs
-
-- CPU
-  - Intel Core i7 10750H
-- EC
-  - ITE5570E running https://github.com/system76/ec
-- Graphics
-  - Intel UHD Graphics
-  - NVIDIA GeForce GTX 1650/1650 Ti/1660 Ti
-  - eDP 15.6" or 17.3" 1920x1080 @ 120 Hz LCD
-  - HDMI, Mini DisplayPort 1.4, and DisplayPort 1.4 over USB-C
-- Memory
-  - Channel 0: 8-GB/16-GB/32-GB DDR4 SO-DIMM
-  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
-- Networking
-  - Gigabit Ethernet
-  - M.2 PCIe/CNVi Wifi/Bluetooth
-    - Intel Wireless-AC 9560, or
-    - Intel Wi-Fi 6 AX200/AX201
-- Power
-  - 120W AC adapter (GTX 1650 and 1650 Ti)
-  - 180W AC adapter (GTX 1660 Ti)
-  - 48.96Wh battery
-- Sound
-  - Realtek ALC293 codec
-  - TAS5825MRHBR smart AMP
-  - Internal speakers and microphone
-  - Combined headphone and microphone 3.5mm jack
-  - HDMI, Mini DisplayPort, USB-C DP audio
-- Storage
-  - M.2 PCIe/SATA SSD-1
-  - M.2 PCIe SSD-2
-  - 2.5" 7mm drive bay
-  - SD card reader
-  - Realtek RTL8411B card reader
-- USB
-  - 1x USB 2.0
-  - 1x USB 3.0
-  - 1x USB 3.1
-  - 1x USB 3.2 Type-C
-
-## Building coreboot
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.system76_gaze15
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25Q127C/GD25Q128C |
-+---------------------+---------------------+
-| Size                | 16 MiB              |
-+---------------------+---------------------+
-| Package             | SOIC-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```

Documentation/mainboard/system76/oryp5.md

@@ -1,71 +0,0 @@
-# System76 Oryx Pro 5 (oryp5)
-
-## Specs
-
-- CPU
-  - Intel Core i7-8750H
-  - Intel Core i7-9750H
-- EC
-  - ITE8587E running https://github.com/system76/ec
-- Graphics
-  - Intel UHD Graphics 630
-  - NVIDIA GeForce RTX 2080/2070/2060
-  - eDP 16.1" or 17.3" 1920x1080 @ 144 Hz LCD
-  - HDMI, Mini DisplayPort 1.3, and DisplayPort 1.3 over USB-C
-- Memory
-  - Channel 0: 8-GB/16-GB/32-GB DDR4 SO-DIMM
-  - Channel 1: 8-GB/16-GB/32-GB DDR4 SO-DIMM
-- Networking
-  - Gigabit Ethernet
-  - Intel Dual Band Wireless-AC 9560 Wireless LAN (802.11ac) + Bluetooth
-- Power
-  - 180W (19.5V, 9.23A) AC adapter
-  - 62Wh 4-cell battery
-- Sound
-  - Realtek ALC1220 codec
-  - TAS5825MRHBR smart AMP
-  - Internal speakers and microphone
-  - Combined headphone and microphone 3.5mm jack
-  - Combined microphone and S/PDIF 3.5mm jack
-  - HDMI, Mini DisplayPort, USB-C DP audio
-- Storage
-  - M.2 PCIe/SATA SSD1
-  - M.2 PCIe/SATA SSD2
-  - 2.5" SATA HDD/SSD
-  - RTS5250 SD card reader
-- USB
-  - 2x USB 3.1 Gen2 Type-C
-  - 2x USB 3.1 Gen1 Type-A
-
-## Building coreboot
-
-```bash
-make distclean
-make defconfig KBUILD_DEFCONFIG=configs/config.system76_oryp5
-make
-```
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+---------------------+
-| Type                | Value               |
-+=====================+=====================+
-| Socketed flash      | no                  |
-+---------------------+---------------------+
-| Vendor              | GigaDevice          |
-+---------------------+---------------------+
-| Model               | GD25Q127C/GD25Q128C |
-+---------------------+---------------------+
-| Size                | 16 MiB              |
-+---------------------+---------------------+
-| Package             | SOIC-8              |
-+---------------------+---------------------+
-| Internal flashing   | yes                 |
-+---------------------+---------------------+
-| External flashing   | yes                 |
-+---------------------+---------------------+
-```
-
-External flashing via ISP requires removing the board from the chassis.
-The IC is located under the touchpad.

Documentation/mainboard/system76/oryp6.md

@@ -1,60 +0,0 @@
-# System76 Oryx Pro (oryp6)
-
-## Specs
-
-- CPU
-  - Intel i7-10875H
-- Chipset
-  - Intel HM470
-- EC
-  - ITE IT5570E running https://github.com/system76/ec
-- GPU
-  - NVIDIA GeForce RTX 2080 Super (Max-Q)
-  - or NVIDIA GeForce RTX 2070 (Max-Q)
-  - or NVIDIA GeForce RTX 2060
-  - eDP 15.6" or 17.3" 1920x1080@144Hz LCD
-  - HDMI, Mini DisplayPort 1.4, and DisplayPort over USB-C
-- Memory
-  - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz
-- Networking
-  - Gigabit Ethernet
-  - M.2 PCIe/CNVi WiFi/Bluetooth
-    - Intel Wi-Fi 6 AX200/AX201
-- Power
-  - 180W (19.5V, 9.23A) AC adapter
-  - 73Wh 3-cell battery
-- Sound
-  - Internal speakers and microphone
-  - Combined headphone and microphone 3.5mm jack
-  - Combined microphone and S/PDIF (optical) 3.5mm jack
-  - HDMI, Mini DisplayPort, USB-C DisplayPort audio
-- USB
-  - 3x USB 3.2 Gen 1 Type-A
-  - 1x USB Type-C with Thunderbolt 3
-- Dimensions
-  - 15": 35.75cm x 23.8cm x 1.98cm, 1.99kg
-  - 17": 39.59cm x 26.495cm x 1.99cm, 2.3kg
-
-## Flashing coreboot
-
-```eval_rst
-+---------------------+-----------------+
-| Type                | Value           |
-+=====================+=================+
-| Socketed flash      | no              |
-+---------------------+-----------------+
-| Vendor              | Macronix        |
-+---------------------+-----------------+
-| Model               | MX25L12872F     |
-+---------------------+-----------------+
-| Size                | 16 MiB          |
-+---------------------+-----------------+
-| Package             | SOIC-8          |
-+---------------------+-----------------+
-| Internal flashing   | yes             |
-+---------------------+-----------------+
-| External flashing   | yes             |
-+---------------------+-----------------+
-```
-
-The flash chip (U53) is above the M.2 SSD connectors.

Documentation/mainboard/up/squared/index.md

@@ -76,15 +76,15 @@ firmware_vendor.rom
 
 ```bash
 [upsquared]$ mkdir extracted && cd extracted
-[extracted]$ ifdtool -x ../firmware_vendor.rom
+[extracted]$ ifdtool -x ../firmware_vendor.rom 
 File ../firmware_vendor.rom is 16777216 bytes
 Peculiar firmware descriptor, assuming Ibex Peak compatibility.
-  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff
-  Flash Region 1 (BIOS): 00001000 - 00efefff
+  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff 
+  Flash Region 1 (BIOS): 00001000 - 00efefff 
   Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
   Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
   Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
-  Flash Region 5 (Reserved): 00eff000 - 00ffefff
+  Flash Region 5 (Reserved): 00eff000 - 00ffefff 
   Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
   Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
   Flash Region 8 (EC): 07fff000 - 00000fff (unused)

Documentation/releases/checklist.md

@@ -177,9 +177,8 @@ commit db508565d2483394b709654c57533e55eebace51 (HEAD, tag: 4.6, origin/master,
 ...
 ````
 
-When you used the script to generate the release, a signed tag was generated in the
-tree that was downloaded. From the coreboot-X.Y tree, just run: `git push origin X.Y`.
-In case you pushed the wrong tag already, you have to force push the new one.
+When you used the script to generate the release, a tag was generated in the tree that was downloaded.
+From the coreboot-X.Y tree, just run: `git push -f origin <TAG (X.Y)>`
 
 You will need write access for tags to the coreboot git repo to do this.
 

Documentation/releases/coreboot-4.14-relnotes.md

@@ -1,161 +1,16 @@
-coreboot 4.14
-=============
+Upcoming release - coreboot 4.14
+================================
 
-coreboot 4.14 was released on May 10th, 2021.
+The 4.14 release is planned for May 2021.
 
-Since 4.13 there have been 3660 new commits by 215 developers.
-Of these, about 50 contributed to coreboot for the first time.
-Welcome to the project!
+Update this document with changes that should be in the release notes.
 
-These changes have been all over the place, so that there's no
-particular area to focus on when describing this release: We had
-improvements to mainboards, to chipsets (including much welcomed
-work to open source implementations of what has been blobs before),
-to the overall architecture.
-
-Thank you to all developers who made coreboot the great open source
-firmware project that it is, and made our code better than ever.
-
-New mainboards
---------------
-
-* AMD Bilby
-* AMD Majolica
-* GIGABYTE GA-D510UD
-* Google Blipper
-* Google Brya
-* Google Cherry
-* Google Collis
-* Google Copano
-* Google Cozmo
-* Google Cret
-* Google Drobit
-* Google Galtic
-* Google Gumboz
-* Google Guybrush
-* Google Herobrine
-* Google Homestar
-* Google Katsu
-* Google Kracko
-* Google Lalala
-* Google Makomo
-* Google Mancomb
-* Google Marzipan
-* Google Pirika
-* Google Sasuke
-* Google Sasukette
-* Google Spherion
-* Google Storo
-* Google Volet
-* HP 280 G2
-* Intel Alderlake-M RVP
-* Intel Alderlake-M RVP with Chrome EC
-* Intel Elkhartlake LPDDR4x CRB
-* Intel shadowmountain
-* Kontron COMe-mAL10
-* MSI H81M-P33 (MS-7817 v1.2)
-* Pine64 ROCKPro64
-* Purism Librem 14
-* System76 darp5
-* System76 galp3-c
-* System76 gaze15
-* System76 oryp5
-* System76 oryp6
-
-Removed mainboards
-------------------
-
-* Google Boldar
-* Intel Cannonlake U LPDDR4 RVP
-* Intel Cannonlake Y LPDDR4 RVP
-
-Deprecations and incompatible changes
--------------------------------------
-
-### SAR support in VPD for Chrome OS
-
-SAR support in VPD has been deprecated for Chrome OS platforms for > 1
-year now. All new Chrome OS platforms have switched to using SAR
-tables from CBFS. For the next release, coreboot is updated to align
-with the Chrome OS factory changes and hence SAR support in VPD is
-deprecated in [CB:51483](https://review.coreboot.org/51483). Starting
-with this release, anyone building coreboot for an already released
-Chrome OS platform with SAR table in VPD will have to extract the
-"wifi_sar" key from VPD and add it as a file to CBFS using following
-steps:
- * On DUT, read SAR value using `vpd -i RO_VPD -g wifi_sar`
- * In coreboot repo, generate CBFS SAR file using:
-    `echo ${SAR_STRING} > site-local/${BOARD}-sar.hex`
- * Add to site-local/Kconfig:
-    ```
-     config WIFI_SAR_CBFS_FILEPATH
-       string
-       default "site-local/${BOARD}-sar.hex"
-    ```
-
-### CBFS stage file format change
-
-[CB:46484](https://review.coreboot.org/46484) changed the in-flash
-file format of coreboot stages to prepare for per-file signature
-verification. As described in the commit message in more details,
-when manipulating stages in a CBFS, the cbfstool build must match the
-coreboot image so that they're using the same format: coreboot.rom
-and cbfstool must be built from coreboot sources that either both
-contain this change or both do not contain this change.
-
-Since stages are usually only handled by the coreboot build system
-which builds its own cbfstool (and therefore it always matches
-coreboot.rom) this shouldn't be a concern in the vast majority of
-scenarios.
+* Please use Markdown.
+* See the past few release notes for the general format.
+* The chip and board additions and removals will be updated right
+  before the release, so those do not need to be added.
 
 Significant changes
 -------------------
 
-### AMD SoC cleanup and initial Cezanne APU support
-
-There's initial support for the AMD Cezanne APUs in the tree. This code
-hasn't started as a copy of the previous generation, but was based on a
-slightly modified version of the example/min86 SoC. During the cleanup
-of the existing Picasso SoC code the common parts of the code were
-moved to the common AMD SoC code, so that they could be used by the
-Cezanne code instead of adding another slightly different copy.
-
-### X86 bootblock layout
-
-The static size C_ENV_BOOTBLOCK_SIZE was mostly dropped in favor of
-dynamically allocating the stage size; the Kconfig is still available
-to use as a fixed size and to enforce a maximum for selected chipsets.
-Linker sections are now top-aligned for a reduced flash footprint and to
-maintain the requirements of near jump from reset vector.
-
-### ACPI GNVS framework
-
-SMI handlers for APM_CNT_GNVS_UDPATE were dropped; GNVS pointer to SMM is
-now passed from within SMM_MODULE_LOADER. Allocation and initialisations
-for common ACPI GNVS table entries were largely moved to one centralized
-implementation.
-
-### Intel Xeon Scalable Processor support is now considered mature
-
-Intel Xeon Scalable Processor (Xeon-SP) family [1] is designed
-primarily to serve the needs of the server market.
-
-coreboot support for Xeon-SP is in src/soc/intel/xeon_sp directory.
-This release has support for SkyLake-SP (SKX-SP) which is the 2nd
-generation, and for CooperLake-SP (CPX-SP) which is the 3rd generation
-or the latest generation [2] on market.
-
-With this release, the codebase for multiple generations of Xeon-SP
-were unified and optimized:
-* SKX-SP SoC code is used in OCP TiogaPass mainboard [3]. Support for
-this board is in Proof Of Concept Status.
-* CPX-SP SoC code is used in OCP DeltaLake mainboard. Support for
-this board is in DVT (Design Validation Test) exit equivalent status.
-Features supported, (performance/stability) test scopes, known issues,
-features gaps are described in [4].
-
-
-[1] https://www.intel.com/content/www/us/en/products/details/processors/xeon/scalable.html
-[2] https://www.intel.com/content/www/us/en/products/docs/processors/xeon/3rd-gen-xeon-scalable-processors-brief.html
-[3] ../mainboard/ocp/tiogapass.md
-[4] ../mainboard/ocp/deltalake.md
+### Add significant changes here

Documentation/security/vboot/index.md

@@ -188,12 +188,12 @@ In addition to adding the coreboot files into the read-only region,
 enabling vboot causes the build script to add the read/write files into
 coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
 
-**RO_REGION_ONLY**
+**RO_REGION_ONLY**  
 
 The files added to this list will only be placed in the read-only region and
 not into the read/write coreboot file systems in *FW_MAIN_A* and *FW_MAIN_B*.
 
-**VBOOT_ENABLE_CBFS_FALLBACK**
+**VBOOT_ENABLE_CBFS_FALLBACK**  
 
 Normally coreboot will use the active read/write coreboot file system for all
 of it's file access when vboot is active and is not in recovery mode.

Documentation/security/vboot/list_vboot.md

@@ -154,9 +154,7 @@
 - Stout (Lenovo Thinkpad X131e Chromebook)
 - Bubs
 - Coachz
-- Homestar
 - Lazor
-- Marzipan
 - Pompom
 - Trogdor
 - Veyron_Jaq (Haier Chromebook 11)
@@ -255,7 +253,7 @@
 ## Supermicro
 - X11SSH-TF
 - X11SSM-F
-- X11SSH-F/X11SSH-LN4F
+- X11SSH-F
 
 ## UP
 - Squared

Documentation/soc/qualcomm/index.md

@@ -5,4 +5,3 @@ This section contains documentation about coreboot on specific Qualcomm SOCs.
 ## Platforms
 
 - [SC7180 series](sc7180/index.md)
-- [SC7280 series](sc7280/index.md)

Documentation/soc/qualcomm/sc7280/index.md

@@ -1,17 +0,0 @@
-# Qualcomm SC7280 documentation
-
-## SOC code
-
-The SOC folder contains functions for:
-* MMU
-* CLOCK
-* GPIO
-* QUPv3 FW (provides a bridge to serial interfaces)
-* UART
-* SPI-NOR
-* AOP FW
-* USB
-
-## Notes about the hardware
-
-The timer is used from the ARMv8 architecture specific code.

Documentation/tutorial/index.md

@@ -3,4 +3,3 @@
 * [Part 1: Starting from scratch](part1.md)
 * [Part 2: Submitting a patch to coreboot.org](part2.md)
 * [Part 3: Writing unit tests](part3.md)
-* [Managing local additions](managing_local_additions.md)

Documentation/tutorial/managing_local_additions.md

@@ -1,43 +0,0 @@
-Managing local additions
-========================
-
-This section describes the site-local mechanism, what it is good for and
-how it can be used.
-
-What is site-local?
--------------------
-site-local is the name of a directory that won't ever appear in the
-upstream coreboot repository but is referred to in several key places of its
-configuration and build system. The intent is provide a single location to
-store local modifications.
-
-By keeping local additions to builds in this place, it can be versioned
-independently from upstream (e.g. controlled by git in another repository)
-and any changes made there won't ever conflict with upstream changes.
-
-This optional directory is searched for in the top-level of the coreboot
-repo and is called `site-local`.
-
-Integration into the configuration system
------------------------------------------
-Kconfig includes `site-local/Kconfig` relatively early, so it can be used
-to pre-define some configuration before coreboot's regular ruleset sets
-up defaults.
-
-Integration into the build system
----------------------------------
-The build system includes, if present, `site-local/Makefile.inc`. The main
-purpose so far has been to add additional files to a CBFS image. A single
-Makefile.inc can serve multiple boards, for example:
-
-    cbfs-files-$(CONFIG_BOARD_INTEL_D945GCLF) += pci8086,2772.rom
-    pci8086,2772.rom-file := intel_d945gclf/pci8086,2772.rom
-    pci8086,2772.rom-type := optionrom
-
-    cbfs-files-$(CONFIG_BOARD_KONTRON_986LCD_M) += pci8086,27a2.rom
-    pci8086,27a2.rom-file := kontron_986lcd-m/pci8086,27a2.rom
-    pci8086,27a2.rom-type := optionrom
-
-This adds the correct Option ROM binary (which are non-redistributable and
-therefore can't become part of the coreboot.org repos) to coreboot.rom when
-built for intel/d945gclf or kontron/986lcd-m.

Documentation/util.md

@@ -2,16 +2,13 @@
 
 ## List of utils
 
-_Scripts and programs found in the coreboot `./util` directory_
+_Scripts and programs found in the `./util` directory_
 * __abuild__ - coreboot autobuild script builds coreboot images for all
 available targets. `bash`
 * __acpi__ - Walk through all ACPI tables with their addresses. `bash`
 * __amdfwtool__ - Create AMD Firmware combination `C`
 * __amdtools__ - A set of tools to compare extended) K8 memory
 settings. `Perl`
-* __apcb__ - AMD PSP Control Block tools
-	* _apcb_edit.py_ - This tool allows patching an existing APCB
-binary with specific SPDs and GPIO selection pins. `Python3`
 * __archive__ - Concatenate files and create an archive `C`
 * __autoport__ - Automated porting coreboot to Sandy Bridge/Ivy Bridge
 platforms `Go`
@@ -23,8 +20,7 @@ status repository `Bash` `Go`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
-	* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file
-`C`
+	* [_cbfstool_](cbfstool/index.md) - For manipulating CBFS file `C`
 	* _fmaptool_ - Converts plaintext fmd files into fmap blobs `C`
 	* _rmodtool_ - Creates rmodules `C`
 	* _ifwitool_ - For manipulating IFWI `C`
@@ -41,18 +37,18 @@ _coreboot.org-status_ and _docs.coreboot.org_
 * __ectool__ - Dumps the RAM of a laptop's Embedded/Environmental
 Controller (EC). `C`
 * __exynos__ - Computes and fills Exynos ROM checksum (for BL1 or BL2).
-`Python3`
+`Python2`
 * __find_usbdebug__ - Help find USB debug ports
 * __futility__ - Firmware utility for signing ChromeOS images `Make`
 * __fuzz-tests__ - Create test cases that crash the jpeg code. `C`
 * __genbuild_h__ - Generate build system definitions `Shell`
+* __genprof__ - Format function tracing logs `Bash` `C`
 * __gitconfig__ - Initialize git repository submodules install git
 hooks `Bash`
-* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware
-Descriptor information `C`
+* [__ifdtool__](ifdtool/index.md) - Extract and dump Intel Firmware Descriptor information
+`C`
 * __intelmetool__ - Dump interesting things about Management Engine
 even if hidden `C`
-* __intelp2m__ - Intel Pad to Macro (intelp2m) converter 'Go'
 * __inteltool__ - Provides information about the Intel CPU/chipset
 hardware configuration (register contents, MSRs, etc). `C`
 * __intelvbttool__ - Parse VBT from VGA BIOS `C`
@@ -69,14 +65,12 @@ firmware of many HP laptops with 8051-based SMSC KBC1098/KBC1126
 embedded controller and insert them to the firmware image. `C`
 * __kconfig__ - Build system `Make`
 * __lint__ - Source linter and linting rules `Shell`
-* __mainboard__ - mainboard specific scripts
-	* _google_ - Directory for google mainboard specific scripts
 * __marvell__ - Add U-Boot boot loader for Marvell ARMADA38X `C`
 * __[me_cleaner](https://github.com/corna/me_cleaner)__ - Tool for
 partial deblobbing of Intel ME/TXE firmware images `Python`
 * __mma__ - Memory Margin Analysis automation tests `Bash`
 * __msrtool__ - Dumps chipset-specific MSR registers. `C`
-* __mtkheader__ - Generate MediaTek bootload header. `Python3`
+* __mtkheader__ - Generate MediaTek bootload header. `Python2`
 * __nvidia__ - nvidia blob parsers
 * __nvramtool__ - Reads and writes coreboot parameters and displaying
 information from the coreboot table in CMOS/NVRAM. `C`
@@ -86,8 +80,6 @@ information from the coreboot table in CMOS/NVRAM. `C`
 ThinkPads. PMH7 is used for switching on and off the power of some
 devices on the board such as dGPU. `C`
 * __post__ - Userspace utility that can be used to test POST cards. `C`
-* __qemu__ - Makefile & comprehensive default config for QEMU Q35
-emulation
 * __qualcomm__ - CMM script to debug Qualcomm coreboot environments.
 `CMM`
 * __release__ - Generate coreboot release `Bash`
@@ -96,7 +88,7 @@ emulation
 can be passed to SPIKE, the RISC-V reference emulator.`Bash`
 	* _sifive-gpt.py_ - Wraps the bootblock in a GPT partition for
 SiFive's bootrom. `Python3`
-* __rockchip__ - Generate Rockchip idblock bootloader. `Python3`
+* __rockchip__ - Generate Rockchip idblock bootloader. `Python2`
 * __sconfig__ - coreboot device tree compiler `Lex` `Yacc`
 * __scripts__
 	* _config_ - Manipulate options in a .config file from the
@@ -125,19 +117,11 @@ file `Perl`
 * __spdtool__ - Dumps SPD ROMs from a given blob to separate files
 using known patterns and reserved bits. Useful for analysing firmware
 that holds SPDs on boards that have soldered down DRAM. `python`
-* __spd_tools__ - Tools for generating SPD files for DDR4 memory used
-in platforms with memory down configuration.
-	* _gen_spd.go_ - Generates de-duplicated SPD files using a
-global memory part list provided by the mainboard in JSON format. `Go`
-	* _gen_part_id.go_ - Allocates DRAM strap IDs for different
-DDR4 memory parts used by the board. `Go`
 * __spkmodem_recv__ - Decode spkmodem signals `C`
 * __superiotool__ - A user-space utility to detect Super I/O of a
 mainboard and provide detailed information about the register contents
 of the Super I/O. `C`
-* __supermicro__ - Tools for supermicro platforms
-	* _smcbiosinfo_ - Generates SMC biosinfo for BMC BIOS updates
-`C`
+* __smcbiosinfo__ - Generates SMC biosinfo for BMC BIOS updates `C`
 * __testing__ - coreboot test targets `Make`
 * __uio_usbdebug__ - Debug coreboot's usbdebug driver inside a running
 operating system (only Linux at this time). `C`
@@ -151,17 +135,6 @@ the documentation `Bash`
 * __xcompile__ - Cross compile setup `Bash`
 
 
- ## In depth documentation
+## In depth documentation
 
 * [ifdtool](ifdtool/index.md)
-
-## Generated documentation
-
-**Please do not edit the markdown file in the documentation directory
-*directly.**
-
-This file was generated by running util_readme.sh. Please make sure it
-is rerun when new tools are added or when documentation is updated.
-
-To update, edit the markdown files in the util directory, then
-re-generate this file by running `util/util_readme/util_readme.sh`

LICENSES/Apache-2.0.txt

@@ -7,17 +7,17 @@ AND DISTRIBUTION
 
    1. Definitions.
 
-
+      
 
 "License" shall mean the terms and conditions for use, reproduction, and distribution
 as defined by Sections 1 through 9 of this document.
 
-
+      
 
 "Licensor" shall mean the copyright owner or entity authorized by the copyright
 owner that is granting the License.
 
-
+      
 
 "Legal Entity" shall mean the union of the acting entity and all other entities
 that control, are controlled by, or are under common control with that entity.
@@ -26,31 +26,31 @@ or indirect, to cause the direction or management of such entity, whether
 by contract or otherwise, or (ii) ownership of fifty percent (50%) or more
 of the outstanding shares, or (iii) beneficial ownership of such entity.
 
-
+      
 
 "You" (or "Your") shall mean an individual or Legal Entity exercising permissions
 granted by this License.
 
-
+      
 
 "Source" form shall mean the preferred form for making modifications, including
 but not limited to software source code, documentation source, and configuration
 files.
 
-
+      
 
 "Object" form shall mean any form resulting from mechanical transformation
 or translation of a Source form, including but not limited to compiled object
 code, generated documentation, and conversions to other media types.
 
-
+      
 
 "Work" shall mean the work of authorship, whether in Source or Object form,
 made available under the License, as indicated by a copyright notice that
 is included in or attached to the work (an example is provided in the Appendix
 below).
 
-
+      
 
 "Derivative Works" shall mean any work, whether in Source or Object form,
 that is based on (or derived from) the Work and for which the editorial revisions,
@@ -59,7 +59,7 @@ original work of authorship. For the purposes of this License, Derivative
 Works shall not include works that remain separable from, or merely link (or
 bind by name) to the interfaces of, the Work and Derivative Works thereof.
 
-
+      
 
 "Contribution" shall mean any work of authorship, including the original version
 of the Work and any modifications or additions to that Work or Derivative
@@ -74,7 +74,7 @@ for the purpose of discussing and improving the Work, but excluding communicatio
 that is conspicuously marked or otherwise designated in writing by the copyright
 owner as "Not a Contribution."
 
-
+      
 
 "Contributor" shall mean Licensor and any individual or Legal Entity on behalf
 of whom a Contribution has been received by Licensor and subsequently incorporated

LICENSES/GPL-2.0-only.txt

@@ -2,7 +2,7 @@ GNU GENERAL PUBLIC LICENSE
 
 Version 2, June 1991
 
-Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+Copyright (C) 1989, 1991 Free Software Foundation, Inc. 
 
 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
 

LICENSES/GPL-2.0-or-later.txt

@@ -2,7 +2,7 @@ GNU GENERAL PUBLIC LICENSE
 
 Version 2, June 1991
 
-Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+Copyright (C) 1989, 1991 Free Software Foundation, Inc. 
 
 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
 

MAINTAINERS

@@ -181,7 +181,6 @@ F:	src/mainboard/asus/maximus_iv_gene-z/
 
 ASUS P5QC PRO MAINBOARD & VARIANTS
 M:	Angel Pons <th3fanbus@gmail.com>
-R:	Stefan Ott <coreboot@desire.ch>
 S:	Maintained
 F:	src/mainboard/asus/p5qc/
 
@@ -246,11 +245,6 @@ F:	src/mainboard/getac/p470/
 
 
 
-GIGABYTE GA-D510UD MAINBOARD
-M:	Angel Pons <th3fanbus@gmail.com>
-S:	Maintained
-F:	src/mainboard/gigabyte/ga-d510ud/
-
 GIGABYTE GA-G41M-ES2L MAINBOARD
 M:	Damien Zammit <damien@zamaudio.com>
 S:	Odd Fixes
@@ -262,26 +256,12 @@ S:	Maintained
 F:	src/mainboard/gigabyte/ga-h61m-series/
 
 
-GOOGLE BRYA MAINBOARDS
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
-S:	Maintained
-F:	src/mainboard/google/brya/
-
-GOOGLE HATCH MAINBOARDS
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
-S:	Maintained
-F:	src/mainboard/google/hatch/
 
 GOOGLE PANTHER MAINBOARD
 M:	Stefan Reinauer <stefan.reinauer@coreboot.org>
 S:	Supported
 F:	src/mainboard/google/panther/
 
-GOOGLE VOLTEER MAINBOARDS
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
-S:	Maintained
-F:	src/mainboard/google/volteer/
-
 GOOGLE MAINBOARDS (Intel-based, legacy/inactive)
 M:	Matt DeVillier <MrChromebox@gmail.com>
 S:	Maintained
@@ -298,13 +278,6 @@ F:	src/mainboard/google/stout/
 
 
 
-HP 280 G2 MAINBOARD
-M:	Angel Pons <th3fanbus@gmail.com>
-S:	Maintained
-F:	src/mainboard/hp/280_g2/
-
-
-
 INTEL D510MO MAINBOARD
 M:	Damien Zammit <damien@zamaudio.com>
 S:	Odd Fixes
@@ -343,15 +316,6 @@ M:	Mike Banon <mikebdp2@gmail.com>
 S:	Maintained
 F:	src/mainboard/lenovo/g505s/
 
-LENOVO X200 MAINBOARD
-R:	Stefan Ott <coreboot@desire.ch>
-S:	Maintained
-F:	src/mainboard/lenovo/x200/
-
-LENOVO X201 MAINBOARD
-R:	Stefan Ott <coreboot@desire.ch>
-S:	Maintained
-F:	src/mainboard/lenovo/x201/
 
 
 LIBRETREND LT1000 MAINBOARD
@@ -361,14 +325,6 @@ S:	Maintained
 F:	src/mainboard/libretrend/lt1000/
 
 
-
-MSI H81M-P33 MAINBOARD
-M:	Angel Pons <th3fanbus@gmail.com>
-S:	Maintained
-F:	src/mainboard/msi/h81m-p33/
-
-
-
 OCP DELTALAKE MAINBOARD
 M:	Jonathan Zhang <jonzhang@fb.com>
 M:	Reddy Chagam <anjaneya.chagam@intel.com>
@@ -520,11 +476,6 @@ F:	src/include/cpu/x86/
 # Embedded Controllers
 ################################################################################
 
-CHROME EC
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
-S:	Maintained
-F:	src/ec/google/chromeec/
-
 LENOVO EC
 M:	Alexander Couzens <lynxis@fe80.eu>
 S:	Maintained
@@ -612,7 +563,6 @@ AMD Cezanne
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Raul E Rangel <rrangel@chromium.org>
 S:	Maintained
 F:	src/soc/amd/cezanne/
 
@@ -620,7 +570,6 @@ AMD common SoC code
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Raul E Rangel <rrangel@chromium.org>
 S:	Maintained
 F:	src/soc/amd/common/
 
@@ -628,16 +577,10 @@ AMD Picasso
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
-M:	Raul E Rangel <rrangel@chromium.org>
 S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
 
-INTEL ALDERLAKE SOC
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
-S:	Maintained
-F:	src/soc/intel/alderlake/
-
 INTEL APOLLOLAKE_SOC
 M:	Andrey Petrov <andrey.petrov@gmail.com>
 S:	Maintained
@@ -651,11 +594,6 @@ S:	Maintained
 F:	/src/soc/intel/braswell/
 F:	/src/vendorcode/intel/fsp/fsp1_1/braswell/
 
-INTEL TIGERLAKE SOC
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
-S:	Maintained
-F:	src/soc/intel/tigerlake/
-
 INTEL Xeon Sacalable Processor Family
 M:	Jonathan Zhang <jonzhang@fb.com>
 M:	Reddy Chagam <anjaneya.chagam@intel.com>
@@ -664,7 +602,7 @@ M:	Morgan Jang <Morgan_Jang@wiwynn.com>
 M:	Ryback Hung <<Ryback.Hung@quantatw.com>
 M:	Bryant Ou <Bryant.Ou@quantatw.com>
 S:	Supported
-F:	src/soc/intel/xeon_sp/
+F:	src/soc/intel/xeon_sp
 F:	src/vendorcode/intel/fsp/fsp2_0/skylake_sp/
 F:	src/vendorcode/intel/fsp/fsp2_0/copperlake_sp/
 
@@ -673,12 +611,6 @@ M:	Hung-Te Lin <hungte@chromium.org>
 S:	Supported
 F:	src/soc/mediatek/
 
-MEDIATEK MT8192
-M:	Xi Chen <xixi.chen@mediatek.com>
-S:	Maintained
-F:	src/soc/mediatek/mt8192/
-F:	src/vendorcode/mediatek/mt8192/
-
 ORPHANED ARM SOCS
 S:	Orphaned
 F:	src/cpu/armltd/
@@ -786,7 +718,6 @@ F:	src/drivers/aspeed/ast2050/
 
 ACPI
 M:	Lance Zhao <lance.zhao@gmail.com>
-M:	Tim Wawrzynczak <twawrzynczak@chromium.org>
 S:	Supported
 F:	src/acpi/
 F:	src/arch/x86/acpi/
@@ -864,11 +795,6 @@ M:	Wim Vervoorn <wvervoorn@eltan.com>
 S:	Maintained
 F:	src/vendorcode/eltan/
 
-TESTS
-M:	Jakub Czapiga <jacz@semihalf.com>
-S:	Maintained
-F:	tests/
-
 MISSING: TIMERS / DELAYS
 
 MISSING: TIMESTAMPS

Makefile

@@ -13,8 +13,6 @@ objutil ?= $(obj)/util
 objk := $(objutil)/kconfig
 absobj := $(abspath $(obj))
 
-additional-dirs :=
-
 VBOOT_HOST_BUILD ?= $(abspath $(objutil)/vboot_lib)
 
 COREBOOT_EXPORTS := COREBOOT_EXPORTS
@@ -24,10 +22,7 @@ COREBOOT_EXPORTS += top src srck obj objutil objk
 LANG:=C
 LC_ALL:=C
 TZ:=UTC0
-SOURCE_DATE_EPOCH := $(shell $(top)/util/genbuild_h/genbuild_h.sh . | sed -n 's/^.define COREBOOT_BUILD_EPOCH\>.*"\(.*\)".*/\1/p')
-# don't use COREBOOT_EXPORTS to ensure build steps outside the coreboot build system
-# are reproducible
-export LANG LC_ALL TZ SOURCE_DATE_EPOCH
+COREBOOT_EXPORTS += LANG LC_ALL TZ
 
 DOTCONFIG ?= $(top)/.config
 KCONFIG_CONFIG = $(DOTCONFIG)
@@ -114,22 +109,16 @@ NOCOMPILE:=1
 endif
 ifneq ($(filter %clean lint% help% what-jenkins-does,$(MAKECMDGOALS)),)
 NOMKDIR:=1
-UNIT_TEST:=1
 endif
 endif
 
-ifneq ($(filter help%, $(MAKECMDGOALS)), )
-NOCOMPILE:=1
-UNIT_TEST:=1
-else
-ifneq ($(filter %-test %-tests, $(MAKECMDGOALS)),)
+ifneq ($(filter %-test %-tests,$(MAKECMDGOALS)),)
 ifneq ($(filter-out %-test %-tests, $(MAKECMDGOALS)),)
 $(error Cannot mix unit-tests targets with other targets)
 endif
 UNIT_TEST:=1
 NOCOMPILE:=
 endif
-endif
 
 $(xcompile): util/xcompile/xcompile
 	rm -f $@
@@ -147,7 +136,6 @@ include $(TOPLEVEL)/Makefile.inc
 include $(TOPLEVEL)/payloads/Makefile.inc
 include $(TOPLEVEL)/util/testing/Makefile.inc
 -include $(TOPLEVEL)/site-local/Makefile.inc
-include $(TOPLEVEL)/tests/Makefile.inc
 real-all:
 	@echo "Error: Expected config file ($(DOTCONFIG)) not present." >&2
 	@echo "Please specify a config file or run 'make menuconfig' to" >&2

Makefile.inc

@@ -42,7 +42,6 @@ COREBOOT_EXPORTS += MAINBOARDDIR VARIANT_DIR CARRIER_DIR
 ## rom image file, are placed under $(objcbfs).
 ## These typically have suffixes .debug .elf .bin and .map
 objcbfs := $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)
-additional-dirs += $(objcbfs)
 COREBOOT_EXPORTS += objcbfs
 
 ## Based on the active configuration, Makefile conditionally collects
@@ -50,7 +49,6 @@ COREBOOT_EXPORTS += objcbfs
 ## Such files that do not have a clear one-to-one relation to a source
 ## file under src/ are placed and built under $(objgenerated)
 objgenerated := $(obj)/generated
-additional-dirs += $(objgenerated)
 COREBOOT_EXPORTS += objgenerated
 
 ## CCACHE_EXTRAFILES can be set by individual rules to help CCACHE
@@ -60,7 +58,7 @@ COREBOOT_EXPORTS += CCACHE_EXTRAFILES
 #######################################################################
 # root rule to resolve if in build mode (ie. configuration exists)
 real-target: $(obj)/config.h coreboot files_added
-coreboot: $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool
+coreboot: build-dirs $(obj)/coreboot.rom $(obj)/cbfstool $(obj)/rmodtool $(obj)/ifwitool
 
 # This target can be used in site local to run scripts or additional
 # targets after the build completes by creating a Makefile.inc in the
@@ -75,7 +73,7 @@ files_added:: build_complete
 
 #######################################################################
 # our phony targets
-PHONY+= clean-abuild coreboot check-style build_complete
+PHONY+= clean-abuild coreboot check-style build-dirs build_complete
 
 #######################################################################
 # root source directories of coreboot
@@ -193,8 +191,6 @@ endif
 ifneq ($(UPDATED_SUBMODULES),1)
 # try to fetch non-optional submodules if the source is under git
 forgetthis:=$(if $(GIT),$(shell git submodule update --init))
-# Checkout Cmocka repository
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/cmocka))
 ifeq ($(CONFIG_USE_BLOBS),y)
 # These items are necessary because each has update=none in .gitmodules.  They are ignored
 # until expressly requested and enabled with --checkout
@@ -263,14 +259,14 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150
 # Redundant offset remarks are not useful in any way and are masking useful
 # ones that might indicate an issue so it is better to hide them.
 REDUNDANT_OFFSET_REMARK = 2158
-# Ignore _HID & _ADR coexisting in Intel Lynxpoint ASL code.
-# See cb:38802
+# Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code.
+# See cb:38803 & cb:38802
 # "Multiple types (Device object requires either a _HID or _ADR, but not both)"
 MULTIPLE_TYPES_WARNING = 3073
 
 IASL_WARNINGS_LIST = $(EMPTY_RESOURCE_TEMPLATE_WARNING) $(REDUNDANT_OFFSET_REMARK)
 
-ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y)
+ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y)
 IASL_WARNINGS_LIST += $(MULTIPLE_TYPES_WARNING)
 endif
 
@@ -339,7 +335,7 @@ endef
 cbfs-files-processor-struct= \
 	$(eval $(2): $(1) $(obj)/build.h $(KCONFIG_AUTOHEADER); \
 		printf "    CC+STRIP   $(1)\n"; \
-		$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) --param asan-globals=0 $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
+		$(CC_ramstage) -MMD $(CPPFLAGS_ramstage) $(CFLAGS_ramstage) $$(ramstage-c-ccopts) -include $(KCONFIG_AUTOHEADER) -MT $(2) -o $(2).tmp -c $(1) && \
 		$(OBJCOPY_ramstage) -O binary --set-section-flags .bss*=alloc,contents,load $(2).tmp $(2); \
 		rm -f $(2).tmp) \
 	$(eval DEPENDENCIES += $(2).d)
@@ -430,7 +426,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11
 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
 CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough
 CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla
-CFLAGS_common += -Wdangling-else
+CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else
 CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie
 ifeq ($(CONFIG_COMPILER_GCC),y)
@@ -439,7 +435,6 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),)
 CFLAGS_common += -Wno-packed-not-aligned
 CFLAGS_common += -fconserve-stack
 CFLAGS_common += -Wnull-dereference -Wreturn-type
-CFLAGS_common += -Wlogical-op -Wduplicated-cond
 # cf. commit f69a99db (coreboot: x86: enable gc-sections)
 CFLAGS_common += -Wno-unused-but-set-variable
 endif
@@ -489,13 +484,7 @@ ADAFLAGS_common += -gnatwa.eeD.HHTU.U.W.Y
 # Disable style checks for now
 ADAFLAGS_common += -gnatyN
 
-LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static
-
-# Workaround for RISC-V linker bug, merge back into above line when fixed.
-# https://sourceware.org/bugzilla/show_bug.cgi?id=27180
-ifneq ($(CONFIG_ARCH_RISCV),y)
-LDFLAGS_common += --emit-relocs
-endif
+LDFLAGS_common := --gc-sections -nostdlib -nostartfiles -static --emit-relocs
 
 ifeq ($(CONFIG_WARNINGS_ARE_ERRORS),y)
 CFLAGS_common += -Werror
@@ -512,7 +501,7 @@ ifeq ($(CONFIG_DEBUG_ADA_CODE),y)
 ADAFLAGS_common += -gnata
 endif
 
-additional-dirs += $(objutil)/cbfstool $(objutil)/ifdtool \
+additional-dirs := $(objutil)/cbfstool $(objutil)/ifdtool \
 		   $(objutil)/options $(objutil)/amdfwtool \
 		   $(objutil)/cbootimage
 
@@ -540,6 +529,9 @@ $(build_h): $$(shell $$(build_h_check))
 	@printf "    GEN        build.h\n"
 	mv $< $@
 
+build-dirs $(objcbfs) $(objgenerated):
+	mkdir -p $(objcbfs) $(objgenerated)
+
 $(obj)/build_info:
 	@echo 'COREBOOT_VERSION: $(call strip_quotes,$(KERNELVERSION))' > $@.tmp
 	@echo 'MAINBOARD_VENDOR: $(call strip_quotes,$(CONFIG_MAINBOARD_VENDOR))' >> $@.tmp
@@ -771,7 +763,7 @@ $(objcbfs)/bootblock.raw.bin: $(objcbfs)/bootblock.raw.elf
 	$(OBJCOPY_bootblock) -O binary $< $@
 
 ifneq ($(CONFIG_HAVE_BOOTBLOCK),y)
-$(objcbfs)/bootblock.bin:
+$(objcbfs)/bootblock.bin: $(objcbfs)
 	dd if=/dev/zero of=$@ bs=64 count=1
 endif
 
@@ -1153,7 +1145,7 @@ RAMSTAGE=
 endif
 
 add_intermediate = \
-	$(1): $(obj)/coreboot.pre $(2) | $(INTERMEDIATE) \
+	$(1): $(2) | $(INTERMEDIATE) \
 	$(eval INTERMEDIATE+=$(1)) $(eval PHONY+=$(1))
 
 $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
@@ -1259,7 +1251,7 @@ cbfs-get-segments-cmd = $(CBFSTOOL) $(obj)/coreboot.pre print -v | sed -n \
 ramstage-symbol-addr-cmd = $(OBJDUMP_ramstage) -t $(objcbfs)/ramstage.elf | \
 	sed -n '/ $(1)$$/s/^\([0-9a-fA-F]*\) .*/0x\1/p'
 
-$(call add_intermediate, check-ramstage-overlaps)
+$(call add_intermediate, check-ramstage-overlaps, $(obj)/coreboot.pre)
 	programs=$$($(foreach file,$(check-ramstage-overlap-files), \
 		$(call cbfs-get-segments-cmd,$(file)) ; )) ; \
 	regions=$$($(foreach region,$(check-ramstage-overlap-regions), \

configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100

@@ -3,15 +3,14 @@
 # the future, then this config can be split into several smaller chunks.
 # Exercises, among other things:
 # + Code coverage
-# + ASAN
 # + UBSAN
 # + Debug options
 # + SMMSTORE
 # + Silicon Image SIL3114 driver
 # + Genesys Logic GL9763E driver
 # + EM100 support
+# + SMM module loader V2
 CONFIG_COVERAGE=y
-CONFIG_ASAN=y
 CONFIG_UBSAN=y
 CONFIG_VENDOR_ASROCK=y
 CONFIG_ONBOARD_VGA_IS_PRIMARY=y
@@ -46,4 +45,5 @@ CONFIG_DEBUG_COVERAGE=y
 CONFIG_DEBUG_BOOT_STATE=y
 CONFIG_DEBUG_ADA_CODE=y
 CONFIG_HAVE_EM100_SUPPORT=y
+CONFIG_X86_SMM_LOADER_VERSION2=y
 CONFIG_EM100=y

configs/config.emulation_qemu_x86_i440fx_asan

@@ -1 +0,0 @@
-CONFIG_ASAN=y

configs/config.emulation_qemu_x86_q35_smm_tseg

@@ -1,4 +0,0 @@
-CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y
-CONFIG_CPU_QEMU_X86_PARALLEL_MP=y
-CONFIG_CPU_QEMU_X86_TSEG_SMM=y
-CONFIG_CPU_QEMU_X86_SMMLOADERV2=y

configs/config.facebook_fbg1701.mboot_vboot

@@ -1,4 +1,5 @@
 CONFIG_VENDOR_FACEBOOK=y
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x6000
 CONFIG_ONBOARD_SAMSUNG_MEM=y
 CONFIG_CPU_MICROCODE_CBFS_LOC=0xFFF8B000
 CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS=y

configs/config.gigabyte_ga-g41m-es2l

@@ -1,13 +0,0 @@
-CONFIG_VENDOR_GIGABYTE=y
-CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
-CONFIG_MAINBOARD_VERSION="1.1"
-CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
-CONFIG_ONBOARD_VGA_IS_PRIMARY=y
-CONFIG_PAYLOAD_CONFIGFILE=".config_seabios"
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_USE_BLOBS=y
-CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
-
-# It is better to take this unique value from old CMOS.
-# Default MAC-address is 00:e0:4c:00:c0:b0
-# CONFIG_REALTEK_8168_MACADDRESS="6c:f0:49:xx:xx:xx"

configs/config.google_volteer.build_test_purposes

@@ -1,32 +0,0 @@
-# Not meant for actual use, but rather to build-test individual options.
-# If keeping this combination of options buildable becomes too hard in
-# the future, then this config can be split into several smaller chunks.
-# Exercises, among other things:
-# + Debug options
-# + Crashlog
-# + Flashconsole
-CONFIG_VENDOR_GOOGLE=y
-CONFIG_CONSOLE_POST=y
-CONFIG_BOARD_GOOGLE_VOLTEER=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-CONFIG_INTEL_TME=y
-CONFIG_SOC_INTEL_CRASHLOG=y
-CONFIG_NO_GFX_INIT=y
-CONFIG_DISPLAY_HOBS=y
-CONFIG_DISPLAY_UPD_DATA=y
-CONFIG_CONSOLE_SPI_FLASH=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
-CONFIG_DISPLAY_MTRRS=y
-CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y
-CONFIG_DISPLAY_FSP_HEADER=y
-CONFIG_VERIFY_HOBS=y
-CONFIG_FATAL_ASSERTS=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_DEBUG_CBFS=y
-CONFIG_DEBUG_SMBUS=y
-CONFIG_DEBUG_SMI=y
-CONFIG_DEBUG_PERIODIC_SMI=y
-CONFIG_DEBUG_MALLOC=y
-CONFIG_DEBUG_CONSOLE_INIT=y
-CONFIG_DEBUG_SPI_FLASH=y
-CONFIG_DEBUG_BOOT_STATE=y

configs/config.system76_gaze15

@@ -1,5 +0,0 @@
-CONFIG_VENDOR_SYSTEM76=y
-CONFIG_BOARD_SYSTEM76_GAZE15=y
-CONFIG_PAYLOAD_TIANOCORE=y
-CONFIG_RUN_FSP_GOP=y
-CONFIG_SMMSTORE=y

configs/config.system76_oryp5

@@ -1,6 +0,0 @@
-CONFIG_VENDOR_SYSTEM76=y
-CONFIG_BOARD_SYSTEM76_ORYP5=y
-CONFIG_PAYLOAD_TIANOCORE=y
-CONFIG_POST_IO=n
-CONFIG_RUN_FSP_GOP=y
-CONFIG_SMMSTORE=y

payloads/Makefile.inc

@@ -10,7 +10,7 @@ img/coreinfo-type := payload
 img/coreinfo-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
 cbfs-files-$(CONFIG_NVRAMCUI_SECONDARY_PAYLOAD) += img/nvramcui
-img/nvramcui-file := payloads/nvramcui/build/nvramcui.elf
+img/nvramcui-file := payloads/nvramcui/nvramcui.elf
 img/nvramcui-type := payload
 img/nvramcui-compression := $(CBFS_SECONDARY_PAYLOAD_COMPRESS_FLAG)
 
@@ -29,14 +29,10 @@ payloads/external/GRUB2 \
 payloads/external/LinuxBoot \
 payloads/external/Yabits \
 
-force-payload:
-
-payloads/coreinfo/build/coreinfo.elf coreinfo: export CCACHE := $(CCACHE)
-payloads/coreinfo/build/coreinfo.elf coreinfo: force-payload
+payloads/coreinfo/build/coreinfo.elf coreinfo:
 	$(MAKE) -C payloads/coreinfo defaultbuild
 
-payloads/nvramcui/build/nvramcui.elf nvramcui: export CCACHE := $(CCACHE)
-payloads/nvramcui/build/nvramcui.elf nvramcui: force-payload
+payloads/nvramcui/nvramcui.elf nvramcui:
 	$(MAKE) -C payloads/nvramcui
 
 clean-payloads:
@@ -48,5 +44,4 @@ distclean-payloads:
 print-repo-info-payloads:
 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
 
-.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads nvramcui coreinfo

payloads/coreinfo/.gitignore

@@ -1,2 +1,2 @@
-libpayload/
-.lp.config*
+lpbuild/
+lp.config*

payloads/coreinfo/Makefile

@@ -1,40 +1,23 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-unexport $(COREBOOT_EXPORTS)
-
 src := $(CURDIR)
-obj := build
-
 srctree := $(src)
 srck := $(src)/../../util/kconfig
+coreinfo_obj := $(src)/build
 objk := $(src)/build/util/kconfig
 
-LIBPAYLOAD_DEFCONFIG ?= $(src)/../libpayload/configs/defconfig-tinycurses
-
-PAYLOAD_DEPS := $(obj)/config.h
-
-OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \
-	  nvram_module.o bootlog_module.o ramdump_module.o \
-	  multiboot_module.o cbfs_module.o timestamps_module.o coreinfo.o
-OBJS    = $(patsubst %,$(obj)/%,$(OBJECTS))
-TARGET  = $(obj)/coreinfo.elf
-
-ARCH := x86_32
-
-all: real-all
-
-include ../libpayload/Makefile.payload
-
 ifeq ($(filter %clean,$(MAKECMDGOALS)),)
-export KERNELVERSION		:= 0.1.0
-export KCONFIG_AUTOHEADER	:= $(obj)/config.h
-export KCONFIG_AUTOCONFIG	:= $(obj)/auto.conf
-export KCONFIG_DEPENDENCIES	:= $(obj)/auto.conf.cmd
-export KCONFIG_SPLITCONFIG	:= $(obj)/config
-export KCONFIG_TRISTATE		:= $(obj)/tristate.conf
-export KCONFIG_CONFIG		:= $(CURDIR)/.config
-export KCONFIG_NEGATIVES	:= 1
-export Kconfig			:= Kconfig
+export KERNELVERSION      := 0.1.0
+export KCONFIG_AUTOHEADER := $(coreinfo_obj)/config.h
+export KCONFIG_AUTOCONFIG := $(coreinfo_obj)/auto.conf
+export KCONFIG_DEPENDENCIES := $(coreinfo_obj)/auto.conf.cmd
+export KCONFIG_SPLITCONFIG := $(coreinfo_obj)/config
+export KCONFIG_TRISTATE := $(coreinfo_obj)/tristate.conf
+export KCONFIG_CONFIG := $(CURDIR)/.config
+export KCONFIG_NEGATIVES := 1
+export Kconfig := Kconfig
+
+export V := $(V)
 
 CONFIG_SHELL := sh
 KBUILD_DEFCONFIG := configs/defconfig
@@ -42,12 +25,52 @@ UNAME_RELEASE := $(shell uname -r)
 HAVE_DOTCONFIG := $(wildcard .config)
 MAKEFLAGS += -rR --no-print-directory
 
+# Make is silent per default, but 'make V=1' will show all compiler calls.
+ifneq ($(V),1)
+.SILENT:
+endif
+
 HOSTCC ?= gcc
 HOSTCXX ?= g++
 HOSTCFLAGS := -I$(srck) -I$(objk)
 HOSTCXXFLAGS := -I$(srck) -I$(objk)
 
-CFLAGS += -I$(obj) -I../../src/commonlib/include
+LIBPAYLOAD_PATH := $(realpath ../libpayload)
+LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload
+HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a)
+LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses
+OBJCOPY ?= objcopy
+
+INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_OBJ)/include/kconfig.h -I$(src)/../../src/commonlib/include
+OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \
+	  nvram_module.o bootlog_module.o ramdump_module.o \
+	  multiboot_module.o cbfs_module.o timestamps_module.o coreinfo.o
+OBJS    = $(patsubst %,$(coreinfo_obj)/%,$(OBJECTS))
+TARGET  = $(coreinfo_obj)/coreinfo.elf
+
+all: real-all
+
+# in addition to the dependency below, create the file if it doesn't exist
+# to silence warnings about a file that would be generated anyway.
+$(if $(wildcard .xcompile),,$(eval $(shell ../../util/xcompile/xcompile $(XGCCPATH) > .xcompile || rm -f .xcompile)))
+.xcompile: ../../util/xcompile/xcompile
+	$< $(XGCCPATH) > $@.tmp
+	\mv -f $@.tmp $@ 2> /dev/null || rm -f $@.tmp $@
+
+CONFIG_COMPILER_GCC := y
+ARCH-y     := x86_32
+
+include .xcompile
+
+CC := $(CC_$(ARCH-y))
+AS := $(AS_$(ARCH-y))
+OBJCOPY := $(OBJCOPY_$(ARCH-y))
+
+LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc
+LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas
+
+CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror
+CFLAGS += -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES)
 
 ifneq ($(strip $(HAVE_DOTCONFIG)),)
 include $(src)/.config
@@ -57,6 +80,21 @@ ifeq ($(CONFIG_LTO),y)
 CFLAGS += -flto
 endif
 
+$(TARGET): $(src)/.config $(coreinfo_obj)/config.h $(OBJS) libpayload
+	printf "    LPCC       $(subst $(CURDIR)/,,$(@)) (LINK)\n"
+	$(LPCC) $(CFLAGS) -o $@ $(OBJS)
+	$(OBJCOPY) --only-keep-debug $@ $(TARGET).debug
+	$(OBJCOPY) --strip-debug $@
+	$(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@
+
+$(coreinfo_obj)/%.S.o: $(src)/%.S libpayload
+	printf "    LPAS       $(subst $(CURDIR)/,,$(@))\n"
+	$(LPAS) -o $@ $<
+
+$(coreinfo_obj)/%.o: $(src)/%.c libpayload
+	printf "    LPCC       $(subst $(CURDIR)/,,$(@))\n"
+	$(LPCC) $(CFLAGS) -c -o $@ $<
+
 else
 real-all: config
 endif
@@ -65,19 +103,34 @@ defaultbuild:
 	$(MAKE) olddefconfig
 	$(MAKE) all
 
-$(obj)/config.h:
+ifneq ($(strip $(HAVE_LIBPAYLOAD)),)
+libpayload:
+	printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n"
+else
+LPOPTS=obj="$(CURDIR)/lpbuild" DOTCONFIG="$(CURDIR)/lp.config"
+libpayload:
+	printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n"
+	$(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) distclean coreinfo_obj=$(coreinfo_obj)/libptmp
+	$(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG)
+	$(MAKE) -C $(LIBPAYLOAD_PATH) $(LPOPTS) install DESTDIR=$(coreinfo_obj)
+endif
+
+$(coreinfo_obj)/config.h:
 	$(MAKE) oldconfig
 
-$(shell mkdir -p $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))
+$(shell mkdir -p $(coreinfo_obj) $(objk)/lxdialog $(KCONFIG_SPLITCONFIG))
 
 include $(srck)/Makefile
 
-.PHONY: $(PHONY) prepare all real-all defaultbuild
+.PHONY: $(PHONY) prepare
 
 else
 
-distclean: clean
-	rm -f .config*
+clean:
+	rm -rf build lpbuild .xcompile
 
-.PHONY: distclean
+distclean: clean
+	rm -f .config* lp.config*
+
+.PHONY: clean distclean
 endif

payloads/coreinfo/README

@@ -22,5 +22,5 @@ Then you can build coreinfo now:
  $ cd coreinfo
 
  $ make menuconfig
-
+ 
  $ make

payloads/external/FILO/Makefile

@@ -44,7 +44,7 @@ libpayload: checkout
 		$(MAKE) && $(MAKE) DESTDIR=../external/FILO/filo/build install
 
 clean:
-	test -d filo && $(MAKE) -C filo clean LIBCONFIG_PATH=../../../libpayload || exit 0
+	test -d filo && $(MAKE) -C filo clean || exit 0
 
 distclean:
 	rm -rf filo

payloads/external/LinuxBoot/Kconfig

@@ -253,10 +253,10 @@ config LINUXBOOT_UROOT_SHELL
 
 config LINUXBOOT_UROOT_COMMANDS
 	string "U-root commands"
-	default "boot coreboot-app"
+	default "coreboot-app"
 	help
 	  List of additional modules to include,
-	  separated by space. (default "boot coreboot-app")
+	  separated by space. (default "coreboot-app")
 
 endif #LINUXBOOT_UROOT
 

payloads/external/LinuxBoot/targets/linux.mk

@@ -18,11 +18,7 @@ decompress_flag=.done
 
 OBJCOPY:=$(LINUXBOOT_CROSS_COMPILE)objcopy
 KERNEL_MAKE_FLAGS = \
-	ARCH=$(ARCH-y) \
-	KBUILD_BUILD_USER="coreboot" \
-	KBUILD_BUILD_HOST="reproducible" \
-	KBUILD_BUILD_TIMESTAMP="$(shell perl -e 'print scalar gmtime($(SOURCE_DATE_EPOCH))')" \
-	KBUILD_BUILD_VERSION="0"
+	ARCH=$(ARCH-y)
 
 ifeq ($(CONFIG_LINUXBOOT_KERNEL_CUSTOM),y)
 	kernel_version:=$(CONFIG_LINUXBOOT_KERNEL_CUSTOM_VERSION)

payloads/external/Makefile.inc

@@ -101,7 +101,7 @@ endif
 
 ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),)
 ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0)
-$(call add_intermediate, seabios_ps2_timeout, $(CBFSTOOL))
+$(call add_intermediate, seabios_ps2_timeout, $(obj)/coreboot.pre $(CBFSTOOL))
 	@printf "    SeaBIOS    Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n"
 	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/ps2-keyboard-spinup 2>/dev/null)
 	$(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup
@@ -109,14 +109,14 @@ endif
 endif
 
 ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y)
-$(call add_intermediate, seabios_sercon, $(CBFSTOOL))
+$(call add_intermediate, seabios_sercon, $(obj)/coreboot.pre $(CBFSTOOL))
 	@printf "    SeaBIOS    Add sercon-port file\n"
 	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/sercon-port 2>/dev/null)
 	$(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port
 endif
 
 ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y)
-$(call add_intermediate, seabios_thread_optionroms, $(CBFSTOOL))
+$(call add_intermediate, seabios_thread_optionroms, $(obj)/coreboot.pre $(CBFSTOOL))
 	@printf "    SeaBIOS    Thread optionroms\n"
 	$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/threads 2>/dev/null)
 	$(CBFSTOOL) $< add-int -i 2 -n etc/threads

payloads/external/U-Boot/Kconfig

@@ -1,6 +1,6 @@
 if PAYLOAD_UBOOT
 
-config PAYLOAD_SPECIFIC_OPTIONS
+config PAYLOAD_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select PAYLOAD_IS_FLAT_BINARY
 

payloads/external/depthcharge/Makefile

@@ -8,12 +8,11 @@ project_config_file=$(project_dir)/.config
 output_dir=$(project_dir)/build
 libpayload_dir=$(abspath $(CURDIR)/../../libpayload)
 libpayload_install_dir=$(output_dir)/lp_$(BOARD)
-coreboot_build_dir=$(abspath $(CURDIR)/../../../build)
 
 VBOOT_SOURCE ?= $(abspath $(CURDIR)/../../../3rdparty/vboot)
 EC_HEADERS ?= $(abspath $(CURDIR)/../../../3rdparty/chromeec/include)
 
-TAG-$(DEPTHCHARGE_MASTER)=origin/main
+TAG-$(DEPTHCHARGE_MASTER)=origin/master
 TAG-$(DEPTHCHARGE_STABLE)=$(STABLE_COMMIT_ID)
 TAG-$(DEPTHCHARGE_REVISION)=$(DEPTHCHARGE_REVISION_ID)
 
@@ -45,17 +44,17 @@ fetch: $(project_dir)
 	@cd $(project_dir); \
 		git show $(TAG-y) >/dev/null 2>&1; \
 		if [ $$? -ne 0 ] || \
-		[ "$(TAG-y)" = "origin/main" ]; then \
+		[ "$(TAG-y)" = "origin/master" ]; then \
 		echo "    Fetching new commits from the $(project_name) git repo"; \
 		git fetch; fi
 
 # Check out the requested version of the tree
-# Don't write a file for main branch so the latest remote version is always used
+# Don't write a file for master branch so the latest remote version is always used
 $(project_dir)/.version_$(TAG-y): fetch
 	echo "    Checking out $(project_name) revision $(TAG-y)"
 	rm -f $(project_dir)/.version_*
 	cd $(project_dir); \
-		git checkout main; \
+		git checkout master; \
 		git branch -D coreboot 2>/dev/null; \
 		git checkout -b coreboot $(TAG-y)
 ifneq ($(DEPTHCHARGE_MASTER),y)
@@ -85,7 +84,6 @@ config: $(project_dir)/.version_$(TAG-y) $(libpayload_install_dir)
 
 build: config
 	echo "    MAKE       $(project_name) $(TAG-y)"
-	cp $(coreboot_build_dir)/static_fw_config.h depthcharge/src/base/
 	$(MAKE) -C $(project_dir) depthcharge BOARD=$(BOARD) \
 		LIBPAYLOAD_DIR=$(libpayload_install_dir)/libpayload \
 		VB_SOURCE=$(VBOOT_SOURCE) \

payloads/external/tianocore/Makefile

@@ -39,14 +39,10 @@ endif
 
 TIMEOUT=-D PLATFORM_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT)
 
-ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
 ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y)
-ARCH=-a IA32 -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc
+ARCH=-a IA32 -p $(bootloader)/$(bootloader)Ia32.dsc
 else
-ARCH=-a IA32 -a X64 -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc
-endif
-else
-ARCH=-a IA32 -a X64 -p UefiPayloadPkg/UefiPayloadPkg.dsc
+ARCH=-a IA32 -a X64 -p $(bootloader)/$(bootloader)Ia32X64.dsc
 endif
 
 BUILD_STR=-q $(ARCH) -t COREBOOT -b $(BUILD_TYPE) $(TIMER) $(TIMEOUT) $(build_flavor)

payloads/external/tint/Makefile

@@ -1,25 +1,5 @@
-#
-# TINT build system - helps to securely download TINT with a checksum verification and build it.
-#
-
-#
-# Properties of the current TINT version
-#
-
-TINT_VERSION=0.05
-TINT_EXT_VERSION=0.05
-TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.tar.xz"
-TINT_ARCHIVE="tint_${TINT_VERSION}.tar.xz"
-TINT_DIR="tint-${TINT_VERSION}"
-TINT_SHA1SUM="859008216930a4584e622d0df41fd75c44d2b47f"
-
-#
-# Locations of the input/output scripts
-#
-
-buildgcc="./../../../util/crossgcc/buildgcc"
-corescript="./core.sh"
-tintified="./tint.sh"
+project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.04+nmu1.tar.gz
+archive_name=tint_0.04+nmu1.tar.gz
 
 unexport KCONFIG_AUTOHEADER
 unexport KCONFIG_AUTOCONFIG
@@ -30,39 +10,28 @@ unexport KCONFIG_NEGATIVES
 
 all: tint
 
-################################################################################
-#
-# Three stages of TINT build system:
-#
-# 1) generate_core.sh extracts the core part from buildgcc script,
-#     most importantly the checksum calculation/verification functions.
-#
-# 2) tintify_core.sh adds the TINT-specific footer/header to the core,
-#     such as the properties of current version including its checksum.
-#
-# 3) tint.sh - generated and "tintified" core script - builds a TINT.
-#
-################################################################################
+tint: patch
+	echo "    MAKE       TINT     "
+	$(MAKE) -C tint
 
-tint:
-	if [ ! -f ${tintified} ]; then \
-		chmod +x "./generate_core.sh" ; \
-		"./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \
-		chmod +x "./tintify_core.sh" ; \
-		"./tintify_core.sh" ${corescript} ${tintified} \
-			${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_SHA1SUM} ; \
-	fi ; \
-	chmod +x ${tintified}
-	${tintified}
+patch: download
+	cd tint; \
+	if [ -e debian ]; then \
+		rm -rf debian typedefs.h Makefile; \
+		touch Makefile; \
+		patch -l -p1 < ../libpayload_tint.patch; \
+	fi
+
+download:
+	test -d tint || { wget $(project_url); \
+		tar -xvf $(archive_name); \
+		rm $(archive_name); \
+		mv tint-0.04+nmu1 tint; }
 
 clean:
-	test -d "./tint/" && $(MAKE) -C "./tint/" clean || exit 0
+	test -d tint && $(MAKE) -C tint clean || exit 0
 
 distclean:
-	rm -rf "./tint/"
-	rm -f ${corescript}
-	rm -f ${tintified}
+	rm -rf tint
 
-.PHONY: tint clean distclean
-
-#
+.PHONY: download patch tint clean distclean

payloads/external/tint/generate_core.sh

@@ -1,102 +0,0 @@
-#!/bin/sh
-#
-# generate_core.sh extracts the core part from buildgcc script,
-# most importantly the checksum calculation/verification functions.
-#
-# Copyright (C) 2019 Mike Banon <mikebdp2@gmail.com>
-#
-##############################################################################
-#
-# USAGE:
-# 	./generate_core.sh <buildgcc> <corescript> prepare_before_patch
-# where
-# 	buildgcc   - path to input buildgcc script
-# 	corescript - path to output core part script
-# 	prepare_before_patch - optional argument to insert prepare_${package}
-# 				call into the unpack_and_patch function, e.g.
-# 				for removing some files with rm command
-# 				in order to reduce the size of patch file
-#
-##############################################################################
-
-buildgcc="$1"
-corescript="$2"
-prepare_before_patch="$3"
-
-#
-# Imports the source file fragment between start and end into the
-# destination file, optionally excluding the last line if not needed
-#
-
-import_from_file() {
-        source="$1"
-        destination="$2"
-	start="$3"
-	end="$4"
-	last_line_disabled="$5"
-	if [ -z "${last_line_disabled}" ] ; then
-		sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" "$source" >> "$destination"
-	else
-		sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" "$source" >> "$destination"
-	fi
-}
-
-#
-# Import the color defines together with UNAME/HALT_FOR_TOOLS variables
-#
-
-import_from_file "$buildgcc" "$corescript" "red=" "HALT_FOR_TOOLS=0" || exit "$?"
-
-#
-# Import the core functions
-#
-
-FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch"
-
-for F in $FUNCTIONS ; do
-	import_from_file "$buildgcc" "$corescript" "$F()" "}" || exit "$?"
-done
-
-#
-# Import a fragment where we find tar/patch/make and other essential tools
-#
-
-import_from_file "$buildgcc" "$corescript" "# Find all the required tools" "# Allow" "last_line_disabled" || exit "$?"
-
-#
-# Import a fragment with conditional exit if some required tools were not found
-#
-
-import_from_file "$buildgcc" "$corescript" "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?"
-
-#
-# Avoid the unnecessary subdirectories holding a single file each
-#
-
-sed -i -e "s/patches\///g" "$corescript"
-sed -i -e "s/sum\///g" "$corescript"
-sed -i -e "s/tarballs\///g" "$corescript"
-sed -i -e "s/cd tarballs || exit 1//g" "$corescript"
-sed -i -e "s/cd \.\.//g" "$corescript"
-
-#
-# Get the known checksum without using a dedicated single-line file
-#
-
-sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" "$corescript"
-
-#
-# Update the paths printed at the error messages
-#
-
-sed -i -e "s/util\/crossgcc\///g" "$corescript"
-
-#
-# Insert prepare_${package} function call between the unpack and patch operations
-#
-
-if [ ! -z "${prepare_before_patch}" ] ; then
-	sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript"
-fi
-
-#

payloads/external/tint/libpayload_tint.patch

@@ -1,6 +1,6 @@
-diff -rupN tint-0.05/config.h tint/config.h
---- tint-0.05/config.h	2001-12-08 00:03:24.000000000 +0100
-+++ tint/config.h	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/config.h tint/config.h
+--- tint-0.04+nmu1/config.h	2001-12-08 00:03:24.000000000 +0100
++++ tint/config.h	2018-02-23 12:00:00.000000000 +0200
 @@ -29,7 +29,15 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
@@ -17,9 +17,9 @@ diff -rupN tint-0.05/config.h tint/config.h
 +#endif
  
  #endif	/* #ifndef CONFIG_H */
-diff -rupN tint-0.05/engine.c tint/engine.c
---- tint-0.05/engine.c	2005-07-17 13:26:22.000000000 +0200
-+++ tint/engine.c	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/engine.c tint/engine.c
+--- tint-0.04+nmu1/engine.c	2005-07-17 13:26:22.000000000 +0200
++++ tint/engine.c	2018-02-23 12:00:00.000000000 +0200
 @@ -27,10 +27,13 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
@@ -35,21 +35,21 @@ diff -rupN tint-0.05/engine.c tint/engine.c
  #include "utils.h"
  #include "io.h"
  #include "engine.h"
-diff -rupN tint-0.05/engine.h tint/engine.h
---- tint-0.05/engine.h	2001-12-07 16:48:08.000000000 +0100
-+++ tint/engine.h	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/engine.h tint/engine.h
+--- tint-0.04+nmu1/engine.h	2001-12-07 16:48:08.000000000 +0100
++++ tint/engine.h	2018-02-23 12:00:00.000000000 +0200
 @@ -29,7 +29,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
- 
+
 -#include "typedefs.h"		/* bool */
 +#include "curses.h"		/* bool */
- 
+
  /*
   * Macros
-diff -rupN tint-0.05/io.c tint/io.c
---- tint-0.05/io.c	2010-06-23 15:05:12.000000000 +0100
-+++ tint/io.c	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/io.c tint/io.c
+--- tint-0.04+nmu1/io.c	2010-06-23 15:05:12.000000000 +0100
++++ tint/io.c	2018-02-23 12:00:00.000000000 +0200
 @@ -27,9 +27,13 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
@@ -102,21 +102,25 @@ diff -rupN tint-0.05/io.c tint/io.c
     return ch;
  }
  
-diff -rupN tint-0.05/io.h tint/io.h
---- tint-0.05/io.h	2010-06-23 14:55:03.000000000 +0100
-+++ tint/io.h	2021-02-09 08:00:00.000000000 +0200
-@@ -30,7 +30,6 @@
+diff -rupN tint-0.04+nmu1/io.h tint/io.h
+--- tint-0.04+nmu1/io.h	2010-06-23 14:55:03.000000000 +0100
++++ tint/io.h	2018-02-23 12:00:00.000000000 +0200
+@@ -29,9 +29,8 @@
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
- 
+-
++
  #include <curses.h>
 -#include <wchar.h>
- 
+-
++
  /*
   * Colors
-diff -rupN tint-0.05/Makefile tint/Makefile
---- tint-0.05/Makefile	2010-06-23 15:06:11.000000000 +0200
-+++ tint/Makefile	2021-02-09 08:00:00.000000000 +0200
-@@ -0,0 +1,106 @@
+  */
+diff -rupN tint-0.04+nmu1/Makefile tint/Makefile
+--- tint-0.04+nmu1/Makefile	2010-06-23 15:06:11.000000000 +0200
++++ tint/Makefile	2018-02-23 12:00:00.000000000 +0200
+@@ -1,0 +1,106 @@
 +
 +# -*- sh -*-
 +
@@ -223,9 +227,9 @@ diff -rupN tint-0.05/Makefile tint/Makefile
 +
 +
 +.PHONY: all clean do-it-all depend with-depends without-depends debian postinst
-diff -rupN tint-0.05/tint.c tint/tint.c
---- tint-0.05/tint.c	2010-08-08 19:42:50.000000000 +0200
-+++ tint/tint.c	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/tint.c tint/tint.c
+--- tint-0.04+nmu1/tint.c	2010-08-08 19:42:50.000000000 +0200
++++ tint/tint.c	2018-02-23 12:00:00.000000000 +0200
 @@ -1,4 +1,3 @@
 -
  /*
@@ -249,15 +253,13 @@ diff -rupN tint-0.05/tint.c tint/tint.c
  #include "utils.h"
  #include "io.h"
  #include "config.h"
-@@ -304,7 +304,7 @@ static void showstatus (engine_t *engine
-           /***************************************************************************/
- 
+@@ -306,4 +306,4 @@
  /* Header for scorefile */
 -#define SCORE_HEADER	"Tint 0.02b (c) Abraham vd Merwe - Scores"
-+#define SCORE_HEADER	"Tint 0.05 (c) Abraham vd Merwe - Scores"
- 
++#define SCORE_HEADER	"Tint 0.04+nmu1 (c) Abraham vd Merwe - Scores"
+-
++
  /* Header for score title */
- static const char scoretitle[] = "\n\t   TINT HIGH SCORES\n\n\tRank   Score        Name\n\n";
 @@ -322,6 +322,7 @@ typedef struct
     time_t timestamp;
  } score_t;
@@ -374,7 +376,7 @@ diff -rupN tint-0.05/tint.c tint/tint.c
     rand_init ();							/* must be called before engine_init () */
     engine_init (&engine,score_function);	/* must be called before using engine.curshape */
     finished = shownext = FALSE;
-@@ -632,12 +651,14 @@ int main (int argc,char *argv[])
+@@ -632,13 +651,15 @@ int main (int argc,char *argv[])
  				  /* pause */
  				case 'p':
  				  out_setcolor (COLOR_WHITE,COLOR_BLACK);
@@ -391,8 +393,8 @@ diff -rupN tint-0.05/tint.c tint/tint.c
  				  break;
  				  /* unknown keypress */
  				default:
-@@ -672,12 +693,32 @@ int main (int argc,char *argv[])
-    while (!finished);
+ 				  out_beep ();
+@@ -673,11 +694,31 @@ int main (int argc,char *argv[])
     /* Restore console settings and exit */
     io_close ();
 +#if 0
@@ -424,9 +426,9 @@ diff -rupN tint-0.05/tint.c tint/tint.c
 +#endif
  }
  
-diff -rupN tint-0.05/utils.c tint/utils.c
---- tint-0.05/utils.c	2001-12-07 16:49:19.000000000 +0100
-+++ tint/utils.c	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/utils.c tint/utils.c
+--- tint-0.04+nmu1/utils.c	2001-12-07 16:49:19.000000000 +0100
++++ tint/utils.c	2018-02-23 12:00:00.000000000 +0200
 @@ -27,11 +27,13 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
@@ -456,15 +458,15 @@ diff -rupN tint-0.05/utils.c tint/utils.c
  }
  
 +#endif
-diff -rupN tint-0.05/utils.h tint/utils.h
---- tint-0.05/utils.h	2001-12-07 16:49:35.000000000 +0100
-+++ tint/utils.h	2021-02-09 08:00:00.000000000 +0200
+diff -rupN tint-0.04+nmu1/utils.h tint/utils.h
+--- tint-0.04+nmu1/utils.h	2001-12-07 16:49:35.000000000 +0100
++++ tint/utils.h	2018-02-23 12:00:00.000000000 +0200
 @@ -29,7 +29,7 @@
   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   */
- 
+
 -#include "typedefs.h"
 +#include <curses.h>
- 
+
  /*
   * Initialize random number generator

payloads/external/tint/tintify_core.sh

@@ -1,98 +0,0 @@
-#!/bin/sh
-#
-# tintify_core.sh adds the TINT-specific footer/header to the core,
-# such as the properties of current TINT version including its checksum.
-#
-# Copyright (C) 2019 Mike Banon <mikebdp2@gmail.com>
-#
-################################################################################
-#
-# USAGE:
-#      	./tintify_core.sh <corescript> <tintified> \
-# 			<TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_SHA1SUM>
-# where
-#       corescript - path to input core script
-#       tintified  - path to output tint script
-#
-################################################################################
-
-corescript="$1"
-tintified="$2"
-
-#
-# TINT-specific header
-#
-
-#
-# Insert the properties of the current TINT version
-#
-
-echo "#!/bin/sh" > "$tintified"
-echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified"
-echo "TINT_ARCHIVE=${4}" >> "$tintified"
-echo "TINT_DIR=${5}" >> "$tintified"
-echo "TINT_SHA1SUM=${6}" >> "$tintified"
-
-#
-# Add the replace_plus_with_minus() function - needed to fix the version number
-#
-
-echo "replace_plus_with_minus() {" >> "$tintified"
-echo "for x in *\"+\"*; do" >> "$tintified"
-echo "y=\$(printf %sa \"\$x\" | tr \"+\" \"-\")" >> "$tintified"
-echo "mv -- \"\$x\" \"\${y%a}\"" >> "$tintified"
-echo "done" >> "$tintified"
-echo "}" >> "$tintified"
-
-#
-# Add the prepare_TINT() function, it will remove the unneeded debian directory
-# as well as typedefs.h and old Makefile to significantly reduce the patch size
-#
-
-echo "prepare_TINT() {" >> "$tintified"
-# echo "replace_plus_with_minus" >> "$tintified"
-echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ] ; then" >> "$tintified"
-echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> "$tintified"
-echo "touch ./\${TINT_DIR}/Makefile;" >> "$tintified"
-echo "fi" >> "$tintified"
-echo "}" >> "$tintified"
-
-#
-# Importing the core script
-#
-
-cat "$corescript" >> "$tintified"
-
-#
-# download() function adjustments - became necessary after a version number fix
-#
-
-sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" "$tintified"
-sed -i -e "s/downloading from \$archive/&_link/g" "$tintified"
-sed -i -e "s/\(download_showing_percentage \"\$archive\)./\1_link\"/g" "$tintified"
-
-#
-# TINT-specific footer
-#
-
-echo "if [ ! -d tint ] ; then" >> "$tintified"
-
-echo "printf \"Downloading and verifying TINT tarball ... \\n\"" >> "$tintified"
-echo "download TINT || exit \"\$?\"" >> "$tintified"
-echo "verify_hash TINT \${TINT_SHA1SUM} || exit \"\$?\"" >> "$tintified"
-echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> "$tintified"
-
-echo "printf \"Unpacking and patching TINT... \\n\"" >> "$tintified"
-echo "unpack_and_patch TINT || exit 1" >> "$tintified"
-echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> "$tintified"
-
-echo "mv ./\${TINT_DIR} ./tint" >> "$tintified"
-echo "fi" >> "$tintified"
-
-echo "printf \"Building TINT ... \\n\"" >> "$tintified"
-echo "make -C ./tint" >> "$tintified"
-echo "printf \"TINT built ... \${green}ok\${NC}\\n\"" >> "$tintified"
-
-chmod +x "$tintified"
-
-#

payloads/libpayload/Kconfig

@@ -385,11 +385,6 @@ config PC_KEYBOARD_LAYOUT_DE
 	depends on PC_KEYBOARD
 	default n
 
-config PC_KEYBOARD_TRANSLATION
-	bool "Enable or Disable translation in PC keyboard set 2 on exit"
-	depends on PC_KEYBOARD
-	default y
-
 endmenu
 
 menu "Drivers"

payloads/libpayload/Makefile.payload

@@ -1,157 +0,0 @@
-# SPDX-License-Identifier: BSD-3-Clause
-
-#
-# This file is meant to be included by in-tree payloads
-# to provide default targets for incremental builds.
-#
-# Variables with file names and directory overrides have
-# to be defined in advance for proper dependency tracking.
-# Then, include this file. e.g
-#
-#     obj := output
-#     OBJS := $(obj)/payload.o
-#     TARGET := $(obj)/payload.elf
-#     include ../path/to/libpayload/Makefile.payload
-#
-
-# Find relative path to libpayload (where this Makefile resides).
-LIBPAYLOAD_SRC := $(dir $(lastword $(MAKEFILE_LIST)))
-LIBPAYLOAD_SRC := $(patsubst %/,%,$(LIBPAYLOAD_SRC))
-
-# Build dir and config for libpayload. Need absolute
-# paths to pass to libpayload's sub-make.
-LIBPAYLOAD_OBJ	?= $(CURDIR)/libpayload
-LIBPAYLOAD	:= $(LIBPAYLOAD_OBJ)/libpayload.a
-LIBPAYLOAD_CONFIG_H := $(LIBPAYLOAD_OBJ)/libpayload-config.h
-LIBPAYLOAD_DOTCONFIG ?= $(CURDIR)/.lp.config
-LIBPAYLOAD_DEFCONFIG ?= $(CURDIR)/$(LIBPAYLOAD_SRC)/configs/defconfig
-
-# Some default dependencies for all targets:
-DEFAULT_DEPS := Makefile $(lastword $(MAKEFILE_LIST))
-DEFAULT_DEPS += $(PAYLOAD_DEPS)
-
-obj ?= build
-
-ARCH ?=
-OBJS ?=
-CCACHE ?=
-
-CFLAGS  = $(GCC_CFLAGS_$(ARCH))
-CFLAGS += -Os -ffreestanding
-CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror
-
-STRIP ?= debug
-
-$(TARGET):
-
-# Make is silent per default, but `make V=1` will show all calls.
-Q:=@
-ifneq ($(V),1)
-ifneq ($(Q),)
-.SILENT:
-MAKEFLAGS += -s
-endif
-endif
-export V
-
-ifeq ($(filter %clean,$(MAKECMDGOALS)),)
-
-xcompile	:= $(obj)/xcompile
-xcompile_script	:= $(LIBPAYLOAD_SRC)/../../util/xcompile/xcompile
-
-# In addition to the dependency below, create the file if it doesn't exist
-# to silence warnings about a file that would be generated anyway.
-$(if $(wildcard $(xcompile)),,$(shell	\
-	mkdir -p $(dir $(xcompile)) &&	\
-	$(xcompile_script) $(XGCCPATH) > $(xcompile) ||	rm -f $(xcompile)))
-
-$(xcompile): $(xcompile_script)
-	$< $(XGCCPATH) > $@
-
-include $(xcompile)
-
-ifneq ($(XCOMPILE_COMPLETE),1)
-$(shell rm -f $(XCOMPILE_COMPLETE))
-$(error $(xcompile) deleted because it's invalid. \
-        Restarting the build should fix that, or explain the problem.)
-endif
-
-# `lpgcc` in in-tree mode:
-LPGCC  = CC="$(CCACHE) $(GCC_CC_$(ARCH))"
-LPGCC += _OBJ="$(LIBPAYLOAD_OBJ)"
-LPGCC += $(LIBPAYLOAD_SRC)/bin/lpgcc
-
-LPAS  = AS="$(AS_$(ARCH))"
-LPAS += $(LIBPAYLOAD_SRC)/bin/lpas
-
-OBJCOPY = $(OBJCOPY_$(ARCH))
-
-$(obj)/%.bin: $(OBJS) $(LIBPAYLOAD) $(DEFAULT_DEPS)
-	@printf "    LPGCC      $(subst $(obj)/,,$@)\n"
-	$(LPGCC) $(CFLAGS) -o $@ $(OBJS)
-
-$(obj)/%.map: $(obj)/%.bin
-	@printf "    SYMS       $(subst $(obj)/,,$@)\n"
-	$(NM_$(ARCH)) -n $< > $@
-
-$(obj)/%.debug: $(obj)/%.bin
-	@printf "    DEBUG      $(subst $(obj)/,,$@)\n"
-	$(OBJCOPY) --only-keep-debug $< $@
-
-.PRECIOUS: $(obj)/%.debug
-
-$(obj)/%.elf: $(obj)/%.bin $(obj)/%.debug
-	@printf "    STRIP      $(subst $(obj)/,,$@)\n"
-	$(OBJCOPY) --strip-$(STRIP) $< $@
-	$(OBJCOPY) --add-gnu-debuglink=$(obj)/$*.debug $@
-
-$(obj)/%.o: %.c $(LIBPAYLOAD_CONFIG_H) $(DEFAULT_DEPS)
-	@printf "    LPGCC      $(subst $(obj)/,,$@)\n"
-	$(LPGCC) -MMD $(CFLAGS) -c $< -o $@
-
-$(obj)/%.S.o: %.S $(LIBPAYLOAD_CONFIG_H) $(DEFAULT_DEPS)
-	@printf "    LPAS       $(subst $(obj)/,,$@)\n"
-	$(LPAS) $< -o $@
-
--include $(OBJS:.o=.d)
-
-.PRECIOUS: $(OBJS)
-
-LIBPAYLOAD_OPTS := obj="$(LIBPAYLOAD_OBJ)"
-LIBPAYLOAD_OPTS += DOTCONFIG="$(LIBPAYLOAD_DOTCONFIG)"
-LIBPAYLOAD_OPTS += $(if $(CCACHE),CONFIG_LP_CCACHE=y)
-
-defconfig: lp-defconfig
-lp-defconfig: $(LIBPAYLOAD_DOTCONFIG)
-$(LIBPAYLOAD_DOTCONFIG): $(LIBPAYLOAD_DEFCONFIG) | $(PAYLOAD_DEPS)
-	$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) \
-		KBUILD_DEFCONFIG=$(LIBPAYLOAD_DEFCONFIG) defconfig
-
-$(LIBPAYLOAD_CONFIG_H): $(LIBPAYLOAD_DOTCONFIG)
-	$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) $(LIBPAYLOAD_CONFIG_H)
-
-oldconfig: lp-oldconfig
-lp-oldconfig:
-	[ ! -f $(LIBPAYLOAD_DOTCONFIG) ] || \
-	$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS) oldconfig
-
-$(LIBPAYLOAD): lp-defconfig | $(LIBPAYLOAD_CONFIG_H)
-	$(MAKE) -C $(LIBPAYLOAD_SRC) $(LIBPAYLOAD_OPTS)
-
-$(shell mkdir -p $(sort $(dir $(OBJS))))
-
-.PHONY: oldconfig lp-oldconfig defconfig lp-defconfig
-
-else # %clean,$(MAKECMDGOALS)
-
-default-payload-clean:
-	rm -rf $(obj) $(LIBPAYLOAD_OBJ)
-clean: default-payload-clean
-
-default-payload-distclean: clean
-	rm -f $(LIBPAYLOAD_DOTCONFIG) $(LIBPAYLOAD_DOTCONFIG).old
-distclean: default-payload-distclean
-
-.PHONY: default-payload-clean clean default-payload-distclean distclean
-
-endif

payloads/libpayload/arch/arm/Kconfig

@@ -28,7 +28,7 @@
 
 if ARCH_ARM
 
-config ARCH_SPECIFIC_OPTIONS
+config ARCH_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select LITTLE_ENDIAN
 

payloads/libpayload/arch/arm64/Kconfig

@@ -28,7 +28,7 @@
 
 if ARCH_ARM64
 
-config ARCH_SPECIFIC_OPTIONS
+config ARCH_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select LITTLE_ENDIAN
 

payloads/libpayload/arch/arm64/mmu.c

@@ -389,7 +389,7 @@ struct mmu_new_range_prop {
 
 /*
  * Func: mmu_is_range_free
- * Desc: We need to ensure that the new range being allocated doesn't overlap
+ * Desc: We need to ensure that the new range being allocated doesnt overlap
  * with any used memory range. Basically:
  * 1. Memory ranges used by the payload (usedmem_ranges)
  * 2. Any area that falls below _end symbol in linker script (Kernel needs to be

payloads/libpayload/arch/x86/Kconfig

@@ -28,7 +28,7 @@
 
 if ARCH_X86
 
-config ARCH_SPECIFIC_OPTIONS
+config ARCH_SPECIFIC_OPTIONS # dummy
 	def_bool y
 	select LITTLE_ENDIAN
 	select IO_ADDRESS_SPACE

payloads/libpayload/configs/config.herobrine

@@ -1,4 +0,0 @@
-CONFIG_LP_CHROMEOS=y
-CONFIG_LP_ARCH_ARM64=y
-CONFIG_LP_TIMER_ARM64_ARCH=y
-CONFIG_LP_SERIAL_CONSOLE=y

payloads/libpayload/drivers/Makefile.inc

@@ -77,7 +77,6 @@ libc-y += video/graphics.c
 libc-$(CONFIG_LP_STORAGE) += storage/storage.c
 libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci.c
 libc-$(CONFIG_LP_STORAGE_AHCI) += storage/ahci_common.c
-libc-$(CONFIG_LP_STORAGE_NVME) += storage/nvme.c
 ifeq ($(CONFIG_LP_STORAGE_ATA),y)
 libc-$(CONFIG_LP_STORAGE_ATA) += storage/ata.c
 libc-$(CONFIG_LP_STORAGE_ATA) += storage/ahci_ata.c

payloads/libpayload/drivers/i8042/i8042.h

@@ -55,7 +55,6 @@
 #define   I8042_MODE_NUM_LOCK_OFF	(0 << 1)
 #define   I8042_MODE_SCROLL_LOCK_ON	(1 << 0)
 #define   I8042_MODE_SCROLL_LOCK_OFF	(0 << 0)
-#define I8042_KBCMD_ECHO		0xee
 #define I8042_KBCMD_SET_SCANCODE	0xf0
 #define I8042_KBCMD_SET_TYPEMATIC	0xf3
 #define I8042_KBCMD_EN			0xf4

payloads/libpayload/drivers/i8042/keyboard.c

@@ -237,17 +237,9 @@ static bool set_scancode_set(const unsigned char set)
 	return ret;
 }
 
-static bool keyboard_peek_echo_result(void)
-{
-	const uint8_t ch = i8042_peek_data_ps2();
-	return ch == 0xee || ch == 0xfe;
-}
-
 static enum keyboard_state {
 	STATE_INIT = 0,
 	STATE_SIMPLIFIED_INIT,
-	STATE_HOTPLUG,
-	STATE_HOTPLUG_ECHO,
 	STATE_DISABLE_SCAN,
 	STATE_DRAIN_INPUT,
 	STATE_DISABLE_TRANSLATION,
@@ -258,16 +250,13 @@ static enum keyboard_state {
 	STATE_ENABLE_TRANSLATION,
 	STATE_ENABLE_SCAN,
 	STATE_RUNNING,
-	STATE_RUNNING_ECHO,
-	STATE_DETENTION,
+	STATE_IGNORE,
 } keyboard_state;
 
 #define STATE_NAMES_ENTRY(name) [STATE_##name] = #name
 static const char *const state_names[] = {
 	STATE_NAMES_ENTRY(INIT),
 	STATE_NAMES_ENTRY(SIMPLIFIED_INIT),
-	STATE_NAMES_ENTRY(HOTPLUG),
-	STATE_NAMES_ENTRY(HOTPLUG_ECHO),
 	STATE_NAMES_ENTRY(DISABLE_SCAN),
 	STATE_NAMES_ENTRY(DRAIN_INPUT),
 	STATE_NAMES_ENTRY(DISABLE_TRANSLATION),
@@ -278,8 +267,7 @@ static const char *const state_names[] = {
 	STATE_NAMES_ENTRY(ENABLE_TRANSLATION),
 	STATE_NAMES_ENTRY(ENABLE_SCAN),
 	STATE_NAMES_ENTRY(RUNNING),
-	STATE_NAMES_ENTRY(RUNNING_ECHO),
-	STATE_NAMES_ENTRY(DETENTION),
+	STATE_NAMES_ENTRY(IGNORE),
 };
 
 __attribute__((unused))
@@ -313,28 +301,6 @@ static void keyboard_poll(void)
 		next_state = STATE_CONFIGURE;
 		break;
 
-	case STATE_HOTPLUG:
-		if (timer_us(state_time) > 1*1000*1000) {
-			i8042_write_data(I8042_KBCMD_ECHO);
-			next_state = STATE_HOTPLUG_ECHO;
-		}
-		break;
-
-	case STATE_HOTPLUG_ECHO:
-		if (!i8042_data_ready_ps2()) {
-			if (timer_us(state_time) > 200*1000)
-				next_state = STATE_HOTPLUG;
-			break;
-		}
-
-		if (keyboard_peek_echo_result()) {
-			next_state = STATE_DISABLE_SCAN;
-			keyboard_time = timer_us(0);
-		}
-		(void)i8042_read_data_ps2();
-
-		break;
-
 	case STATE_DISABLE_SCAN:
 		(void)keyboard_cmd(I8042_KBCMD_DEFAULT_DIS);
 		next_state = STATE_DRAIN_INPUT;
@@ -428,51 +394,23 @@ static void keyboard_poll(void)
 		break;
 
 	case STATE_RUNNING:
-		if (!i8042_data_ready_ps2()) {
-			if (timer_us(state_time) > 500*1000) {
-				i8042_write_data(I8042_KBCMD_ECHO);
-				next_state = STATE_RUNNING_ECHO;
-			}
-		} else {
-			state_time = timer_us(0);
-		}
+		/* TODO: Use echo command to detect detach. */
 		break;
 
-	case STATE_RUNNING_ECHO:
-		if (!i8042_data_ready_ps2()) {
-			if (timer_us(state_time) > 200*1000) {
-				debug("INFO: Keyboard echo timed out.\n");
-				next_state = STATE_HOTPLUG;
-			}
-			break;
-		}
-
-		if (keyboard_peek_echo_result()) {
-			(void)i8042_read_data_ps2();
-			next_state = STATE_RUNNING;
-		}
-
-		state_time = timer_us(0);
-		break;
-
-	case STATE_DETENTION:
-		if (timer_us(state_time) > 5*1000*1000)
-			next_state = STATE_HOTPLUG;
+	case STATE_IGNORE:
+		/* TODO: Try again after timeout if it ever seems useful. */
 		break;
 
 	}
 
 	switch (next_state) {
 	case STATE_INIT:
-	case STATE_HOTPLUG:
-	case STATE_HOTPLUG_ECHO:
 	case STATE_RUNNING:
-	case STATE_RUNNING_ECHO:
-	case STATE_DETENTION:
+	case STATE_IGNORE:
 		break;
 	default:
 		if (timer_us(keyboard_time) > 30*1000*1000)
-			next_state = STATE_DETENTION;
+			next_state = STATE_IGNORE;
 		break;
 	}
 
@@ -486,9 +424,7 @@ static void keyboard_poll(void)
 bool keyboard_havechar(void)
 {
 	keyboard_poll();
-	return i8042_data_ready_ps2() &&
-	       (keyboard_state == STATE_RUNNING ||
-		(keyboard_state == STATE_RUNNING_ECHO && !keyboard_peek_echo_result()));
+	return keyboard_state == STATE_RUNNING && i8042_data_ready_ps2();
 }
 
 unsigned char keyboard_get_scancode(void)
@@ -655,11 +591,6 @@ void keyboard_disconnect(void)
 	keyboard_cmd(I8042_KBCMD_DEFAULT_DIS);
 	keyboard_drain_input();
 
-	/* Nobody but us seems to still use scancode set #1.
-	   So try to hand over with more modern settings. */
-	set_scancode_set(2);
-	i8042_set_kbd_translation(CONFIG(LP_PC_KEYBOARD_TRANSLATION));
-
 	/* Send keyboard disconnect command */
 	i8042_cmd(I8042_CMD_DIS_KB);
 

payloads/libpayload/drivers/storage/Kconfig

@@ -49,10 +49,3 @@ config STORAGE_AHCI_ONLY_TESTED
 	help
 	  If this option is selected, only AHCI controllers which are known
 	  to work will be used.
-
-config STORAGE_NVME
-	bool "Support for NVMe devices"
-	depends on STORAGE && PCI
-	default y
-	help
-	  Select this option if you want support for NVMe devices.

payloads/libpayload/drivers/storage/nvme.c

@@ -1,403 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/*
- * Libpayload NVMe device driver
- * Copyright (C) 2019 secunet Security Networks AG
- */
-
-#include <stdlib.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <pci.h>
-#include <pci/pci.h>
-#include <libpayload.h>
-#include <storage/storage.h>
-#include <storage/nvme.h>
-
-#define NVME_CC_EN	(1 <<  0)
-#define NVME_CC_CSS	(0 <<  4)
-#define NVME_CC_MPS	(0 <<  7)
-#define NVME_CC_AMS	(0 << 11)
-#define NVME_CC_SHN	(0 << 14)
-#define NVME_CC_IOSQES	(6 << 16)
-#define NVME_CC_IOCQES	(4 << 20)
-
-#define NVME_QUEUE_SIZE 2
-#define NVME_SQ_ENTRY_SIZE 64
-#define NVME_CQ_ENTRY_SIZE 16
-
-struct nvme_dev {
-	storage_dev_t storage_dev;
-
-	pcidev_t pci_dev;
-	void *config;
-	struct {
-		void *base;
-		uint32_t *bell;
-		uint16_t idx; // bool pos 0 or 1
-		uint16_t round; // bool round 0 or 1+0xd
-	} queue[4];
-
-	uint64_t *prp_list;
-};
-
-
-struct nvme_s_queue_entry {
-	uint32_t dw[16];
-};
-
-struct nvme_c_queue_entry {
-	uint32_t dw[4];
-};
-
-enum nvme_queue {
-	NVME_ADMIN_QUEUE = 0,
-	ads = 0,
-	adc = 1,
-	NVME_IO_QUEUE = 2,
-	ios = 2,
-	ioc = 3,
-};
-
-static storage_poll_t nvme_poll(struct storage_dev *dev)
-{
-	return POLL_MEDIUM_PRESENT;
-}
-
-static int nvme_cmd(
-		struct nvme_dev *nvme, enum nvme_queue q, const struct nvme_s_queue_entry *cmd)
-{
-	int sq = q, cq = q+1;
-
-	void *s_entry = nvme->queue[sq].base + (nvme->queue[sq].idx * NVME_SQ_ENTRY_SIZE);
-	memcpy(s_entry, cmd, NVME_SQ_ENTRY_SIZE);
-	nvme->queue[sq].idx = (nvme->queue[sq].idx + 1) & (NVME_QUEUE_SIZE - 1);
-	write32(nvme->queue[sq].bell, nvme->queue[sq].idx);
-
-	struct nvme_c_queue_entry *c_entry = nvme->queue[cq].base +
-		(nvme->queue[cq].idx * NVME_CQ_ENTRY_SIZE);
-	while (((read32(&c_entry->dw[3]) >> 16) & 0x1) == nvme->queue[cq].round)
-		;
-	nvme->queue[cq].idx = (nvme->queue[cq].idx + 1) & (NVME_QUEUE_SIZE - 1);
-	write32(nvme->queue[cq].bell, nvme->queue[cq].idx);
-	if (nvme->queue[cq].idx == 0)
-		nvme->queue[cq].round = (nvme->queue[cq].round + 1) & 1;
-	return c_entry->dw[3] >> 17;
-}
-
-static int delete_io_submission_queue(struct nvme_dev *nvme)
-{
-	const struct nvme_s_queue_entry e = {
-		.dw[0]  = 0,
-		.dw[10] = ios,
-	};
-
-	int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
-
-	free(nvme->queue[ios].base);
-	nvme->queue[ios].base = NULL;
-	nvme->queue[ios].bell = NULL;
-	nvme->queue[ios].idx  = 0;
-	return res;
-}
-
-static int delete_io_completion_queue(struct nvme_dev *nvme)
-{
-	const struct nvme_s_queue_entry e = {
-		.dw[0]  = 1,
-		.dw[10] = ioc,
-	};
-
-	int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
-	free(nvme->queue[ioc].base);
-
-	nvme->queue[ioc].base  = NULL;
-	nvme->queue[ioc].bell  = NULL;
-	nvme->queue[ioc].idx   = 0;
-	nvme->queue[ioc].round = 0;
-	return res;
-}
-
-static int delete_admin_queues(struct nvme_dev *nvme)
-{
-	if (nvme->queue[ios].base || nvme->queue[ioc].base)
-		printf("NVMe ERROR: IO queues still active.\n");
-
-	free(nvme->queue[ads].base);
-	nvme->queue[ads].base = NULL;
-	nvme->queue[ads].bell = NULL;
-	nvme->queue[ads].idx  = 0;
-
-	free(nvme->queue[adc].base);
-	nvme->queue[adc].base = NULL;
-	nvme->queue[adc].bell = NULL;
-	nvme->queue[adc].idx  = 0;
-	nvme->queue[adc].round = 0;
-
-	return 0;
-}
-
-static void nvme_detach_device(struct storage_dev *dev)
-{
-	struct nvme_dev *nvme = (struct nvme_dev *)dev;
-
-	if (delete_io_submission_queue(nvme))
-		printf("NVMe ERROR: Failed to delete io submission queue\n");
-	if (delete_io_completion_queue(nvme))
-		printf("NVME ERROR: Failed to delete io completion queue\n");
-	if (delete_admin_queues(nvme))
-		printf("NVME ERROR: Failed to delete admin queues\n");
-
-	write32(nvme->config + 0x1c, 0);
-
-	int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
-	do {
-		status = read32(nvme->config + 0x1c) & 0x3;
-		if (status == 0x2) {
-			printf("NVMe ERROR: Failed to disable controller. FATAL ERROR\n");
-			break;
-		}
-		if (timeout < 0) {
-			printf("NVMe ERROR: Failed to disable controller. Timeout.\n");
-			break;
-		}
-		timeout -= 10;
-		mdelay(10);
-	} while (status != 0x0);
-
-	uint16_t command = pci_read_config16(nvme->pci_dev, PCI_COMMAND);
-	pci_write_config16(nvme->pci_dev, PCI_COMMAND, command & ~PCI_COMMAND_MASTER);
-
-	free(nvme->prp_list);
-}
-
-static int nvme_read(struct nvme_dev *nvme, unsigned char *buffer, uint64_t base, uint16_t count)
-{
-	if (count == 0 || count > 512)
-		return -1;
-
-	struct nvme_s_queue_entry e = {
-		.dw[0] = 0x02,
-		.dw[1] = 0x1,
-		.dw[6] = virt_to_phys(buffer),
-		.dw[10] = base,
-		.dw[11] = base >> 32,
-		.dw[12] = count - 1,
-	};
-
-	const unsigned int start_page = (uintptr_t)buffer >> 12;
-	const unsigned int end_page = ((uintptr_t)buffer + count * 512 - 1) >> 12;
-	if (end_page == start_page) {
-		/* No page crossing, PRP2 is reserved */
-	} else if (end_page == start_page + 1) {
-		/* Crossing exactly one page boundary, PRP2 is second page */
-		e.dw[8] = virt_to_phys(buffer + 0x1000) & ~0xfff;
-	} else {
-		/* Use a single page as PRP list, PRP2 points to the list */
-		unsigned int i;
-		for (i = 0; i < end_page - start_page; ++i) {
-			buffer += 0x1000;
-			nvme->prp_list[i] = virt_to_phys(buffer) & ~0xfff;
-		}
-		e.dw[8] = virt_to_phys(nvme->prp_list);
-	}
-
-	return nvme_cmd(nvme, ios, &e);
-}
-
-static ssize_t nvme_read_blocks512(
-		struct storage_dev *const dev,
-		const lba_t start, const size_t count, unsigned char *const buf)
-{
-	unsigned int off = 0;
-	while (off < count) {
-		const unsigned int blocks = MIN(count - off, 512);
-		if (nvme_read((struct nvme_dev *)dev, buf + (off * 512), start + off, blocks))
-			return off;
-		off += blocks;
-	}
-	return count;
-}
-
-static int create_io_submission_queue(struct nvme_dev *nvme)
-{
-	void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-	if (!sq_buffer) {
-		printf("NVMe ERROR: Failed to allocate memory for io submission queue.\n");
-		return -1;
-	}
-	memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-
-	struct nvme_s_queue_entry e = {
-		.dw[0]  = 0x01,
-		.dw[6]  = virt_to_phys(sq_buffer),
-		.dw[10] = ((NVME_QUEUE_SIZE - 1) << 16) | ios >> 1,
-		.dw[11] = (1 << 16) | 1,
-	};
-
-	int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
-	if (res) {
-		printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
-		free(sq_buffer);
-		return res;
-	}
-
-	uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
-	nvme->queue[ios].base = sq_buffer;
-	nvme->queue[ios].bell = nvme->config + 0x1000 + (ios * (4 << cap_dstrd));
-	nvme->queue[ios].idx = 0;
-	return 0;
-}
-
-static int create_io_completion_queue(struct nvme_dev *nvme)
-{
-	void *const cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-	if (!cq_buffer) {
-		printf("NVMe ERROR: Failed to allocate memory for io completion queue.\n");
-		return -1;
-	}
-	memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-
-	const struct nvme_s_queue_entry e = {
-		.dw[0]  = 0x05,
-		.dw[6]  = virt_to_phys(cq_buffer),
-		.dw[10] = ((NVME_QUEUE_SIZE - 1) << 16) | ioc >> 1,
-		.dw[11] = 1,
-	};
-
-	int res = nvme_cmd(nvme, NVME_ADMIN_QUEUE, &e);
-	if (res) {
-		printf("NVMe ERROR: nvme_cmd returned with %i.\n", res);
-		free(cq_buffer);
-		return res;
-	}
-
-	uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
-	nvme->queue[ioc].base  = cq_buffer;
-	nvme->queue[ioc].bell  = nvme->config + 0x1000 + (ioc * (4 << cap_dstrd));
-	nvme->queue[ioc].idx   = 0;
-	nvme->queue[ioc].round = 0;
-
-	return 0;
-}
-
-static int create_admin_queues(struct nvme_dev *nvme)
-{
-	uint8_t cap_dstrd = (read64(nvme->config) >> 32) & 0xf;
-	write32(nvme->config + 0x24, (NVME_QUEUE_SIZE - 1) << 16 | (NVME_QUEUE_SIZE - 1));
-
-	void *sq_buffer = memalign(0x1000, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-	if (!sq_buffer) {
-		printf("NVMe ERROR: Failed to allocated memory for admin submission queue\n");
-		return -1;
-	}
-	memset(sq_buffer, 0, NVME_SQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-	write64(nvme->config + 0x28, virt_to_phys(sq_buffer));
-
-	nvme->queue[ads].base = sq_buffer;
-	nvme->queue[ads].bell = nvme->config + 0x1000 + (ads * (4 << cap_dstrd));
-	nvme->queue[ads].idx = 0;
-
-	void *cq_buffer = memalign(0x1000, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-	if (!cq_buffer) {
-		printf("NVMe ERROR: Failed to allocate memory for admin completion queue\n");
-		free(cq_buffer);
-		return -1;
-	}
-	memset(cq_buffer, 0, NVME_CQ_ENTRY_SIZE * NVME_QUEUE_SIZE);
-	write64(nvme->config + 0x30, virt_to_phys(cq_buffer));
-
-	nvme->queue[adc].base = cq_buffer;
-	nvme->queue[adc].bell = nvme->config + 0x1000 + (adc * (4 << cap_dstrd));
-	nvme->queue[adc].idx = 0;
-	nvme->queue[adc].round = 0;
-
-	return 0;
-}
-
-static void nvme_init(pcidev_t dev)
-{
-	printf("NVMe init (Device %02x:%02x.%02x)\n",
-			PCI_BUS(dev), PCI_SLOT(dev), PCI_FUNC(dev));
-
-	void *pci_bar0 = phys_to_virt(pci_read_config32(dev, 0x10) & ~0x3ff);
-
-	if (!(((read64(pci_bar0) >> 37) & 0xff) == 0x01)) {
-		printf("NVMe ERROR: PCIe device does not support the NVMe command set\n");
-		return;
-	}
-	struct nvme_dev *nvme = malloc(sizeof(*nvme));
-	if (!nvme) {
-		printf("NVMe ERROR: Failed to allocate buffer for nvme driver struct\n");
-		return;
-	}
-	nvme->storage_dev.port_type		= PORT_TYPE_NVME;
-	nvme->storage_dev.poll			= nvme_poll;
-	nvme->storage_dev.read_blocks512	= nvme_read_blocks512;
-	nvme->storage_dev.write_blocks512	= NULL;
-	nvme->storage_dev.detach_device		= nvme_detach_device;
-	nvme->pci_dev				= dev;
-	nvme->config				= pci_bar0;
-	nvme->prp_list				= memalign(0x1000, 0x1000);
-
-	if (!nvme->prp_list) {
-		printf("NVMe ERROR: Failed to allocate buffer for PRP list\n");
-		goto abort;
-	}
-
-	const uint32_t cc = NVME_CC_EN | NVME_CC_CSS | NVME_CC_MPS | NVME_CC_AMS | NVME_CC_SHN
-			| NVME_CC_IOSQES | NVME_CC_IOCQES;
-
-	write32(nvme->config + 0x1c, 0);
-
-	int status, timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
-	do {
-		status = read32(nvme->config + 0x1c) & 0x3;
-		if (status == 0x2) {
-			printf("NVMe ERROR: Failed to disable controller. FATAL ERROR\n");
-			goto abort;
-		}
-		if (timeout < 0) {
-			printf("NVMe ERROR: Failed to disable controller. Timeout.\n");
-			goto abort;
-		}
-		timeout -= 10;
-		mdelay(10);
-	} while (status != 0x0);
-	if (create_admin_queues(nvme))
-		goto abort;
-	write32(nvme->config + 0x14, cc);
-
-	timeout = (read64(nvme->config) >> 24 & 0xff) * 500;
-	do {
-		status = read32(nvme->config + 0x1c) & 0x3;
-		if (status == 0x2)
-			goto abort;
-		if (timeout < 0)
-			goto abort;
-		timeout -= 10;
-		mdelay(10);
-	} while (status != 0x1);
-
-	uint16_t command = pci_read_config16(dev, PCI_COMMAND);
-	pci_write_config16(dev, PCI_COMMAND, command | PCI_COMMAND_MASTER);
-	if (create_io_completion_queue(nvme))
-		goto abort;
-	if (create_io_submission_queue(nvme))
-		goto abort;
-	storage_attach_device((storage_dev_t *)nvme);
-	printf("NVMe init done.\n");
-	return;
-
-abort:
-	printf("NVMe init failed.\n");
-	delete_io_submission_queue(nvme);
-	delete_io_completion_queue(nvme);
-	delete_admin_queues(nvme);
-	free(nvme->prp_list);
-	free(nvme);
-}
-
-void nvme_initialize(struct pci_dev *dev)
-{
-	nvme_init(PCI_DEV(dev->bus, dev->dev, dev->func));
-}