Merge remote-tracking branch 'upstream/master' into system76_cleanup

2019-06-13 14:36:33 -06:00
parent 8d5df05d7d a2455b2967
commit 80c4017d85
272 changed files with 14440 additions and 3194 deletions
--- a/Documentation/gfx/display-panel.md
+++ b/Documentation/gfx/display-panel.md
@@ -0,0 +1,64 @@
+Display Panel Specifics
+=======================
+
+Timing Parameters
+-----------------
+
+From the binary file `edid` in the sys filesystem on Linux, the panel can be
+identified. The exact path may differ slightly. Here is an example:
+
+```sh
+$ strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid
+@0 5
+LG Display
+LP140WF3-SPD1
+```
+
+To figure out the timing parameters, refer to the [Intel Programmer's Reference
+Manuals](https://01.org/linuxgraphics/documentation/hardware-specification-prms)
+and try to find the datasheet of the panel using the information from `edid`.
+In the example above, you would search for `LP140WF3-SPD1`. Find a table listing
+the power sequence timing parameters, which are usually named T[N] and also
+referenced in Intel's respective registers listing. You need the values for
+`PP_ON_DELAYS`, `PP_OFF_DELAYS` and `PP_DIVISOR` for your `devicetree.cb`:
+
+```eval_rst
+-----------------------------+---------------------------------------+-----+
+| Intel docs                  | devicetree.cb                         | eDP |
+-----------------------------+---------------------------------------+-----+
+| Power up delay              | `gpu_panel_power_up_delay`            | T3  |
+-----------------------------+---------------------------------------+-----+
+| Power on to backlight on    | `gpu_panel_power_backlight_on_delay`  | T7  |
+-----------------------------+---------------------------------------+-----+
+| Power Down delay            | `gpu_panel_power_down_delay`          | T10 |
+-----------------------------+---------------------------------------+-----+
+| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9  |
+-----------------------------+---------------------------------------+-----+
+| Power Cycle Delay           | `gpu_panel_power_cycle_delay`         | T12 |
+-----------------------------+---------------------------------------+-----+
+```
+
+Intel GPU Tools and VBT
+-----------------------
+
+The Intel GPU tools are in a package called either `intel-gpu-tools` or
+`igt-gpu-tools` in most distributions of Linux-based operating systems.
+In the coreboot `util/` directory, you can find `intelvbttool`.
+
+From a running system, you can dump the register values directly:
+```sh
+$ intel_reg dump --all | grep PCH_PP
+                      PCH_PP_STATUS (0x000c7200): 0x80000008
+                     PCH_PP_CONTROL (0x000c7204): 0x00000007
+                   PCH_PP_ON_DELAYS (0x000c7208): 0x07d00001
+                  PCH_PP_OFF_DELAYS (0x000c720c): 0x01f40001
+                     PCH_PP_DIVISOR (0x000c7210): 0x0004af06
+```
+
+You can obtain the timing values from a VBT (Video BIOS Table), which you can
+dump from a vendor UEFI image:
+```sh
+$ intel_vbt_decode data.vbt | grep T3
+                Power Sequence: T3 2000 T7 10 T9 2000 T10 500 T12 5000
+                T3 optimization: no
+```
--- a/Documentation/gfx/libgfxinit.md
+++ b/Documentation/gfx/libgfxinit.md
@@ -55,6 +55,9 @@ follows:
 GMA: Per Board Configuration
 ----------------------------

+In order to set up the display panel, see the
+[display panel-specific documentation](/gfx/display-panel.md).
+
 There are a few Kconfig symbols to consider. To indicate that a
 board can initialize graphics through *libgfxinit*:

--- a/Documentation/index.md
+++ b/Documentation/index.md
@@ -173,6 +173,7 @@ Contents:
 * [Dealing with Untrusted Input in SMM](technotes/2017-02-dealing-with-untrusted-input-in-smm.md)
 * [GPIO toggling in ACPI AML](acpi/gpio.md)
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
+* [Display panel-specific documentation](gfx/display-panel.md)
 * [Architecture-specific documentation](arch/index.md)
 * [Northbridge-specific documentation](northbridge/index.md)
 * [System on Chip-specific documentation](soc/index.md)
--- a/Documentation/mainboard/hp/z220_sff.md
+++ b/Documentation/mainboard/hp/z220_sff.md
@@ -0,0 +1,70 @@
+# HP Z220 SFF Workstation
+
+This page describes how to run coreboot on the [HP Z220 SFF Workstation] desktop
+from [HP].
+
+## TODO
+
+The following things are still missing from this coreboot port:
+
+- Extended HWM reporting
+- Advanced LED control
+- Advanced power configuration in S3
+
+## Flashing coreboot
+
+```eval_rst
+---------------------+-------------+
+| Type                | Value       |
+=====================+=============+
+| Socketed flash      | no          |
+---------------------+-------------+
+| Model               | N25Q128..3E |
+---------------------+-------------+
+| Size                | 16 MiB      |
+---------------------+-------------+
+| In circuit flashing | yes         |
+---------------------+-------------+
+| Package             | SOIC-16     |
+---------------------+-------------+
+| Write protection    | No          |
+---------------------+-------------+
+| Dual BIOS feature   | No          |
+---------------------+-------------+
+| Internal flashing   | yes         |
+---------------------+-------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+### External programming
+
+External programming with an SPI adapter and [flashrom] does work, but it powers the
+whole southbridge complex. You need to supply enough current through the programming adapter.
+
+If you want to use a SOIC pomona test clip, you have to cut the 2nd DRAM DIMM holder,
+as otherwise there's not enough space near the flash.
+
+## Technology
+
+```eval_rst
+------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
+------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
+------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
+------------------+--------------------------------------------------+
+| SuperIO          | :doc:`../../superio/nuvoton/npcd378`             |
+------------------+--------------------------------------------------+
+| EC               |                                                  |
+------------------+--------------------------------------------------+
+| Coprocessor      | Intel ME                                         |
+------------------+--------------------------------------------------+
+```
+
+[HP Z220 SFF Workstation]: https://support.hp.com/za-en/document/c03386950
+[HP]: https://www.hp.com/
+[flashrom]: https://flashrom.org/Flashrom
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -54,6 +54,7 @@ The boards in this section are not real mainboards, but emulators.
 ## HP

 - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md)
+- [Z220 Workstation SFF](hp/z220_sff.md)

 ### EliteBook series

--- a/Documentation/soc/amd/family17h.md
+++ b/Documentation/soc/amd/family17h.md
@@ -0,0 +1,224 @@
+# AMD Family 17h in coreboot
+
+## Abstract
+
+Beginning with Family 17h products (a.k.a. “Zen” cores), AMD
+changed their paradigm for initializing the system and this requires
+major modifications to the execution flow of coreboot.  This file
+discusses the new boot flow, and challenges, and the tradeoffs of the
+initial port into coreboot.
+
+## Introduction
+
+Family 17h products are x86-based designs.  This documentation assumes
+familiarity with x86, its reset state and its early initialization
+requirements.
+
+To the extent necessary, the role of the Platform Security Processor
+(a.k.a. PSP) in system initialization is addressed here.  AMD has
+historically required an NDA for access to the PSP
+specification<sup>1</sup>.  coreboot relies on util/amdfwtool to build
+the structures and add various other firmware to the final image.  The
+Family 17h PSP design guide adds a new BIOS Directory Table, similar to
+the PSP Directory Table.
+
+Support in coreboot for modern AMD products is based on AMD’s
+reference code:  AMD Generic Encapsulated Software Architecture
+(AGESA<sup>TM</sup>).  AGESA contains the technology for enabling DRAM,
+configuring proprietary core logic, assistance with generating ACPI
+tables, and other features.
+
+AGESA for products earlier than Family 17h is known as v5 or
+Arch2008<sup>2</sup>.  Also note that coreboot currently contains both
+open source AGESA and closed source implementations (binaryPI) compiled
+from AGESA.
+
+The first AMD Family 17h device ported to coreboot is codenamed
+“Picasso”<sup>3</sup>, and will be added to soc/amd/picasso.
+
+## Additional Definitions
+
+*   PSP, Platform Security Processor:  Onboard ARM processor that runs
+alongside the main x86 processor; may be viewed as analogous to the
+Intel<sup>R</sup> Management Engine
+*   FCH, Fusion Control Hub, the logical southbridge within the SOC
+*   ABL - AGESA Bootloader - Processor initialization code that runs on
+the PSP
+*   PSP Directory Table - A structured list of pointers to PSP firmware
+and other controller binaries
+*   BIOS Directory Table - A structured list of pointers to BIOS
+related firmware images
+*   Embedded Firmware Structure - Signature and pointers used by the
+PSP to locate the PSP Directory Table and BIOS Directory Table; these
+items are generated during coreboot build and are located in the SPI ROM
+*   Verstage - The code to verify the firmware contained in the
+writable section of the SPI ROM
+*   APCB - AMD PSP Customization Block - A binary containing PSP and
+system configuration preferences (analogous to v5 BUILDOPT_ options),
+and generated by APCBTool to be added to coreboot/utils later
+*   APOB - AGESA PSP Output Buffer - A buffer in main memory for
+storing AGESA BootLoader output.  There are no plans for this to be
+parsed by coreboot
+
+## Problem Statements
+
+AMD has ported early AGESA features to the PSP, which now discovers,
+enables and trains DRAM.  Unlike any other x86 device in coreboot, a
+Picasso system has DRAM online prior to the first instruction fetch.
+
+Cache-as-RAM (CAR) is no longer a supportable feature in AMD hardware.
+Early code expecting CAR behavior <span
+style="text-decoration:underline;">must</span> account for writes
+escaping the L2 cache and going to DRAM.
+
+Without any practical need for CAR, or DRAM initialization, coreboot
+should arguably skip bootblock and romstage, and possibly use ramstage
+as the BIOS image.  This approach presents a number of challenges:
+
+*   At the entry of ramstage, x86 processors are in flat protected
+mode.  Picasso’s initial state is nearly identical to any other x86
+at reset, except its CS shadow register’s base and limit put its
+execution within DRAM, not at 0xfffffff0.  Picasso requires initial
+programming and entry into protected mode prior to ramstage.
+*   coreboot expects cbmem initialization during romstage.
+
+AGESA supporting Picasso is now at v9.  Unlike Arch2008, which defines
+granular entry points for easy inclusion to a legacy BIOS, v9 is
+rewritten for compilation into a UEFI.  The source follows UEFI
+standards, i.e. assumes the presence of UEFI phases, implements
+dependency expressions, much functionality is rewritten as libraries,
+etc.  It would, in no way, fit into the v5 model used in coreboot.
+
+*   For the foreseeable future, AGESA source will distributed only
+under NDA.
+
+## Basic Pre-x86 Boot Flow
+
+The following steps occur prior to x86 processor operation.
+
+*   System power on
+*   PSP executes immutable on-chip boot ROM
+*   PSP locates the Embedded Firmware Table and PSP Directory Table in
+the SPI ROM
+*   PSP verifies and executes the PSP off-chip bootloader
+*   ChromeOS systems:
+    *   Off-chip bootloader attempts to locate verstage via the RO BIOS
+Directory Table
+    *   If verstage is not found, booting continues with ABLs below
+    *   Verstage initializes, setting up GPIOs, UART if needed,
+communication path to the EC, and the SPI controller for direct access
+to the flash device.
+    *   Verstage verifies the RW sections (as is typically performed by
+the main processor)
+    *   Verstage locates the Embedded Firmware Directory within the
+verified FMAP section and passes a pointer to the PSP bootloader.  If
+the verification fails, it passes a pointer to the RO header to the
+bootloader.
+*   PSP parses the PSP Directory Table to find the ABLs and executes
+them
+*   An ABL parses the APCB for system configuration preferences
+*   An ABL initializes system main memory, locates the compressed BIOS
+image in the SPI ROM, and decompresses it into DRAM
+*   An ABL writes the APOB to DRAM  for consumption by the x86-based
+AGESA
+*   PSP releases the x86 processor from reset.  The x86 core fetches
+and executes instructions from the reset vector
+
+## Picasso Reset Vector and First Instructions
+
+As mentioned above, prior to releasing the x86 main core from reset,
+the PSP decompresses a BIOS image into DRAM.  The PSP uses a specific
+BIOS Directory Table entry type to determine the source address (in
+flash), the destination address (in DRAM), and the destination size.
+The decompressed image is at the top of the destination region.  The
+PSP then
+
+Calculates the x86 reset vector as
+
+    reset_vector	= dest_addr + dest_size - 0x10
+
+Sets x86 CS descriptor shadow register to
+
+    base		= dest_addr + dest_size - 0x10000
+    limit		= 0xffff
+
+Like all x86 devices, the main core is allowed to begin executing
+instructions with
+
+    CS:IP		= 0xf000:0xfff0
+
+For example, assume the BIOS Directory Table indicates
+
+    destination	= 0x9b00000
+    size		= 0x300000
+
+… then the BIOS image is placed at the topmost position the region
+0x9b00000-0x9dfffff and
+
+    reset_vector	= 0x9dffff0
+    CS_shdw_base	= 0x9df0000
+    CS:IP		= 0xf000:0xfff0
+
+Although the x86 behaves as though it began executing at 0xfffffff0
+i.e. 0xf000:0xfff0, the initial GDT load must use the physical address
+of the table and not the typical CS-centric address.  And, the first
+jump to protected mode must jump to the physical address in DRAM.  Any
+code that is position-dependent must be linked to run at the final
+destination.
+
+## Initial coreboot Implementation
+
+Supporting Picasso doesn’t fit well with many of the coreboot
+assumptions.  Initial porting shall attempt to fit within existing
+coreboot paradigms and make minimal changes to common code.
+
+### CAR and bootblock
+
+The coreboot bootblock contains features Picasso doesn’t require or
+can’t use, and is assumed to execute in an unusable location.
+Picasso’s requirement for bootblock in coreboot will be eliminated.
+
+### Hybrid romstage
+
+Picasso’s x86 reset state doesn’t meet the coreboot expectations
+for jumping directly to ramstage.  The primary feature of romstage is
+also not needed, however there are other important features that are
+typically in romstage that Picasso does need.
+
+The romstage architecture is designed around the presence of CAR.
+Several features implement ROMSTAGE_CBMEM_INIT_HOOK, expecting to move
+data from CAR to cbmem.  The hybrid romstage consumes DRAM for the
+purpose of implementing the expected CAR storage.  This region as well
+as the DRAM where romstage is decompressed must be reserved and
+unavailable to the OS.
+
+The initial Picasso port implements a hybrid romstage that contains the
+first instruction fetched at the reset vector.  It minimally configures
+flat protected mode, initializes cbmem, then loads the next stage.
+Future work will consider breaking the dependencies mentioned above
+and/or potentially loading ramstage directly from the PSP.
+
+## AGESA v9 on Picasso
+
+Due to the current inability to publish AGESA source, a pre-built
+binary solution remains a requirement.  The rewrite from v5 to v9 for
+direct inclusion into UEFI source makes modifying it for conforming to
+the existing v5 interface impractical.
+
+Given the UEFI nature of modern AGESA, and the existing open source
+work from Intel, Picasso shall support AGESA via an FSP-like prebuilt
+image.  The Intel Firmware Support Package<sup>4</sup> combines
+reference code with EDK II source to create a modular image with
+discoverable entry points.  coreboot source already contains knowledge
+of FSP, how to parse it, integrate it, and how to communicate with it.
+
+## Footnotes
+
+1. “AMD Platform Security Processor BIOS Architecture Design Guide
+for AMD Family 17h Processors” (PID #55758) and “AMD Platform
+Security Processor BIOS Architecture Design Guide” (PID #54267) for
+earlier products
+2. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf)
+3. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso)
+4. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html)
+
--- a/Documentation/soc/amd/index.md
+++ b/Documentation/soc/amd/index.md
@@ -0,0 +1,8 @@
+# AMD SOC-specific documentation
+
+This section contains documentation about coreboot on specific AMD SOCs.
+
+## Technology
+
+- [Family 17h](family17h.md)
+
--- a/Documentation/soc/index.md
+++ b/Documentation/soc/index.md
@@ -4,5 +4,6 @@ This section contains documentation about coreboot on specific SOCs.

 ## Vendor

+- [AMD](amd/index.md)
 - [Cavium](cavium/index.md)
 - [Intel](intel/index.md)
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1058,7 +1058,14 @@ ifneq ($(FIT_ENTRY),)
 FIT_OPTIONS += -q $(FIT_ENTRY)
 endif

-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE)
+ifeq ($(CONFIG_HAVE_RAMSTAGE),y)
+RAMSTAGE=$(objcbfs)/ramstage.elf
+else
+RAMSTAGE=
+endif
+
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE)
+
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 # The full ROM may be larger than the CBFS part, so create an empty
 # file (filled with \377 = 0xff) and copy the CBFS image over it.
@@ -1128,8 +1135,8 @@ endif    # CONFIG_NO_FIXED_XIP_ROM_SIZE
 endif   # CONFIG_NO_XIP_EARLY_STAGES
 endif   # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64

-cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage
-$(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf
+cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage
+$(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE)
 $(CONFIG_CBFS_PREFIX)/ramstage-type := stage
 $(CONFIG_CBFS_PREFIX)/ramstage-compression := $(CBFS_COMPRESS_FLAG)

--- a/payloads/libpayload/configs/config.mistral
+++ b/payloads/libpayload/configs/config.mistral
@@ -3,3 +3,6 @@ CONFIG_LP_ARCH_ARM64=y
 CONFIG_LP_TIMER_ARM64_ARCH=y
 CONFIG_LP_SERIAL_CONSOLE=y
 CONFIG_LP_QCS405_SERIAL_CONSOLE=y
+CONFIG_LP_USB=y
+CONFIG_LP_USB_EHCI=y
+CONFIG_LP_USB_XHCI=y
--- a/payloads/libpayload/drivers/i8042/i8042.h
+++ b/payloads/libpayload/drivers/i8042/i8042.h
@@ -63,7 +63,6 @@
 #define I8042_KBCMD_EN			0xf4
 #define I8042_KBCMD_DEFAULT_DIS		0xf5
 #define I8042_KBCMD_SET_DEFAULT		0xf6
-#define I8042_KBCMD_ACK			0xfa
 #define I8042_KBCMD_RESEND		0xfe
 #define I8042_KBCMD_RESET		0xff

--- a/payloads/libpayload/drivers/i8042/keyboard.c
+++ b/payloads/libpayload/drivers/i8042/keyboard.c
@@ -172,7 +172,7 @@ static unsigned char keyboard_cmd(unsigned char cmd)
 {
 	i8042_write_data(cmd);

-	return i8042_wait_read_ps2() == I8042_KBCMD_ACK;
+	return i8042_wait_read_ps2() == 0xfa;
 }

 int keyboard_havechar(void)
@@ -317,42 +317,27 @@ void keyboard_init(void)
 	/* Enable first PS/2 port */
 	i8042_cmd(I8042_CMD_EN_KB);

-	/* Reset keyboard and self test (keyboard side) */
-	ret = keyboard_cmd(I8042_KBCMD_RESET);
-	if (!ret) {
-		printf("ERROR: Keyboard reset failed!\n");
-		return;
-	}
-
 	/* Set scancode set 1 */
 	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
-		printf("ERROR: Keyboard set scancode failed!\n");
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
-	}

 	ret = keyboard_cmd(I8042_SCANCODE_SET_1);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
-		printf("ERROR: Keyboard scancode set#1 failed!\n");
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
-	}

 	/*
 	 * Set default parameters.
 	 * Fix for broken QEMU ps/2 make scancodes.
 	 */
 	ret = keyboard_cmd(0xf6);
-	if (!ret) {
-		printf("ERROR: Keyboard set default params failed!\n");
+	if (!ret)
 		return;
-	}

 	/* Enable scanning */
 	ret = keyboard_cmd(I8042_KBCMD_EN);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
-		printf("ERROR: Keyboard enable scanning failed!\n");
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
 		return;
-	}

 	console_add_input_driver(&cons);
 }
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -129,6 +129,7 @@ config STATIC_OPTION_TABLE

 config COMPRESS_RAMSTAGE
 	bool "Compress ramstage with LZMA"
+	depends on HAVE_RAMSTAGE
 	# Default value set at the end of the file
 	help
 	  Compress ramstage to save memory in the flash image. Note
@@ -137,7 +138,7 @@ config COMPRESS_RAMSTAGE

 config COMPRESS_PRERAM_STAGES
 	bool "Compress romstage and verstage with LZ4"
-	depends on !ARCH_X86
+	depends on !ARCH_X86 && (HAVE_ROMSTAGE || HAVE_VERSTAGE)
 	# Default value set at the end of the file
 	help
 	  Compress romstage and (if it exists) verstage with LZ4 to save flash
@@ -148,6 +149,7 @@ config COMPRESS_PRERAM_STAGES

 config COMPRESS_BOOTBLOCK
 	bool
+	depends on HAVE_BOOTBLOCK
 	help
 	  This option can be used to compress the bootblock with LZ4 and attach
 	  a small self-decompression stub to its front. This can drastically
@@ -234,6 +236,7 @@ config NO_RELOCATABLE_RAMSTAGE

 config RELOCATABLE_RAMSTAGE
 	bool
+	depends on HAVE_RAMSTAGE
 	default !NO_RELOCATABLE_RAMSTAGE
 	select RELOCATABLE_MODULES
 	help
@@ -277,10 +280,13 @@ config BOOTSPLASH_FILE
 	  The path and filename of the file to use as graphical bootsplash
 	  screen. The file format has to be jpg.

+config HAVE_RAMPAYLOAD
+	bool
+
 config RAMPAYLOAD
 	bool "Enable coreboot flow without executing ramstage"
 	default n
-	depends on ARCH_X86
+	depends on HAVE_RAMPAYLOAD
 	help
 	  If this option is enabled, coreboot flow will skip ramstage
 	  loading and execution of ramstage to load payload.
@@ -1188,3 +1194,26 @@ config BOOTSPLASH_FILE

 config CBFS_SIZE
 	default ROM_SIZE
+
+config HAVE_BOOTBLOCK
+	bool
+	default y
+
+config HAVE_VERSTAGE
+	bool
+	depends on VBOOT_SEPARATE_VERSTAGE
+	default y
+
+config HAVE_ROMSTAGE
+	bool
+	default y
+
+config HAVE_POSTCAR
+	bool
+	depends on POSTCAR_STAGE
+	default y
+
+config HAVE_RAMSTAGE
+	bool
+	default n if RAMPAYLOAD
+	default y
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -336,13 +336,6 @@ ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S
 ramstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S

-smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
-smm-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
-smm-y += memcpy.c
-smm-y += memmove.c
-smm-y += memset.c
-smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
-
 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
 rmodules_x86_32-y += memcpy.c
 rmodules_x86_32-y += memmove.c
@@ -379,11 +372,6 @@ ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/fadt.c),)
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/fadt.c
 endif
 endif # CONFIG_GENERATE_ACPI_TABLES
-ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
-ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),)
-smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c
-endif
-endif

 ramstage-libs ?=

@@ -408,3 +396,16 @@ else
 endif

 endif # CONFIG_ARCH_RAMSTAGE_X86_32 / CONFIG_ARCH_RAMSTAGE_X86_64
+
+smm-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c
+smm-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S
+smm-y += memcpy.c
+smm-y += memmove.c
+smm-y += memset.c
+smm-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
+
+ifeq ($(CONFIG_HAVE_SMI_HANDLER),y)
+ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/smihandler.c),)
+smm-srcs += src/mainboard/$(MAINBOARDDIR)/smihandler.c
+endif
+endif
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -514,6 +514,63 @@ void acpigen_write_field(const char *name, struct fieldlist *l, size_t count,
 	acpigen_pop_len();
 }

+/*
+ * Generate ACPI AML code for IndexField
+ * Arg0: region name
+ * Arg1: Pointer to struct fieldlist.
+ * Arg2: no. of entries in Arg1
+ * Arg3: flags which indicate filed access type, lock rule  & update rule.
+ * Example with fieldlist
+ * struct fieldlist l[] = {
+ *	FIELDLIST_OFFSET(0x84),
+ *	FIELDLIST_NAMESTR("PMCS", 2),
+ *	};
+ * acpigen_write_field("IDX", "DATA" l, ARRAY_SIZE(l), FIELD_ANYACC |
+ *						       FIELD_NOLOCK |
+ *						       FIELD_PRESERVE);
+ * Output:
+ * IndexField (IDX, DATA, AnyAcc, NoLock, Preserve)
+ *	{
+ *		Offset (0x84),
+ *		PMCS,   2
+ *	}
+ */
+void acpigen_write_indexfield(const char *idx, const char *data,
+			      struct fieldlist *l, size_t count, uint8_t flags)
+{
+	uint16_t i;
+	uint32_t current_bit_pos = 0;
+
+	/* FieldOp */
+	acpigen_emit_ext_op(INDEX_FIELD_OP);
+	/* Package Length */
+	acpigen_write_len_f();
+	/* NameString 4 chars only */
+	acpigen_emit_simple_namestring(idx);
+	/* NameString 4 chars only */
+	acpigen_emit_simple_namestring(data);
+	/* Field Flag */
+	acpigen_emit_byte(flags);
+
+	for (i = 0; i < count; i++) {
+		switch (l[i].type) {
+		case NAME_STRING:
+			acpigen_write_field_name(l[i].name, l[i].bits);
+			current_bit_pos += l[i].bits;
+			break;
+		case OFFSET:
+			acpigen_write_field_offset(l[i].bits, current_bit_pos);
+			current_bit_pos = l[i].bits;
+			break;
+		default:
+			printk(BIOS_ERR, "%s: Invalid field type 0x%X\n"
+				, __func__, l[i].type);
+			break;
+		}
+	}
+	acpigen_pop_len();
+}
+
 void acpigen_write_empty_PCT(void)
 {
 /*
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -420,6 +420,12 @@ void acpigen_write_opregion(struct opregion *opreg);
 */
 void acpigen_write_field(const char *name, struct fieldlist *l, size_t count,
 			 uint8_t flags);
+/*
+ * Generate ACPI AML code for IndexField
+ * This function takes input index name, data name, fieldlist, count & flags.
+ */
+void acpigen_write_indexfield(const char *idx, const char *data,
+			      struct fieldlist *l, size_t count, uint8_t flags);

 int get_cst_entries(acpi_cstate_t **);

--- a/src/arch/x86/postcar_loader.c
+++ b/src/arch/x86/postcar_loader.c
@@ -154,8 +154,7 @@ static void load_postcar_cbfs(struct prog *prog, struct postcar_frame *pcf)

 	finalize_load(rsl.params, pcf->stack);

-	if (!CONFIG(NO_STAGE_CACHE))
-		stage_cache_add(STAGE_POSTCAR, prog);
+	stage_cache_add(STAGE_POSTCAR, prog);
 }

 void run_postcar_phase(struct postcar_frame *pcf)
--- a/src/arch/x86/smbios.c
+++ b/src/arch/x86/smbios.c
@@ -372,6 +372,11 @@ static int create_smbios_type17_for_dimm(struct dimm_info *dimm,
 	dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0';
 	smbios_fill_dimm_part_number((char *)dimm->module_part_number, t);

+	/* Voltage Levels */
+	t->configured_voltage = dimm->vdd_voltage;
+	t->minimum_voltage = dimm->vdd_voltage;
+	t->maximum_voltage = dimm->vdd_voltage;
+
 	/* Synchronous = 1 */
 	t->type_detail = 0x0080;
 	/* no handle for error information */
--- a/src/commonlib/include/commonlib/cbmem_id.h
+++ b/src/commonlib/include/commonlib/cbmem_id.h
@@ -19,6 +19,7 @@

 #define CBMEM_ID_ACPI		0x41435049
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
+#define CBMEM_ID_ACPI_UCSI	0x55435349
 #define CBMEM_ID_AFTER_CAR	0xc4787a93
 #define CBMEM_ID_AGESA_RUNTIME	0x41474553
 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E
@@ -82,6 +83,7 @@
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
 	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
+	{ CBMEM_ID_ACPI_UCSI,		"ACPI UCSI  " }, \
 	{ CBMEM_ID_AGESA_RUNTIME,	"AGESA RSVD " }, \
 	{ CBMEM_ID_AFTER_CAR,		"AFTER CAR  " }, \
 	{ CBMEM_ID_AMDMCT_MEMINFO,	"AMDMEM INFO" }, \
--- a/src/console/die.c
+++ b/src/console/die.c
@@ -30,17 +30,15 @@ __weak void die_notify(void)
 }

 /* Report a fatal error */
-void __noreturn die(const char *msg)
+void __noreturn die(const char *fmt, ...)
 {
-	printk(BIOS_EMERG, "%s", msg);
+	va_list args;
+
+	va_start(args, fmt);
+	vprintk(BIOS_EMERG, fmt, args);
+	va_end(args);
+
 	die_notify();
 	halt();
 }
-
-/* Report a fatal error with a post code */
-void __noreturn die_with_post_code(uint8_t value, const char *msg)
-{
-	post_code(value);
-	die(msg);
-}
 #endif
--- a/src/console/printk.c
+++ b/src/console/printk.c
@@ -45,7 +45,7 @@ static void wrap_putchar_cbmemc(unsigned char byte, void *data)
 	__cbmemc_tx_byte(byte);
 }

-int vprintk(int msg_level, const char *fmt, va_list args)
+int do_vprintk(int msg_level, const char *fmt, va_list args)
 {
 	int i, log_this;

@@ -91,7 +91,7 @@ int do_printk(int msg_level, const char *fmt, ...)
 	int i;

 	va_start(args, fmt);
-	i = vprintk(msg_level, fmt, args);
+	i = do_vprintk(msg_level, fmt, args);
 	va_end(args);

 	return i;
--- a/src/cpu/x86/Makefile.inc
+++ b/src/cpu/x86/Makefile.inc
@@ -17,23 +17,27 @@ SIPI_RMOD=$(SIPI_ELF).rmod
 SIPI_BIN=$(SIPI_ELF:.elf=)
 SIPI_DOTO=$(SIPI_ELF:.elf=.o)

-ifeq ($(CONFIG_PARALLEL_MP),y)
-ramstage-srcs += $(SIPI_BIN).manual
-endif
-rmodules_$(ARCH-ramstage-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S
-
-$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-ramstage-y),src/cpu/x86/sipi_vector.S)
-	$(CC_rmodules_$(ARCH-ramstage-y)) $(CFLAGS_rmodules_$(ARCH-ramstage-y)) -nostdlib -r -o $@ $^
-
-ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y)
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_32))
+ifeq ($(CONFIG_HAVE_RAMSTAGE),y)
+TARGET_STAGE=ramstage
+else ifeq ($(CONFIG_RAMPAYLOAD),y)
+TARGET_STAGE=postcar
 else
-$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,x86_64))
+$(error Halting the build due to unknown TARGET_STAGE select)
 endif

+ifeq ($(CONFIG_PARALLEL_MP),y)
+$(TARGET_STAGE)-srcs += $(SIPI_BIN).manual
+endif
+rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S
+
+$(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S)
+	$(CC_rmodules_$(ARCH-$(TARGET_STAGE)-y)) $(CFLAGS_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^
+
+$(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y)))
+
 $(SIPI_BIN): $(SIPI_RMOD)
-	$(OBJCOPY_ramstage) -O binary $< $@
+	$(OBJCOPY_$(TARGET_STAGE)) -O binary $< $@

-$(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN)
+$(call src-to-obj,$(TARGET_STAGE),$(SIPI_BIN).manual): $(SIPI_BIN)
 	@printf "    OBJCOPY    $(subst $(obj)/,,$(@))\n"
-	cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
+	cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@)
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -21,6 +21,7 @@ verstage-y += fsp_util.c
 verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c

 bootblock-y += bootblock.c
+bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
 bootblock-y += fsp_util.c

 romstage-y += car.c
@@ -42,8 +43,6 @@ ramstage-$(CONFIG_MMA) += mma_core.c

 CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include

-cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
-
 postcar-y += stage_cache.c
 ifneq ($(CONFIG_SKIP_FSP_CAR),y)
 postcar-y += temp_ram_exit.c
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc
@@ -5,6 +5,7 @@
 * Copyright (C) 2007-2008 coresystems GmbH
 * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
 * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -16,6 +17,8 @@
 * GNU General Public License for more details.
 */

+#include <cpu/x86/post_code.h>
+
 /*
 * Replacement for cache_as_ram.inc when using the FSP binary.  This code
 * locates the FSP binary, initializes the cache as RAM and performs the
@@ -24,8 +27,10 @@
 * performs the final stage of initialization.
 */

-/* I/O delay between post codes on failure */
-#define LHLT_DELAY	0x50000
+#define LHLT_DELAY	0x50000	/* I/O delay between post codes on failure */
+
+.global	bootblock_pre_c_entry
+bootblock_pre_c_entry:
 	/*
 	 * Per FSP1.1 specs, following registers are preserved:
 	 * EBX, EDI, ESI, EBP, MM0, MM1
@@ -129,10 +134,9 @@ CAR_init_done:
 	/* Need to align stack to 16 bytes at call instruction. Account for
 	the pushes below. */
 	andl	$0xfffffff0, %esp
-	subl	$4, %esp
+	subl	$8, %esp

-	/* Push BIST and initial timestamp on the stack */
-	pushl	%ebx	/* bist */
+	/* Push initial timestamp on the stack */
 	movd	%mm1, %eax
 	pushl	%eax	/* tsc[63:32] */
 	movd	%mm0, %eax
@@ -141,12 +145,10 @@ CAR_init_done:
 before_romstage:
 	post_code(0x2A)

-	/* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-	   in cpu/intel/car/romstage.c */
-	call	bootblock_c_entry_bist
+	/* Call bootblock_c_entry(uint64_t base_timestamp) */
+	call	bootblock_c_entry

-	movb	$0x69, %ah
-	jmp	.Lhlt
+	/* Never reached */

 halt1:
 	/*
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -101,18 +101,6 @@ void mainboard_romstage_entry(unsigned long bist)
 	 * is still enabled. We can directly access work buffer here. */
 	struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");

-	if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) {
-		/* Call into pre-console init code then initialize console. */
-		car_soc_pre_console_init();
-		car_mainboard_pre_console_init();
-		console_init();
-
-		display_mtrrs();
-
-		car_soc_post_console_init();
-		car_mainboard_post_console_init();
-	}
-
 	if (prog_locate(&fsp))
 		die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin");

@@ -125,19 +113,3 @@ void mainboard_romstage_entry(unsigned long bist)

 	cache_as_ram_stage_main(fih);
 }
-
-void __weak car_mainboard_pre_console_init(void)
-{
-}
-
-void __weak car_soc_pre_console_init(void)
-{
-}
-
-void __weak car_mainboard_post_console_init(void)
-{
-}
-
-void __weak car_soc_post_console_init(void)
-{
-}
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -24,12 +24,4 @@
 * cache_as_ram_stage_main() is the stack pointer to use in RAM after
 * exiting cache-as-ram mode. */
 void cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
-
-/* Mainboard and SoC initialization prior to console. */
-void car_mainboard_pre_console_init(void);
-void car_soc_pre_console_init(void);
-/* Mainboard and SoC initialization post console initialization. */
-void car_mainboard_post_console_init(void);
-void car_soc_post_console_init(void);
-
 #endif
--- a/src/drivers/lenovo/hybrid_graphics/Kconfig
+++ b/src/drivers/lenovo/hybrid_graphics/Kconfig
@@ -1,3 +1,5 @@
 config DRIVERS_LENOVO_HYBRID_GRAPHICS
 	bool
 	default n
+	# for dual graphics we need to set this
+	select ONBOARD_VGA_IS_PRIMARY
--- a/src/drivers/spi/adesto.c
+++ b/src/drivers/spi/adesto.c
@@ -201,11 +201,6 @@ out:
 static const struct spi_flash_ops spi_flash_ops = {
 	.write = adesto_write,
 	.erase = spi_flash_cmd_erase,
-#if CONFIG(SPI_FLASH_NO_FAST_READ)
-	.read = spi_flash_cmd_read_slow,
-#else
-	.read = spi_flash_cmd_read_fast,
-#endif
 };

 int spi_flash_probe_adesto(const struct spi_slave *spi, u8 *idcode,
--- a/src/drivers/spi/amic.c
+++ b/src/drivers/spi/amic.c
@@ -176,11 +176,6 @@ out:
 static const struct spi_flash_ops spi_flash_ops = {
 	.write = amic_write,
 	.erase = spi_flash_cmd_erase,
-#if CONFIG(SPI_FLASH_NO_FAST_READ)
-	.read = spi_flash_cmd_read_slow,
-#else
-	.read = spi_flash_cmd_read_fast,
-#endif
 };

 int spi_flash_probe_amic(const struct spi_slave *spi, u8 *idcode,
--- a/src/drivers/spi/atmel.c
+++ b/src/drivers/spi/atmel.c
@@ -157,11 +157,6 @@ out:
 static const struct spi_flash_ops spi_flash_ops = {
 	.write = atmel_write,
 	.erase = spi_flash_cmd_erase,
-#if CONFIG(SPI_FLASH_NO_FAST_READ)
-	.read = spi_flash_cmd_read_slow,
-#else
-	.read = spi_flash_cmd_read_fast,
-#endif
 };

 int spi_flash_probe_atmel(const struct spi_slave *spi, u8 *idcode,
--- a/src/drivers/spi/cbfs_spi.c
+++ b/src/drivers/spi/cbfs_spi.c
@@ -31,21 +31,18 @@ static struct spi_flash spi_flash_info;
 static bool spi_flash_init_done;

 /*
- * Set this to 1 to debug SPI speed, 0 to disable it
- * The format is:
+ * SPI speed logging for big transfers available with BIOS_DEBUG. The format is:
 *
- * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps
+ * read SPI 0x62854 0x7db7: 10416 us, 3089 KB/s, 24.712 Mbps
 *
 * The important number is the last one. It should roughly match your SPI
 * clock. If it doesn't, your driver might need a little tuning.
 */
-#define SPI_SPEED_DEBUG		0
-
 static ssize_t spi_readat(const struct region_device *rd, void *b,
 				size_t offset, size_t size)
 {
 	struct stopwatch sw;
-	bool show = SPI_SPEED_DEBUG && size >= 4 * KiB;
+	bool show = size >= 4 * KiB && console_log_level(BIOS_DEBUG);

 	if (show)
 		stopwatch_init(&sw);
@@ -58,7 +55,7 @@ static ssize_t spi_readat(const struct region_device *rd, void *b,
 		u64 speed;	/* KiB/s */
 		int bps;	/* Bits per second */

-		speed = (u64)size * 1000 / usecs;
+		speed = size * 1000 / usecs;
 		bps = speed * 8;

 		printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n",
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
@@ -292,7 +292,6 @@ static const struct spi_flash_ops spi_flash_ops = {
 	.write = eon_write,
 	.erase = spi_flash_cmd_erase,
 	.status = spi_flash_cmd_status,
-	.read = spi_flash_cmd_read_fast,
 };

 int spi_flash_probe_eon(const struct spi_slave *spi, u8 *idcode,
--- a/src/drivers/spi/gigadevice.c
+++ b/src/drivers/spi/gigadevice.c
@@ -41,118 +41,131 @@

 struct gigadevice_spi_flash_params {
 	uint16_t	id;
-	/* Log2 of page size in power-of-two mode */
-	uint8_t		l2_page_size;
-	uint16_t	pages_per_sector;
-	uint16_t	sectors_per_block;
-	uint16_t	nr_blocks;
-	const char	*name;
+	uint8_t		dual_spi : 1;
+	uint8_t		_reserved_for_flags : 3;
+	uint8_t		l2_page_size_shift : 4;
+	uint8_t		pages_per_sector_shift : 4;
+	uint8_t		sectors_per_block_shift : 4;
+	uint8_t		nr_blocks_shift;
+	const char	name[10];
 };

 static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = {
 	{
-		.id			= 0x3114,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 16,
-		.name			= "GD25T80",
+		.id				= 0x3114,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 4,
+		.name				= "GD25T80",
 	},
 	{
-		.id			= 0x4014,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 16,
-		.name			= "GD25Q80(B)",
+		.id				= 0x4014,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 4,
+		.dual_spi			= 1,
+		.name				= "GD25Q80",
+	},					/* also GD25Q80B */
+	{
+		.id				= 0x4015,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 5,
+		.dual_spi			= 1,
+		.name				= "GD25Q16",
+	},					/* also GD25Q16B */
+	{
+		.id				= 0x4016,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 6,
+		.dual_spi			= 1,
+		.name				= "GD25Q32B",
+	},					/* also GD25Q32B */
+	{
+		.id				= 0x4017,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 7,
+		.dual_spi			= 1,
+		.name				= "GD25Q64",
+	},					/* also GD25Q64B, GD25B64C */
+	{
+		.id				= 0x4018,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 8,
+		.dual_spi			= 1,
+		.name				= "GD25Q128",
+	},					/* also GD25Q128B */
+	{
+		.id				= 0x4214,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 4,
+		.dual_spi			= 1,
+		.name				= "GD25VQ80C",
 	},
 	{
-		.id			= 0x4015,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 32,
-		.name			= "GD25Q16(B)",
+		.id				= 0x4215,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 5,
+		.dual_spi			= 1,
+		.name				= "GD25VQ16C",
 	},
 	{
-		.id			= 0x4016,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 64,
-		.name			= "GD25Q32(B)",
+		.id				= 0x6014,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 4,
+		.dual_spi			= 1,
+		.name				= "GD25LQ80",
 	},
 	{
-		.id			= 0x4017,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 128,
-		.name			= "GD25Q64(B)/GD25B64C",
+		.id				= 0x6015,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 5,
+		.dual_spi			= 1,
+		.name				= "GD25LQ16",
 	},
 	{
-		.id			= 0x4018,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 256,
-		.name			= "GD25Q128(B)",
+		.id				= 0x6016,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 6,
+		.dual_spi			= 1,
+		.name				= "GD25LQ32",
 	},
 	{
-		.id			= 0x4214,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 16,
-		.name			= "GD25VQ80C",
-	},
+		.id				= 0x6017,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 7,
+		.dual_spi			= 1,
+		.name				= "GD25LQ64C",
+	},					/* also GD25LB64C */
 	{
-		.id			= 0x4215,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 32,
-		.name			= "GD25VQ16C",
-	},
-	{
-		.id			= 0x6014,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 16,
-		.name			= "GD25LQ80",
-	},
-	{
-		.id			= 0x6015,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 32,
-		.name			= "GD25LQ16",
-	},
-	{
-		.id			= 0x6016,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 64,
-		.name			= "GD25LQ32",
-	},
-	{
-		.id			= 0x6017,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 128,
-		.name			= "GD25LQ64C/GD25LB64C",
-	},
-	{
-		.id			= 0x6018,
-		.l2_page_size		= 8,
-		.pages_per_sector	= 16,
-		.sectors_per_block	= 16,
-		.nr_blocks		= 256,
-		.name			= "GD25LQ128",
+		.id				= 0x6018,
+		.l2_page_size_shift		= 8,
+		.pages_per_sector_shift		= 4,
+		.sectors_per_block_shift	= 4,
+		.nr_blocks_shift		= 8,
+		.dual_spi			= 1,
+		.name				= "GD25LQ128",
 	},
 };

@@ -222,11 +235,6 @@ static const struct spi_flash_ops spi_flash_ops = {
 	.write = gigadevice_write,
 	.erase = spi_flash_cmd_erase,
 	.status = spi_flash_cmd_status,
-#if CONFIG(SPI_FLASH_NO_FAST_READ)
-	.read = spi_flash_cmd_read_slow,
-#else
-	.read = spi_flash_cmd_read_fast,
-#endif
 };

 int spi_flash_probe_gigadevice(const struct spi_slave *spi, u8 *idcode,
@@ -252,10 +260,12 @@ int spi_flash_probe_gigadevice(const struct spi_slave *spi, u8 *idcode,
 	flash->name = params->name;

 	/* Assuming power-of-two page size initially. */
-	flash->page_size = 1 << params->l2_page_size;
-	flash->sector_size = flash->page_size * params->pages_per_sector;
-	flash->size = flash->sector_size * params->sectors_per_block *
-			params->nr_blocks;
+	flash->page_size = 1 << params->l2_page_size_shift;
+	flash->sector_size = flash->page_size *
+			     (1 << params->pages_per_sector_shift);
+	flash->size = flash->sector_size *
+		      (1 << params->sectors_per_block_shift) *
+		      (1 << params->nr_blocks_shift);
 	flash->erase_cmd = CMD_GD25_SE;
 	flash->status_cmd = CMD_GD25_RDSR;

--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
@@ -268,11 +268,6 @@ static const struct spi_flash_ops spi_flash_ops = {
 	.write = macronix_write,
 	.erase = spi_flash_cmd_erase,
 	.status = spi_flash_cmd_status,
-#if CONFIG(SPI_FLASH_NO_FAST_READ)
-	.read = spi_flash_cmd_read_slow,
-#else
-	.read = spi_flash_cmd_read_fast,
-#endif
 };

 int spi_flash_probe_macronix(const struct spi_slave *spi, u8 *idcode,
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
@@ -282,7 +282,6 @@ static int spansion_write(const struct spi_flash *flash, u32 offset, size_t len,
 static const struct spi_flash_ops spi_flash_ops = {
 	.write = spansion_write,
 	.erase = spi_flash_cmd_erase,
-	.read = spi_flash_cmd_read_slow,
 	.status = spi_flash_cmd_status,
 };

--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -31,7 +31,7 @@ static void spi_flash_addr(u32 addr, u8 *cmd)
 static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout,
 			    size_t bytes_out, void *din, size_t bytes_in)
 {
-	int ret = 1;
+	int ret;
 	/*
 	 * SPI flash requires command-response kind of behavior. Thus, two
 	 * separate SPI vectors are required -- first to transmit dout and other
@@ -49,11 +49,39 @@ static int do_spi_flash_cmd(const struct spi_slave *spi, const void *dout,
 	if (!bytes_in)
 		count = 1;

-	if (spi_claim_bus(spi))
+	ret = spi_claim_bus(spi);
+	if (ret)
 		return ret;

-	if (spi_xfer_vector(spi, vectors, count) == 0)
-		ret = 0;
+	ret = spi_xfer_vector(spi, vectors, count);
+
+	spi_release_bus(spi);
+	return ret;
+}
+
+static int do_dual_read_cmd(const struct spi_slave *spi, const void *dout,
+			    size_t bytes_out, void *din, size_t bytes_in)
+{
+	int ret;
+
+	/*
+	 * spi_xfer_vector() will automatically fall back to .xfer() if
+	 * .xfer_vector() is unimplemented. So using vector API here is more
+	 * flexible, even though a controller that implements .xfer_vector()
+	 * and (the non-vector based) .xfer_dual() but not .xfer() would be
+	 * pretty odd.
+	 */
+	struct spi_op vector = { .dout = dout, .bytesout = bytes_out,
+				 .din = NULL, .bytesin = 0 };
+
+	ret = spi_claim_bus(spi);
+	if (ret)
+		return ret;
+
+	ret = spi_xfer_vector(spi, &vector, 1);
+
+	if (!ret)
+		ret = spi->ctrlr->xfer_dual(spi, NULL, 0, din, bytes_in);

 	spi_release_bus(spi);
 	return ret;
@@ -68,18 +96,6 @@ int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t le
 	return ret;
 }

-static int spi_flash_cmd_read(const struct spi_slave *spi, const u8 *cmd,
-			      size_t cmd_len, void *data, size_t data_len)
-{
-	int ret = do_spi_flash_cmd(spi, cmd, cmd_len, data, data_len);
-	if (ret) {
-		printk(BIOS_WARNING, "SF: Failed to send read command (%zu bytes): %d\n",
-				data_len, ret);
-	}
-
-	return ret;
-}
-
 /* TODO: This code is quite possibly broken and overflowing stacks. Fix ASAP! */
 #pragma GCC diagnostic push
 #if defined(__GNUC__) && !defined(__clang__)
@@ -103,34 +119,43 @@ int spi_flash_cmd_write(const struct spi_slave *spi, const u8 *cmd,
 }
 #pragma GCC diagnostic pop

-static int spi_flash_cmd_read_array(const struct spi_slave *spi, u8 *cmd,
-				    size_t cmd_len, u32 offset,
-				    size_t len, void *data)
-{
-	spi_flash_addr(offset, cmd);
-	return spi_flash_cmd_read(spi, cmd, cmd_len, data, len);
-}
-
 /* Perform the read operation honoring spi controller fifo size, reissuing
 * the read command until the full request completed. */
-static int spi_flash_cmd_read_array_wrapped(const struct spi_slave *spi,
-				u8 *cmd, size_t cmd_len, u32 offset,
-				size_t len, void *buf)
+static int spi_flash_read_chunked(const struct spi_flash *flash, u32 offset,
+				  size_t len, void *buf)
 {
-	int ret;
-	size_t xfer_len;
+	u8 cmd[5];
+	int ret, cmd_len;
+	int (*do_cmd)(const struct spi_slave *spi, const void *din,
+		      size_t in_bytes, void *out, size_t out_bytes);
+
+	if (CONFIG(SPI_FLASH_NO_FAST_READ)) {
+		cmd_len = 4;
+		cmd[0] = CMD_READ_ARRAY_SLOW;
+		do_cmd = do_spi_flash_cmd;
+	} else if (flash->flags.dual_spi && flash->spi.ctrlr->xfer_dual) {
+		cmd_len = 5;
+		cmd[0] = CMD_READ_FAST_DUAL_OUTPUT;
+		cmd[4] = 0;
+		do_cmd = do_dual_read_cmd;
+	} else {
+		cmd_len = 5;
+		cmd[0] = CMD_READ_ARRAY_FAST;
+		cmd[4] = 0;
+		do_cmd = do_spi_flash_cmd;
+	}
+
 	uint8_t *data = buf;
-
 	while (len) {
-		xfer_len = spi_crop_chunk(spi, cmd_len, len);
-
-		/* Perform the read. */
-		ret = spi_flash_cmd_read_array(spi, cmd, cmd_len,
-						offset, xfer_len, data);
-
-		if (ret)
+		size_t xfer_len = spi_crop_chunk(&flash->spi, cmd_len, len);
+		spi_flash_addr(offset, cmd);
+		ret = do_cmd(&flash->spi, cmd, cmd_len, data, xfer_len);
+		if (ret) {
+			printk(BIOS_WARNING,
+			       "SF: Failed to send read command %#.2x(%#x, %#zx): %d\n",
+			       cmd[0], offset, xfer_len, ret);
 			return ret;
-
+		}
 		offset += xfer_len;
 		data += xfer_len;
 		len -= xfer_len;
@@ -139,28 +164,6 @@ static int spi_flash_cmd_read_array_wrapped(const struct spi_slave *spi,
 	return 0;
 }

-int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset,
-			size_t len, void *data)
-{
-	u8 cmd[5];
-
-	cmd[0] = CMD_READ_ARRAY_FAST;
-	cmd[4] = 0x00;
-
-	return spi_flash_cmd_read_array_wrapped(&flash->spi, cmd, sizeof(cmd),
-					offset, len, data);
-}
-
-int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset,
-			size_t len, void *data)
-{
-	u8 cmd[4];
-
-	cmd[0] = CMD_READ_ARRAY_SLOW;
-	return spi_flash_cmd_read_array_wrapped(&flash->spi, cmd, sizeof(cmd),
-					offset, len, data);
-}
-
 int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout,
 			   u8 cmd, u8 poll_bit)
 {
@@ -174,7 +177,7 @@ int spi_flash_cmd_poll_bit(const struct spi_flash *flash, unsigned long timeout,
 	mono_time_add_msecs(&end, timeout);

 	do {
-		ret = spi_flash_cmd_read(spi, &cmd, 1, &status, 1);
+		ret = do_spi_flash_cmd(spi, &cmd, 1, &status, 1);
 		if (ret)
 			return -1;
 		if ((status & poll_bit) == 0)
@@ -377,8 +380,12 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
 		return -1;
 	}

-	printk(BIOS_INFO, "SF: Detected %s with sector size 0x%x, total 0x%x\n",
-			flash->name, flash->sector_size, flash->size);
+	const char *mode_string = "";
+	if (flash->flags.dual_spi && spi.ctrlr->xfer_dual)
+		mode_string = " (Dual SPI mode)";
+	printk(BIOS_INFO,
+	       "SF: Detected %s with sector size 0x%x, total 0x%x%s\n",
+		flash->name, flash->sector_size, flash->size, mode_string);
 	if (bus == CONFIG_BOOT_DEVICE_SPI_FLASH_BUS
 			&& flash->size != CONFIG_ROM_SIZE) {
 		printk(BIOS_ERR, "SF size 0x%x does not correspond to"
@@ -391,7 +398,10 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash)
 int spi_flash_read(const struct spi_flash *flash, u32 offset, size_t len,
 		void *buf)
 {
-	return flash->ops->read(flash, offset, len, buf);
+	if (flash->ops->read)
+		return flash->ops->read(flash, offset, len, buf);
+
+	return spi_flash_read_chunked(flash, offset, len, buf);
 }

 int spi_flash_write(const struct spi_flash *flash, u32 offset, size_t len,
--- a/src/drivers/spi/spi_flash_internal.h
+++ b/src/drivers/spi/spi_flash_internal.h
@@ -23,6 +23,8 @@
 #define CMD_READ_ARRAY_FAST		0x0b
 #define CMD_READ_ARRAY_LEGACY		0xe8

+#define CMD_READ_FAST_DUAL_OUTPUT	0x3b
+
 #define CMD_READ_STATUS			0x05
 #define CMD_WRITE_ENABLE		0x06

@@ -34,12 +36,6 @@
 /* Send a single-byte command to the device and read the response */
 int spi_flash_cmd(const struct spi_slave *spi, u8 cmd, void *response, size_t len);

-int spi_flash_cmd_read_fast(const struct spi_flash *flash, u32 offset,
-		size_t len, void *data);
-
-int spi_flash_cmd_read_slow(const struct spi_flash *flash, u32 offset,
-		size_t len, void *data);
-
 /*
 * Send a multi-byte command to the device followed by (optional)
 * data. Used for programming the flash array, etc.
--- a/src/drivers/spi/sst.c
+++ b/src/drivers/spi/sst.c
@@ -55,14 +55,12 @@ static const struct spi_flash_ops spi_flash_ops_write_ai = {
 	.write = sst_write_ai,
 	.erase = spi_flash_cmd_erase,
 	.status = spi_flash_cmd_status,
-	.read = spi_flash_cmd_read_fast,
 };

 static const struct spi_flash_ops spi_flash_ops_write_256 = {
 	.write = sst_write_256,
 	.erase = spi_flash_cmd_erase,
 	.status = spi_flash_cmd_status,
-	.read = spi_flash_cmd_read_fast,
 };

 #define SST_SECTOR_SIZE (4 * 1024)
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
@@ -351,7 +351,6 @@ out:
 static const struct spi_flash_ops spi_flash_ops = {
 	.write = stmicro_write,
 	.erase = spi_flash_cmd_erase,
-	.read = spi_flash_cmd_read_fast,
 };

 int spi_flash_probe_stmicro(const struct spi_slave *spi, u8 *idcode,
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
@@ -26,7 +26,9 @@

 struct winbond_spi_flash_params {
 	uint16_t id;
-	uint8_t l2_page_size_shift;
+	uint8_t dual_spi : 1;
+	uint8_t _reserved_for_flags : 3;
+	uint8_t l2_page_size_shift : 4;
 	uint8_t pages_per_sector_shift : 4;
 	uint8_t sectors_per_block_shift : 4;
 	uint8_t nr_blocks_shift;
@@ -123,6 +125,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 4,
 		.name				= "W25X80",
+		.dual_spi			= 1,
 	},
 	{
 		.id				= 0x3015,
@@ -131,6 +134,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 5,
 		.name				= "W25X16",
+		.dual_spi			= 1,
 	},
 	{
 		.id				= 0x3016,
@@ -139,6 +143,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 6,
 		.name				= "W25X32",
+		.dual_spi			= 1,
 	},
 	{
 		.id				= 0x3017,
@@ -147,6 +152,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 7,
 		.name				= "W25X64",
+		.dual_spi			= 1,
 	},
 	{
 		.id				= 0x4014,
@@ -155,6 +161,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 4,
 		.name				= "W25Q80_V",
+		.dual_spi			= 1,
 	},
 	{
 		.id				= 0x4015,
@@ -163,6 +170,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 5,
 		.name				= "W25Q16_V",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -173,6 +181,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 5,
 		.name				= "W25Q16DW",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -183,6 +192,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 6,
 		.name				= "W25Q32_V",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -193,6 +203,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 6,
 		.name				= "W25Q32DW",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 3,
 	},
@@ -203,6 +214,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 7,
 		.name				= "W25Q64_V",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 17,
 		.bp_bits			= 3,
 	},
@@ -213,6 +225,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 7,
 		.name				= "W25Q64DW",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 17,
 		.bp_bits			= 3,
 	},
@@ -223,6 +236,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 8,
 		.name				= "W25Q128_V",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -233,6 +247,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 8,
 		.name				= "W25Q128FW",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -243,6 +258,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 8,
 		.name				= "W25Q128J",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 18,
 		.bp_bits			= 3,
 	},
@@ -253,6 +269,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 9,
 		.name				= "W25Q256_V",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 4,
 	},
@@ -263,6 +280,7 @@ static const struct winbond_spi_flash_params winbond_spi_flash_table[] = {
 		.sectors_per_block_shift	= 4,
 		.nr_blocks_shift		= 9,
 		.name				= "W25Q256J",
+		.dual_spi			= 1,
 		.protection_granularity_shift	= 16,
 		.bp_bits			= 4,
 	},
@@ -646,11 +664,6 @@ static const struct spi_flash_ops spi_flash_ops = {
 	.write = winbond_write,
 	.erase = spi_flash_cmd_erase,
 	.status = spi_flash_cmd_status,
-#if CONFIG(SPI_FLASH_NO_FAST_READ)
-	.read = spi_flash_cmd_read_slow,
-#else
-	.read = spi_flash_cmd_read_fast,
-#endif
 	.get_write_protection = winbond_get_write_protection,
 	.set_write_protection = winbond_set_write_protection,
 };
@@ -686,6 +699,8 @@ int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode,
 	flash->erase_cmd = CMD_W25_SE;
 	flash->status_cmd = CMD_W25_RDSR;

+	flash->flags.dual_spi = params->dual_spi;
+
 	flash->ops = &spi_flash_ops;
 	flash->driver_private = params;

--- a/src/ec/google/wilco/acpi/ec.asl
+++ b/src/ec/google/wilco/acpi/ec.asl
@@ -57,6 +57,9 @@ Device (EC0)
 		If (\DPTE == One) {
 			W (DWST, Arg1)
 		}
+
+		/* Initialize UCSI */
+		^UCSI.INIT ()
 	}

 	/*
@@ -165,6 +168,7 @@ Device (EC0)
 	#include "lid.asl"
 	#include "platform.asl"
 	#include "vbtn.asl"
+	#include "ucsi.asl"
 #ifdef EC_ENABLE_DPTF
 	#include "dptf.asl"
 #endif
--- a/src/ec/google/wilco/acpi/ec_ram.asl
+++ b/src/ec/google/wilco/acpi/ec_ram.asl
@@ -143,3 +143,54 @@ Name (DWHY, Package () { 0x37, 0xff, WR })	/* DPTF: Write Hysteresis */
 Name (DWTQ, Package () { 0x38, 0xff, WR })	/* DPTF: Write Trip Query */
 Name (CSOS, Package () { 0xb8, 0xff, WR })	/* OS support for S0ix */
 Name (CSEX, Package () { 0xb9, 0xff, WR })	/* OS enter(1)/exit(0) S0ix */
+
+/*
+ * EC UCSI
+ */
+Name (UVR0, Package () { 0x80, 0xff, RD })	/* UCSI Version */
+Name (UVR1, Package () { 0x81, 0xff, RD })	/* UCSI Version */
+Name (UCI0, Package () { 0x84, 0xff, RD })	/* UCSI Change Indicator */
+Name (UCI1, Package () { 0x85, 0xff, RD })	/* UCSI Change Indicator */
+Name (UCI2, Package () { 0x86, 0xff, RD })	/* UCSI Change Indicator */
+Name (UCI3, Package () { 0x87, 0xff, RD })	/* UCSI Change Indicator */
+Name (UCL0, Package () { 0x88, 0xff, WR })	/* UCSI Control */
+Name (UCL1, Package () { 0x89, 0xff, WR })	/* UCSI Control */
+Name (UCL2, Package () { 0x8a, 0xff, WR })	/* UCSI Control */
+Name (UCL3, Package () { 0x8b, 0xff, WR })	/* UCSI Control */
+Name (UCL4, Package () { 0x8c, 0xff, WR })	/* UCSI Control */
+Name (UCL5, Package () { 0x8d, 0xff, WR })	/* UCSI Control */
+Name (UCL6, Package () { 0x8e, 0xff, WR })	/* UCSI Control */
+Name (UCL7, Package () { 0x8f, 0xff, WR })	/* UCSI Control */
+Name (UMI0, Package () { 0x90, 0xff, RD })	/* UCSI Message In */
+Name (UMI1, Package () { 0x91, 0xff, RD })	/* UCSI Message In */
+Name (UMI2, Package () { 0x92, 0xff, RD })	/* UCSI Message In */
+Name (UMI3, Package () { 0x93, 0xff, RD })	/* UCSI Message In */
+Name (UMI4, Package () { 0x94, 0xff, RD })	/* UCSI Message In */
+Name (UMI5, Package () { 0x95, 0xff, RD })	/* UCSI Message In */
+Name (UMI6, Package () { 0x96, 0xff, RD })	/* UCSI Message In */
+Name (UMI7, Package () { 0x97, 0xff, RD })	/* UCSI Message In */
+Name (UMI8, Package () { 0x98, 0xff, RD })	/* UCSI Message In */
+Name (UMI9, Package () { 0x99, 0xff, RD })	/* UCSI Message In */
+Name (UMIA, Package () { 0x9a, 0xff, RD })	/* UCSI Message In */
+Name (UMIB, Package () { 0x9b, 0xff, RD })	/* UCSI Message In */
+Name (UMIC, Package () { 0x9c, 0xff, RD })	/* UCSI Message In */
+Name (UMID, Package () { 0x9d, 0xff, RD })	/* UCSI Message In */
+Name (UMIE, Package () { 0x9e, 0xff, RD })	/* UCSI Message In */
+Name (UMIF, Package () { 0x9f, 0xff, RD })	/* UCSI Message In */
+Name (UMO0, Package () { 0xa0, 0xff, WR })	/* UCSI Message Out */
+Name (UMO1, Package () { 0xa1, 0xff, WR })	/* UCSI Message Out */
+Name (UMO2, Package () { 0xa2, 0xff, WR })	/* UCSI Message Out */
+Name (UMO3, Package () { 0xa3, 0xff, WR })	/* UCSI Message Out */
+Name (UMO4, Package () { 0xa4, 0xff, WR })	/* UCSI Message Out */
+Name (UMO5, Package () { 0xa5, 0xff, WR })	/* UCSI Message Out */
+Name (UMO6, Package () { 0xa6, 0xff, WR })	/* UCSI Message Out */
+Name (UMO7, Package () { 0xa7, 0xff, WR })	/* UCSI Message Out */
+Name (UMO8, Package () { 0xa8, 0xff, WR })	/* UCSI Message Out */
+Name (UMO9, Package () { 0xa9, 0xff, WR })	/* UCSI Message Out */
+Name (UMOA, Package () { 0xaa, 0xff, WR })	/* UCSI Message Out */
+Name (UMOB, Package () { 0xab, 0xff, WR })	/* UCSI Message Out */
+Name (UMOC, Package () { 0xac, 0xff, WR })	/* UCSI Message Out */
+Name (UMOD, Package () { 0xad, 0xff, WR })	/* UCSI Message Out */
+Name (UMOE, Package () { 0xae, 0xff, WR })	/* UCSI Message Out */
+Name (UMOF, Package () { 0xaf, 0xff, WR })	/* UCSI Message Out */
+Name (UCTL, Package () { 0xb0, 0xff, WR })	/* UCSI Control Register */
--- a/src/ec/google/wilco/acpi/event.asl
+++ b/src/ec/google/wilco/acpi/event.asl
@@ -145,3 +145,10 @@ Method (_Q66, 0, Serialized)
 		ECQ4 (Local0)
 	}
 }
+
+/* UCSI SCI uses a unique event code */
+Method (_Q79, 0, Serialized)
+{
+	Printf ("EC _Q79 UCSI Event")
+	Notify (^UCSI, 0x80)
+}
--- a/src/ec/google/wilco/acpi/ucsi.asl
+++ b/src/ec/google/wilco/acpi/ucsi.asl
@@ -0,0 +1,157 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (UCSI)
+{
+	Name (_HID, "GOOG000E")
+	Name (_CID, EisaId ("PNP0CA0"))
+	Name (_DDN, "Wilco EC UCSI")
+	Name (_UID, One)
+	Name (_ADR, Zero)
+	Name (_STA, 0xf)
+
+	/* Value written to EC control register to start UCSI command */
+	Name (UCMD, 0xE0)
+
+	/* Shared memory fields are defined in the SSDT */
+	External (VER0, FieldUnitObj)
+	External (VER1, FieldUnitObj)
+	External (CCI0, FieldUnitObj)
+	External (CCI1, FieldUnitObj)
+	External (CCI2, FieldUnitObj)
+	External (CCI3, FieldUnitObj)
+	External (CTL0, FieldUnitObj)
+	External (CTL1, FieldUnitObj)
+	External (CTL2, FieldUnitObj)
+	External (CTL3, FieldUnitObj)
+	External (CTL4, FieldUnitObj)
+	External (CTL5, FieldUnitObj)
+	External (CTL6, FieldUnitObj)
+	External (CTL7, FieldUnitObj)
+	External (MGI0, FieldUnitObj)
+	External (MGI1, FieldUnitObj)
+	External (MGI2, FieldUnitObj)
+	External (MGI3, FieldUnitObj)
+	External (MGI4, FieldUnitObj)
+	External (MGI5, FieldUnitObj)
+	External (MGI6, FieldUnitObj)
+	External (MGI7, FieldUnitObj)
+	External (MGI8, FieldUnitObj)
+	External (MGI9, FieldUnitObj)
+	External (MGIA, FieldUnitObj)
+	External (MGIB, FieldUnitObj)
+	External (MGIC, FieldUnitObj)
+	External (MGID, FieldUnitObj)
+	External (MGIE, FieldUnitObj)
+	External (MGIF, FieldUnitObj)
+	External (MGO0, FieldUnitObj)
+	External (MGO1, FieldUnitObj)
+	External (MGO2, FieldUnitObj)
+	External (MGO3, FieldUnitObj)
+	External (MGO4, FieldUnitObj)
+	External (MGO5, FieldUnitObj)
+	External (MGO6, FieldUnitObj)
+	External (MGO7, FieldUnitObj)
+	External (MGO8, FieldUnitObj)
+	External (MGO9, FieldUnitObj)
+	External (MGOA, FieldUnitObj)
+	External (MGOB, FieldUnitObj)
+	External (MGOC, FieldUnitObj)
+	External (MGOD, FieldUnitObj)
+	External (MGOE, FieldUnitObj)
+	External (MGOF, FieldUnitObj)
+
+	Method (INIT)
+	{
+		/* Read UCSI version from EC into shared memory */
+		^VER0 = R (^^UVR0)
+		^VER1 = R (^^UVR1)
+	}
+
+	Method (_DSM, 4, Serialized)
+	{
+		If (Arg0 != ToUUID ("6f8398c2-7ca4-11e4-ad36-631042b5008f")) {
+			Return (Buffer (One) { Zero })
+		}
+
+		Switch (ToInteger (Arg2))
+		{
+			Case (Zero)
+			{
+				Return (Buffer (One) { 0x07 })
+			}
+			Case (One)
+			{
+				/* Write Message Out */
+				W (^^UMO0, ^MGO0)
+				W (^^UMO1, ^MGO1)
+				W (^^UMO2, ^MGO2)
+				W (^^UMO3, ^MGO3)
+				W (^^UMO4, ^MGO4)
+				W (^^UMO5, ^MGO5)
+				W (^^UMO6, ^MGO6)
+				W (^^UMO7, ^MGO7)
+				W (^^UMO8, ^MGO8)
+				W (^^UMO9, ^MGO9)
+				W (^^UMOA, ^MGOA)
+				W (^^UMOB, ^MGOB)
+				W (^^UMOC, ^MGOC)
+				W (^^UMOD, ^MGOD)
+				W (^^UMOE, ^MGOE)
+				W (^^UMOF, ^MGOF)
+
+				/* Write Control */
+				W (^^UCL0, ^CTL0)
+				W (^^UCL1, ^CTL1)
+				W (^^UCL2, ^CTL2)
+				W (^^UCL3, ^CTL3)
+				W (^^UCL4, ^CTL4)
+				W (^^UCL5, ^CTL5)
+				W (^^UCL6, ^CTL6)
+				W (^^UCL7, ^CTL7)
+
+				/* Start EC Command */
+				W (^^UCTL, ^UCMD)
+			}
+			Case (2)
+			{
+				/* Read Message In */
+				^MGI0 = R (^^UMI0)
+				^MGI1 = R (^^UMI1)
+				^MGI2 = R (^^UMI2)
+				^MGI3 = R (^^UMI3)
+				^MGI4 = R (^^UMI4)
+				^MGI5 = R (^^UMI5)
+				^MGI6 = R (^^UMI6)
+				^MGI7 = R (^^UMI7)
+				^MGI8 = R (^^UMI8)
+				^MGI9 = R (^^UMI9)
+				^MGIA = R (^^UMIA)
+				^MGIB = R (^^UMIB)
+				^MGIC = R (^^UMIC)
+				^MGID = R (^^UMID)
+				^MGIE = R (^^UMIE)
+				^MGIF = R (^^UMIF)
+
+				/* Read Status */
+				^CCI0 = R (^^UCI0)
+				^CCI1 = R (^^UCI1)
+				^CCI2 = R (^^UCI2)
+				^CCI3 = R (^^UCI3)
+			}
+		}
+		Return (Buffer (One) { Zero })
+	}
+}
--- a/src/ec/google/wilco/chip.c
+++ b/src/ec/google/wilco/chip.c
@@ -14,7 +14,10 @@
 */

 #include <arch/acpi.h>
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
 #include <bootstate.h>
+#include <cbmem.h>
 #include <device/pnp.h>
 #include <ec/acpi/ec.h>
 #include <pc80/keyboard.h>
@@ -25,6 +28,64 @@
 #include "ec.h"
 #include "chip.h"

+/*
+ * The UCSI fields are defined in the UCSI specification at
+ * https://www.intel.com/content/www/us/en/io/universal-serial-bus/usb-type-c-ucsi-spec.html
+ * https://www.intel.com/content/www/us/en/io/universal-serial-bus/bios-implementation-of-ucsi.html
+ */
+
+static struct fieldlist ucsi_region_fields[] = {
+	FIELDLIST_NAMESTR("VER0", 8),
+	FIELDLIST_NAMESTR("VER1", 8),
+	FIELDLIST_NAMESTR("RSV0", 8),
+	FIELDLIST_NAMESTR("RSV1", 8),
+	FIELDLIST_NAMESTR("CCI0", 8),
+	FIELDLIST_NAMESTR("CCI1", 8),
+	FIELDLIST_NAMESTR("CCI2", 8),
+	FIELDLIST_NAMESTR("CCI3", 8),
+	FIELDLIST_NAMESTR("CTL0", 8),
+	FIELDLIST_NAMESTR("CTL1", 8),
+	FIELDLIST_NAMESTR("CTL2", 8),
+	FIELDLIST_NAMESTR("CTL3", 8),
+	FIELDLIST_NAMESTR("CTL4", 8),
+	FIELDLIST_NAMESTR("CTL5", 8),
+	FIELDLIST_NAMESTR("CTL6", 8),
+	FIELDLIST_NAMESTR("CTL7", 8),
+	FIELDLIST_NAMESTR("MGI0", 8),
+	FIELDLIST_NAMESTR("MGI1", 8),
+	FIELDLIST_NAMESTR("MGI2", 8),
+	FIELDLIST_NAMESTR("MGI3", 8),
+	FIELDLIST_NAMESTR("MGI4", 8),
+	FIELDLIST_NAMESTR("MGI5", 8),
+	FIELDLIST_NAMESTR("MGI6", 8),
+	FIELDLIST_NAMESTR("MGI7", 8),
+	FIELDLIST_NAMESTR("MGI8", 8),
+	FIELDLIST_NAMESTR("MGI9", 8),
+	FIELDLIST_NAMESTR("MGIA", 8),
+	FIELDLIST_NAMESTR("MGIB", 8),
+	FIELDLIST_NAMESTR("MGIC", 8),
+	FIELDLIST_NAMESTR("MGID", 8),
+	FIELDLIST_NAMESTR("MGIE", 8),
+	FIELDLIST_NAMESTR("MGIF", 8),
+	FIELDLIST_NAMESTR("MGO0", 8),
+	FIELDLIST_NAMESTR("MGO1", 8),
+	FIELDLIST_NAMESTR("MGO2", 8),
+	FIELDLIST_NAMESTR("MGO3", 8),
+	FIELDLIST_NAMESTR("MGO4", 8),
+	FIELDLIST_NAMESTR("MGO5", 8),
+	FIELDLIST_NAMESTR("MGO6", 8),
+	FIELDLIST_NAMESTR("MGO7", 8),
+	FIELDLIST_NAMESTR("MGO8", 8),
+	FIELDLIST_NAMESTR("MGO9", 8),
+	FIELDLIST_NAMESTR("MGOA", 8),
+	FIELDLIST_NAMESTR("MGOB", 8),
+	FIELDLIST_NAMESTR("MGOC", 8),
+	FIELDLIST_NAMESTR("MGOD", 8),
+	FIELDLIST_NAMESTR("MGOE", 8),
+	FIELDLIST_NAMESTR("MGOF", 8),
+};
+static const size_t ucsi_region_len = ARRAY_SIZE(ucsi_region_fields);
+
 static void wilco_ec_post_complete(void *unused)
 {
 	wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_POST_COMPLETE);
@@ -111,11 +172,47 @@ static void wilco_ec_read_resources(struct device *dev)
 	wilco_ec_resource(dev, 2, CONFIG_EC_BASE_PACKET, 16);
 }

+static void wilco_ec_fill_ssdt_generator(struct device *dev)
+{
+	struct opregion opreg;
+	void *region_ptr;
+
+	if (!dev->enabled)
+		return;
+
+	region_ptr = cbmem_add(CBMEM_ID_ACPI_UCSI, ucsi_region_len);
+	if (!region_ptr)
+		return;
+	memset(region_ptr, 0, ucsi_region_len);
+
+	opreg.name = "UCSM";
+	opreg.regionspace = SYSTEMMEMORY;
+	opreg.regionoffset = (uintptr_t)region_ptr;
+	opreg.regionlen = ucsi_region_len;
+
+	acpigen_write_scope(acpi_device_path_join(dev, "UCSI"));
+	acpigen_write_name("_CRS");
+	acpigen_write_resourcetemplate_header();
+	acpigen_write_mem32fixed(1, (uintptr_t)region_ptr, ucsi_region_len);
+	acpigen_write_resourcetemplate_footer();
+	acpigen_write_opregion(&opreg);
+	acpigen_write_field(opreg.name, ucsi_region_fields, ucsi_region_len,
+			    FIELD_ANYACC | FIELD_LOCK | FIELD_PRESERVE);
+	acpigen_pop_len(); /* Scope */
+}
+
+static const char *wilco_ec_acpi_name(const struct device *dev)
+{
+	return "EC0";
+}
+
 static struct device_operations ops = {
-	.init			= wilco_ec_init,
-	.read_resources		= wilco_ec_read_resources,
-	.enable_resources	= DEVICE_NOOP,
-	.set_resources		= DEVICE_NOOP,
+	.init				= wilco_ec_init,
+	.read_resources			= wilco_ec_read_resources,
+	.enable_resources		= DEVICE_NOOP,
+	.set_resources			= DEVICE_NOOP,
+	.acpi_fill_ssdt_generator	= wilco_ec_fill_ssdt_generator,
+	.acpi_name			= wilco_ec_acpi_name,
 };

 static struct pnp_info info[] = {
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -42,8 +42,9 @@ void post_log_clear(void);
 #endif
 /* this function is weak and can be overridden by a mainboard function. */
 void mainboard_post(u8 value);
-void __noreturn die(const char *msg);
-void __noreturn die_with_post_code(uint8_t value, const char *msg);
+void __noreturn die(const char *fmt, ...);
+#define die_with_post_code(value, fmt, ...) \
+	do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0)

 /*
 * This function is weak and can be overridden to provide additional
@@ -62,8 +63,8 @@ asmlinkage void console_init(void);
 int console_log_level(int msg_level);
 void do_putchar(unsigned char byte);

-#define printk(LEVEL, fmt, args...) \
-	do { do_printk(LEVEL, fmt, ##args); } while (0)
+#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args)
+#define vprintk(LEVEL, fmt, args) do_vprintk(LEVEL, fmt, args)

 enum { CONSOLE_LOG_NONE = 0, CONSOLE_LOG_FAST, CONSOLE_LOG_ALL };

@@ -83,14 +84,15 @@ static inline int get_console_loglevel(void)
 static inline void console_init(void) {}
 static inline int console_log_level(int msg_level) { return 0; }
 static inline void printk(int LEVEL, const char *fmt, ...) {}
+static inline void vprintk(int LEVEL, const char *fmt, va_list args) {}
 static inline void do_putchar(unsigned char byte) {}
 #endif

-int vprintk(int msg_level, const char *fmt, va_list args);
-
 int do_printk(int msg_level, const char *fmt, ...)
 	__attribute__((format(printf, 2, 3)));

+int do_vprintk(int msg_level, const char *fmt, va_list args);
+
 #endif /* !__ROMCC__ */

 #endif /* CONSOLE_CONSOLE_H_ */
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2696,8 +2696,8 @@
 #define PCI_DEVICE_ID_INTEL_SPT_H_Q170			0xa146
 #define PCI_DEVICE_ID_INTEL_SPT_H_Q150			0xa147
 #define PCI_DEVICE_ID_INTEL_SPT_H_B150			0xa148
-#define PCI_DEVICE_ID_INTEL_KBP_H_C236			0xa149
-#define PCI_DEVICE_ID_INTEL_SPT_H_C236			0xa150
+#define PCI_DEVICE_ID_INTEL_SPT_H_C236			0xa149
+#define PCI_DEVICE_ID_INTEL_SPT_H_CM236			0xa150
 #define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM		0xa14e
 #define PCI_DEVICE_ID_INTEL_SPT_H_H110			0xa143
 #define PCI_DEVICE_ID_INTEL_SPT_H_QM170			0xa14d
@@ -2723,13 +2723,13 @@
 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC	0x9d83
 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370	0xa306
 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370	0xa30c
-#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC	0x3480
-#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0	0x3481
-#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC	0x3482
-#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC		0x3483
-#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC		0x3484
-#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC	0x3487
-#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC	0x3486
+#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI	0x3480
+#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0	0x3481
+#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI	0x3482
+#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI	0x3483
+#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI	0x3484
+#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI	0x3487
+#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI	0x3486
 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC	0x0281
 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC	0x0283
 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC	0x0284
@@ -3076,7 +3076,10 @@
 #define PCI_DEVICE_ID_INTEL_SKL_ID_U	0x1904
 #define PCI_DEVICE_ID_INTEL_SKL_ID_Y	0x190c
 #define PCI_DEVICE_ID_INTEL_SKL_ID_ULX	0x1924
+#define PCI_DEVICE_ID_INTEL_SKL_ID_H_2  0x1900
 #define PCI_DEVICE_ID_INTEL_SKL_ID_H	0x1910
+#define PCI_DEVICE_ID_INTEL_SKL_ID_S_2  0x190f
+#define PCI_DEVICE_ID_INTEL_SKL_ID_S_4  0x191f
 #define PCI_DEVICE_ID_INTEL_KBL_ID_S	0x590f
 #define PCI_DEVICE_ID_INTEL_SKL_ID_H_EM	0x1918
 #define PCI_DEVICE_ID_INTEL_SKL_ID_DT	0x191f
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -86,6 +86,10 @@ struct dimm_info {
 	 * See the smbios.h smbios_memory_bus_width enum.
 	 */
 	uint8_t bus_width;
+	/*
+	 * Voltage Level
+	 */
+	uint16_t vdd_voltage;
 } __packed;

 struct memory_info {
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -257,9 +257,14 @@

 #endif

+#if CONFIG(RAMPAYLOAD)
+/* ENV_PAYLOAD_LOADER is set to ENV_POSTCAR when CONFIG_RAMPAYLOAD is enabled */
+#define ENV_PAYLOAD_LOADER ENV_POSTCAR
+#else
 /* ENV_PAYLOAD_LOADER is set when you are in a stage that loads the payload.
 * For now, that is the ramstage. */
 #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE
+#endif

 /**
 * For pre-DRAM stages and post-CAR always build with simple device model, ie.
--- a/src/include/spi-generic.h
+++ b/src/include/spi-generic.h
@@ -125,6 +125,7 @@ enum {
 * setup:		Setup given SPI device bus.
 * xfer:		Perform one SPI transfer operation.
 * xfer_vector:	Vector of SPI transfer operations.
+ * xfer_dual:		(optional) Perform one SPI transfer in Dual SPI mode.
 * max_xfer_size:	Maximum transfer size supported by the controller
 *			(0 = invalid,
 *			 SPI_CTRLR_DEFAULT_MAX_XFER_SIZE = unlimited)
@@ -145,6 +146,8 @@ struct spi_ctrlr {
 		    size_t bytesout, void *din, size_t bytesin);
 	int (*xfer_vector)(const struct spi_slave *slave,
 			struct spi_op vectors[], size_t count);
+	int (*xfer_dual)(const struct spi_slave *slave, const void *dout,
+			 size_t bytesout, void *din, size_t bytesin);
 	uint32_t max_xfer_size;
 	uint32_t flags;
 	int (*flash_probe)(const struct spi_slave *slave,
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -90,6 +90,13 @@ struct spi_flash_ops {
 struct spi_flash {
 	struct spi_slave spi;
 	u8 vendor;
+	union {
+		u8 raw;
+		struct {
+			u8 dual_spi	: 1;
+			u8 _reserved	: 7;
+		};
+	} flags;
 	u16 model;
 	const char *name;
 	u32 size;
--- a/src/include/stage_cache.h
+++ b/src/include/stage_cache.h
@@ -32,14 +32,21 @@ enum {
 	STAGE_S3_DATA,
 };

+#if CONFIG(CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) \
+		|| CONFIG(RELOCATABLE_RAMSTAGE)
 /* Cache the loaded stage provided according to the parameters. */
 void stage_cache_add(int stage_id, const struct prog *stage);
+/* Load the cached stage at given location returning the stage entry point. */
+void stage_cache_load_stage(int stage_id, struct prog *stage);
+#else /* CONFIG_NO_STAGE_CACHE */
+static inline void stage_cache_add(int stage_id, const struct prog *stage) {}
+static inline void stage_cache_load_stage(int stage_id, struct prog *stage) {}
+#endif
+
 /* Cache non-specific data or code. */
 void stage_cache_add_raw(int stage_id, const void *base, const size_t size);
 /* Get a pointer to cached raw data and its size. */
 void stage_cache_get_raw(int stage_id, void **base, size_t *size);
-/* Load the cached stage at given location returning the stage entry point. */
-void stage_cache_load_stage(int stage_id, struct prog *stage);
 /* Fill in parameters for the external stage cache, if utilized. */
 void stage_cache_external_region(void **base, size_t *size);

--- a/src/lib/prog_loaders.c
+++ b/src/lib/prog_loaders.c
@@ -74,11 +74,6 @@ fail:
 	halt();
 }

-void __weak stage_cache_add(int stage_id,
-						const struct prog *stage) {}
-void __weak stage_cache_load_stage(int stage_id,
-							struct prog *stage) {}
-
 static void ramstage_cache_invalid(void)
 {
 	printk(BIOS_ERR, "ramstage cache invalid.\n");
@@ -155,8 +150,7 @@ void run_ramstage(void)
 	} else if (load_nonrelocatable_ramstage(&ramstage))
 		goto fail;

-	if (!CONFIG(NO_STAGE_CACHE))
-		stage_cache_add(STAGE_RAMSTAGE, &ramstage);
+	stage_cache_add(STAGE_RAMSTAGE, &ramstage);

 	timestamp_add_now(TS_END_COPYRAM);

--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -24,6 +24,8 @@ config BOARD_ROMSIZE_KB_2048
 	bool
 config BOARD_ROMSIZE_KB_4096
 	bool
+config BOARD_ROMSIZE_KB_6144
+	bool
 config BOARD_ROMSIZE_KB_8192
 	bool
 config BOARD_ROMSIZE_KB_10240
@@ -47,6 +49,7 @@ choice
 	default COREBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
 	default COREBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
 	default COREBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
+	default COREBOOT_ROMSIZE_KB_6144 if BOARD_ROMSIZE_KB_6144
 	default COREBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
 	default COREBOOT_ROMSIZE_KB_10240 if BOARD_ROMSIZE_KB_10240
 	default COREBOOT_ROMSIZE_KB_12288 if BOARD_ROMSIZE_KB_12288
@@ -94,6 +97,11 @@ config COREBOOT_ROMSIZE_KB_4096
 	help
 	  Choose this option if you have a 4096 KB (4 MB) ROM chip.

+config COREBOOT_ROMSIZE_KB_6144
+	bool "6144 KB (6 MB)"
+	help
+	  Choose this option if you have a 6144 KB (6 MB) ROM chip.
+
 config COREBOOT_ROMSIZE_KB_8192
 	bool "8192 KB (8 MB)"
 	help
@@ -136,6 +144,7 @@ config COREBOOT_ROMSIZE_KB
 	default 1024 if COREBOOT_ROMSIZE_KB_1024
 	default 2048 if COREBOOT_ROMSIZE_KB_2048
 	default 4096 if COREBOOT_ROMSIZE_KB_4096
+	default 6144 if COREBOOT_ROMSIZE_KB_6144
 	default 8192 if COREBOOT_ROMSIZE_KB_8192
 	default 10240 if COREBOOT_ROMSIZE_KB_10240
 	default 12288 if COREBOOT_ROMSIZE_KB_12288
@@ -153,6 +162,7 @@ config ROM_SIZE
 	default 0x100000 if COREBOOT_ROMSIZE_KB_1024
 	default 0x200000 if COREBOOT_ROMSIZE_KB_2048
 	default 0x400000 if COREBOOT_ROMSIZE_KB_4096
+	default 0x600000 if COREBOOT_ROMSIZE_KB_6144
 	default 0x800000 if COREBOOT_ROMSIZE_KB_8192
 	default 0xa00000 if COREBOOT_ROMSIZE_KB_10240
 	default 0xc00000 if COREBOOT_ROMSIZE_KB_12288
--- a/src/mainboard/amd/gardenia/bootblock/bootblock.c
+++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c
@@ -23,5 +23,5 @@ void bootblock_mainboard_early_init(void)
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
 	gpios = early_gpio_table(&num_gpios);
-	sb_program_gpios(gpios, num_gpios);
+	program_gpios(gpios, num_gpios);
 }
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -82,7 +82,7 @@ static void mainboard_init(void *chip_info)
 	size_t num_gpios;
 	const struct soc_amd_gpio *gpios;
 	gpios = gpio_table(&num_gpios);
-	sb_program_gpios(gpios, num_gpios);
+	program_gpios(gpios, num_gpios);
 }

 /*************************************************
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -64,7 +64,6 @@ chip northbridge/intel/i945
 			register "gpi1_routing" = "2"
 			register "gpi7_routing" = "2"

-			register "sata_ahci" = "0x1"
 			register "sata_ports_implemented" = "0x04"

 			register "gpe0_en" = "0x11000006"
--- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb
@@ -51,7 +51,6 @@ chip northbridge/intel/x4x		# Northbridge
 			register "gpi13_routing" = "2"

 			register "ide_enable_primary" = "0x1"
-			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
 			register "sata_ports_implemented" = "0x3"
 			register "gpe0_en" = "0x440"

--- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb
@@ -46,7 +46,6 @@ chip northbridge/intel/x4x		# Northbridge
 			register "pirqh_routing" = "0x0b"

 			register "ide_enable_primary" = "0x1"
-			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
 			register "sata_ports_implemented" = "0x3"
 			register "gpe0_en" = "0x440"

--- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb
@@ -44,7 +44,6 @@ chip northbridge/intel/x4x		# Northbridge
 			register "pirqh_routing" = "0x0b"

 			register "ide_enable_primary" = "0x1"
-			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
 			register "sata_ports_implemented" = "0x3"
 			register "gpe0_en" = "0x440"

--- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
+++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb
@@ -46,7 +46,6 @@ chip northbridge/intel/x4x		# Northbridge
 			register "pirqh_routing" = "0x0b"

 			register "ide_enable_primary" = "0x1"
-			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
 			register "gpe0_en" = "0x440"

 			device pci 1b.0 on		# Audio
--- a/src/mainboard/asus/p5gc-mx/devicetree.cb
+++ b/src/mainboard/asus/p5gc-mx/devicetree.cb
@@ -53,7 +53,6 @@ chip northbridge/intel/i945
 			register "ide_legacy_combined" = "0x0"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
-			register "sata_ahci" = "0x0"

 			register "p_cnt_throttling_supported" = "0"

--- a/src/mainboard/asus/p5qpl-am/devicetree.cb
+++ b/src/mainboard/asus/p5qpl-am/devicetree.cb
@@ -43,7 +43,6 @@ chip northbridge/intel/x4x		# Northbridge
 			#  2 SCI (if corresponding GPIO_EN bit is also set)

 			register "ide_enable_primary" = "0x1"
-			register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant
 			register "gpe0_en" = "0x04000440"

 			device pci 1b.0 on  end		# Audio
--- a/src/mainboard/foxconn/d41s/devicetree.cb
+++ b/src/mainboard/foxconn/d41s/devicetree.cb
@@ -40,7 +40,6 @@ chip northbridge/intel/pineview		# Northbridge
      register "pirqf_routing" = "0x0b"
      register "pirqg_routing" = "0x0b"
      register "pirqh_routing" = "0x0b"
-      register "sata_ahci" = "0x1"
      register "sata_ports_implemented" = "0x3"
      register "gpe0_en" = "0x441"

--- a/src/mainboard/foxconn/g41s-k/devicetree.cb
+++ b/src/mainboard/foxconn/g41s-k/devicetree.cb
@@ -47,7 +47,6 @@ chip northbridge/intel/x4x		# Northbridge

 			register "ide_enable_primary" = "0x0"
 			register "ide_enable_secondary" = "0x0"
-			register "sata_ahci" = "0x0"	# AHCI does not work
 			register "sata_ports_implemented" = "0x3"

 			device pci 1b.0 on end		# Audio
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -57,7 +57,6 @@ chip northbridge/intel/i945
                        register "ide_legacy_combined" = "0x1"
                        register "ide_enable_primary" = "0x1"
                        register "ide_enable_secondary" = "0x0"
-                        register "sata_ahci" = "0x0"

 			register "c3_latency" = "85"
 			register "docking_supported" = "1"
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -76,7 +76,6 @@ chip northbridge/intel/i945
 			register "ide_legacy_combined" = "0x0"
 			register "ide_enable_primary" = "0x1"
 			register "ide_enable_secondary" = "0x0"
-			register "sata_ahci" = "0x0"
 			register "c3_latency" = "85"

 			register "p_cnt_throttling_supported" = "0"
--- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
@@ -48,7 +48,6 @@ chip northbridge/intel/x4x		# Northbridge
      register "ide_legacy_combined" = "0x0"	# Combined mode broken
      register "ide_enable_primary" = "0x1"
      register "ide_enable_secondary" = "0x0"
-      register "sata_ahci" = "0x0"		# AHCI does not work
      register "sata_ports_implemented" = "0x3"
      register "gpe0_en" = "0x40"

--- a/src/mainboard/google/cyan/Makefile.inc
+++ b/src/mainboard/google/cyan/Makefile.inc
@@ -14,8 +14,9 @@
 ## GNU General Public License for more details.
 ##

+bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
+
 romstage-$(CONFIG_CHROMEOS) += chromeos.c
-romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
 romstage-y += spd/spd.c

 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
--- a/src/mainboard/google/cyan/com_init.c
+++ b/src/mainboard/google/cyan/com_init.c
@@ -14,14 +14,14 @@
 * GNU General Public License for more details.
 */

+#include <bootblock_common.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <soc/gpio.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
-#include <soc/romstage.h>

-void car_mainboard_pre_console_init(void)
+void bootblock_mainboard_early_init(void)
 {
 	uint32_t reg;
 	uint32_t *pad_config_reg;
--- a/src/mainboard/google/dragonegg/romstage_fsp_params.c
+++ b/src/mainboard/google/dragonegg/romstage_fsp_params.c
@@ -13,9 +13,74 @@
 * GNU General Public License for more details.
 */

+#include <assert.h>
 #include <baseboard/variants.h>
+#include <cbfs.h>
+#include <console/console.h>
 #include <soc/romstage.h>

+static uintptr_t mainboard_get_spd_data(void)
+{
+	char *spd_file;
+	size_t spd_file_len;
+	int spd_index;
+	const size_t spd_len = CONFIG_DIMM_SPD_SIZE;
+	const char *spd_bin = "spd.bin";
+
+	spd_index = variant_memory_sku();
+	assert(spd_index >= 0);
+	printk(BIOS_INFO, "SPD index %d\n", spd_index);
+
+	/* Load SPD data from CBFS */
+	spd_file = cbfs_boot_map_with_leak(spd_bin, CBFS_TYPE_SPD,
+					   &spd_file_len);
+	if (!spd_file)
+		die("SPD data not found.");
+
+	/* make sure we have at least one SPD in the file. */
+	if (spd_file_len < spd_len)
+		die("Missing SPD data.");
+
+	/* Make sure we did not overrun the buffer */
+	if (spd_file_len < ((spd_index + 1) * spd_len))
+		die("Invalid SPD index.");
+
+	spd_index *= spd_len;
+
+	return (uintptr_t)(spd_file + spd_index);
+}
+
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+	struct lpddr4_config mem_params;
+
+	memset(&mem_params, 0, sizeof(mem_params));
+	variant_memory_params(&mem_params);
+
+	if (mem_params.dq_map && mem_params.dq_map_size)
+		memcpy(&mem_cfg->DqByteMapCh0, mem_params.dq_map,
+				mem_params.dq_map_size);
+
+	if (mem_params.dqs_map && mem_params.dqs_map_size)
+		memcpy(&mem_cfg->DqsMapCpu2DramCh0, mem_params.dqs_map,
+				mem_params.dqs_map_size);
+
+	memcpy(&mem_cfg->RcompResistor, mem_params.rcomp_resistor,
+		mem_params.rcomp_resistor_size);
+
+	memcpy(&mem_cfg->RcompTarget, mem_params.rcomp_target,
+			mem_params.rcomp_target_size);
+
+	mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
+	mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+	mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
+	mem_cfg->DqPinsInterleaved = 0;
+	mem_cfg->CaVrefConfig = 0x2;
+	mem_cfg->ECT = 1; /* Early Command Training Enabled */
+	mem_cfg->RefClk = 0; /* Auto Select CLK freq */
+	mem_cfg->SpdAddressTable[0] = 0x0;
+	mem_cfg->SpdAddressTable[1] = 0x0;
+	mem_cfg->SpdAddressTable[2] = 0x0;
+	mem_cfg->SpdAddressTable[3] = 0x0;
 }
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -102,8 +102,8 @@ chip soc/intel/icelake
 		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
 		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
-		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
-		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoSkipInit,
+		[PchSerialIoIndexI2C5]  = PchSerialIoDisabled,
 	}"

 	register "SerialIoGSpiMode" = "{
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "100"
+	register "gpu_pp_down_delay_ms"		  = "500"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "1"
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "200"
+
 	# Deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/glados/variants/asuka/devicetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/glados/variants/cave/devicetree.cb
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/glados/variants/glados/devicetree.cb
+++ b/src/mainboard/google/glados/variants/glados/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/glados/variants/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s5_enable_ac" = "1"
 	register "deep_s5_enable_dc" = "1"
--- a/src/mainboard/google/glados/variants/sentry/devicetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb
@@ -1,5 +1,13 @@
 chip soc/intel/skylake

+	register "gpu_pp_up_delay_ms"		  = "200"
+	register "gpu_pp_down_delay_ms"		  = " 50"
+	register "gpu_pp_cycle_delay_ms"	  = "500"
+	register "gpu_pp_backlight_on_delay_ms"	  = "  1"
+	register "gpu_pp_backlight_off_delay_ms"  = "200"
+
+	register "gpu_pch_backlight_pwm_hz"	  = "1000"
+
 	# Enable deep Sx states
 	register "deep_s3_enable_ac" = "0"
 	register "deep_s3_enable_dc" = "0"
--- a/src/mainboard/google/hatch/chromeos-16MiB.fmd
+++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd
@@ -4,17 +4,17 @@ FLASH@0xff000000 0x1000000 {
 		SI_ME@0x1000 0x3ff000
 	}
 	SI_BIOS@0x400000 0xc00000 {
-		RW_SECTION_A@0x0 0x380000 {
+		RW_SECTION_A@0x0 0x368000 {
 			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0x36ffc0
-			RW_FWID_A@0x37ffc0 0x40
+			FW_MAIN_A(CBFS)@0x10000 0x357fc0
+			RW_FWID_A@0x367fc0 0x40
 		}
-		RW_SECTION_B@0x380000 0x380000 {
+		RW_SECTION_B@0x368000 0x368000 {
 			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0x36ffc0
-			RW_FWID_B@0x37ffc0 0x40
+			FW_MAIN_B(CBFS)@0x10000 0x357fc0
+			RW_FWID_B@0x367fc0 0x40
 		}
-		RW_MISC@0x700000 0x30000 {
+		RW_MISC@0x6D0000 0x30000 {
 			UNIFIED_MRC_CACHE@0x0 0x20000 {
 				RECOVERY_MRC_CACHE@0x0 0x10000
 				RW_MRC_CACHE@0x10000 0x10000
@@ -27,7 +27,8 @@ FLASH@0xff000000 0x1000000 {
 			RW_VPD(PRESERVE)@0x28000 0x2000
 			RW_NVRAM(PRESERVE)@0x2a000 0x6000
 		}
-		RW_LEGACY(CBFS)@0x730000 0xd0000
+		# RW_LEGACY needs to be minimum of 1MB
+		RW_LEGACY(CBFS)@0x700000 0x100000
 		WP_RO@0x800000 0x400000 {
 			RO_VPD(PRESERVE)@0x0 0x4000
 			RO_SECTION@0x4000 0x3fc000 {
--- a/src/mainboard/google/hatch/spd/8G_3200.spd.hex
+++ b/src/mainboard/google/hatch/spd/8G_3200.spd.hex
@@ -0,0 +1,32 @@
+23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00
+00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A
+20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 D0 19
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
--- a/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex
+++ b/src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex
@@ -0,0 +1,32 @@
+24 01 0F 0E 15 1A B4 08 00 00 00 0B 0A 03 00 00
+00 00 08 FF D4 01 00 00 78 00 90 A8 90 90 06 D0
+02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 08 7F C2 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -28,7 +28,7 @@ chip soc/intel/cannonlake
 	# Enable System Agent dynamic frequency
 	register "SaGv" = "SaGv_Enabled"
 	# Enable heci communication
-	register "HeciEnabled" = "1"
+	register "HeciEnabled" = "0"
 	# Enable Speed Shift Technology support
 	register "speed_shift_enable" = "1"
 	# Enable S0ix
@@ -99,7 +99,9 @@ chip soc/intel/cannonlake
 	register "gpio_pm[COMM_1]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
 	register "gpio_pm[COMM_2]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
 	register "gpio_pm[COMM_3]" = "MISCCFG_ENABLE_GPIO_PM_CONFIG"
-	register "gpio_pm[COMM_4]" = "MISCCFG_GPSIDEDPCGEN | MISCCFG_GPRTCDLCGEN | MISCCFG_GSXSLCGEN | MISCCFG_GPDPCGEN | MISCCFG_GPDLCGEN"
+	# Disable clock gating on this community so that cr50's short irq
+	# pulses won't be missed.
+	register "gpio_pm[COMM_4]" = "0"

 	device cpu_cluster 0 on
 		device lapic 0 on end
--- a/src/mainboard/google/kahlee/bootblock/bootblock.c
+++ b/src/mainboard/google/kahlee/bootblock/bootblock.c
@@ -17,6 +17,7 @@
 #include <bootblock_common.h>
 #include <soc/gpio.h>
 #include <soc/southbridge.h>
+#include <amdblocks/lpc.h>
 #include <variant/ec.h>
 #include <variant/gpio.h>

@@ -29,7 +30,7 @@ void bootblock_mainboard_early_init(void)
 	mainboard_ec_init();

 	gpios = variant_early_gpio_table(&num_gpios);
-	sb_program_gpios(gpios, num_gpios);
+	program_gpios(gpios, num_gpios);
 }

 void bootblock_mainboard_init(void)
@@ -61,5 +62,5 @@ void bootblock_mainboard_init(void)
 	}

 	/* Setup TPM decode before verstage */
-	sb_tpm_decode_spi();
+	lpc_tpm_decode_spi();
 }
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -16,6 +16,7 @@
 #include <arch/acpi.h>
 #include <console/console.h>
 #include <ec/google/chromeec/ec.h>
+#include <amdblocks/lpc.h>
 #include <soc/southbridge.h>
 #include <variant/ec.h>

@@ -49,7 +50,7 @@ static void early_ec_init(void)
 	printk(BIOS_DEBUG,
 		"LPC Setup google_chromeec_ioport_range: %04x, %08zx\n",
 		ec_ioport_base, ec_ioport_size);
-	status = sb_set_wideio_range(ec_ioport_base, ec_ioport_size);
+	status = lpc_set_wideio_range(ec_ioport_base, ec_ioport_size);
 	if (status == WIDEIO_RANGE_ERROR)
 		printk(BIOS_WARNING, "ERROR: Failed to assign a range\n");
 	else
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -27,6 +27,7 @@
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
+#include <soc/smi.h>
 #include <amdblocks/acpimmio.h>
 #include <variant/ec.h>
 #include <variant/thermal.h>
@@ -126,7 +127,7 @@ static void mainboard_init(void *chip_info)
 	mainboard_ec_init();

 	gpios = variant_gpio_table(&num_gpios);
-	sb_program_gpios(gpios, num_gpios);
+	program_gpios(gpios, num_gpios);

 	/*
 	 * Some platforms use SCI not generated by a GPIO pin (event above 23).
--- a/src/mainboard/google/kahlee/romstage.c
+++ b/src/mainboard/google/kahlee/romstage.c
@@ -34,7 +34,7 @@ void mainboard_romstage_entry(int s3_resume)
 	const struct soc_amd_gpio *gpios;

 	gpios = variant_romstage_gpio_table(&num_gpios);
-	sb_program_gpios(gpios, num_gpios);
+	program_gpios(gpios, num_gpios);

 	variant_romstage_entry(s3_resume);
 }
--- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb
@@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
 	}"
 	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
-	register "uma_size" = "32 * MiB"
+	register "uma_size" = "16 * MiB"
 	register "stapm_percent" = "80"
 	register "stapm_time_ms" = "2500000"
 	register "stapm_power_mw" = "7800"
--- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb
@@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
 	}"
 	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
-	register "uma_size" = "32 * MiB"
+	register "uma_size" = "16 * MiB"
 	register "stapm_percent" = "68"
 	register "stapm_time_ms" = "2500000"
 	register "stapm_power_mw" = "7800"
--- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb
@@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
 	}"
 	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
-	register "uma_size" = "32 * MiB"
+	register "uma_size" = "16 * MiB"
 	register "stapm_percent" = "80"
 	register "stapm_time_ms" = "2500000"
 	register "stapm_power_mw" = "7800"
--- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
@@ -19,7 +19,7 @@ chip soc/amd/stoneyridge
 	}"
 	register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP"
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
-	register "uma_size" = "32 * MiB"
+	register "uma_size" = "16 * MiB"
 	register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms
 	register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms

--- a/src/mainboard/google/mistral/chromeos.fmd
+++ b/src/mainboard/google/mistral/chromeos.fmd
@@ -22,7 +22,7 @@ FLASH@0x0 8M {
 			GBB 0x2f00
 			RO_FRID 0x100
 		}
-		RO_VPD 128K
+		RO_VPD(PRESERVE) 128K
 		RO_DDR_TRAINING(PRESERVE) 8K
 	}

--- a/src/mainboard/google/octopus/Kconfig
+++ b/src/mainboard/google/octopus/Kconfig
@@ -121,26 +121,18 @@ config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 63 # GPE0_DW1_31 (GPIO_63)

-config DRAM_PART_NUM_IN_CBI
+config DRAM_PART_NUM_NOT_ALWAYS_IN_CBI
 	bool
-	default y if BOARD_GOOGLE_PHASER
-	default y if BOARD_GOOGLE_MEEP
-	default y if BOARD_GOOGLE_AMPTON
-	default y if BOARD_GOOGLE_FLEEX
 	default y if BOARD_GOOGLE_BOBBA
-	default y if BOARD_GOOGLE_CASTA
-	default y if BOARD_GOOGLE_BLOOG
-
-config DRAM_PART_NUM_ALWAYS_IN_CBI
-	bool
-	depends on DRAM_PART_NUM_IN_CBI
-	default y if BOARD_GOOGLE_AMPTON
-	default y if BOARD_GOOGLE_CASTA
-	default y if BOARD_GOOGLE_BLOOG
+	default y if BOARD_GOOGLE_FLEEX
+	default y if BOARD_GOOGLE_MEEP
+	default y if BOARD_GOOGLE_OCTOPUS
+	default y if BOARD_GOOGLE_PHASER
+	default y if BOARD_GOOGLE_YORP

 config DRAM_PART_IN_CBI_BOARD_ID_MIN
 	int
-	depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI
+	depends on DRAM_PART_NUM_NOT_ALWAYS_IN_CBI
 	default 255 if BOARD_GOOGLE_YORP
 	default 2 if BOARD_GOOGLE_PHASER
 	default 2 if BOARD_GOOGLE_FLEEX
--- a/src/mainboard/google/octopus/romstage.c
+++ b/src/mainboard/google/octopus/romstage.c
@@ -37,12 +37,7 @@ void mainboard_save_dimm_info(void)
 	char part_num_store[DIMM_INFO_PART_NUMBER_SIZE];
 	const char *part_num = NULL;

-	if (!CONFIG(DRAM_PART_NUM_IN_CBI)) {
-		save_dimm_info_by_sku_config();
-		return;
-	}
-
-	if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+	if (CONFIG(DRAM_PART_NUM_NOT_ALWAYS_IN_CBI)) {
 		/* Fall back on part numbers encoded in lp4cfg array. */
 		if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
 			save_dimm_info_by_sku_config();
--- a/src/mainboard/google/octopus/variants/baseboard/memory.c
+++ b/src/mainboard/google/octopus/variants/baseboard/memory.c
@@ -205,10 +205,7 @@ static const struct lpddr4_cfg cbi_lp4cfg = {

 const struct lpddr4_cfg *__weak variant_lpddr4_config(void)
 {
-	if (!CONFIG(DRAM_PART_NUM_IN_CBI))
-		return &non_cbi_lp4cfg;
-
-	if (!CONFIG(DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+	if (CONFIG(DRAM_PART_NUM_NOT_ALWAYS_IN_CBI)) {
 		/* Fall back non cbi memory config. */
 		if ((int)board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN)
 			return &non_cbi_lp4cfg;
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -155,20 +155,6 @@ chip soc/intel/skylake
 	register "PcieRpAdvancedErrorReporting[0]" = "1"
 	register "PcieRpLtrEnable[0]" = "1"

-        # PCIe Root port 5 (NVMe)
-        #  PcieRpEnable:                 Enable root port
-        #  PcieRpClkReqSupport:          Enable CLKREQ#
-        #  PcieRpClkReqNumber:           Uses SRCCLKREQ4#
-        #  PcieRpClkSrcNumber:           Uses CLKOUT_PCIE_4
-        #  PcieRpAdvancedErrorReporting: Enable Advanced Error Reporting
-        #  PcieRpLtrEnable:              Enable Latency Tolerance Reporting Mechanism
-        register "PcieRpEnable[4]" = "1"
-        register "PcieRpClkReqSupport[4]" = "1"
-        register "PcieRpClkReqNumber[4]" = "4"
-        register "PcieRpClkSrcNumber[4]" = "4"
-        register "PcieRpAdvancedErrorReporting[4]" = "1"
-        register "PcieRpLtrEnable[4]" = "1"
-
 	# USB 2.0
 	register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Empty
@@ -374,7 +360,7 @@ chip soc/intel/skylake
 		device pci 1c.1 off end # PCI Express Port 2
 		device pci 1c.2 off end # PCI Express Port 3
 		device pci 1c.3 off end # PCI Express Port 4
-		device pci 1c.4 on  end # PCI Express Port 5 (NVMe)
+		device pci 1c.4 off end # PCI Express Port 5
 		device pci 1c.5 off end # PCI Express Port 6
 		device pci 1c.6 off end # PCI Express Port 7
 		device pci 1c.7 off end # PCI Express Port 8
--- a/src/mainboard/google/poppy/variants/atlas/gpio.c
+++ b/src/mainboard/google/poppy/variants/atlas/gpio.c
@@ -78,8 +78,8 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_NC(GPP_B7),
 	/* B8  : SRCCLKREQ3# ==> WLAN_PE_RST */
 	PAD_CFG_GPO(GPP_B8, 0, RSMRST),
-	/* B9  : SRCCLKREQ4# ==> NVME_PCIE_CLKREQ_L */
-	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	/* B9  : SRCCLKREQ4# ==> NC */
+	PAD_CFG_NC(GPP_B9),
 	/* B10 : SRCCLKREQ5# ==> NC */
 	PAD_CFG_NC(GPP_B10),
 	/* B11 : EXT_PWR_GATE# ==> NC */
--- a/src/mainboard/google/poppy/variants/nami/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nami/mainboard.c
@@ -215,7 +215,6 @@ const char *mainboard_vbt_filename(void)
 		return "vbt-bard.bin";
 	default:
 		return "vbt.bin";
-		break;
 	}
 }

--- a/Show More
+++ b/Show More