drivers/gfx/nvidia: acpi: Skeleton code for NBCI

Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I5fbc8e1480670457586885c6099c19d73ca06c45

.gitmodules

@@ -1,62 +1,62 @@
 [submodule "3rdparty/blobs"]
 	path = 3rdparty/blobs
-	url = ../blobs.git
+	url = https://review.coreboot.org/blobs.git
 	update = none
 	ignore = dirty
 [submodule "util/nvidia-cbootimage"]
 	path = util/nvidia/cbootimage
-	url = ../nvidia-cbootimage.git
+	url = https://review.coreboot.org/nvidia-cbootimage.git
 [submodule "vboot"]
 	path = 3rdparty/vboot
-	url = ../vboot.git
+	url = https://review.coreboot.org/vboot.git
 	branch = main
 [submodule "arm-trusted-firmware"]
 	path = 3rdparty/arm-trusted-firmware
-	url = ../arm-trusted-firmware.git
+	url = https://review.coreboot.org/arm-trusted-firmware.git
 [submodule "3rdparty/chromeec"]
 	path = 3rdparty/chromeec
-	url = ../chrome-ec.git
+	url = https://review.coreboot.org/chrome-ec.git
 [submodule "libhwbase"]
 	path = 3rdparty/libhwbase
-	url = ../libhwbase.git
+	url = https://review.coreboot.org/libhwbase.git
 [submodule "libgfxinit"]
 	path = 3rdparty/libgfxinit
-	url = ../libgfxinit.git
+	url = https://review.coreboot.org/libgfxinit.git
 [submodule "3rdparty/fsp"]
 	path = 3rdparty/fsp
-	url = ../fsp.git
+	url = https://review.coreboot.org/fsp.git
 	update = none
 	ignore = dirty
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
-	url = ../opensbi.git
+	url = https://review.coreboot.org/opensbi.git
 [submodule "intel-microcode"]
 	path = 3rdparty/intel-microcode
-	url = ../intel-microcode.git
+	url = https://review.coreboot.org/intel-microcode.git
 	update = none
 	ignore = dirty
 	branch = main
 [submodule "3rdparty/ffs"]
 	path = 3rdparty/ffs
-	url = ../ffs.git
+	url = https://review.coreboot.org/ffs.git
 [submodule "3rdparty/amd_blobs"]
 	path = 3rdparty/amd_blobs
-	url = ../amd_blobs
+	url = https://review.coreboot.org/amd_blobs
 	update = none
 	ignore = dirty
 [submodule "3rdparty/cmocka"]
 	path = 3rdparty/cmocka
-	url = ../cmocka.git
+	url = https://review.coreboot.org/cmocka.git
 	update = none
 [submodule "3rdparty/qc_blobs"]
 	path = 3rdparty/qc_blobs
-	url = ../qc_blobs.git
+	url = https://review.coreboot.org/qc_blobs.git
 	update = none
 	ignore = dirty
 [submodule "3rdparty/intel-sec-tools"]
 	path = 3rdparty/intel-sec-tools
-	url = ../9esec-security-tooling.git
+	url = https://review.coreboot.org/9esec-security-tooling.git
 [submodule "3rdparty/stm"]
 	path = 3rdparty/stm
-	url = ../STM
+	url = https://review.coreboot.org/STM
 	branch = stmpe

src/drivers/gfx/nvidia/Kconfig

@@ -0,0 +1,10 @@
+config DRIVERS_GFX_NVIDIA
+	bool
+	default n
+	help
+	  Support for NVIDIA Optimus with GC6 3.0
+
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	hex "PCI bridge for the GPU device"
+	default 0x01
+	depends on DRIVERS_GFX_NVIDIA

src/drivers/gfx/nvidia/Makefile.inc

@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+romstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += romstage.c
+
+ramstage-$(CONFIG_DRIVERS_GFX_NVIDIA) += nvidia.c

src/drivers/gfx/nvidia/acpi/advanced_optimus.asl

@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// NVIDIA Advanced Optimus
+
+#define NVOP_FUNC_SUPPORT		0
+#define NVOP_FUNC_DISPLAYSTATUS		5
+#define NVOP_FUNC_MDTL			6
+#define NVOP_FUNC_GETOBJBYTYPE		16
+#define NVOP_FUNC_GETALLOBJS		17
+#define NVOP_FUNC_OPTIMUSCAPS		26
+#define NVOP_FUNC_OPTIMUSFLAGS		27
+
+Method (NVOP, 2, Serialized)
+{
+	Printf("NVOP {")
+	Local0 = NVIDIA_ERROR_UNSUPPORTED
+
+	Switch (ToInteger(Arg0)) {
+		Case (NVOP_FUNC_SUPPORT) {
+		}
+
+		Case (NVOP_FUNC_OPTIMUSCAPS) {
+			CreateField (Arg1, 0, 1, FLGS)	// Flag updates
+			CreateField (Arg1, 1, 1, PCOT)	// PCIe Configuration Space Owner Target
+			CreateField (Arg1, 2, 1, PCOW)	// PCIe Configuration Space Owner Write
+			CreateField (Arg1, 24, 2, OPCE)	// Optimus Power Control Enable
+		}
+
+		Default {
+			Printf("  Unsupported NVOP_FUNC: %o", ToInteger(Arg0))
+			Local0 = NVIDIA_ERROR_UNSUPPORTED
+		}
+	}
+
+	Printf("} NVOP")
+	Return(Local0)
+}

src/drivers/gfx/nvidia/acpi/boost.asl

@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// NVIDIA GPU Boost for Notebook and All-In-One-Projects
+
+#define GPS_FUNC_SUPPORT		0
+#define GPS_FUNC_GETOBJBYTYPE		16
+#define GPS_FUNC_GETALLOBJS		17
+#define GPS_FUNC_GETCALLBACKS		19
+#define GPS_FUNC_PCONTROL		28
+#define GPS_FUNC_PSHARESTATUS		32
+#define GPS_FUNC_PSHAREPARAMS		42
+
+Method (GPS, 2, Serialized)
+{
+	Printf("GPS {")
+
+	Switch (ToInteger(Arg0)) {
+		// Bit list of supported functions
+		Case (GPS_FUNC_SUPPORT) {
+			Printf("  GPS_FUNC_SUPPORT")
+			// Functions supported: 0, 32, 42
+			Local0 = Buffer () {0x01, 0x00, 0x00, 0x00, 0x01, 0x04, 0x00, 0x00}
+		}
+
+		// Get current platform status, thermal budget
+		Case (GPS_FUNC_PSHARESTATUS) {
+			Printf("  GPS_FUNC_PSHARESTATUS: %o", ToHexString(Arg1))
+			Local0 = Buffer (4) { 0 }
+		}
+
+		// Get GPU Boost platform parameters
+		Case (GPS_FUNC_PSHAREPARAMS) {
+			Printf("  GPS_FUNC_PSHAREPARAMS: %o", ToHexString(Arg1))
+			CreateField (Arg1, 0, 3, QTYP)		// Query Type
+			CreateField (Arg1, 8, 1, GTMP)		// GPU temperature status
+			CreateField (Arg1, 9, 1, CTMP)		// CPU temperature status
+
+			Local0 = Buffer (36) { 0 }
+			CreateDWordField (Local0, 0, STAT)	// Status
+			CreateDWordField (Local0, 4, VERS)	// Version
+			CreateDWordField (Local0, 8, TGPU)	// GPU temperature (C)
+			CreateDWordField (Local0, 12, PDTS)	// CPU package temperature (C)
+
+			VERS = 0x00010000
+			STAT = QTYP
+
+			Printf("    Query Type = %o", ToInteger(QTYP))
+
+			Switch (ToInteger(QTYP)) {
+				// Get current status
+				Case (0) {
+					// TGPU must be 0.
+				}
+
+				// Get supported fields
+				Case (1) {
+					STAT |= 0x100
+					// TGPU must be 0.
+				}
+
+				// Get current operating limits
+				Case (2) {
+					// GPU temperature status must be 1.
+					STAT |= 0x100
+					// TGPU should be 0. GPU will use its own default.
+				}
+
+				Default {
+					Printf("    Unsupported Query Type: %o", ToInteger(QTYP))
+					Local0 = NVIDIA_ERROR_UNSUPPORTED
+				}
+			}
+		}
+
+		Default {
+			Printf("  Unsupported GPS_FUNC: %o", ToInteger(Arg0))
+			Local0 = NVIDIA_ERROR_UNSUPPORTED
+		}
+	}
+
+	Printf("} GPS")
+	Return(Local0)
+}

src/drivers/gfx/nvidia/acpi/gpu.asl

@@ -0,0 +1,197 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define NVIDIA_ERROR_UNSPECIFIED	0x80000001
+#define NVIDIA_ERROR_UNSUPPORTED	0x80000002
+
+#define NBCI_DSM_GUID		"D4A50B75-65C7-46F7-BFB7-41514CEA0244"
+#define NBCI_REVISION_ID	0x102
+
+#define GPS_DSM_GUID		"A3132D01-8CDA-49BA-A52E-BC9D46DF6B81"
+#define GPS_REVISION_ID		0x200
+
+#define JT_DSM_GUID		"CBECA351-067B-4924-9CBD-B46B00B86F34"
+#define JT_REVISION_ID		0x103
+
+#define NVOP_DSM_GUID		"A486D8F8-0BDA-471B-A72B-6042A6B5BEE0"
+#define NVOP_REVISION_ID	0x100
+
+// 00:01.0
+Device (\_SB.PCI0.PEG0)
+{
+	Name (_ADR, CONFIG_DRIVERS_GFX_NVIDIA_BRIDGE << 16)
+
+	PowerResource (PWRR, 0, 0) {
+		Name (_STA, 1)
+
+		Method (_ON)
+		{
+			Printf("PEG0._ON {")
+			// TODO: Check for deferred GCx action
+			\_SB.PCI0.PEG0.DGPU._ON()
+			_STA = 1
+			Printf("} PEG0._ON")
+		}
+
+		Method (_OFF)
+		{
+			Printf("PEG0._OFF {")
+			// TODO: Check for deferred GCx action
+			\_SB.PCI0.PEG0.DGPU._OFF()
+			_STA = 0
+			Printf("} PEG0._OFF")
+		}
+	}
+
+	Name (_PR0, Package () { PWRR })
+	Name (_PR2, Package () { PWRR })
+	Name (_PR3, Package () { PWRR })
+}
+
+// 01:00.0
+Device (\_SB.PCI0.PEG0.DGPU)
+{
+	Name(_ADR, 0x00000000)
+
+	Name (GPWR, 0)		// GPU Power
+	Name (GCST, 6)		// GCx State
+
+	Name (DPC, 0)		// Deferred power control
+	Name (DPCX, 0)		// Deferred power control on exit
+
+
+	Name (NVID, 0x00000000)
+
+	OperationRegion (PCIM, SystemMemory, 0x0E010000, 0xF0)
+	Field (PCIM, AnyAcc, Lock, Preserve)
+	{
+		Offset(0x2c),
+		SSID, 32,
+	}
+
+	// For supporting Hybrid Graphics, the package refers to the PCIe controller
+	// itself, which leverages GC6 Control methods under the dGPU namespace.
+	Name (_PR0, Package() { \_SB.PCI0.PEG0 })
+	Name (_PR3, Package() { \_SB.PCI0.PEG0 })
+
+	Method (_STA)
+	{
+		Printf("DGPU._STA")
+		/*
+		 * Only return "On" when:
+		 * - GPU power is good
+		 * - GPU has completed return to GC0
+		 *
+		 * In all other cases, return "Off".
+		 */
+		If ((GPWR == 1) && (GCST == 0)) {
+			Return (0xF)
+		} Else {
+			Return (0)
+		}
+	}
+
+	Method (_ON)
+	{
+		Printf("DGPU._ON {")
+		Printf("  Enable GPU power")
+		STXS(DGPU_PWR_EN)
+		Sleep(10)
+
+		Printf("  Take GPU out of reset")
+		STXS(DGPU_RST_N)
+		Sleep(10)
+
+		GPWR = 1
+		GCST = 0
+
+		/*
+		// TODO: Actually check link status
+		Printf("Wait for PCIe link")
+		Sleep(100)
+
+		Printf("Restore SSID: %o", NVID)
+		SSID = NVID
+		*/
+
+		Printf("} DGPU._ON")
+	}
+
+	Method (_OFF)
+	{
+		Printf("DGPU._OFF {")
+
+		/*
+		Printf("Save SSID: %o", SSID)
+		NVID = SSID
+
+		// TODO: Actually check link status
+		Printf("Wait for PCIe link")
+		Sleep(100)
+		*/
+
+		Printf("DGPU._OFF {")
+		Printf("  Put GPU in reset")
+		CTXS(DGPU_RST_N)
+		Sleep(10)
+
+		Printf("  Disable GPU power")
+		CTXS(DGPU_PWR_EN)
+
+		GPWR = 0
+		GCST = 6
+		Printf("} DGPU._OFF")
+	}
+
+	Method (_PS0)
+	{
+		// XGXS, XGIS, XCLM
+		Printf("_PS0 {}")
+	}
+
+	Method (_PS3)
+	{
+		// EGNS, EGIS, EGIN
+		Printf("_PS3 {}")
+	}
+
+	Method (_DSM, 4, Serialized)
+	{
+		// Notebook Common Interface
+		If (Arg0 == ToUUID(NBCI_DSM_GUID)) {
+			Printf("NBCI_DSM_GUID")
+			If (Arg1 <= NBCI_REVISION_ID) {
+				Printf("  TODO: Unimplemented!")
+			}
+		}
+
+		// NVIDIA GPU Boost
+		If (Arg0 == ToUUID(GPS_DSM_GUID)) {
+			Printf("GPS_DSM_GUID")
+			If (Arg1 <= GPS_REVISION_ID) {
+				Return(GPS(Arg2, Arg3))
+			}
+		}
+
+		// NVIDIA Low Power States
+		If (Arg0 == ToUUID(JT_DSM_GUID)) {
+			Printf("JT_DSM_GUID")
+			If (Arg1 <= JT_REVISION_ID) {
+				Return(NVJT(Arg2, Arg3))
+			}
+		}
+
+		// Advanced Optimus
+		If (Arg0 == ToUUID(NVOP_DSM_GUID)) {
+			Printf("NVOP_DSM_GUID")
+			If (Arg1 <= NVOP_REVISION_ID) {
+				Printf("  TODO: Unimplemented!")
+			}
+		}
+
+		Printf("Unsupported GUID: %o", ToHexString(Arg0))
+		Return(NVIDIA_ERROR_UNSUPPORTED)
+	}
+
+	#include "boost.asl"
+	#include "low_power_states.asl"
+}

src/drivers/gfx/nvidia/acpi/low_power_states.asl

@@ -0,0 +1,169 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// NVIDIA Low Power States
+
+#define JT_FUNC_SUPPORT		0
+#define JT_FUNC_CAPS		1
+#define JT_FUNC_POWERCONTROL	3
+#define JT_FUNC_PLATPOLICY	4
+
+Method (NVJT, 2, Serialized)
+{
+	Printf("NVJT {")
+
+	Switch (ToInteger(Arg0)) {
+		Case (JT_FUNC_SUPPORT) {
+			Printf("  JT_FUNC_SUPPORT");
+			// Functions supported: 0, 1, 3, 4
+			//Local0 = Buffer() { 0x1B, 0, 0, 0 }
+			Local0 = Buffer() { 0x13, 0, 0, 0 }
+		}
+
+		Case (JT_FUNC_CAPS) {
+			Printf("  JT_FUNC_CAPS");
+			Local0 = Buffer(4) { 0 }
+
+			// G-SYNC NVSR Power Features
+			CreateField (Local0, 0, 1, JTEN)
+			JTEN = 0
+
+			// NVSR
+			CreateField (Local0, 1, 2, NVSE)
+			NVSE = 1
+
+			// Panel Power Rail
+			CreateField (Local0, 3, 2, PPR)
+			PPR = 2
+
+			// Self-Refresh Control (SRC) Power Rail
+			CreateField (Local0, 5, 1, SRPR)
+			SRPR = 0
+
+			// FB Power Rail
+			CreateField (Local0, 6, 2, FBPR)
+			FBPR = 0
+
+			// GPU Power Rail
+			CreateField (Local0, 8, 2, GPR)
+			GPR = 0
+
+			// GC6 ROM
+			CreateField (Local0, 10, 1, GCR)
+			GCR = 0
+
+			// Panic Trap Handler
+			CreateField (Local0, 11, 1, PTH)
+			PTH = 1
+
+			// Supports Notify
+			CreateField (Local0, 12, 1, NOTS)
+			NOTS = 0
+
+			// MS Hybrid Support
+			CreateField (Local0, 13, 1, MHYB)
+			MHYB = 1
+
+			// Root Port Control
+			CreateField (Local0, 14, 1, RPC)
+			RPC = 1
+
+			// GC6 Version
+			CreateField (Local0, 15, 2, GC6V)
+			GC6V = 2
+
+			// GC6 Exit ISR Support
+			CreateField (Local0, 17, 1, GEI)
+			GEI = 0
+
+			// GC6 Self Wakeup Support
+			CreateField (Local0, 18, 1, GSW)
+			GSW = 0
+
+			// Maximum Revision Supported
+			CreateField (Local0, 20, 12, MXRV)
+			MXRV = JT_REVISION_ID
+		}
+
+		Case (JT_FUNC_POWERCONTROL) {
+			Printf("  JT_FUNC_POWERCONTROL: %o", ToHexString(Arg1));
+			// TODO
+			Local0 = NVIDIA_ERROR_UNSUPPORTED
+
+			/*
+			CreateField (Arg1, 0, 3, GPC)		// GPU Power Control
+			CreateField (Arg1, 3, 1, GGP)		// Global GPU Power
+			CreateField (Arg1, 4, 1, PPC)		// Panel Power Control
+			CreateField (Arg1, 6, 2, NOC)		// Notify on complete
+			CreateField (Arg1, 8, 2, PRGX)		// PCIe Root Power GC6 Exit Sequence
+			CreateField (Arg1, 10, 2, PRGE)		// PCIe Root Power GC6 Entry Sequence
+			CreateField (Arg1, 12, 1, PRPC)		// Poll for Root Port Completion
+			CreateField (Arg1, 13, 1, PLON)		// PCIe Root Port Control
+			CreateField (Arg1, 14, 2, DFGC)		// Defer GC6 Enter/Exit until D3cold
+			CreateField (Arg1, 16, 3, GPCX)		// Deferred GC6 Exit Control
+			CreateField (Arg1, 19, 1, EGEI)		// Enable GC6 Exit ISR
+			CreateField (Arg1, 20, 2, PLCM)		// PCIe Root Port Control Method for PLON
+
+			Local0 = Buffer(4) {0, 0, 0, 0}
+			CreateField (Local0, 0, 3, GCS)		// GC State
+			CreateField (Local0, 3, 1, GPS)		// GPU Power Status
+			CreateField (Local0, 7, 1, PSS)		// Panel and SRC State
+			*/
+
+			/*
+			 * DFGC
+			 * 0: Perform request immediately
+			 * 1: Defer GPC and GPCX to be processed when setting Device Power State
+			 * 2: Clear any pending deferred requests
+			 */
+			/*
+			If (DFGC == 2) {
+				DPC = 0
+				DPCX = 0
+			}
+			*/
+
+			/*
+			 * GPC
+			 * 0 GSS) Get current GPU GCx Sleep Status
+			 * 1 EGNS: Entery GC6 only. No SMI trap, No Self-Refresh. Panel
+			 *         and GPU will be powred down as normal. FB will remain powered.
+			 * 2 EGIS: Enter GC6, keep Panel in Self-Refresh. Enable SMI trap on
+			 *         VGA I/O regiters. Control of screen is transitioned to the SRC and
+			 *         then the GPU is powered down. Panel and FB remain powered while
+			 *         the GPU is off.
+			 * 3 XGXS: Exit GC6. Exit Panel Self-Refresh (Sparse). GPU is powered on.
+			 *         Disable SMI traps.
+			 * 4 XGIS: Exit GC6 for Self-Refresh Update (Burst). GPU is powered on, but
+			 *         the SRC continues to retain control of screen refresh, while the
+			 *         GPU sends an update to SRC for display. Disable SMI traps.
+			 * 5 EGIN: Enter GC6, keep Pnael in Self-Refresh. No SMI trap on VGA I/O
+			 *         registers. Control of screen is transitioned to SRC and then
+			 *         GPU is powred down. Panel and FB remain powered while the GPU is off.
+			 * 6 XCLM: Trigger GPU_EVENT only. GPU_EVENT would be assered and de-asserted,
+			 *         regardless of GPU power state, without waiting for any GPU-side
+			 *         signaling. No change in GPU power state is made. SMI traps disabled.
+			 */
+		}
+
+		Case (JT_FUNC_PLATPOLICY) {
+			Printf("  JT_FUNC_PLATPOLICY: %o", ToHexString(Arg1));
+			//CreateField (Arg1, 2, 1, AUD)		// Azalia Audio Device
+			//CreateField (Arg1, 3, 1, ADM)		// Audio Disable Mask
+			//CreateField (Arg1, 4, 4, DGS)		// Driver expected State Mask
+
+			// TODO: Save policy settings to NV CMOS?
+
+			Local0 = Buffer(4) { 0, 0, 0, 0 }
+			//CreateField (Local0, 2, 1, AUD)		// Audio Device status
+			//CreateField (Local0, 4, 3, GRE)		// SBIOS requested GPU state
+		}
+
+		Default {
+			Printf("  Unsupported JT_FUNC: %o", ToInteger(Arg0))
+			Local0 = NVIDIA_ERROR_UNSUPPORTED
+		}
+	}
+
+	Printf("} NVJT")
+	Return(Local0)
+}

src/drivers/gfx/nvidia/acpi/nbci.asl

@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+// Notebook Common Interface
+
+#define NBCI_FUNC_SUPPORT		0
+#define NBCI_FUNC_PLATCAPS		1
+#define NBCI_FUNC_PLATPOLICY		4
+#define NBCI_FUNC_DISPLAYSTATUS		5
+#define NBCI_FUNC_GETOBJBYTYPE		16
+#define NBCI_FUNC_GETALLOBJS		17
+#define NBCI_FUNC_GETEVENTLIST		18
+#define NBCI_FUNC_CALLBACKS		29
+#define NBCI_FUNC_GETBACKLIGHT		20
+#define NBCI_FUNC_GETLICENSE		22
+#define NBCI_FUNC_GETEFITABLE		23
+
+Scope (\_SB.PCI0.PEG0.DGPU)
+{
+	Method (NBCI, 2, NotSerialized)
+	{
+		Printf("NBCI {")
+		Local0 = NVIDIA_ERROR_UNSUPPORTED
+
+		Switch (ToInteger(Arg0)) {
+			// Bit list of supported functions
+			Case (NBCI_FUNC_SUPPORT) {
+				// Supported functions: 0
+				Local0 = Buffer() {0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+			}
+
+			// Query Plaform Capabilities
+			Case (NBCI_FUNC_PLATCAPS) {
+				Printf("  NBCI_FUNC_PLATCAPS: Unimplemented!")
+			}
+
+			// Query Platform Policies
+			Case (NBCI_FUNC_PLATPOLICY) {
+				Printf("  NBCI_FUNC_PLATPOLICY: Unimplemented!")
+			}
+
+			// Query Display status
+			Case (NBCI_FUNC_DISPLAYSTATUS) {
+				Printf("  NBCI_FUNC_DISPLAYSTATUS: Unimplemented!")
+			}
+
+			// Fetch and specific Object by Type
+			Case (NBCI_FUNC_GETOBJBYTYPE) {
+				Printf("  NBCI_FUNC_GETOBJBYTYPE: Unimplemented!")
+			}
+
+			// Fetch all Objects
+			Case (NBCI_FUNC_GETALLOBJS) {
+				Printf("  NBCI_FUNC_GETALLOBJS: Unimplemented!")
+			}
+
+			// Get list of Notify events and their meaning
+			Case (NBCI_FUNC_GETEVENTLIST) {
+				Printf("  NBCI_FUNC_GETEVENTLIST: Unimplemented!")
+			}
+
+			// Get list of system-required callbacks
+			Case (NBCI_FUNC_CALLBACKS) {
+				Printf("  NBCI_FUNC_CALLBACKS: Unimplemented!")
+			}
+
+			// Get the Backlight setup settings
+			Case (NBCI_FUNC_GETBACKLIGHT) {
+				Printf("  NBCI_FUNC_GETBACKLIGHT: Unimplemented!")
+			}
+
+			// Get Software License Number
+			Case (NBCI_FUNC_GETLICENSE) {
+				Printf("  NBCI_FUNC_GETLICENSE: Unimplemented!")
+			}
+
+			// Get EFI System Table
+			Case (NBCI_FUNC_GETEFITABLE) {
+				Printf("  NBCI_FUNC_GETEFITABLE: Unimplemented!")
+			}
+
+			Default {
+				Printf("  Unsupported NBCI_FUNC: %o", ToInteger(Arg0))
+				Local0 = NVIDIA_ERROR_UNSUPPORTED
+			}
+		}
+
+		Printf("} NBCI")
+		Return(Local0)
+	}
+}

src/drivers/gfx/nvidia/chip.h

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_CHIP_H_
+#define _DRIVERS_GFX_NVIDIA_CHIP_H_
+
+struct drivers_gfx_nvidia_config {
+	/* TODO: Set GPIOs in devicetree? */
+};
+
+#endif /* _DRIVERS_GFX_NVIDIA_CHIP_H_ */

src/drivers/gfx/nvidia/gpu.h

@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _DRIVERS_GFX_NVIDIA_GPU_H_
+#define _DRIVERS_GFX_NVIDIA_GPU_H_
+
+#include <stdbool.h>
+
+struct nvidia_gpu_config {
+	/* GPIO for GPU_PWR_EN */
+	unsigned int power_gpio;
+	/* GPIO for GPU_RST# */
+	unsigned int reset_gpio;
+	/* Enable or disable GPU power */
+	bool enable;
+};
+
+void nvidia_set_power(const struct nvidia_gpu_config *config);
+
+#endif /* _DRIVERS_NVIDIA_GPU_H_ */

src/drivers/gfx/nvidia/nvidia.c

@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "chip.h"
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+
+#define NVIDIA_SUBSYSTEM_ID_OFFSET 0x40
+
+static void nvidia_read_resources(struct device *dev)
+{
+	printk(BIOS_DEBUG, "%s: %s\n", __func__, dev_path(dev));
+
+	pci_dev_read_resources(dev);
+
+	// Find all BARs on GPU, mark them above 4g if prefetchable
+	for (int bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
+		struct resource *res = probe_resource(dev, bar);
+
+		if (res) {
+			if (res->flags & IORESOURCE_PREFETCH) {
+				printk(BIOS_INFO, "  BAR at 0x%02x marked above 4g\n", bar);
+				res->flags |= IORESOURCE_ABOVE_4G;
+			} else {
+				printk(BIOS_DEBUG, "  BAR at 0x%02x not prefetch\n", bar);
+			}
+		} else {
+			printk(BIOS_DEBUG, "  BAR at 0x%02x not found\n", bar);
+		}
+	}
+}
+
+static void nvidia_set_subsystem(struct device *dev, unsigned int vendor, unsigned int device)
+{
+	pci_write_config32(dev, NVIDIA_SUBSYSTEM_ID_OFFSET,
+		((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+static struct pci_operations nvidia_device_ops_pci = {
+	.set_subsystem = nvidia_set_subsystem,
+};
+
+static struct device_operations nvidia_device_ops = {
+	.read_resources   = nvidia_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+#if CONFIG(HAVE_ACPI_TABLES)
+	.write_acpi_tables = pci_rom_write_acpi_tables,
+	.acpi_fill_ssdt    = pci_rom_ssdt,
+#endif
+	.init             = pci_dev_init,
+	.ops_pci          = &nvidia_device_ops_pci,
+
+};
+
+static void nvidia_enable(struct device *dev)
+{
+	if (!dev->enabled || dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	dev->ops = &nvidia_device_ops;
+}
+
+struct chip_operations drivers_gfx_nvidia_ops = {
+	CHIP_NAME("NVIDIA Optimus graphics device")
+	.enable_dev = nvidia_enable
+};

src/drivers/gfx/nvidia/romstage.c

@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <gpio.h>
+#include "chip.h"
+#include "gpu.h"
+
+void nvidia_set_power(const struct nvidia_gpu_config *config)
+{
+	if (!config->power_gpio || !config->reset_gpio) {
+		printk(BIOS_ERR, "%s: GPU_PWR_EN and GPU_RST# must be set\n", __func__);
+		return;
+	}
+
+	printk(BIOS_DEBUG, "%s: GPU_PWR_EN = %d\n", __func__, config->power_gpio);
+	printk(BIOS_DEBUG, "%s: GPU_RST# = %d\n", __func__, config->reset_gpio);
+
+	gpio_set(config->reset_gpio, 0);
+	mdelay(4);
+
+	if (config->enable) {
+		gpio_set(config->power_gpio, 1);
+		mdelay(4);
+		gpio_set(config->reset_gpio, 1);
+	} else {
+		gpio_set(config->power_gpio, 0);
+	}
+
+	mdelay(4);
+}

src/ec/system76/ec/Kconfig

@@ -13,6 +13,11 @@ config EC_SYSTEM76_EC_COLOR_KEYBOARD
 	bool
 	default n
 
+config EC_SYSTEM76_EC_DGPU
+	depends on EC_SYSTEM76_EC
+	bool
+	default n
+
 config EC_SYSTEM76_EC_OLED
 	depends on EC_SYSTEM76_EC
 	bool

src/ec/system76/ec/acpi/s76.asl

@@ -117,6 +117,9 @@ Device (S76D) {
 	Method (NFAN, 0, Serialized) {
 		Return (Package() {
 			"CPU fan",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU fan",
+#endif
 		})
 	}
 
@@ -144,6 +147,9 @@ Device (S76D) {
 	Method (NTMP, 0, Serialized) {
 		Return (Package() {
 			"CPU temp",
+#if CONFIG(EC_SYSTEM76_EC_DGPU)
+			"GPU temp",
+#endif
 		})
 	}
 

src/include/cpu/intel/cpu_ids.h

@@ -44,7 +44,8 @@
 #define CPUID_COMETLAKE_H_S_6_2_G0	0xa0650
 #define CPUID_COMETLAKE_H_S_6_2_G1	0xa0653
 #define CPUID_COMETLAKE_H_S_10_2_P0	0xa0651
-#define CPUID_COMETLAKE_H_S_10_2_Q0_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_P1	0xa0654
+#define CPUID_COMETLAKE_H_S_10_2_Q0	0xa0655
 #define CPUID_TIGERLAKE_A0		0x806c0
 #define CPUID_TIGERLAKE_B0		0x806c1
 #define CPUID_TIGERLAKE_R0		0x806d1

src/mainboard/system76/addw1/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_ADDW1 || BOARD_SYSTEM76_ADDW2
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select EC_SYSTEM76_EC_OLED
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
@@ -60,6 +62,9 @@ config ONBOARD_VGA_IS_PRIMARY
 config UART_FOR_CONSOLE
 	default 2
 
+config MAX_CPUS
+	default 16
+
 config DIMM_MAX
 	default 2
 

src/mainboard/system76/addw1/acpi/mainboard.asl

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>

src/mainboard/system76/addw1/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/addw1/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/addw1/devicetree.cb

@@ -58,6 +58,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on  end # Integrated Graphics Device
 		device pci 04.0 on      # SA Thermal device

src/mainboard/system76/addw1/include/variant/gpio.h

@@ -3,7 +3,15 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/addw1/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Allow higher memory speeds
 	memupd->FspmConfig.SaOcSupport = 1;
 

src/mainboard/system76/bonw14/Kconfig

@@ -3,10 +3,12 @@ if BOARD_SYSTEM76_BONW14
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT

src/mainboard/system76/bonw14/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/bonw14/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/bonw14/devicetree.cb

@@ -62,11 +62,13 @@ chip soc/intel/cannonlake
 			register "PcieClkSrcUsage[7]" = "0x40"
 			register "PcieClkSrcClkReq[7]" = "7"
 
+			chip drivers/gfx/nvidia
 				device pci 00.0 on end # VGA controller
 				device pci 00.1 on end # Audio device
 				device pci 00.2 on end # USB xHCI Host controller
 				device pci 00.3 on end # USB Type-C UCSI controller
 			end
+		end
 		# TODO: is this enough to disable iGPU?
 		device pci 02.0 off end # Integrated Graphics Device
 		device pci 04.0 on  end # SA Thermal device

src/mainboard/system76/cml-u/Kconfig

@@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/cml-u"

src/mainboard/system76/cml-u/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/cml-u/acpi/mainboard.asl

@@ -6,6 +6,9 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/cml-u/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/cml-u/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/cml-u/dsdt.asl

@@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/darp7/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/darp7/acpi/mainboard.asl

@@ -6,4 +6,7 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/darp7/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Enable

src/mainboard/system76/darp7/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/darp7/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/galp5/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_GALP5
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_INTEL_USB4_RETIMER
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
 	select HAVE_OPTION_TABLE
@@ -22,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/galp5"
@@ -57,4 +60,7 @@ config UART_FOR_CONSOLE
 config USE_PM_ACPI_TIMER
 	default n
 
+config DRIVERS_GFX_NVIDIA_BRIDGE
+	default 0x1c
+
 endif

src/mainboard/system76/galp5/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/galp5/acpi/dgpu.asl

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.RP05)
+{
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+
+		// Fix SSID being lost across sleep by saving it
+		Name(NVSS, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve)
+		{
+			Offset (0x40),
+			SSID, 32,
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0)
+		{
+			Name (_STA, 1)
+
+			Method (_ON)
+			{
+				^^SSID = ^^NVSS
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF)
+			{
+				^^NVSS = ^^SSID
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}

src/mainboard/system76/galp5/acpi/mainboard.asl

@@ -1,9 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "dgpu.asl"
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/galp5/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Enable

src/mainboard/system76/galp5/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/galp5/devicetree.cb

@@ -278,6 +278,13 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "2" # PEG_CLKREQ#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref pcie_rp9 on
 			# PCIe root port #9 x1, Clock 3 (CARD)

src/mainboard/system76/galp5/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/galp5/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_U4
+#define DGPU_PWR_EN	GPP_U5
+#define DGPU_GC6	GPP_D2
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), // UART2_TXD
@@ -222,4 +228,6 @@ static const struct pad_config gpio_table[] = {
 	//PAD_CFG_GPO(GPP_U5, 0, DEEP), // DGPU_PWR_EN
 };
 
+#endif /* __ACPI__ */
+
 #endif /* MAINBOARD_GPIO_H */

src/mainboard/system76/galp5/romstage.c

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "gpio.h"
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
@@ -18,5 +20,20 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	// Allow memory clocks higher than 2933 MHz
+	mupd->FspmConfig.SaOcSupport = 1;
+
 	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/gaze15/Kconfig

@@ -3,10 +3,12 @@ if BOARD_SYSTEM76_GAZE14 || BOARD_SYSTEM76_GAZE15
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT

src/mainboard/system76/gaze15/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/gaze15/acpi/mainboard.asl

@@ -1,11 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/gaze15/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/gaze15/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/gaze15/devicetree.cb

@@ -57,6 +57,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/gaze15/dsdt.asl

@@ -18,7 +18,6 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze15/include/variant/gpio.h

@@ -3,7 +3,15 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/gaze15/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 static const struct cnl_mb_cfg memcfg = {
 	.spd[0] = {
@@ -20,5 +22,17 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);
 }

src/mainboard/system76/gaze16/Kconfig

@@ -3,10 +3,12 @@ if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GA
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -19,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select NO_UART_ON_SUPERIO
 	select SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_TIGERLAKE_PCH_H
+	select SOC_INTEL_TIGERLAKE_S3
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP

src/mainboard/system76/gaze16/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/gaze16/acpi/dgpu.asl

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Scope (\_SB.PCI0.PEG1)
+{
+	Device (DEV0)
+	{
+		Name(_ADR, 0x00000000)
+
+		// Fix SSID being lost across sleep by saving it
+		Name(NVSS, 0x00000000)
+
+		OperationRegion (PCIC, PCI_Config, 0x00, 0x50)
+		Field (PCIC, DwordAcc, NoLock, Preserve)
+		{
+			Offset (0x40),
+			SSID, 32,
+		}
+
+		Name (_PR0, Package () { PWRR })
+		Name (_PR3, Package () { PWRR })
+		PowerResource (PWRR, 0, 0)
+		{
+			Name (_STA, 1)
+
+			Method (_ON)
+			{
+				^^SSID = ^^NVSS
+				Printf("GPU _ON %o", ToHexString(^^SSID))
+				_STA = 1
+			}
+
+			Method (_OFF)
+			{
+				^^NVSS = ^^SSID
+				Printf("GPU _OFF %o", ToHexString(^^SSID))
+				_STA = 0
+			}
+		}
+	}
+}

src/mainboard/system76/gaze16/acpi/mainboard.asl

@@ -1,9 +1,14 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include "dgpu.asl"
+
 #define EC_GPE_SCI 0x6E
 #define EC_GPE_SWI 0x6B
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/gaze16/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/gaze16/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/gaze16/devicetree.cb

@@ -125,7 +125,9 @@ chip soc/intel/tigerlake
 				device i2c 15 on end
 			end
 		end
-		device ref heci1 on end
+		device ref heci1 on
+			register "HeciEnabled" = "1"
+		end
 		device ref uart2 on
 			# Debug console
 			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"

src/mainboard/system76/gaze16/dsdt.asl

@@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/gaze16/romstage.c

@@ -1,8 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <fsp/util.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include "variant.h"
 
 static const struct mb_cfg board_cfg = {
@@ -22,9 +24,21 @@ static const struct mem_spd spd_info = {
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
 	variant_memory_init_params(mupd);
 
-	const bool half_populated = false;
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
 
 	memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated);
 }

src/mainboard/system76/gaze16/variants/3050/include/variant/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
@@ -285,4 +291,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
 };
 
+#endif /* __ACPI__ */
+
 #endif /* VARIANT_GPIO_H */

src/mainboard/system76/gaze16/variants/3050/overridetree.cb

@@ -17,6 +17,13 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "-1" # GFX_CLKREQ0#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref peg0 on
 			# PCIe PEG0 x4, Clock 4 (SSD2)

src/mainboard/system76/gaze16/variants/3060/include/variant/gpio.h

@@ -5,6 +5,12 @@
 
 #include <soc/gpio.h>
 
+#define DGPU_RST_N	GPP_F8
+#define DGPU_PWR_EN	GPP_F9
+#define DGPU_GC6	GPP_K11
+
+#ifndef __ACPI__
+
 static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
 	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
@@ -285,4 +291,6 @@ static const struct pad_config gpio_table[] = {
 	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
 };
 
+#endif /* __ACPI__ */
+
 #endif /* VARIANT_GPIO_H */

src/mainboard/system76/gaze16/variants/3060/overridetree.cb

@@ -17,6 +17,13 @@ chip soc/intel/tigerlake
 				register "srcclk_pin" = "-1" # PEG_CLKREQ#
 				device generic 0 on end
 			end
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device ref peg0 on
 			# PCIe PEG0 x4, Clock 7 (SSD1)

src/mainboard/system76/kbl-u/Kconfig

@@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_KABYLAKE
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/kbl-u"

src/mainboard/system76/lemp10/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/lemp10/acpi/mainboard.asl

@@ -6,4 +6,7 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }

src/mainboard/system76/lemp10/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Enable

src/mainboard/system76/lemp10/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/lemp10/dsdt.asl

@@ -20,7 +20,6 @@ DefinitionBlock(
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/tigerlake/acpi/southbridge.asl>
 		#include <soc/intel/tigerlake/acpi/tcss.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/lemp9/Kconfig

@@ -21,7 +21,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
-	select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/lemp9"
@@ -59,10 +59,6 @@ config VGA_BIOS_ID
 	string
 	default "8086,9b41"
 
-config TPM_PIRQ
-	hex
-	default 0x10 # GPP_A7/PIRQA#
-
 config POST_DEVICE
 	bool
 	default n

src/mainboard/system76/lemp9/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		 5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/lemp9/acpi/mainboard.asl

@@ -6,6 +6,9 @@
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/lemp9/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/lemp9/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/oryp5/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_ORYP5
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -22,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP
+	select TPM_RDRESP_NEED_DELAY
 
 config MAINBOARD_DIR
 	default "system76/oryp5"

src/mainboard/system76/oryp5/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/oryp5/acpi/mainboard.asl

@@ -1,5 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <mainboard/gpio.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x17 /* GPP_B23 */
 #define EC_GPE_SWI 0x26 /* GPP_G6 */
 #include <ec/system76/ec/acpi/ec.asl>
@@ -7,6 +10,9 @@
 Scope (\_SB)
 {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE)

src/mainboard/system76/oryp5/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/oryp5/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/oryp5/devicetree.cb

@@ -65,6 +65,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/oryp5/dsdt.asl

@@ -19,7 +19,6 @@ DefinitionBlock(
 	{
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/oryp5/include/mainboard/gpio.h

@@ -3,7 +3,15 @@
 #ifndef MAINBOARD_GPIO_H
 #define MAINBOARD_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_C12
+
+#ifndef __ACPI__
 void mainboard_configure_early_gpios(void);
 void mainboard_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/oryp5/romstage.c

@@ -1,5 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
+#include <mainboard/gpio.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
 
@@ -20,6 +22,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	// Allow memory speeds higher than 2666 MT/s
 	memupd->FspmConfig.SaOcSupport = 1;
 

src/mainboard/system76/oryp6/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_ORYP6 || BOARD_SYSTEM76_ORYP7
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT

src/mainboard/system76/oryp6/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}

src/mainboard/system76/oryp6/acpi/mainboard.asl

@@ -1,11 +1,17 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <variant/gpio.h>
+#include <drivers/gfx/nvidia/acpi/gpu.asl>
+
 #define EC_GPE_SCI 0x03 /* GPP_K3 */
 #define EC_GPE_SWI 0x06 /* GPP_K6 */
 #include <ec/system76/ec/acpi/ec.asl>
 
 Scope (\_SB) {
 	#include "sleep.asl"
+	Scope (PCI0) {
+		#include "backlight.asl"
+	}
 }
 
 Scope (\_GPE) {

src/mainboard/system76/oryp6/cmos.default

@@ -1,2 +1,3 @@
 boot_option=Fallback
 debug_level=Debug
+me_state=Disable

src/mainboard/system76/oryp6/cmos.layout

@@ -12,10 +12,15 @@ entries
 400	8	r	0	century
 
 412	4	e	6	debug_level
-984	16	h	0	check_sum
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+976	16	h	0	check_sum
 
 enumerations
 
+2	0	Enable
+2	1	Disable
+
 4	0	Fallback
 4	1	Normal
 
@@ -31,4 +36,4 @@ enumerations
 
 checksums
 
-checksum 408 983 984
+checksum 408 975 976

src/mainboard/system76/oryp6/devicetree.cb

@@ -62,6 +62,13 @@ chip soc/intel/cannonlake
 			# PCI Express Graphics #0 x16, Clock 8 (NVIDIA GPU)
 			register "PcieClkSrcUsage[8]" = "0x40"
 			register "PcieClkSrcClkReq[8]" = "8"
+
+			chip drivers/gfx/nvidia
+				device pci 00.0 on end # VGA controller
+				device pci 00.1 on end # Audio device
+				device pci 00.2 on end # USB xHCI Host controller
+				device pci 00.3 on end # USB Type-C UCSI controller
+			end
 		end
 		device pci 02.0 on      # Integrated Graphics Device
 			register "gfx" = "GMA_DEFAULT_PANEL(0)"

src/mainboard/system76/oryp6/dsdt.asl

@@ -18,7 +18,6 @@ DefinitionBlock(
 	Device (\_SB.PCI0) {
 		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
 		#include <soc/intel/cannonlake/acpi/southbridge.asl>
-		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
 	}
 
 	#include <southbridge/intel/common/acpi/sleepstates.asl>

src/mainboard/system76/oryp6/include/variant/gpio.h

@@ -3,7 +3,15 @@
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_F22
+#define DGPU_PWR_EN	GPP_F23
+#define DGPU_GC6	GPP_K21
+
+#ifndef __ACPI__
 void variant_configure_early_gpios(void);
 void variant_configure_gpios(void);
+#endif
 
 #endif

src/mainboard/system76/oryp6/romstage.c

@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/cnl_memcfg_init.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 #include <variant/romstage.h>
 
 static const struct cnl_mb_cfg memcfg = {
@@ -21,6 +23,18 @@ static const struct cnl_mb_cfg memcfg = {
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	memupd->FspmConfig.PrimaryDisplay = 0;
+
 	variant_configure_fspm(memupd);
 
 	cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg);

src/mainboard/system76/oryp8/Kconfig

@@ -3,11 +3,13 @@ if BOARD_SYSTEM76_ORYP8
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_GFX_NVIDIA
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_TAS5825M
 	select EC_SYSTEM76_EC
 	select EC_SYSTEM76_EC_BAT_THRESHOLDS
 	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
 	select HAVE_ACPI_RESUME
 	select HAVE_ACPI_TABLES
 	select HAVE_CMOS_DEFAULT
@@ -21,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G
 	select SOC_INTEL_TIGERLAKE
 	select SOC_INTEL_TIGERLAKE_PCH_H
+	select SOC_INTEL_TIGERLAKE_S3
 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
 	select SPD_READ_BY_WORD
 	select SYSTEM_TYPE_LAPTOP

src/mainboard/system76/oryp8/acpi/backlight.asl

@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/intel/gma/acpi/gma.asl>
+
+Scope (GFX0)
+{
+	Name (BRIG, Package (22) {
+		40, /* default AC */
+		40, /* default Battery */
+		5,
+		10,
+		15,
+		20,
+		25,
+		30,
+		35,
+		40,
+		45,
+		50,
+		55,
+		60,
+		65,
+		70,
+		75,
+		80,
+		85,
+		90,
+		95,
+		100
+	})
+}