Begin rewriting the ACPI support according to the Design Guide.
Partially implements Low Power States and GPU Boost methods.
Change-Id: I119f3206685ad337dcbb73d55cc807d00d5659fb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The addw1 supports an i9-9980HK and the addw2 uses an i7-10875H.
These CPUs have 8 cores and 16 threads. Fixes booting on addw2.
Change-Id: I4639b40c3ab9c6d6ad5abbbb3618c750c7d40695
Fixes: 6a93a45242 ("mb/system76/addw1: Add System76 Adder Workstation 1")
Signed-off-by: Tim Crawford <tcrawford@system76.com>
The option table is shrunk 1 byte to force coreboot to invalid the table
and write the new defaults. This will ensure the IME is in the correct
mode on the next update.
Change-Id: I805c53fee55fea69fa3363fea0609858cc88f2d3
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H,
and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER.
The HECI device must be enabled in devicetree for switching modes to
function correctly.
Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add .enable method that will set the CSME state. The state is based on
the new CMOS option me_state, with values of 0 and 1. The method is very
stable when switching between different firmware platforms.
This method should not be used in combination with USE_ME_CLEANER.
State 1 will result in:
ME: Current Working State : 4
ME: Current Operation State : 1
ME: Current Operation Mode : 3
ME: Error Code : 2
State 0 will result in:
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 0
Tested on:
KBL-R: i7-8550u
CML: i3-10110u, i7-10710u
TGL: i3-1110G4, i7-1165G7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add a driver for systems with NVIDIA Optimus (hybrid) graphics using
GC6 3.0. The driver provides ACPI support for dynamically powering on
and off the GPU, and a function for enabling the GPU power in romstage.
Tested on system76/gaze15.
Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Software Connection Manager doesn't work with Linux 5.13 or later and
results in TBT ports timing out. Not advertising this results in
Firmware Connection Manager being used and TBT works correctly.
Linux patch:
c6da62a219
Tested on:
* StarBook Mk V
* System76 Oryx Pro 8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
1. Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
2. Configure DMA buffer in DRAM
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
CONFIG(SMP) was an invalid condition to use in cases where one
stage requires spinlocks and another one does not. The
stage not requiring spinlock still required <smp/spinlock.h>
to be implemented with no-op stubs.
This reverts commit 037ee4b556
soc/amd/picasso: Add dummy spinlock for psp_verstage
Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change adds about 30 KiB to FSP-M. When not using the SPI DMA
controller, this change actually has a ~7 ms boot time penalty. When
we use the DMA engine, we end up with about a 5 ms decrease. Once we
switch to 100 MHz SPI this will help even more since we have effectively
eliminated the decompression time.
BUG=b:179699789
TEST=Boot nipperkin to OS and take boot time measurements
fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed)
fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed)
- FSP-M / no async -
| 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) |
...
| 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) |
- FSP-M / async -
| 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) |
...
| 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) |
| 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Calling reboot_into_recovery with NULL context fails. Initializing ctx
early also fails because the cmos is not ready until after
verstage_soc_early_init. So just reboot and hope for the best.
BUG=None
TEST=Boot guybrush, suspend/resume guybrush
BRANCH=None
Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format
warning below:
CC romstage/soc/intel/xeon_sp/memmap.o
src/soc/intel/xeon_sp/memmap.c: In function 'fill_postcar_frame':
src/soc/intel/xeon_sp/memmap.c:39:62: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
39 | printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size);
| ~~^ ~~~~~~~~~~
| | |
| long unsigned int size_t {aka unsigned int}
| %x
As `cbmem_size` is of type `size_t` use the appropriate length modifier
`z`.
Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5
Found-by: gcc (Debian 11.2.0-10) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lance Zhao
Do not place console output in low-level GPIO functions.
The caller of get_recovery_mode_switch() is in vboot_logic.c
that is linked in romstage. So presumably recovery mode
is broken and is not fixed with this commit either.
Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add APU device apc driver and set up permissions.
APU has its own device apc for control access by domains.
For Domain 0, the access to the following slaves are restricted to
security read and write:
apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser,
apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4
apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4
For VPU, D0/D5 are set as no protection, other domains are forbidden.
For other slaves, the D0 is no protection, other domains are forbidden.
BUG=b:203145462
BRANCH=cherry
TEST=boot cherry, check dump log and test permissions
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
FSP-S is normally memmapped and then decompressed. There are about 7 ms
between starting ramstage, and loading FSP-S. By preloading we can
ensure the fsps.bin is already in RAM by the time we need it. This
reduces boot time by about 7 ms.
BUG=b:
TEST=Boot nipperkin and see ~7ms reduction in boot time
| 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) |
| 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) |
| 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) |
| 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) |
| 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) |
| 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) |
CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1)
CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208
waiting for thread
took 1 us <-- fsps.bin was preloaded
CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This will enable reading FSP-S/M using the SPI DMA controller.
BUG=B:179699789
TEST=Build guybrush with SPI DMA enabled and verify alignment is set
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make the `codec_init()` function non-static so that it can be used in
other places. Rename it to `azalia_codec_init()` for consistency with
the other functions of the API.
Also, update the function's signature to make it more flexible. Remove
the unused `dev` parameter and allow callers to pass the verb table to
use. Update the original call site to preserve behavior.
Change-Id: I5343796242065b5fedc78cd95bcf010c9e2623dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59117
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the `codecs_init()` function non-static so that it can be used in
other places. Rename it to `azalia_codecs_init()` to avoid name clashes
with static definitions in southbridge code (which will be removed in
subsequent commits).
Change-Id: I080a73102b0c4f9f8a283cd93bba9b3b23169be0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For consistency with other Intel southbridges, program PC BEEP verbs.
None of the boards in the tree using this southbridge provide PC BEEP
verbs, so this change makes no difference.
Change-Id: I94d24999af819cf3951510586fd4864d1ed3f2f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use the `azalia_program_verb_table()` function in preparation to
deduplicate Azalia init code.
With this change, the "Azalia: verb loaded." message is now printed when
programming the verbs failed. This will be addressed once `codec_init()`
has been deduplicated.
Change-Id: I5d9e0f19429620166f2a6ef48ec7c963ee64b59c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Currently all the power sequencing for FPMCU is done explicitly in
different stages of coreboot. This can all be done by adding ACPI power
resources for FPMCU and clean up the unused code. Here is the expected
power sequence:
PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL
Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL
Reboot : Shutdown -> 200 ms delay -> PowerUp
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to
unlock the system after the first login attempt. Ensure that the FP is
able to wakeup the system. Observed that the power resource is added
correctly in the FPMCU ACPI object
Name (_PR0, Package (0x01) // _PR0: Power Resources for D0
{
PR01
})
Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot
{
PR01
})
PowerResource (PR01, 0x00, 0x0000)
{
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x01)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
\_SB.CTXS (0x0B)
\_SB.STXS (0x20)
\_SB.STXS (0x0B)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.CTXS (0x0B)
\_SB.CTXS (0x20)
}
}
Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
We need to put USB setting in mux order.
BUG=b:204230406
TEST=Type C mux configuration is correct.
Wrong:
added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
Correct:
added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add wifi sar for galtic/galtic360/galith360
Using convertible mode of SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
BUG=b:203741126
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).
Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.
BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Unknown
....
With this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Row Of Chips
....
Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We are currently counting how long it takes to print the waiting
message, in addition to the actual time we spent waiting. This results
in inflating the measurement by 1.7ms when the serial console is
enabled. This CL makes it so the print happens before the stopwatch
starts.
BUG=b:179699789
TEST=No longer see printk time taken into account on serial console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add documentation describing how to add support for a new memory
technology to spd_tools:
- Add a section to the README.
- Document the memTech interface in spd_gen.go.
BUG=b:191776301
TEST=None
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie710c1c686ddf5288db35cf43e5f1ac9b1974305
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16
of the misc I2C pad control registers is defined as BiasCrtEn, so rename
I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update charger performance control table of DPTF for bugzzy.
Since the EC change chromium:197776876 modified maximum charging current
to reduce skin temperature, this change adjusts the charging performance
table with the modified value.
BUG=b:197776876
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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