soc/amd/cezanne: enable LPC decodes if platform uses LPC

Change-Id: I2473fe61b299d1c6221844cd744791b8012c5c67
Signed-off-by: Jeremy Soller <jeremy@system76.com>

src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb

@@ -68,6 +68,9 @@ chip soc/intel/alderlake
 	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
 	register "PchHdaIDispCodecEnable" = "1"
 
+        # FIVR RFI Spread Spectrum 1.5%
+        register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb

@@ -74,6 +74,9 @@ chip soc/intel/alderlake
 	register "PchHdaIDispLinkFrequency" = "HDA_LINKFREQ_96MHZ"
 	register "PchHdaIDispCodecEnable" = "1"
 
+	# FIVR RFI Spread Spectrum 1.5%
+	register "FivrSpreadSpectrum" = "FIVR_SS_1_5"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

src/mainboard/google/brya/variants/redrix/overridetree.cb

@@ -34,6 +34,8 @@ chip soc/intel/alderlake
 	register "SaGv" = "SaGv_Enabled"
 
 	register "CnviBtAudioOffload" = "true"
+	# FIVR RFI Spread Spectrum 6%
+	register "FivrSpreadSpectrum" = "FIVR_SS_6"
 
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+

src/mainboard/google/dedede/Kconfig.name

@@ -150,6 +150,7 @@ config BOARD_GOOGLE_BUGZZY
 	select BASEBOARD_DEDEDE_LAPTOP
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_DA7219
+	select GEO_SAR_ENABLE if CHROMEOS_WIFI_SAR
 
 config BOARD_GOOGLE_CORORI
 	bool "->  Corori"

src/mainboard/google/dedede/variants/bugzzy/overridetree.cb

@@ -63,12 +63,18 @@ chip soc/intel/jasperlake
 		},
 		.i2c[1] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 133,
+			.fall_time_ns = 29,
 		},
 		.i2c[2] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 227,
+			.fall_time_ns = 9,
 		},
 		.i2c[3] = {
 			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 91,
+			.fall_time_ns = 2,
 		},
 		.i2c[4] = {
 			.speed = I2C_SPEED_FAST,
@@ -114,10 +120,10 @@ chip soc/intel/jasperlake
 					}
 				}"
 				register "controls.charger_perf" = "{
-					[0] = {  55, 3500 },
-					[1] = {  47, 3000 },
-					[2] = {  39, 2500 },
-					[3] = {  31, 2000 },
+					[0] = { 255, 2800 },
+					[1] = {  39, 2500 },
+					[2] = {  31, 2000 },
+					[3] = {  23, 1500 },
 				}"
 				device generic 0 on end
 			end

src/mainboard/google/dedede/variants/magolor/overridetree.cb

@@ -19,6 +19,7 @@ fw_config
 		option TS_RAYD_0001 4
 		option TS_WDHT0002 5
 		option TS_GTCH7503 6
+		option TS_ELAN_9004 7
 	end
 	field AUDIO_CODEC_SOURCE 49 51
 		option AUDIO_CODEC_UNPROVISIONED 0
@@ -227,6 +228,26 @@ chip soc/intel/jasperlake
 					probe TS_SOURCE TS_ELAN_6918
 				end
 			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN9004""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D5)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.reset_off_delay_ms" = "2"
+				register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)"
+				register "generic.stop_delay_ms" = "280"
+				register "generic.stop_off_delay_ms" = "2"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)"
+				register "generic.enable_delay_ms" = "1"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on
+					probe TS_SOURCE TS_ELAN_9004
+				end
+			end
 			chip drivers/i2c/hid
 				register "generic.hid" = ""WDHT0002""
 				register "generic.desc" = ""WDT Touchscreen""

src/mainboard/google/dedede/variants/metaknight/overridetree.cb

@@ -243,15 +243,28 @@ chip soc/intel/jasperlake
 				register "hid" = ""10EC1015""
 				register "desc" = ""Realtek SPK AMP L""
 				register "uid" = "0"
-				device i2c 28 on end
+				device i2c 28 on
+					probe AUDIO_AMP UNPROVISIONED
+					probe AUDIO_AMP RT1015_I2C
+				end
 			end
 			chip drivers/i2c/generic
 				register "hid" = ""10EC1015""
 				register "desc" = ""Realtek SPK AMP R""
 				register "uid" = "1"
-				device i2c 29 on end
+				device i2c 29 on
+					probe AUDIO_AMP UNPROVISIONED
+					probe AUDIO_AMP RT1015_I2C
+				end
 			end
 		end
-		device pci 1f.3 on end # Intel HDA
+		device pci 1f.3 on
+			chip drivers/generic/alc1015
+				register "sdb" =  "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D17)"
+				device generic 0 on
+					probe AUDIO_AMP RT1015P_AUTO
+				end
+			end
+		end # Intel HDA
 	end
 end

src/mainboard/google/trogdor/chromeos.c

@@ -22,6 +22,8 @@ void setup_chromeos_gpios(void)
 	} else {
 		gpio_output(GPIO_EN_PP3300_DX_EDP, 0);
 		gpio_output(GPIO_EDP_BRIDGE_ENABLE, 0);
+		gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 0);
+		gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0);
 	}
 
 	if (CONFIG(TROGDOR_HAS_FINGERPRINT)) {

src/mainboard/google/trogdor/mainboard.c

@@ -106,12 +106,18 @@ static void power_on_ps8640_bridge(void)
 	gpio_output(GPIO_EN_PP3300_DX_EDP, 1);
 
 	gpio_output(GPIO_PS8640_EDP_BRIDGE_3V3_ENABLE, 1);
-	gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1);
-	gpio_output(GPIO_PS8640_EDP_BRIDGE_RST_L, 0);
 
 	/*
-	 * According to ps8640 app note v0.6, wait for 2ms ("t1") after
-	 * VDD33 goes high and then deassert RST.
+	 * According to ps8640 v1.4 spec, and the raise time of vdd33 is a bit
+	 * long, so wait for 4ms after VDD33 goes high and then deassert PD.
+	 */
+	mdelay(4);
+
+	gpio_output(GPIO_PS8640_EDP_BRIDGE_PD_L, 1);
+
+	/*
+	 * According to ps8640 app note v0.6, wait for 2ms after VDD33 goes
+	 * high and then deassert RST.
 	 */
 	mdelay(2);
 

src/mainboard/intel/adlrvp/chromeos.fmd

@@ -15,7 +15,7 @@ FLASH 32M {
 			VBLOCK_A 64K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
-			ME_RW_A(CBFS) 4032K
+			ME_RW_A(CBFS) 3520K
 		}
 		RW_LEGACY(CBFS) 1M
 		RW_MISC 1M {
@@ -39,7 +39,7 @@ FLASH 32M {
 			VBLOCK_B 64K
 			FW_MAIN_B(CBFS)
 			RW_FWID_B 64
-			ME_RW_B(CBFS) 4032K
+			ME_RW_B(CBFS) 3520K
 		}
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.

src/soc/amd/cezanne/early_fch.c

@@ -21,6 +21,12 @@ static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
 	I2C_RESET_SCL_PIN(I2C3_SCL_PIN, GPIO_I2C3_SCL),
 };
 
+static void lpc_configure_decodes(void)
+{
+	if (CONFIG(POST_IO) && (CONFIG_POST_IO_PORT == 0x80))
+		lpc_enable_port80();
+}
+
 static void reset_i2c_peripherals(void)
 {
 	const struct soc_amd_cezanne_config *cfg = config_of_soc();
@@ -41,6 +47,9 @@ void fch_pre_init(void)
 	/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
 	lpc_early_init();
 
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
+		lpc_configure_decodes();
+
 	/* Setup eSPI to enable port80 routing if the board is using eSPI and the eSPI
 	   interface hasn't already been set up in verstage on PSP */
 	if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI) && !CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))

src/soc/amd/cezanne/include/soc/southbridge.h

@@ -99,15 +99,15 @@
 #define MISC_I2C1_PAD_CTRL		0xdc
 #define MISC_I2C2_PAD_CTRL		0xe0
 #define MISC_I2C3_PAD_CTRL		0xe4
-#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) + BIT(1) + BIT(2) + BIT(3))
+#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define     I2C_PAD_CTRL_NG_NORMAL	0xc
-#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) + BIT(5))
+#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
 #define     I2C_PAD_CTRL_RX_SHIFT	4
 #define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
 #define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
 #define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
 #define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
-#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) + BIT(8))
+#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
 #define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
 #define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
 #define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
@@ -118,7 +118,7 @@
 #define   I2C_PAD_CTRL_CAP_UP		BIT(13)
 #define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
 #define   I2C_PAD_CTRL_RES_UP		BIT(15)
-#define   I2C_PAD_CTRL_BIOS_CRT_EN	BIT(16)
+#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
 #define   I2C_PAD_CTRL_SPARE0		BIT(17)
 #define   I2C_PAD_CTRL_SPARE1		BIT(18)
 

src/soc/amd/picasso/include/soc/southbridge.h

@@ -96,15 +96,15 @@
 #define MISC_I2C1_PAD_CTRL		0xdc
 #define MISC_I2C2_PAD_CTRL		0xe0
 #define MISC_I2C3_PAD_CTRL		0xe4
-#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) + BIT(1) + BIT(2) + BIT(3))
+#define   I2C_PAD_CTRL_NG_MASK		(BIT(0) | BIT(1) | BIT(2) | BIT(3))
 #define     I2C_PAD_CTRL_NG_NORMAL	0xc
-#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) + BIT(5))
+#define   I2C_PAD_CTRL_RX_SEL_MASK	(BIT(4) | BIT(5))
 #define     I2C_PAD_CTRL_RX_SHIFT	4
 #define     I2C_PAD_CTRL_RX_SEL_OFF	(0 << I2C_PAD_CTRL_RX_SHIFT)
 #define     I2C_PAD_CTRL_RX_SEL_3_3V	(1 << I2C_PAD_CTRL_RX_SHIFT)
 #define     I2C_PAD_CTRL_RX_SEL_1_8V	(3 << I2C_PAD_CTRL_RX_SHIFT)
 #define   I2C_PAD_CTRL_PULLDOWN_EN	BIT(6)
-#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) + BIT(8))
+#define   I2C_PAD_CTRL_FALLSLEW_MASK	(BIT(7) | BIT(8))
 #define     I2C_PAD_CTRL_FALLSLEW_SHIFT	7
 #define     I2C_PAD_CTRL_FALLSLEW_STD	(0 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
 #define     I2C_PAD_CTRL_FALLSLEW_LOW	(1 << I2C_PAD_CTRL_FALLSLEW_SHIFT)
@@ -115,7 +115,7 @@
 #define   I2C_PAD_CTRL_CAP_UP		BIT(13)
 #define   I2C_PAD_CTRL_RES_DOWN		BIT(14)
 #define   I2C_PAD_CTRL_RES_UP		BIT(15)
-#define   I2C_PAD_CTRL_BIOS_CRT_EN	BIT(16)
+#define   I2C_PAD_CTRL_BIAS_CRT_EN	BIT(16)
 #define   I2C_PAD_CTRL_SPARE0		BIT(17)
 #define   I2C_PAD_CTRL_SPARE1		BIT(18)
 

src/soc/intel/alderlake/chip.h

@@ -135,6 +135,22 @@ enum lpm_state_mask {
 		     | LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4,
 };
 
+/*
+ * FivrSpreadSpectrum:
+ * Values
+ *  0 - 0.5%, 3 - 1%, 8 - 1.5%, 18 - 2%, 28 - 3%, 34 - 4%, 39 - 5%, 44 - 6%
+ */
+enum fivr_spread_spectrum_ratio {
+	FIVR_SS_0_5 = 0,
+	FIVR_SS_1 = 3,
+	FIVR_SS_1_5 = 8,
+	FIVR_SS_2 = 18,
+	FIVR_SS_3 = 28,
+	FIVR_SS_4 = 34,
+	FIVR_SS_5 = 39,
+	FIVR_SS_6 = 44,
+};
+
 struct soc_intel_alderlake_config {
 
 	/* Common struct containing soc config data required by common code */
@@ -495,6 +511,23 @@ struct soc_intel_alderlake_config {
 
 	/* Platform Power Pmax */
 	uint16_t PsysPmax;
+	/*
+	 * FivrRfiFrequency
+	 * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
+	 * 0: Auto
+	 * Range varies based on XTAL clock:
+	 *   0-1918*100 KHz (Up to 191.8MHz) for 24MHz clock
+	 *   0-1535*100 KHz (Up to 153.5MHz) for 19MHz clock
+	 */
+	uint32_t FivrRfiFrequency;
+	/*
+	 * FivrSpreadSpectrum
+	 * Set the Spread Spectrum Range.
+	 *   Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%.
+	 *   Each Range is translated to an encoded value for FIVR register.
+	 *   0.5% = 0, 1% = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
+	 */
+	uint8_t FivrSpreadSpectrum;
 };
 
 typedef struct soc_intel_alderlake_config config_t;

src/soc/intel/alderlake/fsp_params.c

@@ -731,6 +731,14 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
 			config->ext_fivr_settings.vnn_icc_max_ma;
 }
 
+static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	/* transform from Hz to 100 KHz */
+	s_cfg->FivrRfiFrequency = config->FivrRfiFrequency / (100 * KHz);
+	s_cfg->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+}
+
 static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		struct soc_intel_alderlake_config *config)
 {
@@ -761,6 +769,7 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_misc_power_params,
 		fill_fsps_irq_params,
 		fill_fsps_fivr_params,
+		fill_fsps_fivr_rfi_params,
 	};
 
 	for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)

src/soc/intel/apollolake/acpi.c

@@ -12,7 +12,6 @@
 #include <gpio.h>
 #include <intelblocks/acpi.h>
 #include <intelblocks/pmclib.h>
-#include <intelblocks/sgx.h>
 #include <intelblocks/p2sb.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
@@ -88,9 +87,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 		gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
 	}
 
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
-		sgx_fill_gnvs(gnvs);
-
 	/* Fill in Above 4GB MMIO resource */
 	sa_fill_gnvs(gnvs);
 }

src/soc/intel/apollolake/acpi/globalnvs.asl

@@ -23,9 +23,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	SCDP,	8,      // 0x29 - SD_CD GPIO portid
 	SCDO,	8,      // 0x2A - GPIO pad offset relative to the community
 	UIOR,	8,      // 0x2B - UART debug controller init on S3 resume
-	EPCS,   8,      // 0x2C - SGX Enabled status
-	EMNA,   64,     // 0x2D - 0x34 EPC base address
-	ELNG,   64,     // 0x35 - 0x3C EPC Length
-	A4GB,	64,	// 0x3D - 0x44 Base of above 4GB MMIO Resource
-	A4GS,	64,	// 0x45 - 0x4C Length of above 4GB MMIO Resource
+	A4GB,	64,	// 0x2C - 0x33 Base of above 4GB MMIO Resource
+	A4GS,	64,	// 0x34 - 0x3B Length of above 4GB MMIO Resource
 }

src/soc/intel/apollolake/include/soc/nvs.h

@@ -28,11 +28,8 @@ struct __packed global_nvs {
 	uint8_t		scdo; /* 0x2A - GPIO pad offset relative to the community */
 	uint8_t		uior; /* 0x2B - UART debug controller init on S3
 					 resume */
-	uint8_t		epcs; /* 0x2C - SGX Enabled status */
-	uint64_t	emna; /* 0x2D - 0x34 EPC base address */
-	uint64_t	elng; /* 0x35 - 0x3C EPC Length */
-	uint64_t	a4gb; /* 0x3D - 0x44 Base of above 4GB MMIO Resource */
-	uint64_t	a4gs; /* 0x45 - 0x4C Length of above 4GB MMIO Resource */
+	uint64_t	a4gb; /* 0x2C - 0x33 Base of above 4GB MMIO Resource */
+	uint64_t	a4gs; /* 0x34 - 0x3B Length of above 4GB MMIO Resource */
 };
 
 #endif	/* _SOC_APOLLOLAKE_NVS_H_ */

src/soc/intel/common/acpi/sgx.asl

@@ -6,6 +6,9 @@ Scope(\_SB)
 	// Secure Enclave memory
 	Device (EPC)
 	{
+		External (EPCS, IntObj)
+		External (EMNA, IntObj)
+		External (ELNG, IntObj)
 		Name (_HID, EISAID ("INT0E0C"))
 		Name (_STR, Unicode ("Enclave Page Cache 1.0"))
 		Name (_MLS, Package () {

src/soc/intel/common/block/acpi/acpi.c

@@ -15,6 +15,7 @@
 #include <intelblocks/acpi_wake_source.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pmclib.h>
+#include <intelblocks/sgx.h>
 #include <intelblocks/uart.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
@@ -427,4 +428,7 @@ void generate_cpu_entries(const struct device *device)
 
 	/* Add a method to notify processor nodes */
 	acpigen_write_processor_cnot(num_virt);
+
+	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
+		sgx_fill_ssdt();
 }

src/soc/intel/common/block/acpi/acpi/globalnvs.asl

@@ -25,7 +25,4 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	A4GB,	64,	// 0x30 - 0x37 Base of above 4GB MMIO Resource
 	A4GS,	64,	// 0x38 - 0x3f Length of above 4GB MMIO Resource
 	,	64, 	// 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code)
-	EPCS,	8,	// 0x48 - SGX enabled status
-	EMNA,	64,	// 0x49 - 0x50 EPC base address
-	ELNG,	64,	// 0x51 - 0x58 EPC length
 }

src/soc/intel/common/block/include/intelblocks/nvs.h

@@ -27,10 +27,6 @@ struct __packed global_nvs {
 	u64	a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
 	u64	a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
 	u64	hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */
-	/* SGX */
-	u8	epcs; /* 0x48 - SGX enabled status */
-	u64	emna; /* 0x49 - 0x50 EPC base address */
-	u64	elng; /* 0x51 - 0x58 EPC length */
 };
 
 #endif

src/soc/intel/common/block/include/intelblocks/sgx.h

@@ -17,7 +17,7 @@ void prmrr_core_configure(void);
  */
 void sgx_configure(void *unused);
 
-/* Fill GNVS data with SGX status, EPC base and length */
-void sgx_fill_gnvs(struct global_nvs *gnvs);
+/* Fill SSDT for SGX status, EPC base and length */
+void sgx_fill_ssdt(void);
 
 #endif	/* SOC_INTEL_COMMON_BLOCK_SGX_H */

src/soc/intel/common/block/sgx/sgx.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <acpi/acpigen.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
@@ -10,7 +11,6 @@
 #include <intelblocks/sgx.h>
 #include <intelblocks/systemagent.h>
 #include <soc/cpu.h>
-#include <soc/nvs.h>
 #include <soc/pci_devs.h>
 
 static inline uint64_t sgx_resource(uint32_t low, uint32_t high)
@@ -235,31 +235,40 @@ void sgx_configure(void *unused)
 		activate_sgx();
 }
 
-void sgx_fill_gnvs(struct global_nvs *gnvs)
+void sgx_fill_ssdt(void)
 {
+	bool epcs = false;
 	struct cpuid_result cpuid_regs;
+	uint64_t emna = 0, elng = 0;
 
-	if (!is_sgx_supported()) {
-		printk(BIOS_DEBUG,
-			"SGX: not supported. skip gnvs fill\n");
-		return;
+	if (is_sgx_supported()) {
+		/*
+		 * Get EPC base and size.
+		 * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or
+		 * Higher for enumeration of SGX Resources. Same Table mentions
+		 * about return values of the CPUID
+		 */
+		cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,
+					SGX_RESOURCE_ENUM_CPUID_SUBLEAF);
+
+		if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {
+			/* EPC section enumerated */
+			epcs = true;
+			emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx);
+			elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx);
+		}
+
+		printk(BIOS_DEBUG, "SGX: EPC status = %d base = 0x%llx len = 0x%llx\n",
+				   epcs, emna, elng);
+	} else {
+		printk(BIOS_DEBUG, "SGX: not supported.\n");
 	}
 
-	/* Get EPC base and size.
-	 * Intel SDM: Table 36-6. CPUID Leaf 12H, Sub-Leaf Index 2 or
-	 * Higher for enumeration of SGX Resources. Same Table mentions
-	 * about return values of the CPUID */
-	cpuid_regs = cpuid_ext(SGX_RESOURCE_ENUM_CPUID_LEAF,
-				SGX_RESOURCE_ENUM_CPUID_SUBLEAF);
-
-	if (cpuid_regs.eax & SGX_RESOURCE_ENUM_BIT) {
-		/* EPC section enumerated */
-		gnvs->epcs = 1;
-		gnvs->emna = sgx_resource(cpuid_regs.eax, cpuid_regs.ebx);
-		gnvs->elng = sgx_resource(cpuid_regs.ecx, cpuid_regs.edx);
+	acpigen_write_scope("\\_SB.EPC");
+	{
+		acpigen_write_name_byte("EPCS", epcs);
+		acpigen_write_name_qword("EMNA", emna);
+		acpigen_write_name_qword("ELNG", elng);
 	}
-
-	printk(BIOS_DEBUG,
-		"SGX: gnvs EPC status = %d base = 0x%llx len = 0x%llx\n",
-			gnvs->epcs, gnvs->emna, gnvs->elng);
+	acpigen_pop_len();
 }

src/soc/intel/skylake/acpi.c

@@ -13,7 +13,6 @@
 #include <intelblocks/acpi_wake_source.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/pmclib.h>
-#include <intelblocks/sgx.h>
 #include <soc/cpu.h>
 #include <soc/msr.h>
 #include <soc/pm.h>
@@ -179,9 +178,6 @@ void soc_fill_gnvs(struct global_nvs *gnvs)
 	gnvs->u2we = config->usb2_wake_enable_bitmap;
 	gnvs->u3we = config->usb3_wake_enable_bitmap;
 
-	if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE))
-		sgx_fill_gnvs(gnvs);
-
 	/* Fill in Above 4GB MMIO resource */
 	sa_fill_gnvs(gnvs);
 }

util/spd_tools/README.md

@@ -590,3 +590,48 @@ util/spd_tools/bin/part_id_gen \
         `dram_id.generated.txt` with the new part.
     *   Upload the changes to `Makefile.inc` and `dram_id.generated.txt` for
         review.
+
+## How to add support for a new memory technology
+
+### 1. Gather the SPD requirements
+
+To generate SPDs for the new memory technology, information is needed about the
+list of bytes in the SPD and how the value of each byte should be determined.
+This information usually comes from a combination of:
+
+*   The JEDEC spec for the memory technology, e.g. JESD209-5B for LPDDR5.
+*   The JEDEC SPD spec for the memory technology, e.g. SPD4.1.2.M-2 for LPDDR3/4
+    (also used for LP4x and LP5).
+*   Platform-specific requirements. SoC vendors often don't follow the JEDEC
+    specs exactly. E.g. the memory training code may expect certain SPD bytes to
+    encode a different value to what is stated in the spec. So for each SoC
+    platform using the new memory technology, any platform-specific requirements
+    need to be gathered.
+
+### 2. Implement support in spd_tools
+
+Support for the new memory technology needs to be added to both the `spd_gen`
+and `part_id_gen` tools.
+
+#### `spd_gen`
+
+Adding support to `spd_gen` requires implementing the logic to generate SPDs for
+the new memory technology. The changes required are:
+
+*   Add the new memory technology to the `memTechMap` in `spd_gen/spd_gen.go`.
+*   Add a new file `spd_gen/<mem_tech>.go`. This file will contain all the logic
+    for generating SPDs for the new memory technology. It needs to implement the
+    `memTech` interface defined in `spd_gen/spd_gen.go`. The interface functions
+    are documented inline. Examples of how the interface is implemented for
+    existing memory technologies can be found in the `spd_gen/` directory, e.g.
+    `lp4x.go`, `ddr4.go`, `lp5.go`. While not strictly necessary, it is
+    recommended to follow the overall structure of these existing files when
+    adding a new memory technology.
+
+#### `part_id_gen`
+
+The `part_id_gen` tool is memory technology-agnostic, so the only change
+required is:
+
+*   Add the new memory technology to the `supportedMemTechs` list in
+    `part_id_gen/part_id_gen.go`.

util/spd_tools/src/spd_gen/spd_gen.go

@@ -28,10 +28,37 @@ type memPart struct {
 }
 
 type memTech interface {
+	/*
+	 * Returns the set -> platform mapping for the memory technology. Platforms with the
+	 * same SPD requirements should be grouped together into a single set.
+	 */
 	getSetMap() map[int][]int
+
+	/*
+	 * Takes the name and attributes of a part, as read from the memory_parts JSON file.
+	 * Validates the attributes, returning an error if any attribute has an invalid value.
+	 * Stores the name and attributes internally to be used later.
+	 */
 	addNewPart(string, interface{}) error
+
+	/*
+	 * Takes the name of a part and a set number.
+	 * Retrieves the part's attributes which were stored by addNewPart(). Updates them by
+	 * setting any optional attributes which weren't specified in the JSON file to their
+	 * default values.
+	 * Returns these updated attributes.
+	 */
 	getSPDAttribs(string, int) (interface{}, error)
+
+	/*
+	 * Returns the size of an SPD file for this memory technology.
+	 */
 	getSPDLen() int
+
+	/*
+	 * Takes an SPD byte index and the attributes of a part.
+	 * Returns the value which that SPD byte should be set to based on the attributes.
+	 */
 	getSPDByte(int, interface{}) byte
 }